1 Utility-Based Partitioning of Shared Caches Moinuddin K. Qureshi Yale N. Patt International Symposium on Microarchitecture (MICRO) 2006.
Hardware Transactional Memory for GPU Architectures Wilson W. L. Fung Inderpeet Singh Andrew Brownsword Tor M. Aamodt University of British Columbia In.
Http:// Achieving Non-Inclusive Cache Performance with Inclusive Caches Temporal Locality Aware (TLA) Cache Management Policies Aamer Jaleel,
QoS-Aware Memory Systems (Wrap Up) Onur Mutlu [email protected] July 9, 2013 INRIA.
Many-Thread Aware Prefetching Mechanisms for GPGPU Application
GP GPU Applications and Simulations Mike Metzger [email protected] MS - ECE.
GP GPU Applications and Simulations
Power to the People : Leveraging Human Physiological Traits for Microprocessor Frequency Control
QoS -Aware Memory Systems (Wrap Up)
Into the Wild: Studying Real User Activity Patterns to Guide Power Optimizations for Mobile Architectures Alex Shye, Benjamin Scholbrock, and Gokhan Memik.
CS 194 Research Proposal
Multi-core Systems and Coherence Hierarchies
