Maurice Goodrick & Bart Hommels, University of Cambridge WP2.2 - Study of data paths on ECAL Slab Paths between VFE Chips and the FE Chip : Clock and Control.
Maurice Goodrick & Bart Hommels, University of Cambridge ECAL DIF: Issues & Solutions Readout Architecture.
Maurice Goodrick & Bart Hommels, University of Cambridge ECAL SLAB Interconnect Making the interconnections between the Slab component PCBs (“ASUs”) is.
