Agile Cafe Boulder - Panelist and keynote slides
Techniques for Combinational Logic Optimization. Minimizing Circuits Karnaugh Maps.
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT
117520548-EC2354-VLSI-DESIGN-Unit-5-ppt.pdf
ECE465 FSM State Minimization for Completely Specified Machines Shantanu Dutt Acknowledgement: Slides prepared by Huan Ren from Prof. Dutt’s Lecture Notes.
Asynchronous comparator design
Asynchronous Datapath Design
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed L
