1 A Case for MLP-Aware Cache Replacement International Symposium on Computer Architecture (ISCA) 2006 Moinuddin K. Qureshi Daniel N. Lynch, Onur Mutlu,
JOHAN TORP STHLM GAME DEVELOPER FORUM 5/5 2011. ›M.Sc. Computer Science. OO (Java) and functional programming (Haskell) ›Worked ~5 years outside game.
FFT Accelerator Project Rohit Prakash Anand Silodia Date: June 7 th, 2007.
A step towards data orientation
Energy Efficient Latency Tolerance: Single-Thread Performance for the Multi-Core Era
Lightweight, High-Resolution Monitoring for Troubleshooting Production Systems S. Bhatia, A. Kumar, M. E. Fiuczynski, L. Peterson (Princeton & Google),
Duke :: March 18, 2010 Energy Efficient Latency Tolerance: Single-Thread Performance for the Multi-Core Era Andrew Hilton University of Pennsylvania [email protected].
