OPNET Slides
Day2 Verilog HDL Basic
Digital Systems Verification Lecture 13 Alessandra Nardi.
Protocol implementation on NS2
Using the M5 Simulator - ASPLOS XIII
System on Chip Design and Modelling Dr. David J Greaves
Introduction to Logic Synthesis Using Verilog HDL
Computer Aids for VLSI Design1
Classification of Simulators Logic Simulators Emulator-basedSchematic-basedHDL-based Event-drivenCycle-basedGateSystem.
StarFish: highly-available block storage Eran Gabber Jeff Fellin Michael Flaster Fengrui Gu Bruce Hillyer Wee Teck Ng Banu O¨ zden Elizabeth Shriver 2003.
Testing4.pdf
Accelerating Simulation of Agent-Based Models on Heterogeneous Architectures
