ATV312 ProfibusDP CommsManual
IRDH575-v1.6_TGH_A
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum & Minerals.
DRACO Architecture Research Group. DSN, Edinburgh UK, 06.25.2007 Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance.
Simulation of Fault Detection for Robot Applications Chase Baker, Taeghyun Kang, Michael Shin Ph.D. Interaction with robot applications are becoming increasingly.
High-Level Test Generation
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
A Look Inside the San Andreas fault at Parkfield Through Vertical Seismic Profiling Chavarria, Malin, Catchings, and Shalev Science, 302, pp 1746-1748,
