Lab inv l
4 ee600 lab2_grp
vnu_DIGITAL_QB.pdf
finl DIGITAL QB.doc
TTL CMOS
Lab2 Inverter S Edit
Process Flow Steps Steps –Choose a substrate Add epitaxial layers if needed –Form n and p regions –Deposit contacts and local interconnects –Deposit.
Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.
