Intel trng report_20120312
Runtime Reconfigurable Network-on-chips for FPGA-based Systems
Q2.12: Idle Power States Nomenclature
TECD Self-covered Template
POWER EFFICIENT ALU DESIGN WITH CLOCK AND CONTROL-SIGNAL GATING TECHNIQUE
From virtual to high end HW routing for the adult
SAM D Family_E_US_021014_Web.pdf
-1- UC San Diego / VLSI CAD Laboratory OCV-Aware Top-Level Clock Tree Optimization Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee and Siddhartha.
Processing Efficiency Jonah Probell Multimedia Systems Engineer Tensilica Truly Understanding Low-Power Multimedia Chip Design.
April 30, 2014 1 Cost efficient soft-error protection for ASICs Tuvia Liran; Ramon Chips Ltd. [email protected].
System Design Tricks for Low-Power Video Processing Jonah Probell, Director of Multimedia Solutions, ARC International.
Feng-Xiang Huang A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures.
