Dst
Battery Model for Embedded Systems Venkat Rao, EE Department, IIT Delhi. Gaurav Singhal, CSE Department, IIT Delhi. Anshul Kumar, CSE Department, IIT Delhi.
Battery Aware Dynamic Scheduling for Periodic Task Graphs Venkat Rao #, Nicolas Navet #, Gaurav Singhal *, Anshul Kumar, GS Visweswaran Venkat Rao #, Nicolas.
Lec Jan12 2009
Lec Feb02 2009
Lec Feb05 2009
Lec Jan19 2009
Lec Feb09 2009
pcfreaks
Anshul Kumar, CSE IITD CSL718 : Memory Hierarchy Cache Performance Improvement 23rd Feb, 2006.
Anshul Kumar, CSE IITD CSL718 : Pipelined Processors PipelineTimings 12th Jan, 2006.
Anshul Kumar, CSE IITD Other Architectures & Examples Multithreaded architectures Dataflow architectures Multiprocessor examples 1 st May, 2006.
