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Xilinx Design Flow
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The IIntegrated SSoftware EEnvironment
Advanced DesignAdvanced DesignTechniquesTechniquesGNU Embedded ToolsWind River Xilinx EditionEmbedded Development Kit IMPACTSystem ACE Configuration
Manager
Verification TechnologiesVerification TechnologiesModelSim Xilinx Edition Static Timing AnalyzerChipScope ProXPower power estimationFormal Verification support3rd Party HDL simulationChipViewerFPGA Editor with ProbeHDL Bencher testbench generator
Design EntryDesign EntryHDL Edit and EntrySystem Generator for DSPCORE IP Generator Architecture WizardsECS Schematic EditorStateCAD State Diagram EditorRTL Checker
SynthesisSynthesisSynplicity Synplify and Synplify ProSynplicity Amplify physical synthesisMentorGraphics LeonardoSpectrumMentor Graphics Precision RTL
physical synthesisSynopsys FPGA Compiler IIXilinx Synthesis Technology (XST)
ImplementationImplementationFloorplanner and PACEConstraints EditorTiming Driven Place & RouteModular DesignIncremental DesignTiming Improvement Wizard
Board Level IntegrationBoard Level IntegrationIBIS ModelsSTAMP ModelsLMG Smart ModelsHSPICE Models
One solution for all your logic design needs
3rd party partner tools
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Translate
Map
Place & Route
Xilinx Design Flow
Plan & Budget HDL RTLSimulation
Synthesizeto create netlist
FunctionalSimulation
CreateBit File
Attain Timing Closure
TimingSimulation
Implement
Create Code/Schematic
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Creating a Project
Select File New ProjectNew Project Wizard guides you through the process
Project name and locationTarget deviceSoftware flowCreate or add source files
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Creating and AddingSource Files
To include an existing source file, double-click Add Existing SourceTo create a new source file, double-click Create New Sourceand choose the type of file
HDL fileIPSchematicState diagramTestbenchConstraints file
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Text Entry
Color coding helps you quickly understand and enter the design
Blue= Reserved words
Pink= Signal type
Green= Comments
Black = User input
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Language Templates
Two methods to open templates:
Language Icon
Edit -> Language Templates
Language Templates provide common templates for designs:
Component instantiation
Language templates
Synthesis templates
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Schematic Source File
Files with .schextension
Selecting this source type will open the ECS (Engineering Capture System) schematic editor
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Options and Symbols
Components are divided into categories
Exact symbols are located in the Symbol box
Symbol Name Filter for easier search
Orientation
Rotate 0, 90,180, 270
Mirror and rotate 0, 90, 180, 270
The Options tab selections change, depending on which function is selected
For example, if you are adding a net name, the net name options would be shown
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Files with .diaextension
Selecting this surcetype
will invoke StateCAD
State Diagram Source
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Implementation Status
ISE will run all of the necessary steps to implement the design
Synthesize HDL codeTranslateMapPlace & Route
Progress and status are indicated by iconsGreen check mark ( ) indicates that the process was completed successfullyYellow exclamation point ( ! ) indicates warningsYellow question mark ( ? ) indicates a file that is out of dateRed “X” indicates errors
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Simulating a Design
To simulate a design:In the Sources in Project window, select a testbench file In the Processes for Source window, expand ModelSim Simulator Double-click Simulate Behavioral Model or Simulate Post-Place & Route Model
• Can also simulate after Translate or after Map
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Sub-Processes
Each process can be expanded to view sub-tools and sub-processes
Translate• Floorplan• Assign Package Pins
Map• Analyze timing
Place & Route• Analyze timing• Floorplan • FPGA Editor• Analyze power• Create simulation model
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Program the FPGA
There are two ways to program an FPGA
Through a PROM device• You will need to generate a file
that the PROM programmer will understand
Directly from the computer• Use the iMPACT configuration tool
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ISE 6.1i is designed and tested to run with the leading HDL simulators in the industry
Cadence NC-SimModel Technology ModelSimSynopsys VCS-MX and Scirocco
All Xilinx libraries and netlists conform to IEEE VHDL-93, VITAL-2000 and Verilog-2001 standards
Other simulators are available to perform Xilinx CPLD and FPGA verification
3rd Party Simulation Integration
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3rd Party Synthesis Integration
Synplify/Pro 7.3.1Ability to use the parity bit in Virtex™-II, Virtex-II Pro™, and Spartan™-3 devices to optimize Block RAM implementationsImproved area optimization for Virtex-II, Virtex-II Pro, and Spartan-3 devices
Precision 2003bSupport Virtex-E/-II/-II Pro, Spartan-II/-IIE/-3 Advanced design analysis
LeonardoSpectrum 2003bSupport Spartan-3 family
FCII v3.8Support for Spartan-3 devicesSupport for all Virtex-II Pro devices
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Simulation Tool
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Simulation in the FPGA Environment
Gate Level Simulation
HDL GateTiming
HDL GateTiming
Place & Route
HDL GateFunctional
Synthesis
HDL RTL
Design Entry
VITAL orVerilog
SimulationLibrary
RTLSimulation
FunctionalSimulation
RTL Simulation
Highest performance
Many spins
• highest throughput
Functional Simulation
• Does function match RTL Golden model
Gate Level Simulation
• Highest impact on simulation run time
• Full timing
• Does function match RTL Golden model
Source Templates and Wizards, HDS, IPX, XilinxLogiCORE, CORE Generator
ModelSim
Leonardo Spectrum
XilinxISE
ModelSim
ModelSim
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HDL Bencher
Creates timing constrained VHDL and Verilog self-checking testbenches
No knowledge of HDL or scripting required
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Create a New Source
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Create a New Source
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HDL Bencher
Unit under test is analyzed, when selected
Port problems
Syntax violations
Inconsistencies
Design timing selected
Clocked or combinatorial?
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Create Waveforms
Data values
1, 0 ,X ,Z, U
Assignments
Double-click bit signal to toggle value
Pattern wizard assigns a range of cell values
WaveTableassign signals like a spreadsheet
By default, decimal values are shown in the WaveTable
Waveform values are checked as they are entered
Validation check for non-binary inputs only (for example, hex, or decimal)
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Toggling
Toggling bit values is the easiest way to assign bit signals
Simply click directly on the signal’s waveform at the time where changes should take place
Click directly on these boxes, at the time where signals should toggle
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Pattern Wizard
Aids complex waveform input
To access, click a signal at the time it should be changed to access value cell editor
Note: light blue background = input assignment,
light yellow background = output assignment
Click in this areaClick here for Pattern Wizard
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Pattern Wizard
Available patterns
Pattern description
Changes depending on the pattern selected
Count unit in clock cycles
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Testbench
Waveform file extensions are TBW
Waveform file can be seen in the Sources in Project window of the Project Navigator
To view testbench:
In Sources in Project Window, select the TBW file
Then in the Processes for Current Source window, click View Behavioral Testbench
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Modelsim In ISE (FPGA)•RTL Simulation
•Functional Simulation•Does function match RTL Golden model
•Gate Level Simulation ( only gate delay)
•Gate Level Simulation ( gate delay + wire delay)
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Modelsim In ISE
TestBench type code
Simulation process
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Top Answer Records Hits
#15338: How do I compile simulation Models
#16233: BlockRAMCollision Errors
#10629: What are $setup and $hold violations
#15501: How do I install SmartModels?
#6537: How do I use the glbl.v file for Verilog?
#15969: Using the ASYNC_REG constraint
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CORE Generator
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What are Cores?
A core is a ready-made function that you can instantiate into your design as a “black box”Cores can range in complexity
Simple arithmetic operators, such as adders, accumulators, and multipliersSystem-level building blocks, including filters, transforms, and memoriesSpecialized functions, such as bus interfaces, controllers, and microprocessors
Some cores can be customized
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Sample Functions
LogiCORE solutionsDSP functions
• Time skew buffers, FIR filters, correlators
Math functions• Accumulators, adders, multipliers,
integrators, square rootMemories
• Pipelined delay elements, single and dual-port RAM
• Synchronous FIFOsPCI master and slave interfaces, PCI bridge
AllianceCORE solutionsPeripherals
• DMA controllers• Programmable interrupt controllers• UARTs
Communications and networking• ATM• Reed-Solomon encoders / decoders• T1 framers
Standard bus interfaces• PCMCIA, USB
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Invoking the CORE Generator System
From the Project Navigator, select Project → New SourceSelect IP (CoreGen & Architecture Wizard) and enter a filenameClick Next, then select the type of core
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Xilinx CORE Generator System GUI
Cores can be organized by function, vendor, or device family
Core type, version, device support, vendor, and status
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Core Customize Window
Parameters tab allows you to customize the core
Contact tab provides information about the vendor
Data sheet access
Web Links tab provides direct access to related Web pages
Core Overview tab provides version information and a brief functional description
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CORE Data Sheets
Performance expectations (not shown)
Features
Functionality
Pinout
Resource utilization
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Architecture Wizard
Architecture Wizard contains two wizards:
Clocking Wizard RocketIO Wizard
Double-click Create New Source
Select IP (CoreGen & Architecture Wizard), then click Next
• Expand Clocking and select desired function
• Expand I/O Interfacesand select RocketIO*
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DCM Wizard --General Setup Options
Select which pins are requiredDefine attributes:
Input Clock FrequencyCLKIN SourceDivide By ValueFeedback SourceFeedback ValueDuty Cycle CorrectionPhase Shift (DPS)
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DCM Wizard– DFS setting
Frequency synthesizerSelect M / D valueORSpecify frequency
“Calculate” button for jitterPeriod jitter is evaluated for CLKFX output
Note: This dialog appears only if the CLKFX output was selected
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Where Can I Learn More?
Xilinx IP Center http://www.xilinx.com/ipcenterSoftware updatesDownload new cores as they are released
Tech Tips on http://support.xilinx.comSoftware manuals: CORE Generator GuideDCM constraints: Online Software Manuals → Constraints GuideDCM architecture:
Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Detailed DescriptionVirtex-II, Virtex-II Pro, Spartan-3 User Guides → Design Considerations → DCM
DCM timing parameters: Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Electrical CharacteristicsVirtex-II, Virtex-II Pro, Spartan-3 Interactive Data Sheets →http://support.xilinx.com/applications/web_ds/index_top.htm
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