Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design
Spring 2014Spring 2014 Linear Programming – A Mathematical Linear Programming – A Mathematical
Optimization TechniqueOptimization TechniqueVishwani D. AgrawalVishwani D. Agrawal
James J. Danaher ProfessorJames J. Danaher Professor
ECE Department, Auburn UniversityECE Department, Auburn University
Auburn, AL 36849Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22
What is Linear ProgrammingWhat is Linear Programming Linear programming (LP) is a mathematical
method for selecting the best solution from the available solutions of a problem.
Method: State the problem and define variables whose
values will be determined. Develop a linear programming model:
Write the problem as an optimization formula (a linear expression to be minimized or maximized)
Write a set of linear constraints
An available LP solver (computer program) gives the values of variables.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 33
Types of LPsTypes of LPs
LP – all variables are real. ILP – all variables are integers. MILP – some variables are integers, others are
real. A reference:
S. I. Gass, An Illustrated Guide to Linear Programming, New York: Dover, 1990.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44
A Single-Variable ProblemA Single-Variable Problem
Consider variable x Problem: find the maximum value of x subject to
constraint, 0 ≤ x ≤ 15. Solution: x = 15.
0 15
Constraint satisfied
x
Solution x = 15
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55
Single Variable Problem (Cont.)Single Variable Problem (Cont.) Consider more complex constraints: Maximize x, subject to following constraints:
x ≥ 0 (1) 5x ≤ 75 (2) 6x ≤ 30 (3) x ≤ 10 (4)
0 5 10 15x (1)
(2)(3)
(4)All constraints
satisfied
Solution, x = 5
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66
A Two-Variable ProblemA Two-Variable Problem Manufacture of chairs and tables:
Resources available: Material: 400 boards of wood Labor: 450 man-hours
Profit: Chair: $45 Table: $80
Resources needed: Chair
5 boards of wood 10 man-hours
Table 20 boards of wood 15 man-hours
Problem: How many chairs and how many tables should be manufactured to maximize the total profit?
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77
Formulating Two-Variable ProblemFormulating Two-Variable Problem
Manufacture x1 chairs and x2 tables to maximize profit:
P = 45x1 + 80x2 dollars
Subject to given resource constraints: 400 boards of wood, 5x1 + 20x2 ≤ 400 (1)
450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2)
x1 ≥ 0 (3)
x2 ≥ 0 (4)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 88
Solution: Two-Variable ProblemSolution: Two-Variable Problem
Chairs, x1
Tab
les,
x2
(1)
(2)
0 10 20 30 40 50 60 70 80 90
40
30
20
10
0
(24, 14)
Profi
t increasing
decresing
P = 2200
P = 0
Best solution: 24 chairs, 14 tablesProfit = 45×24 + 80×14 = 2200 dollars
(3)(4)
Material constraint
Man-power constraint
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99
Change Profit of Chair to $64/UnitChange Profit of Chair to $64/Unit
Manufacture x1 chairs and x2 tables to maximize profit:
P = 64x1 + 80x2 dollars
Subject to given resource constraints: 400 boards of wood, 5x1 + 20x2 ≤ 400 (1)
450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2)
x1 ≥ 0 (3)
x2 ≥ 0 (4)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010
Solution: $64 Profit/ChairSolution: $64 Profit/Chair
Chairs, x1
Tab
les,
x2
(1)
(2)
Profi
t increasing
decresing
P = 2880
P = 0
Best solution: 45 chairs, 0 tablesProfit = 64×45 + 80×0 = 2880 dollars
0 10 20 30 40 50 60 70 80 90
(24, 14)
40
30
20
10
0
(3)(4)
Material constraint
Man-power constraint
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1111
A Dual ProblemA Dual Problem Explore an alternative. Questions:
Should we make tables and chairs? Or, auction off the available resources?
To answer this question we need to know: What is the minimum price for the resources that will
provide us with same amount of revenue from sale as the profits from tables and chairs?
This is the dual of the original problem.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1212
Formulating the Dual ProblemFormulating the Dual Problem Revenue received by selling off resources:
For each board, w1
For each man-hour, w2
Minimize 400w1 + 450w2
Subject to constraints: 5w1 + 10w2 ≥ 45
20w1 + 15w2 ≥ 80
w1 ≥ 0
w2 ≥ 0
Resources:Material: 400 boards Labor: 450 man-hrs
Profit:Chair: $45Table: $80
Resources needed:Chair
5 boards of wood10 man-hours
Table20 boards of wood15 man-hours
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1313
The Duality TheoremThe Duality Theorem
If the primal has a finite optimum solution, so If the primal has a finite optimum solution, so does the dual, and the optimum values of the does the dual, and the optimum values of the objective functions are equal.objective functions are equal.
Reference:Reference:
G. Strang, G. Strang, Linear Algebra and Its ApplicationsLinear Algebra and Its Applications. . Fort Worth: Harcourt Brace Javanovich College Fort Worth: Harcourt Brace Javanovich College Publishers, third edition, 1988.Publishers, third edition, 1988.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1414
Primal-Dual ProblemsPrimal-Dual Problems Primal problem
Fixed resources Maximize profit
Variables: x1 (number of chairs) x2 (number of tables)
Maximize profit 45x1+80x2
Subject to: 5x1 + 20x2 ≤ 400 10x1 + 15x2 ≤ 450 x1 ≥ 0 x2 ≥ 0
Solution: x1 = 24 chairs, x2 = 14 tables Profit = $2200
Dual Problem Fixed profit Minimize value
Variables: w1 ($ value/board of wood) w2 ($ value/man-hour)
Minimize value 400w1+450w2
Subject to: 5w1 + 10w2 ≥ 45 20w1 + 15w2 ≥ 80 w1 ≥ 0 w2 ≥ 0
Solution: w1 = $1, w2 = $4 value = $2200
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1515
LP for LP for nn Variables Variables n
minimize Σ cj xj Objective functionj =1
n
subject to Σ aij xj ≤ bi, i = 1, 2, . . ., m j =1
n
Σ cij xj = di, i = 1, 2, . . ., p j =1
Variables: xjConstants: cj, aij, bi, cij, di
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1616
Algorithms for Solving LPAlgorithms for Solving LP
Simplex methodSimplex method G. B. Dantzig, G. B. Dantzig, Linear Programming and ExtensionLinear Programming and Extension, Princeton, New , Princeton, New
Jersey, Princeton University Press, 1963.Jersey, Princeton University Press, 1963. Ellipsoid methodEllipsoid method
L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” Soviet Math. DoklSoviet Math. Dokl., vol. 20, pp. 191-194, 1984.., vol. 20, pp. 191-194, 1984.
Interior-point methodInterior-point method N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear
Programming,” Programming,” CombinatoricaCombinatorica, vol. 4, pp. 373-395, 1984., vol. 4, pp. 373-395, 1984. Course website of Prof. Lieven Vandenberghe (UCLA), Course website of Prof. Lieven Vandenberghe (UCLA),
http://www.ee.ucla.edu/ee236a/ee236a.html
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1717
Basic Ideas of Solution methodsBasic Ideas of Solution methods
Constraints
Extreme points
Objective function Constraints
Extreme points
Objective function
Simplex: search on extreme points.Complexity: polynomial in n, number of variables
Interior-point methods: Successivelyiterate with interior spaces of analytic convex boundaries.Complexity: O(n3.5L), L = no. of int. values
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1818
Integer Linear Programming (ILP)Integer Linear Programming (ILP)
Variables are integers.Variables are integers. Complexity is exponential – higher than LP.Complexity is exponential – higher than LP. LP relaxationLP relaxation
Convert all variables to real, preserve ranges.Convert all variables to real, preserve ranges. LP solution provides guidance.LP solution provides guidance. Rounding LP solution can provide a non-optimal Rounding LP solution can provide a non-optimal
solution.solution.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1919
Traveling Salesperson Problem (TSP)Traveling Salesperson Problem (TSP)
1
32
5
412
27
18
10
5
20
1215
19
6
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2020
Solving TSP: Five CitiesSolving TSP: Five CitiesDistances (dij) in miles (symmetric TSP, general TSP is asymmetric)
CityCity j=1j=1 j=2j=2 j=3j=3 j=4j=4 j=5j=5
i=1i=1 00 1818 1010 1212 2727
i=2i=2 1818 00 55 1212 2020
i=3i=3 1010 55 00 1515 1919
i=4i=4 1212 1212 1515 00 66
i=5i=5 2727 2020 1919 66 00
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2121
Search Space: No. of ToursSearch Space: No. of Tours
Asymmetric TSP toursAsymmetric TSP tours Five-city problem: 4 Five-city problem: 4 × 3 × 2 × 1 = 24 tours× 3 × 2 × 1 = 24 tours Ten-city problem: 362,880 toursTen-city problem: 362,880 tours 15-city problem: 87,178,291,200 tours15-city problem: 87,178,291,200 tours 50-city problem: 49! = 6.08×1050-city problem: 49! = 6.08×1062 tours tours
Time for enumerative search assuming 1 Time for enumerative search assuming 1 μμs per tour s per tour evaluationevaluation == 1.93×101.93×1055 years years
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2222
A Greedy Heuristic SolutionA Greedy Heuristic Solution
City j = 1 j = 2 j = 3 j = 4 j = 5
i = 1
(start)0 18 10 12 27
i = 2 18 0 5 12 20
i = 3 10 5 0 15 19
i = 4 12 12 15 0 6
i = 5 27 20 19 6 0
Tour length = 10 + 5 + 12 + 6 + 27 = 60 miles (non-optimal)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2323
ILP Variables, Constants and ConstraintsILP Variables, Constants and Constraints
1
32
5
4 d14 = 12
d15 = 27
d12 = 18
d13 = 10
x14 ε [0,1]
x15 ε [0,1]
x12 ε [0,1]
x13 ε [0,1]
x12 + x13 + x14 + x15 = 1 four other similar equations
Integer variables:xij = 1, travel i to jxij = 0, do not travel i to j
Real constants:dij = distance from i to j
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2424
Objective Function and ILP SolutionObjective Function and ILP Solution 5 i - 1
Minimize ∑ ∑ xij × dij i = 1 j = 1
xijxij j=1j=1 22 33 44 55
i=1i=1 00 00 11 00 00
22 11 00 00 00 00
33 00 11 00 00 00
44 00 00 00 00 11
55 00 00 00 11 00
∑ xij = 1 and xii = 0 for all i j ≠ i
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2525
ILP SolutionILP Solution
1
32
5
4
d13 = 10
d45 = 6
Total length = 45 but not a single tour
d54 = 6
d21 = 18
d32 = 5
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2626
Additional Constraints for Single TourAdditional Constraints for Single Tour
Following constraints prevent split tours. For any Following constraints prevent split tours. For any subset S of cities, the tour must enter and exit subset S of cities, the tour must enter and exit that subset:that subset:
∑ xij ≥ 2 for all S, |S| < 5i ε S j ε S
Any subset
Remaining set At least two
arrows must crossthis boundary.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2727
ILP SolutionILP Solution
1
32
5
4
d13 = 10
d41 = 12
Total length = 53
d54 = 6
d25 = 20
d32 = 5
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2828
ILP Example: Test MinimizationILP Example: Test Minimization A combinational circuit has A combinational circuit has nn test vectors that detect test vectors that detect mm
faults. Each vector detects a subset of faults. Find the faults. Each vector detects a subset of faults. Find the smallest subset of test vectors such that each fault is smallest subset of test vectors such that each fault is detected by at least detected by at least NN vectors. vectors.
Simulate vectors without dropping faults.Simulate vectors without dropping faults.
T1 T2 . . Tj . . . Tn
F1 1 0 0 1 1 0 1 0 0
F2 0 0 1 1 0 0 0 1 0
. . . . . . . . . .
. . . . . . . . . .
Fj 1 0 0 1 1 0 0 1 1
. . . . . . . . . .
Fm 0 1 1 1 0 0 0 0 1
Fa
ults
Test vectors
fij = 1, if test Tidetects fault Fj
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2929
Test Minimization by ILPTest Minimization by ILP
n
minimize Σ ti Objective function i=1
n
subject to Σ fij ti ≥ N, j = 1, 2, . . ., mi=1
Construct an ILP model:1.Assign an integer variable ti ε [0,1] to ith test vector such that ti = 1, if we select ti, otherwise ti= 0.
2.Define an integer constant fij ε [0,1] such that fij = 1, if ith vector detects jth fault, otherwise fij = 0. Values of constants fij are determined by fault simulation.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3030
N-Detect Tests (N-Detect Tests (NN = 5) = 5)
CircuitCircuit Unoptimized vectorsUnoptimized vectorsILP (exact)ILP (exact)
Minimum vectorsMinimum vectors CPU sCPU s
c432c432 608608 197197 1.01.0
c499c499 379379 260260 2.32.3
c880c880 1,0231,023 127127 881.8881.8
c1355c1355 755755 420420 4.44.4
c1908c1908 1,0551,055 543543 6.96.9
c2670c2670 959959 477477 7.27.2
c3540c3540 1,9711,971 471471 20008.520008.5
c5315c5315 1,0791,079 376376 40.740.7
c6288c6288 243243 5757 34740.034740.0
c7552c7552 2,1652,165 841841 114.3114.3
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3131
Why ILP Solution is Exponential?Why ILP Solution is Exponential?LP solutionfound inpolynomial time(bound on ILPsolution)
Must try all2n roundoffpoints
First variable
Se
con
d va
ria
ble
Constraints
Objective(maximize)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3232
Characteristics of ILPCharacteristics of ILP Worst-case complexity is exponential in number of Worst-case complexity is exponential in number of
variables.variables. Linear programming (LP) relaxation, where integer Linear programming (LP) relaxation, where integer
variables are treated as real, gives a lower bound on the variables are treated as real, gives a lower bound on the objective function.objective function.
Recursive roundingRecursive rounding of relaxed LP solution to nearest of relaxed LP solution to nearest integers gives an approximate solution to the ILP integers gives an approximate solution to the ILP problem.problem. K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity
Algorithm for Minimizing Algorithm for Minimizing NN-Detect Tests,” -Detect Tests,” Proc. 20Proc. 20thth International International Conf. VLSI DesignConf. VLSI Design, January 2007, pp. 492-497., January 2007, pp. 492-497.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3333
Recursive Rounding AlgorithmRecursive Rounding Algorithm
1.1. Obtain a relaxed LP solution. Obtain a relaxed LP solution. Stop if each if each variable in the solution is an integer.variable in the solution is an integer.
2.2. Round the variable closest to an integer.Round the variable closest to an integer.
3.3. Remove any constraints that are now Remove any constraints that are now unconditionally satisfied.unconditionally satisfied.
4.4. Go to step 1.Go to step 1.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3434
Complexity of ApproximationComplexity of Approximation Recursive rounding:Recursive rounding:
ILP is transformed into k LPs with progressively reducing ILP is transformed into k LPs with progressively reducing number of variables, where k is the size of the solution.number of variables, where k is the size of the solution.
A solution that satisfies all constraints is guaranteed; this A solution that satisfies all constraints is guaranteed; this solution is often close to optimal.solution is often close to optimal.
Number of LPs, k, is the size of the final solution, i.e., the Number of LPs, k, is the size of the final solution, i.e., the number of non-zero variables in the test minimization number of non-zero variables in the test minimization problem.problem.
Recursive rounding complexity is k × O(nRecursive rounding complexity is k × O(npp), where k ≤ n, ), where k ≤ n, n is number of variables.n is number of variables.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3535
Four-Bit ALU CircuitFour-Bit ALU Circuit
Initial vectorsInitial vectorsILPILP Recursive roundingRecursive rounding
VectorsVectors CPU sCPU s VectorsVectors CPU sCPU s
285285 1414 0.650.65 1414 0.420.42
400400 1313 1.071.07 1313 1.001.00
500500 1212 4.384.38 1313 3.003.00
1,0001,000 1212 4.174.17 1212 3.003.00
5,0005,000 1212 12.9512.95 1212 9.009.00
10,00010,000 1212 34.6134.61 1212 17.017.0
16,384 = 216,384 = 214 14
(exhaustive set)(exhaustive set)1212 87.4787.47 1212 37.037.0
14 inputs, 8 outputs
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3636
ILP vs. Recursive RoundingILP vs. Recursive Rounding
0 5,000 10,000 15,000 Vectors
100
75
50
25
0
ILP
Recursive Rounding
CPU
s
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3737
N-Detect Tests (N-Detect Tests (N N = 5)= 5)
CircuitCircuit Unoptimized Unoptimized vectorsvectors
Relaxed LP/Recur. Relaxed LP/Recur. roundingrounding ILP (exact)ILP (exact)
Lower Lower boundbound
Min. Min. vectorsvectors CPU sCPU s Min. Min.
vectorsvectors CPU sCPU s
c432c432 608608 196.38196.38 197197 1.01.0 197197 1.01.0
c499c499 379379 260.00260.00 260260 1.21.2 260260 2.32.3
c880c880 1,0231,023 125.97125.97 128128 14.014.0 127127 881.8881.8
c1355c1355 755755 420.00420.00 420420 3.23.2 420420 4.44.4
c1908c1908 1,0551,055 543.00543.00 543543 4.64.6 543543 6.96.9
c2670c2670 959959 477.00477.00 477477 4.74.7 477477 7.27.2
c3540c3540 1,9711,971 467.25467.25 477477 72.072.0 471471 20008.520008.5
c5315c5315 1,0791,079 374.33374.33 377377 18.018.0 376376 40.740.7
c6288c6288 243243 52.5252.52 5757 39.039.0 5757 34740.034740.0
c7552c7552 2,1652,165 841.00841.00 841841 52.052.0 841841 114.3114.3
A Primal-Dual Solution (A Primal-Dual Solution (NN = 1) = 1)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3838
Circuit Name
Lower bound
on vectors
Recursive LP minimization Primal-dual minimization
Unopt. vectors
LPCPU s
Minimized vectors
Unopt. vectors
TotalCPU s
Minimized vectors
c432 27 608 2.00 36 983 5.52 31c499 52 379 1.00 52 221 1.35 52c880 13 1023 31.00 28 1008 227.21 25c1355 84 755 5.00 84 507 1.95 84c1908 106 1055 8.00 107 728 2.50 107c2670 44 959 9.00 84 1039 17.41 79c3540 78 1971 197.00 105 2042 276.91 95c5315 37 1079 464.00 72 1117 524.53 67c6288 6 243 78.00 18 258 218.9 17c7552 65 2165 151.00 145 2016 71.21 139
M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test Generation Problem,” Proc. 12th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp. 269-279.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3939
Finding LP/ILP SolversFinding LP/ILP Solvers
R. Fourer, D. M. Gay and B. W. Kernighan, R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling AMPL: A Modeling Language for Mathematical ProgrammingLanguage for Mathematical Programming, South San Francisco, , South San Francisco, California: Scientific Press, 1993. Several of programs described in California: Scientific Press, 1993. Several of programs described in this book are available to Auburn users.this book are available to Auburn users.
B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and A Guide to MATLAB for Beginners and Experienced UsersExperienced Users, Cambridge University Press, 2006., Cambridge University Press, 2006.
Search the web. Many programs with small number of variables can Search the web. Many programs with small number of variables can be downloaded free.be downloaded free.
A Circuit Optimization ProblemA Circuit Optimization Problem
Given:Given: Circuit netlistCircuit netlist Cell library with multiple versions for each cellCell library with multiple versions for each cell
Select cell versions to optimize a specified Select cell versions to optimize a specified characteristic of the circuit. Typical characteristic of the circuit. Typical characteristics are:characteristics are: AreaArea PowerPower DelayDelay
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4040
Example: Cell(X), X = 0 or 1Example: Cell(X), X = 0 or 1
X: an integer variable for each gate.X: an integer variable for each gate. X = 0X = 0
Delay = dDelay = d Power = 3 Power = 3 × × pp
X = 1X = 1 Delay = 2 Delay = 2 × × dd Power = 0.5 Power = 0.5 × × pp
Cell delay = (1 – X) d + 2 X dCell delay = (1 – X) d + 2 X d Power = 3(1 – X) p + 0.5 X pPower = 3(1 – X) p + 0.5 X p
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4141
ILP Model: Minimum Power & DelayILP Model: Minimum Power & Delay
Ti = signal arrival time at ith input; Ti = 0 for all PIsTi = signal arrival time at ith input; Ti = 0 for all PIs Tk = signal arrival time at cell outputTk = signal arrival time at cell output Tk Tk ≥ Ti + ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all i(1 – Xk) dk + 2 Xk dk, for all i
Where, Where, dk = nominal delay of gatedk = nominal delay of gate
Xk = 0 or 1, specifies version of cellXk = 0 or 1, specifies version of cell
Minimize Minimize αα TPO + ∑ [3(1 – Xk) pk + 0.5 Xk pk] TPO + ∑ [3(1 – Xk) pk + 0.5 Xk pk] αα is constant is constant
all kall k
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4242
kth Cell Arrival time = Tk
Arrival time = T1
Ti
Given Clock SpecificationGiven Clock Specification Tj = 0, for all primary inputs jTj = 0, for all primary inputs j Tk Tk ≤ clock period, for all primary outputs k≤ clock period, for all primary outputs k Tk Tk ≥ Ti + ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all gates k with input i(1 – Xk) dk + 2 Xk dk, for all gates k with input i
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4343
Combinational Logic
Re
gis
ter
Re
gis
ter
Clock
Minimum Power DesignMinimum Power Design
MinimizeMinimize ∑∑ 3(1 – Xk) pk + 0.5 Xk pk 3(1 – Xk) pk + 0.5 Xk pk
all kall k
wherewhere pk = nominal power consumption of pk = nominal power consumption of kth cellkth cell
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4444
Logic MinimizationLogic Minimization
Consider a four-variable function, {2,4,6,8,9,10,12,13,15}Consider a four-variable function, {2,4,6,8,9,10,12,13,15} Karnaugh map shows prime implicants (PI) found by Karnaugh map shows prime implicants (PI) found by
Quine-McCluskey procedure.Quine-McCluskey procedure. Find the minimum number of Pis to cover all minterms.Find the minimum number of Pis to cover all minterms.
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4545
1 1 1
1 1
1
1 1 1
A
B
C
DEPI’s
Non-EPI’s Non-EPI’s
Select a Minimal Set of PI’sSelect a Minimal Set of PI’sCovered by EPI → x x x x x
Minterm → 2 4 6 8 9 10 12 13 15
PI1 x x x x
PI2 x x
PI3 x x
PI4 x x
PI5 x x
PI6 x x
PI7 x x
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4646
1. First select essential prime implicants (EPIs).2. Cover remaining minterms with smallest number of prime
implicants (Pis).
Cover Remaining MintermsCover Remaining MintermsRemaining minterms → 2 4 6 10
PI2 x x
PI3 x x
PI4 x x
PI5 x
PI6 x
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4747
Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select PIk; xk = 0, do not select PIk.Minimize k xk, subject to following constraints:
x2 + x3 ≥ 1 (cover minterm 2)x4 + x5 ≥ 1 (cover minterm 4)x2 + x4 ≥ 1 (cover minterm 6)x3 + x6 ≥ 1 (cover minterm 10)
A solution is x3 = x4 = 1, x2 = x5 = x6 = 0
Minimized FunctionMinimized Function
F(A,B,C,D) =F(A,B,C,D) = PI1PI1 + PI3 + PI4 + + PI3 + PI4 + PI7PI7
== AACC + +B CB CD D ++A BA BD D + + A B DA B D
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4848
1 1 1
1 1
1
1 1 1
A
B
C
DEPI’s in MSOP
Selected PIs Pis not selected
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4949
Comb. Circuit Power OptimizationComb. Circuit Power Optimization
Given a set of test vectorsGiven a set of test vectors Reorder vectors to minimize the number of Reorder vectors to minimize the number of
transitions at primary inputstransitions at primary inputs
Combinational circuit(tested by exhaustive
vectors)
010101010011001100001111
01111000Rearranged vector set 00110011 produces 7 transitions
00011110
11 transitions
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 5050
Reducing Comb. Test Power Reducing Comb. Test Power
1 1 0 0 01 0 1 0 01 0 1 0 11 0 1 1 1
V1 V2 V3
V4 V5
3 4
1
3 223
2
1
1
Original tests:V1 V2 V3 V4 V5
10 input transitions
Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once.But, we need an open loop solution.
Reordered tests:V1 V3 V5 V4 V21 0 0 0 11 1 0 0 01 1 1 0 01 1 1 1 0
5 input transitions
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 5151
Open-Loop TSP Open-Loop TSP
Add a node V0 at distance 0 from all other nodes.Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph.Solve TSP for the new graph. Delete V0 from the solution.Delete V0 from the solution.
V1 V2 V3
V4 V5
3 4
1
32
23
2
1
1V0
0
00
0
0
Combinational Vector OrderingCombinational Vector Ordering See: P. Wray, “See: P. Wray, “Minimize test power for benchmark circuit c6288 by Minimize test power for benchmark circuit c6288 by
optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring 2009, 2009, www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/
TSP has exponential complexity; good heuristics are available.TSP has exponential complexity; good heuristics are available. For other extensions:For other extensions:
V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, “Techniques for Minimizing Power Dissipation in Scan and “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” Combinational Circuits During Test Application,” IEEE Trans. CADIEEE Trans. CAD, , vol. 17, no. 12, pp. 1325-1333, Dec. 1998.vol. 17, no. 12, pp. 1325-1333, Dec. 1998.
Typical average power saving:Typical average power saving: 30-50%30-50% 50-60% with vector repetition (to satisfy peak power)50-60% with vector repetition (to satisfy peak power) ? ? ? With inserted vectors (to satisfy peak power)? ? ? With inserted vectors (to satisfy peak power)
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 5252
Spring 2014, Feb 26 . . .Spring 2014, Feb 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 5353
Traveling Salesperson ProblemTraveling Salesperson Problem A. V. Aho, J. E. Hopcroft anf J. D. Ullman, A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Data
Structures and AlgorithmsStructures and Algorithms, Reading, , Reading, Massachusetts: Addison-Wesley, 1983.Massachusetts: Addison-Wesley, 1983.
E. Horowitz and S. Sahni, E. Horowitz and S. Sahni, Fundamentals of Fundamentals of Computer AlgorithmsComputer Algorithms, Computer Science Press, , Computer Science Press, 1984.1984.
B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, R. Coombes, J. E. Osborn and G. J. Stuck, A A Guide to MATLAB for Beginners and Guide to MATLAB for Beginners and Experienced UsersExperienced Users, Cambridge University , Cambridge University Press, 2006.Press, 2006.
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