Virtual Platforms for Memory
Controller Design Space
ExplorationMatthias Jung, Christian Weis, Norbert WehnUniversity of Kaiserslautern, Germany
Microelectronic
Systems Design
64B
Standard Memory System
msms
HDD/SSDDRAM
L3 shared cache 8-12MB
.
Mem
ory
Con
trolle
r: 3
Channels
L2 private cache 256KB
L1 private cache 64KB
CORE
16B
ns
SRAM
Pin limitation
due to package
Power hungry I/O transceiver
s
Bandwidth Requirements Memory Wall
512B
Microelectronic
Systems Design
3D Stacked Wide I/O DRAM
• Stacked DRAM dies
• TSV connections
• Multiple Channels
Increasing bandwidth demand
Higher available bandwidth
1 or 2Channel DDR3
Memory controllerbottleneck
New generation of Memory Controllers is required
3D stacked DRAM
MPSoC
Microelectronic
Systems Design
Design Space Exploration with Virtual Platforms• Huge design space of 3D-DRAM controller• Flexible and cycle approx. models are needed for fast
investigation• RTL simulation is too slow for system level analysis
TLM based virtual platforms with Synopsys Platform Architect Speedup of TLM models up to 377x compared to CA1
Simulating in seconds instead of hours
1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, in Proc. HiPEAC Conference 2013, Berlin.
Microelectronic
Systems Design
Special TLM DRAM Protocol1
• Application specific phases with
DECLARE_EXTENDED_PHASE()
• Phases derived from DRAM commands (Jedec Wide I/O
Standard)
• DRAM commands: ACT, PRE, RD, WR, REFA …Example:
1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, HiPEAC, 2013, Berlin.
Microelectronic
Systems DesignExperiments and Results
• TLM model was compared with cycle accurate SystemC implementation
• Tested with Mediabench and CHStone Benchmark traces
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de1.000 s
10.000 s
100.000 s
1000.000 s
10000.000 s
Runtimes (Log-Scale)
CA ModelTLM Model
Speedup up to two magnitudes!
1h
41m
42s
Microelectronic
Systems Design
Power Modeling of 3D-DRAM with TLM2.02
Two parts of power consumption:
1. Background Power2. Command Power
DRAM Power states accounted with TLM phases
2 M. Jung et al. Power Modelling of 3D-Stacked Memories with TLM2.0, SNUG 2013, Munich
ACT WR PRE ACT RD WR PRE
I
t
Microelectronic
Systems Design
Results (Power Simulation)
chstone-gsm
chstone-jpeg
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media-jpegencode
mediabench-mpeg2decode
0 10 20 30 40 50 60 70 80
CA SystemC
DRAMPower
TLM2.0 Model
mW
• TLM model was compared with a cycle accurate SystemC implementation and the standalone power simulator DRAMPower3
• Tested with Mediabench and CHStone Benchmark traces
Deviation max 5%
to referencemodels
3 www.drampower.info
Microelectronic
Systems Design
Current Work: Thermal Simulation
• Co-simulation with 3D-ICE Simulator3
• Traces will be generated from GEM54
• Closed Loop Control
3 http://esl.epfl.ch/3d-ice.html 4 http://www.gem5.org/
Microelectronic
Systems Design
Conclusion
• 3D stacked DRAMs are the future technology
• Virtual platform for DSE of new multi-channel Wide I/O DRAM controllers are mandatory
• DRAM specific TLM protocol was introduced(can be used for any kind of DRAM)
• Precise Power model presented
• Early checkpoint for SW implementations
• Current and Future Work: Advanced scheduling and arbitration algorithms
Microelectronic
Systems DesignThank
you!
Visit my Poster!
http://www.uni-kl.de/3d-dram
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