Kuhn - 2009 2nd International CMOS Variability Conference - London1
Variation in 45nm and Implications for 32nm and Beyond
Kelin J. KuhnIntel Fellow
Director of Advanced Device Technology
Kuhn - 2009 2nd International CMOS Variability Conference - London2
AGENDATechnology scaling
I. Physical Variation Sources and Mitigation
II.
Measurements, results and interpretation II.
Next generation challengesClosing thoughts
1a
Kuhn - 2009 2nd International CMOS Variability Conference - London3
Technology Scaling
1b
Kuhn - 2009 2nd International CMOS Variability Conference - London4
Lithography Scaling LimitationsFrom Broers
[1] IEDM Plenary Session 1980
1c
1980: Optical Lithography Limit
~ 400nm
Kuhn - 2009 2nd International CMOS Variability Conference - London5
Transistor Scaling LimitationsFrom Meindl
[2] IEDM Plenary Session 1983
1d
1983: Transistor architecture limit
200-400nm (SCE)
Kuhn - 2009 2nd International CMOS Variability Conference - London6
Transistor Scaling LimitationsFrom Heilmeier
[4] IEDM Plenary Session 1984
1984: Transistor architecture limit300-500nm (laundry list of reasons…)
1e
Kuhn - 2009 2nd International CMOS Variability Conference - London7
How small is a 32nm memory cell?
K. Kuhn 2007
Blood cell: Elec. Mic. Fac. (NCI-Frederick) 2007
32nm SRAM Cell: 0.171 um2
Small enough that a 2008 32nm SRAM cell is dwarfed by a human redblood
cell
~300nm
~500nm
1983-84 limits on gate size, are commensurate with the dimensions
of 2008’s entire 32nm SRAM cell!
2
Kuhn - 2009 2nd International CMOS Variability Conference - London8
1980 SRAM Cell: 1700 um2 32nm SRAM Cell: 0.171 um2
M. Bohr 2007
Small enough that a 2008 32nm SRAM cell is dwarfed by a 1980 SRAM cell CONTACT
How small is a 32nm memory cell?
10000X
3
Kuhn - 2009 2nd International CMOS Variability Conference - London9
Small enough that a 2008 32nm SRAM cell is dwarfed by a 1980 SRAM cell CONTACT
Contact 1978
32nm SRAM Cell 2008
1 m
How small is a 32nm memory cell?
M. Bohr, ISCC, 2009 4
Kuhn - 2009 2nd International CMOS Variability Conference - London10
Atomic dimensions are now routine
5
Kuhn - 2009 2nd International CMOS Variability Conference - London11
Part I: Physical Variation
Sources and Mitigation
6
Kuhn - 2009 2nd International CMOS Variability Conference - London12
Part I –
Physical Variation Sources and Mitigation
Polish
Patterning
Strain
7
Kuhn - 2009 2nd International CMOS Variability Conference - London13
Part I –
Physical Variation Sources and Mitigation
Polish
Patterning
Strain
8
Kuhn - 2009 2nd International CMOS Variability Conference - London14
How small is a 45nm transistor?
•
5.5X smaller than the 193nm light that prints it•
~15X smaller than visible green light
K. Kuhn 2007 9
Kuhn - 2009 2nd International CMOS Variability Conference - London15
Etch
Design
OPC/RET Trim mask Reticle
manufacturing
Phase mask
Exposure
(magnified 25,000X)
Trim mask data
Phase mask data
Putting it all together for the gate layer of a
65nm MPU
10 C. KenyonTOK conf.Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London16
Etch
Design
OPC/RET Trim mask Reticle
manufacturing
Phase mask
Exposure
(magnified 25,000X)
Trim mask data
Phase mask data
Putting it all together for the gate layer of a
65nm MPU
11 C. KenyonTOK conf.Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London17
Optical Proximity Correction (OPC) As a Resolution Enhancement Technique
Contour prediction –
no OPC Contour prediction –
with OPC
SEM Image –
no OPC SEM Image –
with OPC
K. Wells-Kilpatrick: 200712
Kuhn - 2009 2nd International CMOS Variability Conference - London18
45nm: OPC as a Variation Management Technique
Top-down resist CD meets spec, but poor contrast leads to poor resist profile which gets transferred to metal pattern after etch, resulting in shorting marginality
Computational lithography solutionK. Kuhn, IEDM 2007
Kuhn - 2009 2nd International CMOS Variability Conference - London19
Etch
Design
OPC/RET Trim mask Reticle
manufacturing
Phase mask
Exposure
(magnified 25,000X)
Trim mask data
Phase mask data
Putting it all together for the gate layer of a
65nm MPU
14 C. KenyonTOK conf.Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London20
MEEF Mask Error Enhancement Factor
•
MEEF is a scaling factor that causes certain layout geometries to exhibit a greater sensitivity to mask dimension tolerances.
•
Any dimensional error in the mask is magnified on the wafer by the MEEF value.
•
Depending on the value of the mask error and the lithography exposure/focus conditions the final printed pattern can be either larger or smaller.
Wwafer
= MEEF * Wmask
15
Kuhn - 2009 2nd International CMOS Variability Conference - London21
MEEF Impact on Ze Error
Ze error can be eitherpositive or negative
YellowYellow: DCCD contour after OPCGreen: with -3.375 nm mask making errorRed: with 3.375 nm mask making error
65nm Simulation
MEEF = 8.4
Notch width = 120nmNotch height = 250nm
16
Kuhn - 2009 2nd International CMOS Variability Conference - London22
MEEF and Historical gate CD vs. pitch
Low MEEF requires targeting in the “flat”
portion of CD vs. pitch Process innovations continue this trend in the 32nm node
1262 CD vs. Pitch
50
60
70
80
90
100
110
120
100 200 300 400 500 600 700 800 900 1000
Pitch (nm)
CD
(nm
)C
D (n
m)
90nm node 1264 PSM CD vs. Pitch
30
40
50
60
70
80
90
100 200 300 400 500 600
Pitch (nm)
CD
(nm
)C
D (n
m)
65nm node
50 100 150 200 250 300 350 400
Pitch (nm)
CD (n
m)
CD
(nm
)
45nm node
1260 CD vs. Pitch
100
110
120
130
140
150
160
170
200 300 400 500 600 700 800 900 1000
Pitch (nm)
CD
(nm
)C
D (n
m)
130nm node
Contacted gate pitch
1268 PSM CD vs. Pitch
40
45
50
55
60
65
70
80 100 120 140 160 180
Pitch (nm)
CD
(nm
)
32nm node
CD
(nm
)
193nm; APSM; model-
based OPC248nm; OAI; model-
based OPC193nm; OAI; model-
based OPC
193nm; APSM; model-
based OPC
double patterning193nm; immersion; APSM; model-
based OPC; double patterning; polarization
C. KenyonTOK conf.Dec. 2008
17
Kuhn - 2009 2nd International CMOS Variability Conference - London23
Etch
Design
OPC/RET Trim mask Reticle
manufacturing
Phase mask
Exposure
(magnified 25,000X)
Trim mask data
Phase mask data
Putting it all together for the gate layer of a
65nm MPU
18 C. KenyonTOK conf.Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London24
FLARE•
Flare is unwanted scattered light arriving at the wafer
•
Flare is caused by interactions that force the light to travel in a "non-ray trace" direction.
•
Flare is both a function of local environment around a feature (short range flare) and the total amount of energy going through the lens (long range flare).
19
Kuhn - 2009 2nd International CMOS Variability Conference - London25
Impact of flare on gate CDs
•
During 65nm process development, large CD deviations were observed for structures having identical pitch and reticle CD due to flare
•
Gates only 500m away from one another could be >5nm different in CD
All structures have identical reticle CD and pitch
Moderate chrome density
Low chrome density
1x09
0a D
CC
D
63
64
65
66
67
68
69
70
71
72
73
74
DV Near Etest E-Test FREA Nested DV Nested Metro
Structure
1nm
CD
(nm
)
High chrome density
C. KenyonTOK conf.Dec. 2008
20
Kuhn - 2009 2nd International CMOS Variability Conference - London26
Development effort produced an algorithm capable of scanning designs and binning regions by local chrome fraction
Binning algorithm is combined with flare-calibrated OPC model
56.0 – 63.0
49.0 - 56.0
42.0 – 49.0
35.0 – 42.0
28.0 – 35.0
21.0 – 28.0
14.0 – 21.0
7.0 – 14.0
0.0 – 7.0
Color Code
Chrome Fraction56.0 – 63.0
49.0 - 56.0
42.0 – 49.0
35.0 – 42.0
28.0 – 35.0
21.0 – 28.0
14.0 – 21.0
7.0 – 14.0
0.0 – 7.0
Color Code
Chrome Fraction
Flare Variation Improvement with OPC
C. Kenyon, TOK conf., Dec. 2008 21
Kuhn - 2009 2nd International CMOS Variability Conference - London27
Etch
Design
OPC/RET Trim mask Reticle
manufacturing
Phase mask
Exposure
(magnified 25,000X)
Trim mask data
Phase mask data
Putting it all together for the gate layer of a
65nm MPU
22 C. KenyonTOK conf.Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London28
45nm highlights role of lithography/etch in resolving LER/LWR
K. Kuhn, ITJ, 2008
Original
Improvements B,C
Improvement A
Final after improvements A,B,C
23
Kuhn - 2009 2nd International CMOS Variability Conference - London29
Gate CD variation improvements with technology scaling
0.1
1
10
130nm336
90nm260
65nm220
45nm160
32nm112.5
LOG
(Var
iatio
n no
rmal
ized
to 1
30nm
WIW-total TOTAL
WID-total0.7X
Critical to management of variation is the ability to deliver a 0.7X gate CD variation improvement in each generation
enabled by continuous process technology improvements
Technology Trend Systematic Gate CD Lithography Variation
GENERATIONGATE PITCH
24
Kuhn - 2009 2nd International CMOS Variability Conference - London30
Part I –
Physical Variation Sources and Mitigation
Polish
Patterning
Strain
25
Kuhn - 2009 2nd International CMOS Variability Conference - London31
CMP Integration at 45 nm –
HiK
Metal Gate
First Generation HiK
–
Replacement Metal GateThree critical CMP operations in the FE
K.Mistry et al., IEDM (2007)C.Auth et al. VLSI Symp, (2008)J. Steigerwald, IEDM (2008)J. Steigerwald, IEDM (2008)
STI deposition and polish
Wells and VT implants
ALD deposition of high-k gate dielectric
Polysilicon
deposition and gate patterning
S/D extensions, spacer, Si recess and SiGe
deposition
S/D formation, Ni silicidation, ILD0 deposition
Poly Opening Polish, Poly removal
PMOS workfunction
metal deposition
Metal gate patterning, NMOS WF metal deposition
Metal gate fill and polish, ESL deposition
STI STI CMPCMP
MGD MGD CMPCMP
POP POP CMPCMP
26
Kuhn - 2009 2nd International CMOS Variability Conference - London32
CMP Integration at 45 nm –
HiK
Metal Gate
First Generation HiK
–
Replacement Metal GateThree critical CMP operations in the FE
K.Mistry et al., IEDM (2007)C.Auth et al. VLSI Symp, (2008)J. Steigerwald, IEDM (2008)J. Steigerwald, IEDM (2008)
STI deposition and polish
Wells and VT implants
ALD deposition of high-k gate dielectric
Polysilicon
deposition and gate patterning
S/D extensions, spacer, Si recess and SiGe
deposition
S/D formation, Ni silicidation, ILD0 deposition
Poly Opening Polish, Poly removal
PMOS workfunction
metal deposition
Metal gate patterning, NMOS WF metal deposition
Metal gate fill and polish, ESL deposition MGD MGD CMPCMP
POP POP CMPCMP
STI STI CMPCMP
27
Kuhn - 2009 2nd International CMOS Variability Conference - London33
STR Pattern Density Variation Impact
High Pattern Density Low Pattern Density
Slower Polish Rate Faster Polish Rate
OxideSiliconNitride
28
Kuhn - 2009 2nd International CMOS Variability Conference - London34
STI Step Height Variation
STI
Positive Step Height Zero Step Height
STI
High PatternDensity Area
Low PatternDensity Area
STI topography
impacts transistorLe and Ze
29
Kuhn - 2009 2nd International CMOS Variability Conference - London35
STI Step Height Variation
STI
Zero Step Height
STI
High PatternDensity Area
Low PatternDensity Area
STI topographyimpacts transistorLe and Ze
Poly Poly
30
Kuhn - 2009 2nd International CMOS Variability Conference - London36
Poly
Poly
STI Step Height Impact on Gate CD
PositiveStep Height
NegativeStep Height
“Dogbone”Lg
is longer at the diffusion boundary
GATE
GATE
Diffusion
Diffusion
STI
STI
“Icicle”Gate CD is shorter at the diffusion boundary
31
Kuhn - 2009 2nd International CMOS Variability Conference - London37
SRAM Density Scaling
90nm – TALL1.0 m2
65nm – WIDE - 0.57 m245nm – WIDE
0.346 m2
32nm – WIDE 0.171 m2
65nm to 32nm: Patterning and polish enhancements•
Improved CD uniformity across STI boundaries
•
Square corners (eliminate “dogbone”
and “icicle”
corners)
32
Kuhn - 2009 2nd International CMOS Variability Conference - London38
CMP Integration at 45 nm –
HiK
Metal Gate
First Generation HiK
–
Replacement Metal GateThree critical CMP operations in the FE
K.Mistry et al., IEDM (2007)C.Auth et al. VLSI Symp, (2008)J. Steigerwald, IEDM (2008)J. Steigerwald, IEDM (2008)
STI deposition and polish
Wells and VT implants
ALD deposition of high-k gate dielectric
Polysilicon
deposition and gate patterning
S/D extensions, spacer, Si recess and SiGe
deposition
S/D formation, Ni silicidation, ILD0 deposition
Poly Opening Polish, Poly removal
PMOS workfunction
metal deposition
Metal gate patterning, NMOS WF metal deposition
Metal gate fill and polish, ESL deposition
STI STI CMPCMP
POP POP CMPCMP
MGD MGD CMPCMP
33
Kuhn - 2009 2nd International CMOS Variability Conference - London39
•
Gate height control critical to reducing variation•
PMOS/NMOS differences complicate CMP
NMOS PMOS
C.Auth et al. VLSI Symp, (2008)
Epi
S/D
NiSi
HiK
J. Steigerwald, IEDM 2008
Variation Challenges of RMG CMP Steps
nWFM pWFM
HiK
34
Kuhn - 2009 2nd International CMOS Variability Conference - London40
Variation Challenges of RMG CMP Steps
S/D region –
attacked during poly etch
Gate region
J. Steigerwald, IEDM 2008
NMOS S/D region contact
S/D region –
marginal contact
OVERPOLISHExposes raised S/DRext/mobility impact
UNDERPOLISHUnderetched
contact
Rext
impact
35
Kuhn - 2009 2nd International CMOS Variability Conference - London41
Poly Opening Polish (POP) Thickness Control
45nm: with-in die (WID) and with-in wafer (WIW) improvementHigh selectivity between films is required.
Key aspect is control of polish rate at edge of wafer.
POP: WID by process Rev.
Process Rev
Patterned Wafers: WIW Profiles
0.2
0.4
0.6
0.8
1
1.2
1.4
0 25 50 75 100 125 150
Radius (mm)O
xide
Thi
ckne
ss
J. Steigerwald, IEDM 2008
Initial Rev 1 Final
0.5
0.6
0.7
0.8
0.9
1.0
Initial
Rev 1
Final
36
Kuhn - 2009 2nd International CMOS Variability Conference - London42
45 nm: POP CMP Improvement Overscaling
Topography Improvement
Improvements in polish enabled dramatic improvements in topography variation
Technology node (nm)
CM
P To
pogr
aphy
0.01
0.1
1
350 250 180 130 90 65 45
45nm: 2X greater than standard
technology scale
J. Steigerwald, IEDM 2008
0.7X improvement
37
Kuhn - 2009 2nd International CMOS Variability Conference - London43
Part I –
Physical Variation Sources and Mitigation
Polish
Patterning
Strain
38
Kuhn - 2009 2nd International CMOS Variability Conference - London44
Strain: Importance in scaling
Strain (first introduced at 90nm) is a critical ingredient in modern transistor scaling
130nm 90nm 65nm 45nm 32nm
PMOS
Cha
nnel
str
ain
39
Kuhn - 2009 2nd International CMOS Variability Conference - London45
Strain: Pitch dependence
NMOS Pitch degradation increases with film pinchoff, requires
higher stress, thinner films
PMOS eSiGe
S/D mobility strongly dependent
on pitch
C. Auth, VLSI 2008
220 160 Pitch (nm)
0.80.91.01.11.21.31.4
Nor
mal
ized
Idsa
t5
7
9
11
13
100150200250300Pitch (nm)
Idsa
t%
gai
n
40
Kuhn - 2009 2nd International CMOS Variability Conference - London46
NMOS strain: Scaling with pitch
+10%
1
10
100
1000
0.70 0.90 1.10 1.30Idsat (mA/m)
Ioff
(nA
/ m
)
Tensile FillControl
VDD = 1.0V
+10%
1
10
100
1000
0.70 0.90 1.10 1.30Idsat (mA/m)Idsat (mA/m)
Ioff
(nA
/ m
)Io
ff(n
A/
m)
Tensile FillControlTensile FillControl
VDD = 1.0V
Tensile trench contacts
+5%
1
10
100
1000
0.9 1.1 1.3 1.5Idsat (mA/m)
Ioff
(nA
/ m
)
Compressive GateControl
VDD = 1.0V
+5%
1
10
100
1000
0.9 1.1 1.3 1.5Idsat (mA/m)Idsat (mA/m)
Ioff
(nA
/ m
) Io
ff(n
A/
m)
Compressive GateControl
VDD = 1.0V
Compressive gate stress C. Auth, VLSI 2008
41
Kuhn - 2009 2nd International CMOS Variability Conference - London47
PMOS strain: Scaling with pitch
1.2
1.3
1.4
65nm 45nm
Technology node
Removal of Gate
Increase to30% Ge
ProximityReduction
C. Auth, VLSI 2008
IDSA
T (a
.u.)
Increase%Ge
Move SiGe
Remove Gate
42
Kuhn - 2009 2nd International CMOS Variability Conference - London48
Random VT
variability and strain
Similar VT
matching with CESL while 35% ION
enhancement is achieved
10-12
10-11
10-10
10-9
10-8
300 400 500 600 700 800 900
Off
Cur
rent
I off (A
.um
)On Current I
on (uA/um)
+35%
SOI + t-CESL
SOI ref.
L=25nm
Vdd
=1V
(W+2TSi
) normalization=60nm
650µA/µm –
30pA/µm at Vdd
=1V and Lg
=25nm
0
0.5
1
1.5
Vd=50mV Vd=1V
SOI ref.SOI + CESL
AVt
(mV.
um)
Weber et al.IEDM 2008
pp. 245-248
4
Kuhn - 2009 2nd International CMOS Variability Conference - London49
DO BOTHDO BOTHPart II:
Measurements, results and interpretation
44
Kuhn - 2009 2nd International CMOS Variability Conference - London50
Systematic and Random
•
Statistician’s viewpoint:
•
Process engineer’s viewpoint:
•
Device engineer’s viewpoint:
Systematic
Random
Random
Systematic
FixFix
Random
Systematic
VT1
S D
VT2
S D
VT1
S D
VT2
S D
45
Kuhn - 2009 2nd International CMOS Variability Conference - London5146
Measurement “food pyramid”•
In-line or off-line physical measurements of test wafers (TEM, SIMs, Auger, etc.)
•
Device parametric measurements on test material (Ion/Ioff, IG/VG etc.)
•
In-line physical measurements of selected sites in product (CD, thickness, etc.)
•
Device parametric measurements on product (Idsat/lin, VT)
•
Device parametric measurements on simple circuits (fmax, fmin, etc)
•
Device sort on completed product (Vccmin
and performance)
INC
REA
SIN
G D
ATA
QU
AN
TITY
D
ECR
EASI
NG
AB
ILIT
Y TO
SEG
MEN
T O
RIG
IN
Very limited dataHuge sample size
Highly detailed dataTiny sample size
Kuhn - 2009 2nd International CMOS Variability Conference - London52
Measurement of Random and Systematic VT Variation at the Device Level
Traditional method: 1.
Measure two identical adjacent devices and extract the difference (VTA-VTB)
2.
Measure the entire population of all devices and extract (VTpop)
Random Variation for a matched pair
)()( DVTVTVTStdDevRandom BAmp
22
2)()(
DVTVTSystematic pop
Random Variation for a single device 2
)(2
)( DVTVTVTStdDevRandom BAdeviceone
Systematic Variation for a single device
VT1
S D
VT2
S D
47
Kuhn - 2009 2nd International CMOS Variability Conference - London53
Pelgrom
Plots: What is AVT
anyway? Two
choices are widely used in the literature
Choice ASlope of VT vs
1/LW
Choice BSlope of VT vs
1/LW
2
IEDM 2008: ArnaudIEDM 2008: Weber
<48
Kuhn - 2009 2nd International CMOS Variability Conference - London54
What did Pelgrom
say?
•
Eq. 5 defines a generic AP
for a parameter P; implying AVT
would then be the parameter for VT
•
However, one page further in the paper, he explicitly defines AVT
in terms of VT
only in equation 8:
•
So –
which is did he mean? Well, I asked him.
Pelgrom
“Matching properties of MOS transistors”(IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, Oct. 1989)
49
Kuhn - 2009 2nd International CMOS Variability Conference - London5550
What is AVT
anyway? Two choices are widely used in the literature
Choice ASlope of VT vs
1/LW
Choice BSlope of VT vs
1/LW
2 This is AVT
<
IEDM 2008: ArnaudIEDM 2008: Weber
Kuhn - 2009 2nd International CMOS Variability Conference - London56
What is AVT
anyway? Two choices are widely used in the literature
Choice ASlope of VT vs
1/LW
Choice BSlope of VT vs
1/LW
2I will call this CVT (or C2)
CVT
= AVT
/ This is AVT
<
IEDM 2008: ArnaudIEDM 2008: Weber
51
12-11-07 IEDM 2007 57
)1(21
24 2
44 3
ZeffLeffc
ZeffLeffNTq
Vox
oxBsiTran
RDF is frequently described by (Stolk):
C2 is proportional to the slope of the 1 / line
ZeffLeff
Characterizing RDF
1/ LeffZeff (1/m)
V T
(mV)
0
10
20
30
40
50
60
0 20 40 60
1/ LeffZeff (1/m)
V T
(mV)
0
10
20
30
40
50
60
0 20 40 60
P. Stolk, F. Widdershoven, and D/ Klaassen, “Modeling statistical dopant fluctuations in MOS transistors”
IEEE Trans. on Elec. Dev., 45:9, pp 1960-1971, Sept. 1998
Additional propagation of confusion (By me, it turns out …)
K. Kuhn, IEDM 2007
12-11-07 IEDM 2007 58
)1(21
24 2
44 3
ZeffLeffc
ZeffLeffNTq
Vox
oxBsiTran
RDF is frequently described by (Stolk):
C2 is proportional to the slope of the 1 / line vs
VT
ZeffLeff
Characterizing RDF
1/ LeffZeff (1/m)
V T
(mV)
0
10
20
30
40
50
60
0 20 40 60
1/ LeffZeff (1/m)
V T
(mV)
0
10
20
30
40
50
60
0 20 40 60
P. Stolk, F. Widdershoven, and D/ Klaassen, “Modeling statistical dopant fluctuations in MOS transistors”
IEEE Trans. on Elec. Dev., 45:9, pp 1960-1971, Sept. 1998
K. Kuhn, IEDM 2007
Additional propagation of confusion (By me, it turns out …)
Kuhn - 2009 2nd International CMOS Variability Conference - London59
What is BVT
then?
Slope of VT vs
(Tinv(VT+0.1)/LW) BVT
Fig. 3: Takeuchi, IEDM 200754
Kuhn - 2009 2nd International CMOS Variability Conference - London60
But what about simple circuits?
One powerful tool for assessment of variation is locating ring-oscillators (ROs) routinely in all product designs
55
Kuhn - 2009 2nd International CMOS Variability Conference - London61
Random and Systematic Variationfor Matched Ring Oscillators
Random:• Calculate Delta
• Random Variation
2200*
FreqBFreqAFreqBFreqADelta
)(DeltaStdDevRand
2)()( FreqBMeanFreqAMean
22
100* RandSyst
)(FreqAStdDevSystematic:• Total Sigma
• Grand Mean
• Systematic Variation
per data unit
per data unit
per data unit
Total Variation: 100*)()(
FreqAMeanFreqAStdDevTotal per data unit
56
Kuhn - 2009 2nd International CMOS Variability Conference - London62
0
0.5
1
1.5
NO
RM
ALI
ZED
% V
aria
tion
Standard oscillator
RANDOM
15cm
8 cm
0
0.5
1
1.5
NO
RM
ALI
ZED
% V
aria
tion
Standard oscillator
SYSTEMATIC
15cm
8 cm
45nm: Within Wafer Variation
For random variation: Uniform across waferFor systematic variation: More variation at the wafer edge
15cm 14cm 13cm 12cm 11cm 10cm 9cm 8cm
57
Kuhn - 2009 2nd International CMOS Variability Conference - London63
0
0.5
1
1.5
2
NO
RM
ALI
ZED
% V
aria
tion
Standard oscillator
SYSTEMATIC
Entire population
One wafer
One die
Standard oscillator
0
0.5
1
1.5
2
NO
RM
ALI
ZED
% V
aria
tion
RANDOM
Entire population
One wafer
One die
45nm: Within Die (WID), Within Wafer (WIW) and Wafer to Wafer (WTW)
For random variation: Uniform with population choiceFor systematic variation: Variation increases significantly
going from within-die (WID) to within-wafer (WIW)
58
Kuhn - 2009 2nd International CMOS Variability Conference - London64
45nm Product wafer: Random variation
0
0.5
1
1.5
NO
RM
ALI
ZED
% V
aria
tion
Standard oscillator
15cm
8 cm
K. Kuhn, ITJ 2008
59
Kuhn - 2009 2nd International CMOS Variability Conference - London65
Normalized random variationstandard deviation per oscillator (%)
012
345
130nm 90nm 65nm 45nm 32nm
PE
RC
EN
T (%
) Normalized systematic variation
standard deviation per oscillator (%)
0
1
2
3
4
5
130nm 90nm 65nm 45nm 32nm
PE
RC
EN
T (%
)
Random and Systematic Variation Trends
Systematic WIW variation is comparable from one generation to the next
Random WIW variation in 32nm is comparable to 45nm and significantly
improved over 65nm and 90nm due to HiK-MG
HiK-MG
60
Kuhn - 2009 2nd International CMOS Variability Conference - London66
What about more complex circuits? RSM Methodology for Variation Model Parameters
•
Identify the set of input parameters in variation modeling files that can be allowed to vary
•
Create DOE to vary all parameters within selected limits
•
Create a series of variation modeling files, using the matrix of parameters from the DOE
•
Simulate an appropriate set of circuits and devices to obtain responses to the set of variation modeling files
•
Enter simulation results back into DOE to determine sensitivity to model parameters
•
Optimize variation modeling file parameters to get best match to measured data
61
Kuhn - 2009 2nd International CMOS Variability Conference - London67
Example Matrix of Inputs and Associated Responses
BA JIHGFEDC
1
4
3
2
Inputs
Res
pons
es
Not all responses are sensitive to all inputs–
key is to determine which responses are appropriate for setting each input parameter
Sensitivity of response “2”
to input “E”
62
Kuhn - 2009 2nd International CMOS Variability Conference - London68
32nm SRAM Test Chip
291Mbit SRAM
SRAM test chip with advanced test features (PBIST, eFUSE, ECC, etc.) to support development of 32nm high-volume manufacturing process
3.25Mb SRAM Macro
K. Zhang, ISCC 2009 63
Kuhn - 2009 2nd International CMOS Variability Conference - London69Wafer-level SRAM P/NMOS transistor systematic systematic VT variation
Typical SlowFast
Die-level Read / Write VCCmin
Transistor randomrandomVT
variation (VT, random
)
Read: Static-Noise-Margin (SNM)&
Dynamic StabilityWrite: Dynamic Writability
SRAM VSRAM VCCmin CCmin ––
Silicon to SimulationSilicon to Simulation
MeasurementMeasurement
VT, system
0
20
40
60
80
100
VCCmin (A.U.)
Perc
entil
e (%
)
write
Read
Simulation
K. Zhang, ISCC 2009
Kuhn - 2009 2nd International CMOS Variability Conference - London70
3.25Mb SRAM Macro
Frequency (GHz)Frequency (GHz)22 33 44 55 66
VCC
(V)
VCC
(V)
1.11.1
1.01.0
0.90.9
0.80.8
1.21.2
1.31.3
32nm Voltage-Frequency Shmoo
•
32nm SRAM operates over a broad range of supply voltages, enabling dynamic voltage scaling for low-power application
•
32nm SRAM achieves operating frequency of 4GHz at 1.0V, 15% better than 45nm design
4GHz4GHz2GHz FAILFAIL
PASSPASS
K. Zhang, ISCC 2009 65
Kuhn - 2009 2nd International CMOS Variability Conference - London71
Part III: Next generation
challenges
66
Kuhn - 2009 2nd International CMOS Variability Conference - London72
Lithography Pipeline
Extend 193nm Optical Lithography as far as possibleDeploy EUV Lithography when available/affordable
0.01
0.1
1
1980 1990 2000 2010 2020
MIC
RO
N
10
100
1000
32nm22nm
15nmFeature Size
Wavelength248nm
193nm
EUV13.5nm
OPCPhase shiftImmersion
NA
NO
MET
ER
67
Kuhn - 2009 2nd International CMOS Variability Conference - London73
Extreme Ultraviolet Lithography
Intel EUV Mask
C
2H 08
2007
1H’08
Target
2H’08
Continued progress towards EUV implementationPhotoresist
Development Nikon EUV1 printed wafer
ASML ADT printed wafer
Philips beta source
Cymer beta source
M. Bohr, ISCC, 2009 68
Kuhn - 2009 2nd International CMOS Variability Conference - London74
Pitch Doubling 2-D Features
Double Patterning•
Pitch doubling
•
Improved 2-D features
Non-EUV Lithography Beyond 32 nm
Spacer Gate Patterning•
Pitch doubling
•
Improved variation
M. Bohr, ISCC, 2009Bencher et al, Proc. of SPIE Vol. 6924 69244E-7
69
Kuhn - 2009 2nd International CMOS Variability Conference - London7570
Pitch doubling and gate CD control
Gate layerPattern transfer layer
Gate layer2nd
pattern transfer layer1st
pattern transfer layer
Resist freeze
Both techniques still require resolutionof a very small space (MEEF, LWR etc.)
NeitherResist Freeze norDouble Pattern Transfer achieve full benefit of patterning at ½
pitch
Double PatternTransfer
C. Kenyon, TOK conf., Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London76
Disadvantages of Double-patterning
Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability
Transistor parameters can be affected by asymmetry between the source and drain regions
Print 1 Print 2
Misalignment
Registration (nm)
NO
RM
ALZ
ED ID
SAT
71
Kuhn - 2009 2nd International CMOS Variability Conference - London77
Pitch doubling and gate CD matching
Pitch doubling eliminates the close correlation which currently exists between the CDs of adjacent gates
This has implications for memory cells and other circuits which depend upon this CD matching
A A
B
A
B BB1266
12641262
860
Gate CD mismatch
SRA
M V
ccm
in
72 C. Kenyon, TOK conf., Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London7873
Single patterning: the distribution of CD mismatches between adjacent gates is a very small fraction of total gate CD variation
Pitch doubling: the distribution of CD mismatches is GREATER than the total gate CD variation
Pitch doubling and gate CD matching
-4 -3 -2 -1 0 1 2 3 4
Pitch doublingadjacent gate CD
mismatches
Total gate CD distribution
Single patterning adjacent gate CD mismatches
C. Kenyon, TOK conf., Dec. 2008
Kuhn - 2009 2nd International CMOS Variability Conference - London79
Pitch Doubling 2-D Features
Double Patterning•
Pitch doubling
•
Improved 2-D features
Non-EUV Lithography Beyond 32 nm
Spacer Gate Patterning•
Pitch doubling
•
Improved variation
M. Bohr, ISCC, 2009Bencher et al, Proc. of SPIE Vol. 6924 69244E-7
74
Kuhn - 2009 2nd International CMOS Variability Conference - London80
Bencher et al, Patterning by CVD Spacer Self Alignment DoublePatterning
(SADP), Proc. of SPIE Vol. 6924 69244E-7
Spacer patterning retains correlation between doubled features
Alternative: Spacer patterning
75
Kuhn - 2009 2nd International CMOS Variability Conference - London81
Spacer inhomogenities
not transferred to patterned features
Alternative: Spacer patterning
Bencher et al, Patterning by CVD Spacer Self Alignment DoublePatterning
(SADP), Proc. of SPIE Vol. 6924 69244E-7 76
Kuhn - 2009 2nd International CMOS Variability Conference - London82
65nm node 45nm node 32nm node
Uniformity matters: Logic images vs. technology node
Kuhn - 2009 2nd International CMOS Variability Conference - London83
Layout Restrictions 65nm to 32nm65 nm Layout Style 32 nm Layout Style
•
Bi-directional features•
Varied gate dimensions•
Varied pitches
•
Uni-directional features•
Uniform gate dimension•
Gridded layout
M. Bohr, ISCC, 200978
Kuhn - 2009 2nd International CMOS Variability Conference - London84
Transistor Architecture Enhancements
Fully depleted devices (such as UTB or FinFET) are examples of innovations which permit significant improvement in RDF due to the ability to maintain channel control at lower channel doping.
Weber et al. IEDM 2008 pp. 245-248
Vellianitis et al. IEDM 2008 pp. 681-683
79
85
0
20
40
60
80
100
120
-105 -87 -69 -51 -33 -15 0 15 33 51 69 87 105
σΔVt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ΔVt (mV)
0
20
40
60
80
100
120
-105 -87 -69 -51 -33 -15 0 15 33 51 69 87 105
σΔVt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ΔVt (mV)
0.5
1
1.5
2
2.5
3
10 20 30 40 50 60
AV
t (mV
.um
)Gate length L (nm)
Bulk platformFDSOI MOSFETs
ST 65nmST 45nm
IBM 90nm
Intel 45nm
Intel 65nm
This work
ST FDSOI
ST GAA
IMEC FinFET
HitachiFDSOI
FDSOI
IBM alliance32nm
Square Vd
=1V circle Vd
=50mV
L=25nmW=60nm
(σVt
=σΔVt
/√2 to compare measurements on pairs and on arrays of transistors in the literature)
1/(LZ)=25.8
VT
matching performance
C2
(mV-
um)
Weber et al.IEDM 2008
pp. 245-248
Fully depleted devices (such as UTB or FinFET) are examples of innovations which permit significant improvement in RDF due to the ability to maintain channel control at lower channel doping.
Weber’s
Kuhn - 2009 2nd International CMOS Variability Conference - London86
Closing Thoughts
81
Kuhn - 2009 2nd International CMOS Variability Conference - London87
Normalized random variationstandard deviation per oscillator (%)
012
345
130nm 90nm 65nm 45nm 32nm
PE
RC
EN
T (%
) Normalized systematic variation
standard deviation per oscillator (%)
0
1
2
3
4
5
130nm 90nm 65nm 45nm 32nm
PE
RC
EN
T (%
)
Random and Systematic Variation Trends
Systematic WIW variation is comparable from one generation to the next
Random WIW variation in 32nm is comparable to 45nm and significantly
improved over 65nm and 90nm due to HiK-MG
HiK-MG
82
Kuhn - 2009 2nd International CMOS Variability Conference - London88
45 nm: POP CMP Improvement Overscaling
Topography Improvement
Improvements in polish enabled dramatic improvements in topography variation
Technology node (nm)
CM
P To
pogr
aphy
0.01
0.1
1
350 250 180 130 90 65 45
45nm: 2X greater than standard
technology scale
J. Steigerwald, IEDM 2008
0.7X improvement
83
Kuhn - 2009 2nd International CMOS Variability Conference - London89
Gate CD variation improvements with technology scaling
0.1
1
10
130nm336
90nm260
65nm220
45nm160
32nm112.5
LOG
(Var
iatio
n no
rmal
ized
to 1
30nm
WIW-total TOTAL
WID-total0.7X
Critical to management of variation is the ability to deliver a 0.7X gate CD variation improvement in each generation
enabled by continuous process technology improvements
Technology Trend Systematic Gate CD Lithography Variation
GENERATIONGATE PITCH
84
Kuhn - 2009 2nd International CMOS Variability Conference - London90
SRAM Density Scaling
0.10
1.00
10.00
90nm 65nm 45nm 32nmProcess generation
Bitc
ell A
rea
(m
2 )
2X bitcell area scaling
Improved fidelity / uniformity on 32nm vs
90nm
K. Zhang, ISCC, 2009
85
Kuhn - 2009 2nd International CMOS Variability Conference - London91
For further information on Intel's silicon technology, please visit our Technology & Research page at
www.intel.com/technology
Q&A
Blood cell: Elec. Mic. Fac. (NCI-Frederick) 2007
32nm SRAM Cell: 0.171 um2
86
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