SMDK-V210_USER’S MANUAL_REV 0.0
Preliminary
User’s Manual (SMDK S5PV210 Rev0.0)
Development Kit
for S5PV210 Dec 02, 2009
REV 0.0
SMDK-V210_USER’S MANUAL_REV 0.0
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.
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S5PV210 RISC Microprocessor SMDK S5PV210 User’s manual, Revision 0.0
Copyright © 2008 Samsung Electronics Co.,Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd.
Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea 446-711
Home Page: http://www.samsungsemi.com/ E-Mail: [email protected]
Printed in the Republic of Korea
SMDK-V210_USER’S MANUAL_REV 0.0
Revision History
Rev. No Description of Change Refer to Author(s) Effective Date
(MM/DD/YY)
0.00 - Initial Release (SMDK S5PV210 Rev0.00) AP
development Dec, 02, 2009
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Table of Contents 1 INTRODUCTION ............................................................................................6
1.1 SYSTEM OVERVIEW......................................................................................................... 6 1.2 SMDK S5PV210 FEATURES.............................................................................................. 8
2 SMDK S5PV210 REAL VIEW ...............................................................................9 2.1 SMDK S5PV210 CPU BOARD REAL VIEW..................................................................... 9 2.2 SMDK S5PV210 BASE BOARD REAL VIEW .................................................................11 2.3 SMDK S5PV210 LCD BOARD REAL VIEW ...................................................................13
3 CIRCUIT DESCRIPTION .................................................................................. 13 3.1 POWER DISTRIBUTION TREE........................................................................................13 3.2 FUNCTIONAL BLOCK DIAGRAM..................................................................................16
4 SMDK S5PV210 SYSTEM CONFIGURATIONS........................................................... 17 4.1 PLL CLOCK SOURCE SELECTION.................................................................................20 4.2 BOOT MODE SELECTION ...............................................................................................20
4.2.1 Switch Configuration..................................................................................................20 4.3 CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD .....................................21
4.3.1 CFG3: SELECTION FOR CS#4,#5 ...........................................................................21 4.3.2 J2: SELECTION for Interrupt of Ext. OneNAND .....................................................21 4.3.3 CFG2: Configuration of MMC slot 0 ..........................................................................22 4.3.4 CFG1: TSI I/F..............................................................................................................22 4.3.5 J3: PSHOLD selection .................................................................................................22 4.3.6 JP1: JIG ON selection..................................................................................................22
4.4 CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD...................................24 4.4.1 CFGB1: SROM BANK0 CHIP SELECTOR ..............................................................24 4.4.2 CFGB2: SROM BANK1 CHIP SELECTOR ..............................................................24 4.4.3 CFGB3: SROM BANK2 CHIP SELECTOR ..............................................................24 4.4.4 CFGB4: SROM BANK3 CHIP SELECTOR ..............................................................24 4.4.5 CFGB5: SROM BANK4 CHIP SELECTOR ..............................................................25 4.4.6 CFGB6: SROM BANK5 CHIP SELECTOR ..............................................................25 4.4.7 CF,MODEM,CAM_B,KEY,MHL,SROM ADDR SWITCHING...............................25 4.4.8 CFGB10: Audio Port ...................................................................................................26 4.4.9 CFGB11: Audio Codec(WM8580) Master clock selection .........................................26 4.4.10 CFGB12: Audio Device Input/Output Connection.....................................................27 4.4.11 CFGB13: UART/IrDA Connection .............................................................................27
4.5 LED & SWITCH Description ..............................................................................................27 4.5.1 LED description...........................................................................................................27 4.5.2 Switch description .......................................................................................................28
5 SMDK Daughter Board .................................................................................. 29 5.1 External OneNAND.............................................................................................................29
5.1.1 Real view .....................................................................................................................29 5.1.2 Schematic.....................................................................................................................29
5.2 CSI Daughter Board.............................................................................................................29 5.2.1 Real view .....................................................................................................................29 5.2.2 Schematic.....................................................................................................................30
5.3 DSI Daughter Board.............................................................................................................30 5.3.1 Real view .....................................................................................................................31 5.3.2 Schematic.....................................................................................................................31
6 SMDK SCHEMATIC REVISION HISTORY ................................................................ 32 7 SMDK SCHEMATIC ....................................................................................... 32
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Figure List Figure 1 S5PV210 Functional Block Diagram ...............................................................7 Figure 2 S5PV210 CPU BOARD TOP VIEW ...................................................................9 Figure 3 S5PV210 CPU BOARD BOTTOM VIEW ............................................................ 10 Figure 5 S5PV210 BASE BOARD BOTTOM VIEW ........................................................... 12 Figure 6 S5PV210 LCD BOARD TOP VIEW.................................................................. 13 Figure 7 S5PV210 BASE BOARD POWER DISTRIBUTION TREE ........................................... 14 Figure 8 S5PV210 CPU BOARD POWER DISTRIBUTION TREE ............................................ 15 Figure 9 S5PV210 SMDK FUNCTIONAL BLOCK DIAGRAM................................................. 16 Figure 10 External OneNAND ............................................................................... 29 Figure 11 CSI Daughter Board .............................................................................. 30 Figure 12 DSI Daughter Board .............................................................................. 31
Figure 13 Camera module......................................오류! 책갈피가 정의되어 있지 않습니다.
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1 INTRODUCTION
1.1 SYSTEM OVERVIEW SMDK S5PV210 ( S5PV210 Development Kit) is a platform for code development of SAMSUNG's S5PV210 16/32-bit RISC microcontroller (ARM-CORTEX A8). S5PV210 is used in hand-held devices and general applications. The S5PV210 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an ARM Cortex-A8 which implements the ARM architecture V7-A with supporting numerous peripherals.
To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PV210 adopts 64-bit internal bus architecture and includes many powerful hardware accelerators for tasks such as motion video processing, display control and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG-1/2/4, H.263, H.264 and decoding of VC1, Divx. This Hardware accelerators support realtime video conferencing and Analog TV out, HDMI for NTSC and PAL mode
The S5PV210 has an optimized interface to external memory capable of sustaining the demanding memory bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port for high bandwidth. DRAM port can be configured to support LPDDR1(=mobile DDR), DDR2 or LPDDR2.
Flash/ROM Port supports NAND Flash, NOR-Flash, OneNAND, SRAM and ROM type external memory.
To reduce total system cost and enhance overall functionality, S5PV210 includes many hardware peripherals such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for power management, ATA I/F, 4 UART, 24-channel DMA, 4 Timers, General I/O Ports, 3 IIS, S/PDIF, 3 IIC-BUS interface, 3 HS-SPI, USB Host 2.0, USB OTG 2.0 operating at high speed (480Mbps), 4 SD Host & High Speed Multi-Media Card Interface and 4 PLLs for clock generation.
Package on Package (POP) option with MCP is available for small form factor applications.
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CPU Core
Memory Interface
Multimedia
Connectivity
System Peripheral
Multi layer AHB/AXI Bus
Power Management
RTC
PLL x 4
Timer with PWM (4ch)
Watchdog Timer
DMA (24ch)
Keypad (14x8)
TS-ADC (12bit/10ch)
Audio IF
IIS x3 / PCM x 3
S/PDIF / AC97
Storage IF
HSMMC/SD x 4
ATA
Connectivity
USB Host2.0 / OTG 2.0
UART x 4
IIC x 3
HS-SPI x 3
GPIO
CortexA8
32KB/32KB I/D cache800MHz/1GHz @ 1.1V/1.2V
512KBL2 cache NEON
128KBRAM
64KBROM
Crypto Engines
Clock gating / Power gating /
Dynamic Voltage Frequency Scaling
12MP Camera IF / MIPI CSI-2
1080p 30fps MFCCodec – H.263/H.264/MPEG4Decoder – MPEG2/VC-1/Divx
2D VG / 3D Graphics engine
NTSC / PAL TV out& HDMI
JPEG Codec
SRAM / ROM
LPDDR1 / OneDRAMLPDDR2 / DDR2
SLC / MLC NAND with 16bit ECC
Audio DSP
Modem IF
(Flex) OneNAND
TFT LCD controllerXGA resolution
Figure 1 S5PV210 Functional Block Diagram
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1.2 SMDK S5PV210 FEATURES The SMDK S5PV210 (S5PV210 Development Kit) highlights the basic system-based hardware design which uses the S5PV210. It can evaluate the basic operations of the S5PV210 and assist in developing codes. The features of SMDK S5PV210 include:
- Microcontroller : S5PV210 (16/32 bit RISC microcontroller, ARM-CORTEX A8 ) - External memory
. AMD 8Mbit NOR Flash (Socket 1EA)
. SAMSUNG NAND Flash (Socket 1EA)
. SAMSUNG OneNAND (External Board, Optional)
. SAMSUNG 16Mbit SRAM 1EA
. Dram port 0 : SAMSUNG 4 x 1Gb DDR2 SDRAM(x8)
. Dram port 1 : SAMSUNG 4 x 1Gb DDR2 SDRAM(x8) or SAMSUNG 4 x 2Gb DDR2 SDRAM(x8)
- TFT LCD & Touch panel interface (External Board, default: 4.8” WVGA LMS480KF02) - ATA interface (2 CF card sockets) - SD/SDIO/MMC interface (3 SD Sockets) - Digital Video & Audio : HDMI 1.3 Video(720p) & S/PDIF 5.1 Channel Audio I/F - TV Out interface (Composite) - USB Host , USB OTG 2.0 interface - High Speed SPI interface - IIS/AC97/PCM Interface : WM9713, WM8580 Audio CODEC on board - General Camera Interface : 2 port - MIPI Camera Interface : MIPI-CSI2 (1Gbps/Lane Serial Communication) - High Speed Serial MIPI Interface LCD : MIPI-DSI (1Gbps/Lane Serial Communication) - Keypad interface - Ethernet Interface : DM9000(10/100Mbps Ethernet controller) on board - 2 port UART interface - JTAG port - Module Connector (M1 ~ M4)
. M1 (Module1): For GPS Daughter Board (UART, SPI) : Samsung GPD14B01 (SiRFSTAR III GSD3) (Optional)
. M2 (Module2): For Mobile TV Daughter Board (SPI, IIC) or HD Radio (SPI, IIS) Mobile TV: Samsung S5P4F31 (TBD, Optional) HD Radio: SiPORT SD1010 (TBD, Optional) , Samsung (TBD, Optional)
. M3 (Module3): For Bluetooth Daughter Board (UART, PCM for PMIC Audio Codec)
. M4 (Module4): For Audio Daughter Board (AC97, IIS, IIC)
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2 SMDK S5PV210 REAL VIEW
2.1 SMDK S5PV210 CPU BOARD REAL VIEW
Figure 2 S5PV210 CPU BOARD TOP VIEW
JTAG5V/3
USB HOST
USB OTG HDMI
S5PV210
LCD I/F
MIPI-DSI
MIPI-CSI CAMERA-A Port
RESETPOWER
CFG3(CS)
CFG4(OM)
External OneNAND
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Figure 3 S5PV210 CPU BOARD BOTTOM VIEW
SD/MMC SLOT 1
SD/MMC SLOT 0
SD/MMC SLOT 2
B2B CONNECTOR To Base Board
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2.2 SMDK S5PV210 BASE BOARD REAL VIEW
AUDIO
NAND NOR
M1 M2
M3 M4
ROM Bus Connector
B2B CONNECTOR For CPU Board
Figure 4 S5PV210 BASE BOARD TOP VIEW
MODEM & MHL I/F
Composite IrDA
Camera B-Port
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Figure 5 S5PV210 BASE BOARD BOTTOM VIEW
Compact Flash Socket
QWERTY KEYPAD
UART 1/2/3 Composite
LANS/PDIF
Audio CODEC
UART 0
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2.3 SMDK S5PV210 LCD BOARD REAL VIEW
Figure 6 S5PV210 LCD BOARD TOP VIEW
3 CIRCUIT DESCRIPTION The SMDK S5PV210 is designed to test S5PV210 and develop software while hardware is being developed. Figure 10 highlights the SMDK S5PV210's block diagram.
3.1 POWER DISTRIBUTION TREE SMDK S5PV210 is operated by 1.1V for Internal, 1.8V for Memory and 3.3V for Input/Output pad and several peripherals. SMDK S5PV210 is supplied by 5V/3A DC Adaptor Power. The SMDK S5PV210 has distributed power plane, with power going separately to the MCU and the main power plane.
3.1” 480 x 800 WVGA OLED
4.8” 800 x 480 WVGA
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Connector For Base Board
DC
5V
VDD
_3V3
VDD
_1V8
VDD
_MSM
VDD
_AU
D
VDD
_DA
C
VDD
_EX
T
VDD
_SY
S
VDD_2V5 Regulator
PWROn_BOARD
VDD_3V3
VDD_CAM_EXT Regulator
PWROn_BOARD
DC5V(2.8V)
BASE Board Power TREE (S5PV210)
Figure 7 S5PV210 BASE BOARD POWER DISTRIBUTION TREE
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Figure 8 S5PV210 CPU BOARD POWER DISTRIBUTION TREE
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3.2 FUNCTIONAL BLOCK DIAGRAM
PLL
HD
MI
RT
C
US
B
Figure 9 S5PV210 SMDK FUNCTIONAL BLOCK DIAGRAM
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4 SMDK S5PV210 SYSTEM CONFIGURATIONS Perform the following steps to use SMDK S5PV210 board. - CFG is on CPU board and CFGB is on Base board. - Configuration value meaning - X: don’t care, 1: ON 0: OFF
Configuration Switch (DIP Switch) 1 ――→ 2 ――→ 3 ――→ 4 ――→ Off(Switch Open) → On (Switch Short)
1. Select the Clock source(CFG4)
Please refer to ‘PLL CLOCK SOURCE SELECTION’
2. Select the Boot Device(storage) and set Boot Mode configuration switches (CFG4)
Please refer to ‘BOOT MODE SELECTION’
3. Set the CFG switch or Jumper for each booting device.
External OneNAND
- Check If OneNAND daughter card is connected on CON14(on CPU board).
- Set CFG3[6:1] to X0X010. (Xm0CSn4)
CFG3
CS5 CS4
[6] [5] [4] [3] [2] [1]
X OFF X OFF ON OFF
- Set J2(on CPU board) to 1-2 SHORT.
J2
-
SD/MMC or eMMC
- Insert a Card to HS-MMC slot0 (CON13 on CPU board).
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- Set CFG2[2:1] to X0. (to use SDMMC channel 0 of S5PV210)
CFG2 Description
[1] OFF
NAND Flash
- Insert a NAND Flash to NAND socket (U4 on Baseboard).
- Set CFGB3[2:1] to 10. (Xm0CSn2)
CFGB3
[2] [1]
ON OFF
NOR Flash
- Insert a NOR Flash to NOR socket (U3 on Baseboard).
- Set CFGB1[2:1] to 01. (Xm0CSn0)
CFGB1
[2] [1]
OFF ON
- Set CFGB7[2:1] to 00 and CFGB8[2:1] to 11 and CFGB9[2:1] to 00. ( to use SROM Addr [16:22])
CFGB7
[2] [1]
OFF OFF
CFGB8
[2] [1]
ON ON
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CFGB9
[2] [1]
OFF OFF
4. Set CFGB13 for debugging message channel .
UART ch2 is for default debugging message channel and booting channel.(ch3 in case of EVT0)
- Connect to UART cable to COM2(CON15 on Base board)
- Set CFGB13[4:1] to 0001
CFGB13 [4] [3] [2] [1]
UART2 OFF OFF OFF ON
5. Check default Jumper setting.
<CPU Board>
- JP1~40 Short
- J4 1-2 short
- J5 1-2 short
- J8 2-3 short
- JP41 Open
<BASE Board>
- JP1 Short
- J1,J2 Open
6. Connect 5V power adapter and push the power button.
7. Check the Power LED if it is operating normally.
Refer to LED description section.
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4.1 PLL CLOCK SOURCE SELECTION Main input clock for the S5PV210 system can be selected by setting the XOM[0] values.
Description CFG4[1] , (XOM[0])
24MHz X-tal Clock (XXTI) OFF
24MHz X-tal Clock (XusbXTI) ON (default)
4.2 BOOT MODE SELECTION
4.2.1 Switch Configuration Description CFG4[6:2]
CFG4[6] CFG4[5:2] CFG4[6] CFG4[5] CFG4[4] CFG4[3] CFG4[2]
eSSD OFF
Nand 2KB, 5cycle (Nand 8bit ECC)
OFF ON
Nand 4KB, 5cycle (Nand 8bit ECC)
OFF
Nand 4KB, 5cycle (Nand 16bit ECC)
OFF
ON ON
OnenandMux OFF
OnenandDemux OFF
ON
SD/MMC OFF
eMMC(4-bit)
OFF
ON
ON ON
Reserved ON
Nand 2KB, 4cycle (Nand 8bit ECC)
OFF ON
NOR boot OFF
I-ROM Booting
sequence: Storage
eMMC(8-bit)
OFF
ON OFF
ON ON
I-ROM
eSSD OFF
Booting sequence: Nand 2KB, 5cycle
ON OFF OFF OFF
ON
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UART ->USB
->Storage Nand 4KB, 5cycle OFF
Nand 4KB, 5cycle
(Nand 16bit ECC)
ON ON
OnenandMux(Audi) OFF
OnenandDemux(Audi)
OFF
ON
SD/MMC OFF
eMMC(4-bit)
ON
ON ON
Note) If CFG4[6] is set to 1, It is used for debug mode that UART boot is first and USB boot is second. UART boot has some kind of error case. In case of UART error, the iROM boot sequence moves to USB boot. USB boot also has some kind of error case like UART. If USB boot is fail, boot sequence move to main storage boot. Please refer to iROM application note which is more detail about error case.
4.3 CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD
4.3.1 CFG3: SELECTION FOR CS#4,#5 CFG3
CS5 CS4 Description
[6] [5] [4] [3] [2] [1]
ON External OneNand
Connect to Base CS#5 External
OneNand Connect to Base CS#4
4.3.2 J2: SELECTION for Interrupt of Ext. OneNAND J2 Description
1-2 short Connect to ONDXL_INT0
2-3 short Connect to ONDXL_INT1(default)
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4.3.3 CFG2: Configuration of MMC slot 0 CFG2 Description
[1] ON : MMC port 1 4bit Data Width
OFF : MMC port 0 8bit Data Width (default)
[2] ON : HDMI I2C Buffer Disable
OFF : HDMI I2C Buffer Enable
4.3.4 CFG1: TSI I/F CFG3 Description
[1] ON : TSI I/F Buffer Enable
OFF : TSI I/F Buffer Disable
[2] ON : TSI RX
OFF : TSI TX
4.3.5 J3: PSHOLD selection J3 Description
1-2 short Not using PSHOLD
2-3 short
Using PSHOLD.
PSHOLD should be programmed Output-HIGH during pressing the power button ,.
4.3.6 JP1: JIG ON selection JIG ON is used to turn on board without pressing power button.
JP1 Description
short Turn on system power always.
open Turn on system power by pressing power button.
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4.4 CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD
4.4.1 CFGB1: SROM BANK0 CHIP SELECTOR CFGB1 component is used to select devices as SROM BUS I/F 0(B_Xm0CSn0).
CFGB1 Description
[2] [1]
NOR (AMD) Flash OFF ON
SRAM ON OFF
4.4.2 CFGB2: SROM BANK1 CHIP SELECTOR CFGB2 component is used to select devices as SROM BUS I/F 1(B_Xm0CSn1).
CFGB2 Description
[2] [1]
NOR (AMD) Flash OFF ON
SRAM ON OFF
4.4.3 CFGB3: SROM BANK2 CHIP SELECTOR CFGB3 component is used to select devices as SROM BUS I/F 2(B_Xm0CSn2/NFCSn0).
CFGB3 Description
[2] [1]
SRAM OFF ON
Nand CS 0 ON OFF
4.4.4 CFGB4: SROM BANK3 CHIP SELECTOR CFGB4 component is used to select devices as SROM BUS I/F 3(B_Xm0CSn3/NFCSn1).
CFGB4 Description
[2] [1]
SRAM OFF ON
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Nand CS 1 ON OFF
4.4.5 CFGB5: SROM BANK4 CHIP SELECTOR CFGB5 component is used to select devices as SROM BUS I/F 4(B_Xm0CSn4/NFCSn2).
CFGB5 Description
[4] [3] [2] [1]
SRAM OFF OFF OFF ON
NAND CS 2 OFF OFF ON OFF
External Rom Bus Connector OFF ON OFF OFF
Ethernet ON OFF OFF OFF
4.4.6 CFGB6: SROM BANK5 CHIP SELECTOR CFGB6 component is used to select devices as SROM BUS I/F 5(B_Xm0CSn5/NFCSn3).
CFGB6 Description
[4] [3] [2] [1]
SRAM OFF OFF OFF ON
NAND CS 3 OFF OFF ON OFF
External Rom Bus Connector OFF ON OFF OFF
Ethernet ON OFF OFF OFF
4.4.7 CF,MODEM,CAM_B,KEY,MHL,SROM ADDR SWITCHING CFGB7,8,9 component is used to switching Xmsm signals which are muxed following signals.
(CF Card I/F, Modem I/F, Camera B I/F, Keypad I/F, MHL I/F, SROM Addr[16:22] )
Description CFGB7 CFGB8 CFGB9
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[1] [2] [1] [2] [1] [2]
CF Card OFF OFF ON ON ON/OFF OFF
SROM Addr [22:16] OFF OFF ON ON ON/OFF OFF
MHL I/F OFF ON ON OFF ON/OFF OFF
MODEM I/F OFF OFF ON OFF ON/OFF OFF
Camera B port ON OFF OFF OFF ON/OFF OFF
Keypad muxed with Xmsm signals OFF OFF ON ON ON ON
Keypad muxed with XEINT signals ON OFF
4.4.8 CFGB10: Audio Port CFGB10 component is used to select devices as Audio I/F 1,2.
Audio2 Audio1 Description
[2] [1]
OFF SPDIF Out AC97(WM9713)
ON IIS/PCM(WM8580) IIS/PCM(WM8580)
4.4.9 CFGB11: Audio Codec(WM8580) Master clock selection CFGB11 Mater Clock source
[1] I2S0 CDCLK
[2] I2S1,2 CDCLK
[3] External CLK
[4] External Voice CLK
[5] External HDMI Audio CLK
[6] AP CLKOUT
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4.4.10 CFGB12: Audio Device Input/Output Connection CFGB12 Description
[1] : Speaker
[2] : MIC
[3] : Line In
OFF: IIS (WM8580)
ON: AC97 (WM9713)
[4] : WM8580 OFF: Line In ON: MIC
4.4.11 CFGB13: UART/IrDA Connection CFGB13 component is used to select COM2(CON15) Port connection.
CFGB13 [1] [2] [3] [4]
UART1 OFF X X X
UART2 ON OFF X X
UART3 ON ON OFF X
IrDA X X ON X
4.5 LED & SWITCH Description
4.5.1 LED description <CPU Board>
1. LED4: 5V Power(adapter) Status
2. LED5: System power(from PMIC) Status
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3. LED3: Card Insertion status of MMC slot 0
4. LED1: Card Insertion status of MMC slot 1
5. LED2: Card Insertion status of MMC slot 2
<Base Board>
6. LED1: CF card Power status
7. LED2,3,4: Ethernet status
8. LED6: For debugging (GPH2_4)
9. LED7: For debugging (GPH2_5)
10. LED8: For debugging (GPH2_6)
11. LED9: For debugging (GPH2_7)
12. LED10: 5V Power(adapter) Status
4.5.2 Switch description <CPU Board>
1. SW2 : Warm reset switch
2. SW3: System reset switch
3. SW1: Power On switch
<Base Board>
4. SW6 : For EINT test (XEINT4)
5. SW7 : For EINT test (XEINT31)
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5 SMDK Daughter Board Each Daughter board can be connected on SMDK connector.
5.1 External OneNAND External OneNAND can be mounted on CON14.
5.1.1 Real view
Figure 10 External OneNAND
5.1.2 Schematic
EXTERNAL_ONENAND.pdf
5.2 CSI Daughter Board CSI Daughter Board can be mounted on CON2.
5.2.1 Real view
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Figure 11 CSI Daughter Board
5.2.2 Schematic
CSI_daughter_BOARD.pdf
5.3 DSI Daughter Board DSI Daughter Board can be mounted on CON1.
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5.3.1 Real view
Figure 12 DSI Daughter Board
5.3.2 Schematic
MIPI-LCM&LAN_BD_SCHEMATIC_R
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6 SMDK SCHEMATIC REVISION HISTORY
This document contains information of corrected points on the schematic of SMDK S5PV210.
Boards Page Contents Corrected points (ECN)
CPU Board
Base Board
LCD Board
7 SMDK SCHEMATIC There are 3 parts of SMDK Schematic.
1. CPU & Base Board Rev0.1
2. LCD Board Rev0.1
SMDKV210_CPU_REV0_1.pdf
SMDKV210_BASE_BD_SCH_REV01.p
S5PV210_SMDK_LCD_SCHEMATIC_V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Revision History 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
1 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Revision History 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
1 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Revision History 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
1 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
Date
<Component><Number>---------------------------------------------------U : Component or Regurator ICC : CapacitorCB : Capacitor BypassCT : Capacitor TantalCTB : Capacitor Tantal BypassJ : JumperJB : CPU To Base connectorJP : Jumper PowerR : ResistorRA : Resistor ArrayRP : Resistor PowerVR : Variable ResistorL : InductorFB : Ferrite BeadOSC : OscillatorX : X-tal (Crystal)Q : Transistor or FETD : DiodeZD : Zener DiodeLED : LED DiodeSW : SWitch Tact/PushCON : CONnectorCFG : ConFiGure switch (DIP/Slide)TP : Test Point (SMD)TPH : Test Point Hole (Through Hole)MTH: Mount Through HoleMOD : MODule Interface connector
SMDK_S5PV210_CPU B'd (S5PV210 Evaluation Board) Schematics
Part Reference
Revision
Page Function-------------------------------------------------------01 Revision History02 S5PV210 (SYS&Connectivity)/ Boot Option03 S5PV210 (MCP & SROM Memory)04 S5PV210 (Media)05 S5PV210 (Gen_Power)06 XM1 DDR2(1Gbit *2) #0,1 07 XM1 DDR2(1Gbit *2) #2,308 XM2 DDR2(1Gbit *2) #0,1 09 XM1 DDR2(1Gbit *2) #2,3 10 Power Jumper shunt11 Power (DC jack & Regulator) 12 Reset/ Clock Source/ JTAG13 Power (PMIC)14 Memory (SROM EBI IF)15 OneNAND / LCD I/F(NonMIPI)16 MMC #017 MMC #1/#2/ HS-SPI 18 Camera A-Port I/F19 HDMI/ MIPI-CSI/ MIPI-HSI/ USB20 MIPI-DSI21 B2B Connector(CPU)
Preliminary Version
Description
Table of Contents
2009. 09Rev 0.0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XOM2
XOM5
XOM0XOM1
XOM4XOM3
VDD_SYS
VDD_EXT
XjTDI [12]
XXTI [12]
XjTMS [12]XjTCK [12]
XjTRSTn [12]
XjTDO [12]
XusbXTI [12]XXTO [12]
XusbXTO [12]
XpwmTOUT0 [21]XpwmTOUT1 [21]XpwmTOUT2 [21]XpwmTOUT3/PWM_MIE [15,20,21]
XuRTSn0[21]XuCTSn0[21]
XuRXD0[21]XuTXD0[21]
Xi2cSCL1 [19,20,21]
Xi2cSCL0 [15,18,21]
Xi2cSCL2/IEM_SPWI [13]Xi2cSDA2/IEM_SCLK [13]
Xi2cSDA1 [19,20,21]
Xi2cSDA0 [15,18,21]
XEINT1 [13,21]
XEINT12/HDMI_CEC [19]
XEINT28/KP_ROW4 [21]
XEINT20/KP_COL4 [21]
XEINT6 [15,20]
XEINT8 [17]
XEINT5 [18,21]
XEINT25/KP_ROW1 [17,21]
XEINT11 [21]
XEINT13/HDMI_HPD [19]
XEINT21/KP_COL5 [21]
XEINT26/KP_ROW2 [21]
XEINT4 [13,21]
XEINT14 [13,21]
XEINT17/KP_COL1 [20,21]
XEINT0/PSHOLD [13]
XEINT9 [21]
XEINT7 [16]
XEINT23/KP_COL7 [21]
XEINT16/KP_COL0 [21]
XEINT30/KP_ROW6 [21]XEINT29/KP_ROW5 [21]
XEINT31/KP_ROW7 [21]
XEINT10 [18,21]
XEINT2 [18,21]
XEINT15 [13,21]
XEINT18/KP_COL2 [21]
XEINT24/KP_ROW0 [19,21]
XEINT3 [19,21]
XEINT19/KP_COL3 [21]
XEINT22/KP_COL6 [21]
XEINT27/KP_ROW3 [18,21]
XuRTSn1[21]XuCTSn1[21]
XuTXD1[21]XuRXD1[21]
XuRXD2/UART_AUDIO_RXD[12,21]XuTXD2/UART_AUDIO_TXD[12,21]
XuRXD3/CTSn2/UART_AUDIO_CTSn[21]XuTXD3/RTSn2/UART_AUDIO_RTSn[21]
XspiCSn0[17]XspiCLK0[17]
XspiMISO0[17]XspiMOSI0[17]
XspiCLK1[17]
XspiMOSI1[17]
XspiCSn1[17]XspiMISO1[17]
Xmmc2CMD/SPI_2_nSS[17]
Xmmc2DATA0/SPI_2_MOSI[17]
Xmmc2DATA2[17]
Xi2sSDO1/PCM_SOUT1/AC97_SDO[21]
Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[21]
Xmmc0DATA1[16]
Xmmc0CLK[16]
Xmmc2CLK/SPI_2_CLK[17]
Xi2sLRCK0/PCM_FSYNC2[21]
Xmmc2CDn/SPI_2_MISO[17]
Xmmc1CMD[16]Xmmc1CDn[16]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2[21]
Xmmc1DATA3/MMC0_DATA7[16]
Xi2sSDO0_0/PCM_SOUT2[21]
Xmmc1DATA1/MMC0_DATA5[16]
XpcmSOUT0/Xi2sSDO2[21]
Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[21]
Xmmc0DATA2[16]
Xmmc0CMD[16]
Xmmc1DATA0/MMC0_DATA4[16]
Xi2sCDCLK0/PCM_EXTCLK2[21]
Xi2sSDI0/PCM_SIN2[21]
Xi2sSDO0_2[21]
Xmmc1DATA2/MMC0_DATA6[16]
Xmmc1CLK[16]
Xmmc0CDn[16]
Xi2sSCLK0/PCM_SCLK2[21]
Xi2sSDO0_1[21]
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2[21]XpcmSIN0/Xi2sSDI2[21]
Xmmc0DATA0[16]
Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[21]
Xmmc2DATA1[17]
Xmmc2DATA3[17]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2[21]
Xmmc0DATA3[16]
Xi2sSDI1/PCM_SIN1/AC97_SDI[21]
XuhDN[19]XuhREXT[19]
XuhPWREN[19]
XuhDP[19]
XuhOVERCUR[19]
XuoDM[19]
XuoID[19]XuoVBUS[19]
XuoDRVVBUS[19]
XuoDP[19]
XuoREXT[19]
Xmmc3DATA1/MMC2_DATA5[17]
Xmmc3CMD[17]
Xmmc3DATA0/MMC2_DATA4[17]
Xmmc3CLK[17]
Xmmc3CDn[17]
Xmmc3DATA2/MMC2_DATA6[17]Xmmc3DATA3/MMC2_DATA7[17]
XOM0[21]XOM1[21]XOM2[21]XOM3[21]XOM4[21]XOM5[21]
XrtcXTO [12]XrtcXTI [12]
XhdmiXTI [12]XhdmiXTO [12]
XRTCCLKO
XCLKOUT [21]
XnRESET [12,21]XnWRESET [12]
XnRSTOUT
XPWRRGTON [13]
Title
Size Document Number Rev
Date: Sheet of
S5PV210 (SYS&Connectivity)/ Boot Option 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
2 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (SYS&Connectivity)/ Boot Option 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
2 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (SYS&Connectivity)/ Boot Option 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
2 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
BootingMode OptionSelection
596 PinFCFBGA
<Silk>OM[5:0]
OneNAND DeMux(Audi)
NAND 4KB-5cycle 8-ECC0: Storage
0: X-TAL
NAND 4KB-5cycle 16-ECC
0 0 0 0
0 0 1 1
0 0 0 1
0 1 1 1
0 0 1 0
1 0 0 0
1 0 0 1
1:USB->UART->Storage
0 1 1 0
1 0 1 0
0 1 0 0
OM[4:1]
0 1 0 1
1 0 1 1
OneNAND Mux(Audi)
OM[5]
SD/MMC
BootSeq.
eMMC(4bit)
Reserved
NAND 2KByte Page, 4cycle
iROM NOR boot
NAND 512B-4cycle
1:X-TAL(USB)
eMMC(8bit)
OM[0]
NAND 2KB-5cycle
Storage
0: Storage
<Silk>
* OM can be tied VDD or GND directly.
<I2C pull-up resistor>For High speed - 1KohmFor HDMI - 1.8Kohm
R270 100KR270 100K
R274 100KR274 100K
R277 100KR277 100K
R278 1KR278 1K
TP57TP57
R271 100KR271 100K
CB1721.8nFCB1721.8nF
R279 1KR279 1K
R273 100KR273 100K
R276 0R276 0TP59TP59
R272 100KR272 100K
UART/IrDA
HS-SPI
USB OTG 2.0
HS-MMC
I2S/PCM/AC97
PWM Timer
CLOCK
JTAG
EINTKEYPAD
SYSTEMOPTION
RESET
SYSTEM
I2C
(VDD_EXT0)
(VDD_EXT1)
(VDD_EXT0)
(VDD_EXT2)
(VDD_UOTG_A)
USB HOST 2.0(VDD_UHOST_A)
(VDD_AUD)
(VDD_EXT0)
(VDD_EXT1)
(VDD_EXT2)
(VDD_SYS0)
(VDD_EXT0)
(VDD_SYS0)
(VDD_SYS1)
(VDD_KEY)
(VDD_EXT0)
(VDD_EXT1)
(VDD_SYS0)
(VDD_SYS0)
RTC CLOCK(VDD_RTC)
(VDD_CKO)
EPLL Filter
U55A
S5PV210
UART/IrDA
HS-SPI
USB OTG 2.0
HS-MMC
I2S/PCM/AC97
PWM Timer
CLOCK
JTAG
EINTKEYPAD
SYSTEMOPTION
RESET
SYSTEM
I2C
(VDD_EXT0)
(VDD_EXT1)
(VDD_EXT0)
(VDD_EXT2)
(VDD_UOTG_A)
USB HOST 2.0(VDD_UHOST_A)
(VDD_AUD)
(VDD_EXT0)
(VDD_EXT1)
(VDD_EXT2)
(VDD_SYS0)
(VDD_EXT0)
(VDD_SYS0)
(VDD_SYS1)
(VDD_KEY)
(VDD_EXT0)
(VDD_EXT1)
(VDD_SYS0)
(VDD_SYS0)
RTC CLOCK(VDD_RTC)
(VDD_CKO)
EPLL Filter
U55A
S5PV210
XuRXD0/GPA0_0C8XuTXD0/GPA0_1D8XuCTSn0/GPA0_2D9XuRTSn0/GPA0_3A7
XuRXD1/GPA0_4G10XuTXD1/GPA0_5F10XuCTSn1/GPA0_6B8XuRTSn1/GPA0_7E10
XuRXD2/UART_AUDIO_RXD/GPA1_0AC20XuTXD2/UART_AUDIO_TXD/GPA1_1AC14
XuRXD3/CTSn2/UART_AUDIO_CTSn/GPA1_2AC13XuTXD3/RTSn2/UART_AUDIO_RTSn/GPA1_3AB13
XspiMISO0/GPB2J9
XspiCLK0/GPB0B7
XspiMOSI0/GPB3J11
XspiCSn0/GPB1E9
XspiMISO1/GPB6G13
XspiCLK1/GPB4G12
XspiMOSI1/GPB7A11
XspiCSn1/GPB5B11
XuhDPAE19XuhDMAD19
XuoDMAE21
XuoVBUSAC18 XuoIDAD18 XuoREXTAE18
Xmmc1CLK/GPG1_0B6Xmmc1CMD/GPG1_1F8
Xmmc1DATA0/Xmmc0DATA4/GPG1_3D7Xmmc1DATA1/Xmmc0DATA5/GPG1_4E7Xmmc1DATA2/Xmmc0DATA6/GPG1_5A6Xmmc1DATA3/Xmmc0DATA7/GPG1_6F9
Xmmc0CLK/GPG0_0B5Xmmc0CMD/GPG0_1E6
Xmmc0DATA0/GPG0_3C5Xmmc0DATA1/GPG0_4A5Xmmc0DATA2/GPG0_5D6Xmmc0DATA3/GPG0_6C6
Xmmc0CDn/GPG0_2F7
Xi2sLRCK0/PCM_FSYNC2AE3 Xi2sCDCLK0/PCM_EXTCLK2AC4 Xi2sSCLK0/PCM_SCLK2AD2
Xi2sSDI0/PCM_SIN2AE2Xi2sSDO0_0/PCM_SOUT2AD3Xi2sSDO0_1AC3Xi2sSDO0_2AA3
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2/GPC1_0AA2XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2/GPC1_1AA1XpcmFSYNC0/LCD_FRM/Xi2sLRCK2/GPC1_2AB1
XEINT0/GPH0_0 Y21XEINT1/GPH0_1 W25XEINT2/GPH0_2 W23XEINT3/GPH0_3 Y25XEINT4/GPH0_4 AA22XEINT5/GPH0_5 W24XEINT6/GPH0_6 W21XEINT7/GPH0_7 AA25XEINT8/GPH1_0 V20XEINT9/GPH1_1 V22
XEINT10/GPH1_2 Y24XEINT11/GPH1_3 W22
XEINT12/HDMI_CEC/GPH1_4 AA24XEINT13/HDMI_HPD/GPH1_5 AC23
XEINT14/GPH1_6 AB25XEINT15/GPH1_7 W20
XpwmTOUT2/GPD0_2 A8XpwmTOUT1/GPD0_1 B9XpwmTOUT0/GPD0_0 E8
XrtcXTI T24XrtcXTO T25
XXTI U24XXTO U25
XjTRSTn P5XjTMS R5XjTCK U4XjTDI T5
XjTDO W3XjDBGSEL P3
XOM0 T23XOM1 T22XOM2 V23XOM3 U21XOM4 V25
XPWRRGTON U22
XCLKOUT AE24
XnRESET U23XnRSTOUT T20
XpcmSIN0/Xi2sSDI2/GPC1_3AB2XpcmSOUT0/Xi2sSDO2/GPC1_4AC1
Xmmc2CLK/SPI_CLK2/GPG2_0Y6Xmmc2CMD/SPI_CSn2/GPG2_1W6
Xmmc2DATA0/SPI_MOSI2/GPG2_3Y4Xmmc2DATA1/GPG2_4Y5Xmmc2DATA2/GPG2_5Y3Xmmc2DATA3/GPG2_6W4
Xmmc1CDn/GPG1_2C7
Xmmc2CDn/SPI_MISO2/GPG2_2AA4
XusbXTI AD20XusbXTO AE20
XEINT16/KP_COL0/GPH2_0 U20XEINT17/KP_COL1/GPH2_1 Y23XEINT18/KP_COL2/GPH2_2 V21XEINT19/KP_COL3/GPH2_3 AB24XEINT20/KP_COL4/GPH2_4 AA21XEINT21/KP_COL5/GPH2_5 AA23XEINT22/KP_COL6/GPH2_6 AC25XEINT23/KP_COL7/GPH2_7 Y20
XEINT24/KP_ROW0/GPH3_0 AC24XEINT25/KP_ROW1/GPH3_1 AB22XEINT26/KP_ROW2/GPH3_2 AD25XEINT27/KP_ROW3/GPH3_3 Y22XEINT28/KP_ROW4/GPH3_4 AD24XEINT29/KP_ROW5/GPH3_5 AA20XEINT30/KP_ROW6/GPH3_6 Y19XEINT31/KP_ROW7/GPH3_7 AB23
XuhREXTAC17
Xmmc3CLK/GPG3_0A9Xmmc3CMD/GPG3_1D10Xmmc3CDn/GPG3_2E11Xmmc3DATA0/Xmmc2DATA4/GPG3_3B10Xmmc3DATA1/Xmmc2DATA5/GPG3_4C10Xmmc3DATA2/Xmmc2DATA6/GPG3_5D11Xmmc3DATA3/Xmmc2DATA7/GPG3_6A10
XOM5 V24
XpwmTOUT3/PWM_MIE/GPD20_3 F12
Xi2sSCLK1/PCM_SCLK1/AC97BITCLK/GPC0_0AD1Xi2sCDCLK1/PCM_EXTCLK1/AC97RESETn/GPC0_1AB3Xi2sLRCK1/PCM_FSYNC1/AC97SYNC/GPC0_2AC2Xi2sSDI1/PCM_SIN1/AC97SDI/GPC0_3AA5Xi2sSDO1/PCM_SOUT1/AC97SDO/GPC0_4AB4
Xi2cSDA0/GPD1_0 F11Xi2cSCL0/GPD1_1 C9Xi2cSDA1/GPD1_2 AE23Xi2cSCL1/GPD1_3 AD22
Xi2cSDA2/IEM_SCLK/GPD1_4 AC16Xi2cSCL2/IEM_SPWI/GPD1_5 AE22
XuoDRWBUSAC19
XuhPWRENAD23XuhOVERCURAC22
XnWRESET T21
XRTCCLKO R22
XhdmiXTI Y2XhdmiXTO Y1
XuoDPAD21
XefFSOURCE AD4
NC/EPLL(evt1) R21
TP58TP58
R282 1KR282 1K
R280 1.8KR280 1.8KR281 1.8KR281 1.8K
R275 100KR275 100K
R283 1KR283 1K
CFG4KHS06
CFG4KHS06
123487
6 59 10 11 12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm0DATA13
Xm0ADDR8
Xm0ADDR6
Xm0DATA2
Xm0ADDR12
Xm0DATA6
Xm0ADDR15
Xm0DATA10
Xm0ADDR1
Xm0DATA12
Xm0ADDR5
Xm0ADDR11
Xm0DATA5
Xm0ADDR14
Xm0DATA9
Xm0ADDR0
Xm0ADDR4
Xm0DATA15
Xm0ADDR10
Xm0DATA4
Xm0DATA8
Xm0DATA1
Xm0ADDR3
Xm0DATA14
Xm0ADDR9
Xm0ADDR7
Xm0DATA3
Xm0ADDR13
Xm0DATA7
Xm0DATA0
Xm0DATA11
Xm0ADDR2
Xm1ADDR0Xm1ADDR1Xm1ADDR2Xm1ADDR3Xm1ADDR4Xm1ADDR5Xm1ADDR6Xm1ADDR7Xm1ADDR8Xm1ADDR9Xm1ADDR10Xm1ADDR11Xm1ADDR12Xm1ADDR13
Xm1DATA0Xm1DATA1Xm1DATA2Xm1DATA3Xm1DATA4Xm1DATA5Xm1DATA6Xm1DATA7Xm1DATA8Xm1DATA9Xm1DATA10Xm1DATA11Xm1DATA12Xm1DATA13Xm1DATA14Xm1DATA15Xm1DATA16Xm1DATA17Xm1DATA18Xm1DATA19Xm1DATA20Xm1DATA21Xm1DATA22Xm1DATA23Xm1DATA24Xm1DATA25Xm1DATA26Xm1DATA27Xm1DATA28Xm1DATA29Xm1DATA30Xm1DATA31
Xm1DQS0
Xm1DQS1
Xm1DQS2
Xm1DQS3
Xm1DQSn0
Xm1DQSn1
Xm1DQSn2
Xm1DQSn3Xm1DM0Xm1DM1Xm1DM2Xm1DM3Xm1SCLKXm1SCLKn
Xm1BA0Xm1BA1Xm1CASnXm1RASnXm1WEnXm1CKE0
Xm1CSn0Xm1CSn1/BA2
Xm2ADDR0Xm2ADDR1Xm2ADDR2Xm2ADDR3Xm2ADDR4Xm2ADDR5Xm2ADDR6Xm2ADDR7Xm2ADDR8Xm2ADDR9Xm2ADDR10Xm2ADDR11Xm2ADDR12Xm2ADDR13
Xm2DATA0Xm2DATA1Xm2DATA2Xm2DATA3Xm2DATA4Xm2DATA5Xm2DATA6Xm2DATA7Xm2DATA8Xm2DATA9Xm2DATA10Xm2DATA11Xm2DATA12Xm2DATA13Xm2DATA14Xm2DATA15Xm2DATA16Xm2DATA17Xm2DATA18Xm2DATA19Xm2DATA20Xm2DATA21Xm2DATA22Xm2DATA23Xm2DATA24Xm2DATA25Xm2DATA26Xm2DATA27Xm2DATA28Xm2DATA29Xm2DATA30Xm2DATA31
Xm2CASnXm2RASn
Xm2DQSn0
Xm2DM1Xm2DM2Xm2DM3Xm2SCLK
Xm2CSn0Xm2CSn1/BA2
Xm2DQSn1
Xm2DQSn2
Xm2DQSn3
Xm2DQS0
Xm2DM0
Xm2SCLKn
Xm2DQS1
Xm2DQS2
Xm2DQS3
Xm2BA0Xm2BA1
Xm2WEnXm2CKE0
Xm1ADDR14 Xm2ADDR14
VDD_MEM
VDD_SYS
Xm0ADDR[15:0][14,15]
Xm0DATA[15:0][14,15]
Xm0CSn0 [14]Xm0CSn1 [14]Xm0CSn2/NFCSn0 [14,15]Xm0CSn3/NFCSn1 [14]Xm0CSn4/NFCSn2/ONANDXL_CSn0 [14]
Xm0OEn [14,15]Xm0CSn5/NFCSn3/ONANDXL_CSn1 [14]
Xm0BE0 [14]Xm0WEn [14,15]
Xm0DATA_RDn [14,21]Xm0WAITn [21]
Xm0FCLE/ONDXL_AVD [14,15]
Xm0FWEn/ONDXL_RPn [14,15]
Xm0FRnB1/ONDXL_INT1 [14,21]
Xm0FALE/ONDXL_SMCLK [14,15]
Xm0FRnB3 [21]Xm0FRnB2 [21]
Xm0FRnB0/ONDXL_INT0 [14,21]Xm0FREn [14,15]
Xm0BE1 [14]
Xm1ADDR[13:0][6,7]
Xm1DATA[31:0][6,7]
Xm1BA0[6,7]Xm1BA1[6,7]Xm1CASn[6,7]Xm1RASn[6,7]Xm1WEn[6,7]Xm1CKE0[6,7]
Xm1CSn0[6,7]Xm1CSn1/BA2[6,7]Xm1DQS0[6]Xm1DQSn0[6]Xm1DQS1[6]Xm1DQSn1[6]Xm1DQS2[7]Xm1DQSn2[7]Xm1DQS3[7]Xm1DQSn3[7]Xm1DM0[6]Xm1DM1[6]Xm1DM2[7]Xm1DM3[7]Xm1SCLK[6,7]Xm1SCLKn[6,7]
Xm2DATA[31:0] [8,9]
Xm2ADDR[13:0] [8,9]
Xm2SCLKn [8,9]
Xm2CSn1/BA2 [8,9]Xm2DQS0 [8]Xm2DQSn0 [8]Xm2DQS1 [8]Xm2DQSn1 [8]Xm2DQS2 [9]Xm2DQSn2 [9]
Xm2BA0 [8,9]
Xm2DQS3 [9]
Xm2BA1 [8,9]
Xm2DQSn3 [9]
Xm2CASn [8,9]
Xm2DM0 [8]
Xm2RASn [8,9]
Xm2DM1 [8]Xm2DM2 [9]Xm2DM3 [9]Xm2SCLK [8,9]
Xm2CSn0 [8,9]
Xm2CKE0 [8,9]Xm2WEn [8,9]
Xm2ADDR14 [8,9]
Title
Size Document Number Rev
Date: Sheet of
S5PV210 (DRR2 & SROM Memory) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
3 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (DRR2 & SROM Memory) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
3 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (DRR2 & SROM Memory) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
3 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
XM1,2 MEMORY InterfaceOneNAND Interface
TP56TP56
Memory Port0SROM/NAND/ONENAND
(VDD_M0)
(VDD_SYS0)
(VDD_M1)
Memory Port1DDR2/mDDR/mDDR2
(VDD_M2)
Memory Port2DDR2/mDDR/mDDR2
U55B
S5PV210
Memory Port0SROM/NAND/ONENAND
(VDD_M0)
(VDD_SYS0)
(VDD_M1)
Memory Port1DDR2/mDDR/mDDR2
(VDD_M2)
Memory Port2DDR2/mDDR/mDDR2
U55B
S5PV210
Xm0ADDR0/MP04_0K5Xm0ADDR1/MP04_1L7Xm0ADDR2/MP04_2J4Xm0ADDR3/MP04_3H5Xm0ADDR4/MP04_4J6Xm0ADDR5/MP04_5K4Xm0ADDR6/MP04_6K6Xm0ADDR7/MP04_7J5Xm0ADDR8/MP05_0H4Xm0ADDR9/MP05_1G4Xm0ADDR10/MP05_2J3Xm0ADDR11/MP05_3K7Xm0ADDR12/MP05_4H6Xm0ADDR13/MP05_5G5Xm0ADDR14/MP05_6F4Xm0ADDR15/MP05_7H3
Xm0DATA0/MP06_0K3Xm0DATA1/MP06_1L3Xm0DATA2/MP06_2L5Xm0DATA3/MP06_3M4Xm0DATA4/MP06_4N1Xm0DATA5/MP06_5N2Xm0DATA6/MP06_6P1Xm0DATA7/MP06_7N4Xm0DATA8/MP07_0L1Xm0DATA9/MP07_1L2Xm0DATA10/MP07_2L4Xm0DATA11/MP07_3M1Xm0DATA12/MP07_4M3Xm0DATA13/MP07_5M5Xm0DATA14/MP07_6N5Xm0DATA15/MP07_7P2
XDDR2SEL AB18
Xm0CSn0/MP01_0 U3Xm0CSn1/MP01_1 T4
Xm0CSn2/NFCSn0/MP01_2 J1Xm0CSn3/NFCSn1/MP01_3 N9
Xm0CSn4/NFCSn2/ONANDXL_CSn0/MP01_4 N3Xm0CSn5/NFCSn3/ONANDXL_CSn1/MP01_5 N7
Xm0OEn/MP01_6 R4Xm0WEn/MP01_7 P4Xm0BE0/MP02_0 T3Xm0BE1/MP02_1 N6
Xm0WAITn/MP02_2 W2Xm0DATA_RDn/MP02_3 M7
Xm0FCLE/ONDXL_AVD/MP03_0 K1Xm0FALE/ONDXL_SMCLK/MP03_1 K2
Xm0FWEn/ONDXL_RPn/MP03_2 J2Xm0FREn/MP03_3 M2
Xm0FRnB0/ONDXL_INT0/MP03_4 R3Xm0FRnB1/ONDXL_INT1/MP03_5 M6
Xm0FRnB2/MP03_6 V3Xm0FRnB3/MP03_7 L6
Xm1ADDR0E21Xm1ADDR1E20Xm1ADDR2E17Xm1ADDR3E15Xm1ADDR4D18Xm1ADDR5F15Xm1ADDR6D19Xm1ADDR7D20Xm1ADDR8E18Xm1ADDR9F16Xm1ADDR10F19Xm1ADDR11F14Xm1ADDR12E19Xm1ADDR13F18Xm1BA0E16Xm1BA1D21Xm1CASnF17Xm1RASnE12Xm1WEnG17Xm1CKE0G15Xm1CKE1/ADDR14G16Xm1CSn0G18Xm1CSn1G14Xm1DQS0B22
Xm1DQS1B18
Xm1DQS3D12
Xm1DQS2A15
Xm1DQSn3C12
Xm1DQSn1A18
Xm1DQSn2B15
Xm1DQSn0A22
Xm1DM2D14 Xm1DM1D17
Xm1DM3C11
Xm1DM0C21
Xm1SCLKnB16 Xm1SCLKA16
Xm1DATA0A24Xm1DATA1C22Xm1DATA2B23Xm1DATA3A23Xm1DATA4B21Xm1DATA5A21Xm1DATA6C20Xm1DATA7C19Xm1DATA8B19Xm1DATA9B20Xm1DATA10A20Xm1DATA11A19Xm1DATA12C18Xm1DATA13A17Xm1DATA14B17Xm1DATA15C17Xm1DATA16D16Xm1DATA17C16Xm1DATA18D15Xm1DATA19C15Xm1DATA20E13Xm1DATA21E14Xm1DATA22F13Xm1DATA23C14Xm1DATA24D13
Xm1DATA26A14 Xm1DATA25B14
Xm1DATA27C13Xm1DATA28B13Xm1DATA29A13Xm1DATA30B12Xm1DATA31A12
Xm2ADDR7 J19Xm2ADDR8 G20Xm2ADDR9 H19
Xm2ADDR10 K22Xm2ADDR11 H23Xm2ADDR12 J22Xm2ADDR13 H20
Xm2BA0 J20Xm2BA1 K20
Xm2CASn J23Xm2RASn J21Xm2WEn P22
Xm2CKE0 J24Xm2CKE1/ADDR14 G21
Xm2CSn0 N21Xm2CSn1 K21Xm2DQS0 N24
Xm2DQSn0 N25Xm2DQS1 L24
Xm2DQSn1 L25Xm2DQS2 F24
Xm2DQSn2 F25Xm2DQS3 C24
Xm2DQSn3 C25Xm2DM0 P25Xm2DM1 L22Xm2DM2 H21Xm2DM3 E22
Xm2SCLK G24Xm2SCLKn G25
Xm2DATA0 P23Xm2DATA1 R24Xm2DATA2 R25Xm2DATA3 P24Xm2DATA4 N23Xm2DATA5 M22Xm2DATA6 N22Xm2DATA7 M23Xm2DATA8 M21Xm2DATA9 M24
Xm2DATA10 L23Xm2DATA11 M25Xm2DATA12 K25Xm2DATA13 K23Xm2DATA14 J25Xm2DATA15 K24Xm2DATA16 H25Xm2DATA17 H24Xm2DATA18 G23Xm2DATA19 G22Xm2DATA20 F23Xm2DATA21 E25Xm2DATA22 E24Xm2DATA23 E23Xm2DATA24 D25Xm2DATA25 D24Xm2DATA26 D23Xm2DATA27 F22Xm2DATA28 D22Xm2DATA29 B25Xm2DATA30 C23Xm2DATA31 B24
Xm2ADDR0 L20Xm2ADDR1 L19Xm2ADDR2 L21Xm2ADDR3 R23Xm2ADDR4 F21Xm2ADDR5 F20Xm2ADDR6 H22
R26
34.
7KR
263
4.7K
R26
74.
7KR
267
4.7K
R26
64.
7KR
266
4.7K
R269
NC
R269
NC
R26
44.
7KR
264
4.7K
R268
100K
R268
100K
R26
54.
7KR
265
4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AXadcAIN9XadcAIN7
XadcAIN4XadcAIN3XadcAIN5
XadcAIN1XadcAIN0
XvVD5XvVD4
XvVD0
XvVD23
XvVD20
XvVD16
XvVD8
XvVD17
XvVD6
XvVD1
XvVD21
XvVD18
XvVD14
XvVD9
XvVD7
XvVD2XvVD3
XvVD10
XvVD22
XvVD15
XvVD12
XvVD19
XvVD13
XvVD11
XdacOUT_0
XdacOUT_0
XadcAIN0XadcAIN1XadcAIN2XadcAIN3XadcAIN4XadcAIN5XadcAIN6XadcAIN7XadcAIN8XadcAIN9
XadcAIN2
XadcAIN6XadcAIN8
VDD_DAC
VDD_DAC_AP
XvVD[23:0][15]
SYS_OE/VEN_FIELD[15]VSYNC_LDI[15]
XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA [20,21]
XhdmiTX2N [19]
XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3 [21]
XhdmiTX2P [19]
XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0 [21]XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR [20,21]
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK [20,21]
XhdmiTXCP [19]
XhdmiTX0P [19]
XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC [20,21]
XhdmiTX1P [19]
XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2 [21]
XmsmADDR13/KP_COL0/SROM_ADDR21/MHL_D6 [21]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK [20,21]
XhdmiREXT [19]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK [20,21]
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1 [21]
XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4 [21]XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5 [21]
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL [20,21]
XhdmiTX0N [19]
XhdmiTXCN [19]
XhdmiTX1N [19]
XvVCLK/SYSWE/V601CLK[15]XvVDEN/SYSRC/VENHREF[15]
XvHSYNC/SYSCS0/VENHSYNC[15]XvVSYNC/SYSCS1/VENVSYNC[15]
XmipiSDN2 [19]
XmipiSDN0 [19]XmipiSDP0 [19]
XmipiSDN3 [19]
XmipiSDN1 [19]XmipiSDP2 [19]
XmipiSDP1 [19]
XmipiSDP3 [19]
XmipiSDPCLK [19]XmipiSDNCLK [19]
XmipiMDNCLK [20]XmipiMDPCLK [20]
XmipiMDN2 [20]
XmipiMDN1 [20]
XmipiMDN0 [20]XmipiMDP1 [20]
XmipiMDP0 [20]
XmipiMDP2 [20]
XmipiMDP3 [20]XmipiMDN3 [20]
XmsmDATA4/KP_COL5/CF_DATA4/MHL_D11 [21]
XmsmDATA14/KP_ROW7/CF_DATA14/MHL_D21 [21]
XmsmDATA11/KP_ROW4/CF_DATA11/MHL_D18 [21]
XmsmDATA3/KP_COL4/CF_DATA3/MHL_D10 [21]
XmsmDATA7/KP_ROW0/CF_DATA7/MHL_D14 [21]
XmsmDATA12/KP_ROW5/CF_DATA12/MHL_D19 [21]
XmsmDATA6/KP_COL7/CF_DATA6/MHL_D13 [21]
XmsmDATA8/KP_ROW1/CF_DATA8/MHL_D15 [21]XmsmDATA9/KP_ROW2/CF_DATA9/MHL_D16 [21]
XmsmDATA13/KP_ROW6/CF_DATA13/MHL_D20 [21]
XmsmDATA1/KP_COL2/CF_DATA1/MHL_D8 [21]XmsmDATA0/KP_COL1/CF_DATA0/MHL_D7 [21]
XmsmDATA2/KP_COL3/CF_DATA3/MHL_D9 [21]
XmsmDATA10/KP_ROW3/CF_DATA10/MHL_D17 [21]
XmsmDATA15/KP_ROW8/CF_DATA15/MHL_D22 [21]
XmsmDATA5/KP_COL6/CF_DATA5/MHL_D12 [21]
XmsmWEn/KP_ROW10/CF_CSn1/MHL_HSYNC [21]
XmsmADVN/KP_ROW13/SROM_ADDR22/MHL_DE [21]
XmsmCSn/KP_ROW9/CF_CSn0/MHL_D23 [21]
XmsmREn/KP_ROW11/CF_IORN/MHL_IDCK [21]XmsmIRQn/KP_ROW12/CF_IOWN/MHL_VSYNC [21]
TSXM0 [15]TSYP0 [15]
TSXP0 [15]
TSYM0 [15]
TSXP1 [15]TSXM1 [15]TSYP1 [15]TSYM1 [15]
CAM_A_CLK[18]
CSI_CLK[19]XciFIELD[18]
XciYDATA0[18]
XciYDATA4[18]
XciYDATA6[18]XciYDATA5[18]
XciPCLK[18]
XciHREF[18]
XciYDATA7[18]
XciVSYNC[18]
XciYDATA1[18]XciYDATA2[18]XciYDATA3[18]
DACOUT0 [21]
Title
Size Document Number Rev
Date: Sheet of
S5PV210 (Media) 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
4 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (Media) 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
4 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (Media) 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
4 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
<Silk>ADC Header
ClosetoCON1
Close to AP
2009.10.20. REV0.1 ADD
R256
6.34K/1%
R256
6.34K/1%
+CTB74
10uF/6.3V
+CTB74
10uF/6.3V
CB173100nF CB173100nF
R257 0R257 0
CB169
2nF
CB169
2nF
R26075/1%R26075/1%
C55
100nF
C55
100nF
R2614.7K/1608
R2614.7K/1608
RA50
RA501
357
2468
R26
220
0/1%
R26
220
0/1%
TVOUT DAC
TouchScreen ADC
LCDC
MIPI-DSI/CSI
HDMI
CAM
(VDD_LCD)
(VDD_ADC)
(VDD_DAC_A)
(VDD_CAM)
(VDD_MIPI_A)
(VDD_HDMI)
ModemCamera BCFMHLKeySROM addr[16:22](VDD_MODEM)
U55C
S5PV210
TVOUT DAC
TouchScreen ADC
LCDC
MIPI-DSI/CSI
HDMI
CAM
(VDD_LCD)
(VDD_ADC)
(VDD_DAC_A)
(VDD_CAM)
(VDD_MIPI_A)
(VDD_HDMI)
ModemCamera BCFMHLKeySROM addr[16:22](VDD_MODEM)
U55C
S5PV210
XciHREF/GPE0_2AB14
XciPCLK/GPE0_0AC21
XciCLKenb/GPE1_3AA18
XciVSYNC/GPE0_1AA14
XciYDATA0/GPE0_3AB15XciYDATA1/GPE0_4AB16XciYDATA2/GPE0_5AB20XciYDATA3/GPE0_6AA19XciYDATA4/GPE0_7AB21XciYDATA5/GPE1_0Y18XciYDATA6/GPE1_1AB17XciYDATA7/GPE1_2AA17
XdacOUT_0U5
XdacIREFW5XdacVREFV5XdacCOMPV4
XadcAIN_9AB12 XadcAIN_8AA11 XadcAIN_7AA12 XadcAIN_6Y12 XadcAIN_5W12 XadcAIN_4Y11 XadcAIN_3AC10 XadcAIN_2AB11
XvVD0/SYSD0/VEND0/GPF0_4AA9XvVD1/SYSD1/VEND1/GPF0_5AB9XvVD2/SYSD2/VEND2/GPF0_6AB8XvVD3/SYSD3/VEND3/GPF0_7AB7XvVD4/SYSD4/VEND4/GPF1_0Y9XvVD5/SYSD5/VEND5/GPF1_1AB6XvVD6/SYSD6/VEND6/GPF1_2AE7XvVD7/SYSD7/VEND7/GPF1_3AC9XvVD8/SYSD8/V656D0/GPF1_4AA8XvVD9/SYSD9/V656D1/GPF1_5W9XvVD10/SYSD10/V656D2/GPF1_6AE6XvVD11/SYSD11/V656D3/GPF1_7AC8XvVD12/SYSD12/V656D4/GPF2_0Y8XvVD13/SYSD13/V656D5/GPF2_1AC7XvVD14/SYSD14/V656D6/GPF2_2AD6XvVD15/SYSD15/V656D7/GPF2_3AE5XvVD16/SYSD16/GPF2_4AD7XvVD17/SYSD17/GPF2_5AA7XvVD18/SYSD18/GPF2_6AD5XvVD19/SYSD19/GPF2_7AA6XvVD20/SYSD20/GPF3_0AB5XvVD21/SYSD21/GPF3_1AC5XvVD22/SYSD22/GPF3_2AC6XvVD23/SYSD23/V656_CLK/GPF3_3Y7
XvHSYNC/SYSCS0/VENHSYNC/GPF0_0AA13XvVSYNC/SYSCS1/VENVSYNC/GPF0_1Y10XvVDEN/SYSRS/VENHREF/GPF0_2AB10XvVCLK/SYSWE/V601CLK/GPF0_3AA10
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK/GPJ0_0 H1XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK/GPJ0_1 G6
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK/GPJ0_2 E4XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC/GPJ0_3 H7
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL/GPJ0_4 G1XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA/GPJ0_5 H2
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR/GPJ0_6 F5XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0/GPJ0_7 D5
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1/GPJ1_0 F6XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2/GPJ1_1 G2XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3/GPJ1_2 F1XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4/GPJ1_3 G3
XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5/GPJ1_4 E5
XciFIELD/GPE1_4AB19
XadcAIN_1AC12 XadcAIN_0AC11
XhdmiTX0P T2XhdmiTX0N T1XhdmiTX1P U2XhdmiTX1N U1XhdmiTX2P V2XhdmiTX2N V1XhdmiTXCP R2XhdmiTXCN R1XhdmiREXT W1
XmipiMDP0 AE17XmipiMDN0 AD17XmipiMDP1 AE16XmipiMDN1 AD16XmipiMDP2 AE14XmipiMDN2 AD14XmipiMDP3 AE13XmipiMDN3 AD13
VSYNC_LDI/GPF3_4W8SYS_OE/VEN_FIELD/GPF3_5AE4
XmipiSDP0 AD12XmipiSDN0 AE12XmipiSDP1 AD11XmipiSDN1 AE11XmipiSDP2 AD9XmipiSDN2 AE9XmipiSDP3 AD8XmipiSDN3 AE8
XmipiSDPCLK AD10XmipiSDNCLK AE10
XmsmADDR13/KP_COL_0/SROM_ADDR21/MHL_D6/GPJ1_5 F2
XmsmDATA0/KP_COL_1/CF_DATA0/MHL_D7/GPJ2_0 F3XmsmDATA1/KP_COL_2/CF_DATA1/MHL_D8/GPJ2_1 E2XmsmDATA2/KP_COL_3/CF_DATA2/MHL_D9/GPJ2_2 E1
XmsmDATA3/KP_COL_4/CF_DATA3/MHL_D10/GPJ2_3 D3XmsmDATA4/KP_COL_5/CF_DATA4/MHL_D11/GPJ2_4 D1XmsmDATA5/KP_COL_6/CF_DATA5/MHL_D12/GPJ2_5 E3XmsmDATA6/KP_COL_7/CF_DATA6/MHL_D13/GPJ2_6 D2
XmsmDATA7/KP_ROW_0/CF_DATA7/MHL_D14/GPJ2_7 C1XmsmDATA8/KP_ROW_1/CF_DATA8/MHL_D15/GPJ3_0 C2XmsmDATA9/KP_ROW_2/CF_DATA9/MHL_D16/GPJ3_1 D4
XmsmDATA10/KP_ROW_3/CF_DATA10/MHL_D17/GPJ3_2 B1XmsmDATA11/KP_ROW_4/CF_DATA11/MHL_D18/GPJ3_3 C3XmsmDATA12/KP_ROW_5/CF_DATA12/MHL_D19/GPJ3_4 C4XmsmDATA13/KP_ROW_6/CF_DATA13/MHL_D20/GPJ3_5 B2XmsmDATA14/KP_ROW_7/CF_DATA14/MHL_D21/GPJ3_6 B3XmsmDATA15/KP_ROW_8/CF_DATA15/MHL_D22/GPJ3_7 A2
XmsmCSn/KP_ROW_9/CF_CSn0/MHL_D23/GPJ4_0 G8XmsmWEn/KP_ROW_10/CF_CSn1/MHL_HSYNC/GPJ4_1 B4
XmsmRn/KP_ROW_11/CF_IORN/MHL_IDCK/GPJ4_2 G9XmsmIRQn/KP_ROW_12/CF_IOWN/MHL_VSYNC/GPJ4_3 A3
XmsmADVN/KP_ROW_13/SROM_ADDR22/MHL_DE/GPJ4_4 A4
XmipiVREG_0P4V AC15
XmipiMDPCLK AE15XmipiMDNCLK AD15
CB171
100nF
CB171
100nFU56
NJM2561F1
U56
NJM2561F1
POWER 1VOUT 2VSAG 3VIN4 GND5 V+6
TP55TP55
CON16
A3B-12PA-2DSA
CON16
A3B-12PA-2DSA
579
4
810
13
6
2
11 12
RA40
RA401
357
2468
CB170
100nF
CB170
100nF
+
CTB7633uF/6.3V+
CTB7633uF/6.3V
+
CTB7533uF/6.3V+
CTB7533uF/6.3V
R259 NCR259 NC
R258 0R258 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD_ADC_APVDD_MODEM_AP
VDD_MIPI_A_APVDD_UHOST_A_AP VDD_UOTG_A_AP
VDD_EXT2_AP VDD_CAM_AP
VDD_DAC_AP
VDD_EXT0_AP
VDD_ALIVE_AP VDD_M0_AP VDD_M1_AP
VDD_INT_AP
VDD_EXT1_AP VDD_RTC_AP
VDD_APLL_AP VDD_MPLL_AP
VDD_MIPI_PLL_APVDD_DAC_AP
VDD_MIPI_D_AP
VDD_KEY_APVDD_LCD_AP
VDD_MIPI_PLL_AP
VDD_CAM_AP
VDD_DAC_A_APVDD_HDMI_AP VDD_HDMI_OSC_AP
VDD_M2_AP
VDD_VPLL_APVDD_EPLL_AP
VDD_HDMI_PLL_AP
VDD_UOTG_D_APVDD_MIPI_D_AP
VDD_KEY_AP
VDD_AUD_AP
VDD_CKO_AP
VDD_UHOST_D_AP
VDD_SYS0_AP VDD_SYS1_AP
VDD_LCD_AP
VDD_ARM_AP
VDD_CKO_AP
VDD_MODEM_AP
VDD_MIPI_A_AP
VDD_ARM_AP
VDD_INT_AP
VDD_EXT2_AP
VDD_EXT0_APVDD_RTC_AP
VDD_ALIVE_AP
VDD_M0_AP
VDD_M1_AP
VDD_M2_AP
VDD_ADC_AP
VDD_AUD_AP
VDD_SYS1_AP
VDD_SYS0_AP
VDD_EXT1_AP
VDD_APLL_AP
VDD_VPLL_AP
VDD_MPLL_APVDD_EPLL_AP
VDD_DAC_A_AP
VDD_HDMI_APVDD_HDMI_PLL_APVDD_HDMI_OSC_AP
VDD_UHOST_D_APVDD_UOTG_D_AP
VDD_UOTG_A_APVDD_UHOST_A_AP
Title
Size Document Number Rev
Date: Sheet of
S5PV210 (Gen. Power) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
5 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (Gen. Power) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
5 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
S5PV210 (Gen. Power) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
5 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
CB119
1nF
CB119
1nF
+CTB72
10uF/6.3V
+CTB72
10uF/6.3V
CB146
100nF
CB146
100nF
CB123
100nF
CB123
100nF
CB168
1nF
CB168
1nF
+CTB71
10uF/6.3V
+CTB71
10uF/6.3V
CB99
100nF
CB99
100nF
CB110
1nF
CB110
1nF
CB152
100nF
CB152
100nF
CB132
100nF
CB132
100nF
CB167
1nF
CB167
1nF
+CTB69
10uF/6.3V
+CTB69
10uF/6.3V
CB144
100nF
CB144
100nF
CB161
100nF
CB161
100nF
CB126
100nF
CB126
100nF
CB153
100nF
CB153
100nF
CB102
100nF
CB102
100nF
CB141
100nF
CB141
100nF
CB124
100nF
CB124
100nF
CB108
100nF
CB108
100nF
CB111
1nF
CB111
1nF
CB101
100nF
CB101
100nF
CB100
100nF
CB100
100nF
CB143
100nF
CB143
100nF
CB120
100nF
CB120
100nF
CB109
100nF
CB109
100nF
CB105
100nF
CB105
100nF
CB103
1nF
CB103
1nF
CB134
100nF
CB134
100nF
CB130
100nF
CB130
100nF
CB118
100nF
CB118
100nF
CB128
100nF
CB128
100nF
CB139
100nF
CB139
100nF
+CTB46
10uF/6.3V
+CTB46
10uF/6.3V
CB121
100nF
CB121
100nF
CB166
100nF
CB166
100nF
U55D
S5PV210
U55D
S5PV210
VDD_INT_2K15
VDD_SYS0_2U17
VSS_6 J12
VDD_INT_5M11
VDD_APLLM20
VSS_23 P16
VDD_INT_11R13
VSS_5 G19
VSS_19 N17
VSS_25 R10
VSS_31 T13
VSS_10 K16
VDD_ARM_4M14
VDD_SYS0_0P9
VDD_INT_4L11
VSS_17 M16
VDD_ARM_10P15
VSS_26 R14
VDD_SYS0_1U16
VSS_11 K19
VSS_21 P12
VSS_29 T10
VSS_24 R9
VSS_35 W7
VSS_27 R15
VDD_INT_6N10
VSS_8 K11
VDD_INT_9R11
VSS_2 AE1
VSS_9 K12
VSS_1 A25
VDD_ARM_9P14
VDD_ARM_3M13
VSS_22 P13
VSS_20 P10
VDD_INT_8P11
VSS_13 L12VSS_14 L16
VSS_16 M12
VSS_12 L9
VDD_ARM_0L13VDD_ARM_1L14
VDD_INT_1K14
VSS_7 K10
VSS_32 T14
VDD_INT_10R12
VSS_28 R16
VDD_ARM_7N15
VDD_ARM_2L15
VDD_ARM_6N14
VDD_INT_12T11
VSS_36 W19
VSS_33 T15
VDD_INT_3L10
VDD_RTCP21
VSS_4 G7
VDD_INT_7N11
VSS_3 AE25
VDD_ARM_5M15
VDD_ALIVE_1W15
VSS_30 T12
VSS_34 T16
VDD_ARM_8N16
VSS_15 M10
VSS_18 N12
VDD_INT_0K13
VDD_MPLLN20
VSS_0 A1
VDD_ALIVE_0R17
VDD_M1_0J13VDD_M1_1J14VDD_M1_2J15VDD_M1_3J16
VDD_M2_0J17VDD_M2_1K17VDD_M2_2L17VDD_M2_3M17
VDD_EXT0J10VDD_EXT1_0T9VDD_EXT1_1W18VDD_EXT2G11
VDD_VPLLP20
VDD_SYS1T19
VDD_EPLLR20
VSS_APLL M19VSS_MPLL N19VSS_EPLL R19VSS_VPLL P19
VDD_ADC_0W10
VDD_AUD_0U9VDD_AUD_1U19VDD_CAMV19
VDD_CKOP17
VDD_DACV7
VDD_HDMIP6
VDD_MODEMJ7VDD_KEYT17VDD_LCDU10
VDD_MIPI_D_0U12VDD_MIPI_D_1U13VDD_MIPI_PLLW14VDD_MIPI_AY13
VDD_UHOST_AY16VDD_UOTG_AW16
VDD_DAC_AU7
VDD_UHOST_DW13VDD_UOTG_DU15
VDD_HDMI_OSCT7VDD_HDMI_PLLR6
VDD_M0_0K9VDD_M0_1M9
VSS_ADC_0 W11VSS_DAC V6
VSS_HDMI R7VSS_MIPI_0 U11VSS_MIPI_1 U14VSS_DAC_A U6
VSS_UHOST_A AA15VSS_UOTG_A Y17
VSS_UHOST_AC AA16VSS_UOTG_AC Y15VSS_UHOST_D Y14
VSS_UOTG_D W17VSS_HDMI_OSC T6VSS_HDMI_PLL P7
CB156
1nF
CB156
1nF
CB145
100nF
CB145
100nF
CB131
100nF
CB131
100nF
CB136
1nF
CB136
1nF
CB148
100nF
CB148
100nF
CB135
100nF
CB135
100nF
CB150
100nF
CB150
100nF
CB104
1nF
CB104
1nF
CB117
100nF
CB117
100nF
+CTB44
10uF/6.3V
+CTB44
10uF/6.3V
CB122
100nF
CB122
100nF
CB151
100nF
CB151
100nF
CB127
100nF
CB127
100nF
CB137
100nF
CB137
100nF
CB129
100nF
CB129
100nF
CB147
100nF
CB147
100nF
+CTB48
10uF/6.3V
+CTB48
10uF/6.3V
CB133
100nF
CB133
100nF
CB116
1nF
CB116
1nF
CB138
1nF
CB138
1nF
CB142
100nF
CB142
100nF
CB149
100nF
CB149
100nF
CB157
1nF
CB157
1nF
CB140
1nF
CB140
1nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm1DATA0
Xm1ADDR7Xm1ADDR8Xm1ADDR9Xm1ADDR10Xm1ADDR11Xm1ADDR12
Xm1ADDR0
Xm1ADDR13
Xm1ADDR1Xm1ADDR2Xm1ADDR3Xm1ADDR4Xm1ADDR5Xm1ADDR6
Xm1ADDR7Xm1ADDR8Xm1ADDR9Xm1ADDR10Xm1ADDR11Xm1ADDR12
Xm1ADDR0
Xm1ADDR13
Xm1ADDR1Xm1ADDR2Xm1ADDR3Xm1ADDR4Xm1ADDR5Xm1ADDR6
Xm1DATA1Xm1DATA2Xm1DATA3Xm1DATA4Xm1DATA5Xm1DATA6Xm1DATA7
Xm1DATA8Xm1DATA9Xm1DATA10Xm1DATA11Xm1DATA12Xm1DATA13Xm1DATA14Xm1DATA15
VDD_MEM1
VDD_MEM1
VDD_MEM1VDD_MEM1
Xm1DATA[7:0] [3]Xm1DATA[15:8] [3]
Xm1ADDR[13:0][3,7]Xm1ADDR[13:0][3,7]
Xm1DM1[3]
Xm1CKE0[3,7]Xm1CSn0[3,7]
Xm1CSn1/BA2[3,7]
Xm1DQSn1[3]Xm1DQS1[3]
Xm1SCLKn[3,7]Xm1SCLK[3,7]
Xm1RASn[3,7]Xm1CASn[3,7]
Xm1WEn[3,7]
Xm1BA0[3,7]Xm1BA1[3,7]
Xm1DM0[3]
Xm1CKE0[3,7]Xm1CSn0[3,7]
Xm1CSn1/BA2[3,7]
Xm1DQSn0[3]Xm1DQS0[3]
Xm1SCLKn[3,7]Xm1SCLK[3,7]
Xm1RASn[3,7]Xm1CASn[3,7]
Xm1WEn[3,7]
Xm1BA0[3,7]Xm1BA1[3,7]
Xm1ODT [7]Xm1ODT [7]
Title
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #1,2 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
6 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #1,2 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
6 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #1,2 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
6 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDXM1 DDR2(For 1Gbit x8)
CB93
1nF
CB93
1nF
+
CTB
4210
uF/6
.3V
+
CTB
4210
uF/6
.3V
CB97
100nF
CB97
100nF
+
CTB
4110
uF/6
.3V
+
CTB
4110
uF/6
.3V
CB92
100nF
CB92
100nF
CB90
1nF
CB90
1nF
CB95
100nF
CB95
100nF
CB91
100nF
CB91
100nF
CB94
1nF
CB94
1nF
U53
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
U53
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
A0H8A1H3A2H7A3J2A4J8A5J3A6J7A7K2A8K8A9K3A10/APH2A11K7A12L2
BA0G2BA1G3
DQ0 C8
VREF E2
ODT F9
DQ1 C2DQ2 D7DQ3 D3
DQ5 D9DQ4 D1
DQ6 B1DQ7 B9
VDDQ0 A9VDDQ1 C1VDDQ2 C9VDDQ3 C7VDDQ4 C3
VDD0 A1VDD1 E9VDD2 H9VDD3 L1
NC0 L3NC1 L7
VDDL E1
VSSDL E7
BA2G1
nDQSA8DQSB7
DM/RDQSB3NU/nRDQSA2
nCKF8CKE8
nRASF7nCASG7
nCSG8CKEF2nWEF3
VSSQ0B8VSSQ1B2VSSQ2A7VSSQ3D2VSSQ4D8
VSS0K9VSS1J1VSS2A3VSS3E3
A13L8
U54
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
U54
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
A0H8A1H3A2H7A3J2A4J8A5J3A6J7A7K2A8K8A9K3A10/APH2A11K7A12L2
BA0G2BA1G3
DQ0 C8
VREF E2
ODT F9
DQ1 C2DQ2 D7DQ3 D3
DQ5 D9DQ4 D1
DQ6 B1DQ7 B9
VDDQ0 A9VDDQ1 C1VDDQ2 C9VDDQ3 C7VDDQ4 C3
VDD0 A1VDD1 E9VDD2 H9VDD3 L1
NC0 L3NC1 L7
VDDL E1
VSSDL E7
BA2G1
nDQSA8DQSB7
DM/RDQSB3NU/nRDQSA2
nCKF8CKE8
nRASF7nCASG7
nCSG8CKEF2nWEF3
VSSQ0B8VSSQ1B2VSSQ2A7VSSQ3D2VSSQ4D8
VSS0K9VSS1J1VSS2A3VSS3E3
A13L8
R25510K/1%R25510K/1%
CB96
100nF
CB96
100nF
CB88
100nF
CB88
100nF
CB87
100nF
CB87
100nF
R25410K/1%R25410K/1%
R25310K/1%R25310K/1%
CB98
100nF
CB98
100nF
CB89
1nF
CB89
1nF
R25210K/1%R25210K/1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm1DATA24Xm1DATA16
Xm1ADDR0
Xm1DATA17Xm1DATA18Xm1DATA19Xm1DATA20Xm1DATA21Xm1DATA22Xm1DATA23
Xm1ADDR1Xm1ADDR2Xm1ADDR3Xm1ADDR4Xm1ADDR5Xm1ADDR6Xm1ADDR7Xm1ADDR8Xm1ADDR9Xm1ADDR10Xm1ADDR11Xm1ADDR12Xm1ADDR13
Xm1ADDR7Xm1ADDR8Xm1ADDR9Xm1ADDR10Xm1ADDR11Xm1ADDR12
Xm1ADDR0
Xm1ADDR13
Xm1ADDR1Xm1ADDR2Xm1ADDR3Xm1ADDR4Xm1ADDR5Xm1ADDR6
Xm1DATA25Xm1DATA26Xm1DATA27Xm1DATA28Xm1DATA29Xm1DATA30Xm1DATA31
VDD_MEM1VDD_MEM1
VDD_MEM1
VDD_MEM1VDD_MEM1
Xm1DATA[31:24] [3]
Xm1DM2[3]
Xm1CKE0[3,6]Xm1CSn0[3,6]
Xm1CSn1/BA2[3,6]
Xm1DQSn2[3]
Xm1ADDR[13:0][3,6]
Xm1DQS2[3]
Xm1SCLKn[3,6]Xm1SCLK[3,6]
Xm1DATA[23:16] [3]Xm1RASn[3,6]Xm1CASn[3,6]
Xm1WEn[3,6]
Xm1BA0[3,6]Xm1BA1[3,6]
Xm1DM3[3]
Xm1CKE0[3,6]Xm1CSn0[3,6]
Xm1CSn1/BA2[3,6]
Xm1DQSn3[3]Xm1DQS3[3]
Xm1SCLKn[3,6]Xm1SCLK[3,6]
Xm1RASn[3,6]Xm1CASn[3,6]
Xm1WEn[3,6]
Xm1BA0[3,6]Xm1BA1[3,6]
Xm1ADDR[13:0][3,6]
Xm1ODT[6]
Xm1ODT [6]Xm1ODT [6]
Title
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #2,3 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
7 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #2,3 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
7 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(1Gbit*4) XM1 #2,3 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
7 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDXM1 DDR2(For 1Gbit x8)
+
CTB
3910
uF/6
.3V
+
CTB
3910
uF/6
.3V
+
CTB
4010
uF/6
.3V
+
CTB
4010
uF/6
.3V
R24810K/1%R24810K/1%
U52
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
U52
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
A0H8A1H3A2H7A3J2A4J8A5J3A6J7A7K2A8K8A9K3A10/APH2A11K7A12L2
BA0G2BA1G3
DQ0 C8
VREF E2
ODT F9
DQ1 C2DQ2 D7DQ3 D3
DQ5 D9DQ4 D1
DQ6 B1DQ7 B9
VDDQ0 A9VDDQ1 C1VDDQ2 C9VDDQ3 C7VDDQ4 C3
VDD0 A1VDD1 E9VDD2 H9VDD3 L1
NC0 L3NC1 L7
VDDL E1
VSSDL E7
BA2G1
nDQSA8DQSB7
DM/RDQSB3NU/nRDQSA2
nCKF8CKE8
nRASF7nCASG7
nCSG8CKEF2nWEF3
VSSQ0B8VSSQ1B2VSSQ2A7VSSQ3D2VSSQ4D8
VSS0K9VSS1J1VSS2A3VSS3E3
A13L8
CB83
100nF
CB83
100nF
R24610K/1%R24610K/1%
CB79
100nF
CB79
100nF
CB85
100nF
CB85
100nF
CB82
1nF
CB82
1nF
CB75
100nF
CB75
100nF
R24910K/1%R24910K/1%
CB80
100nF
CB80
100nF
CB77
1nF
CB77
1nF
R24710K/1%R24710K/1%
CB84
100nF
CB84
100nF
U51
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
U51
K4T1G084QQ-HCE6 or HCF7 (DDR2, 1Gb)
A0H8A1H3A2H7A3J2A4J8A5J3A6J7A7K2A8K8A9K3A10/APH2A11K7A12L2
BA0G2BA1G3
DQ0 C8
VREF E2
ODT F9
DQ1 C2DQ2 D7DQ3 D3
DQ5 D9DQ4 D1
DQ6 B1DQ7 B9
VDDQ0 A9VDDQ1 C1VDDQ2 C9VDDQ3 C7VDDQ4 C3
VDD0 A1VDD1 E9VDD2 H9VDD3 L1
NC0 L3NC1 L7
VDDL E1
VSSDL E7
BA2G1
nDQSA8DQSB7
DM/RDQSB3NU/nRDQSA2
nCKF8CKE8
nRASF7nCASG7
nCSG8CKEF2nWEF3
VSSQ0B8VSSQ1B2VSSQ2A7VSSQ3D2VSSQ4D8
VSS0K9VSS1J1VSS2A3VSS3E3
A13L8
CB76
100nF
CB76
100nF
R25110K/NCR25110K/NC
CB86
100nF
CB86
100nF
R25010KR25010K
CB81
1nF
CB81
1nF
CB78
1nF
CB78
1nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm2DATA8Xm2DATA0Xm2DATA1Xm2DATA2Xm2DATA3Xm2DATA4Xm2DATA5Xm2DATA6Xm2DATA7
Xm2DATA9Xm2DATA10Xm2DATA11Xm2DATA12Xm2DATA13Xm2DATA14Xm2DATA15
Xm2ADDR13
Xm2ADDR6
Xm2ADDR10
Xm2ADDR5
Xm2ADDR9
Xm2ADDR5
Xm2ADDR9
Xm2ADDR2
Xm2ADDR12
Xm2ADDR4
Xm2ADDR8Xm2ADDR8
Xm2ADDR13
Xm2ADDR11
Xm2ADDR7
Xm2ADDR4
Xm2ADDR7
Xm2ADDR12
Xm2ADDR3
Xm2ADDR1
Xm2ADDR2
Xm2ADDR6
Xm2ADDR3Xm2ADDR1
Xm2ADDR10
Xm2ADDR0
Xm2ADDR11
Xm2ADDR0VDD_MEM2
VDD_MEM2
VDD_MEM2VDD_MEM2
Xm2DATA[15:8] [3]Xm2DATA[7:0] [3]
Xm2ADDR[13:0][3,9]Xm2ADDR[13:0][3,9]
Xm2DM0[3]
Xm2CKE0[3,9]Xm2CSn0[3,9]
Xm2CSn1/BA2[3,9]
Xm2DQSn0[3]Xm2DQS0[3]
Xm2SCLKn[3,9]Xm2SCLK[3,9]
Xm2RASn[3,9]Xm2CASn[3,9]
Xm2WEn[3,9]
Xm2BA0[3,9]Xm2BA1[3,9]
Xm2DM1[3]
Xm2CKE0[3,9]Xm2CSn0[3,9]
Xm2CSn1/BA2[3,9]
Xm2DQSn1[3]Xm2DQS1[3]
Xm2SCLKn[3,9]Xm2SCLK[3,9]
Xm2RASn[3,9]Xm2CASn[3,9]
Xm2WEn[3,9]
Xm2BA0[3,9]Xm2BA1[3,9]
Xm2ODT [9]Xm2ODT [9]
Xm2ADDR14[3,9]Xm2ADDR14[3,9]
Title
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #0,1 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
8 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #0,1 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
8 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #0,1 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
8 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDXM2 DDR2(For 2Gbit x8)
CB64
100nF
CB64
100nF
R24510K/1%R24510K/1%
R24410K/1%R24410K/1%
R24310K/1%R24310K/1%
+
CTB
3710
uF/6
.3V
+
CTB
3710
uF/6
.3V
U50
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
U50
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10/APM2A11P7A12R2A13R8A14R3
BA0L2BA1L3BA2L1
nDQSE8DQSF7
DM/RDQSF3NU/nRDQSE2
nCKK8CKJ8
nRASK7nCASL7
nCSL8CKEK2nWEK3
VSSQ0H8VSSQ1H2VSSQ2E7VSSQ3F2VSSQ4F8
VSS0P9VSS1N1VSS2J3VSS3E3
VDDQ0 E9VDDQ1 G1VDDQ2 G9VDDQ3 G7VDDQ4 G3
VDD0 E1VDD1 J9VDD2 M9VDD3 R1
VDDL J1
VSSDL J7
VREF J2
ODT K9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
NC0 A1NC1 A2NC2 A8NC3 A9NC4 W1NC5 W2NC6 W8NC7 W9NC8 R7
+
CTB
3810
uF/6
.3V
+
CTB
3810
uF/6
.3V
R24210K/1%R24210K/1%
CB69
1nF
CB69
1nF
CB74
100nF
CB74
100nF
CB71
100nF
CB71
100nF
CB63
100nF
CB63
100nF
CB73
100nF
CB73
100nF
CB70
1nF
CB70
1nF
CB67
100nF
CB67
100nF
CB66
1nF
CB66
1nF
CB68
100nF
CB68
100nF
CB65
1nF
CB65
1nF
U49
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
U49
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10/APM2A11P7A12R2A13R8A14R3
BA0L2BA1L3BA2L1
nDQSE8DQSF7
DM/RDQSF3NU/nRDQSE2
nCKK8CKJ8
nRASK7nCASL7
nCSL8CKEK2nWEK3
VSSQ0H8VSSQ1H2VSSQ2E7VSSQ3F2VSSQ4F8
VSS0P9VSS1N1VSS2J3VSS3E3
VDDQ0 E9VDDQ1 G1VDDQ2 G9VDDQ3 G7VDDQ4 G3
VDD0 E1VDD1 J9VDD2 M9VDD3 R1
VDDL J1
VSSDL J7
VREF J2
ODT K9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
NC0 A1NC1 A2NC2 A8NC3 A9NC4 W1NC5 W2NC6 W8NC7 W9NC8 R7
CB72
100nF
CB72
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm2DATA16
Xm2ADDR0
Xm2DATA17Xm2DATA18Xm2DATA19Xm2DATA20Xm2DATA21Xm2DATA22Xm2DATA23
Xm2ADDR1Xm2ADDR2Xm2ADDR3Xm2ADDR4Xm2ADDR5Xm2ADDR6Xm2ADDR7Xm2ADDR8Xm2ADDR9Xm2ADDR10Xm2ADDR11Xm2ADDR12Xm2ADDR13
Xm2ADDR13
Xm2ADDR0
Xm2ADDR3Xm2ADDR4Xm2ADDR5Xm2ADDR6Xm2ADDR7Xm2ADDR8Xm2ADDR9Xm2ADDR10
Xm2ADDR1
Xm2ADDR11
Xm2ADDR2
Xm2ADDR12
Xm2DATA24Xm2DATA25Xm2DATA26Xm2DATA27Xm2DATA28Xm2DATA29Xm2DATA30Xm2DATA31
VDD_MEM2VDD_MEM2
VDD_MEM2VDD_MEM2
VDD_MEM2
Xm2DATA[31:24] [3]
Xm2DM2[3]
Xm2CKE0[3,8]Xm2CSn0[3,8]
Xm2CSn1/BA2[3,8]
Xm2DQSn2[3]
Xm2ADDR[13:0][3,8]
Xm2DQS2[3]
Xm2SCLKn[3,8]Xm2SCLK[3,8]
Xm2DATA[23:16] [3]Xm2RASn[3,8]Xm2CASn[3,8]
Xm2WEn[3,8]
Xm2BA0[3,8]Xm2BA1[3,8]
Xm2DM3[3]
Xm2CKE0[3,8]Xm2CSn0[3,8]
Xm2CSn1/BA2[3,8]
Xm2DQSn3[3]
Xm2ADDR[13:0][3,8]
Xm2DQS3[3]
Xm2SCLKn[3,8]Xm2SCLK[3,8]
Xm2RASn[3,8]Xm2CASn[3,8]
Xm2WEn[3,8]
Xm2BA0[3,8]Xm2BA1[3,8]
Xm2ODT[8]
Xm2ODT [8]Xm2ODT [8]
Xm2ADDR14[3,8]Xm2ADDR14[3,8]
Title
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #2,3 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
9 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #2,3 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
9 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
DDR2(2Gbit*4) XM2 #2,3 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
9 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
XM2 DDR2(For 2Gbit x8)
CB57
1nF
CB57
1nF
CB60
100nF
CB60
100nF
CB61
100nF
CB61
100nF
R23710K/1%R23710K/1%
CB56
100nF
CB56
100nF
CB62
100nF
CB62
100nF
CB54
1nF
CB54
1nF
U48
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
U48
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10/APM2A11P7A12R2A13R8A14R3
BA0L2BA1L3BA2L1
nDQSE8DQSF7
DM/RDQSF3NU/nRDQSE2
nCKK8CKJ8
nRASK7nCASL7
nCSL8CKEK2nWEK3
VSSQ0H8VSSQ1H2VSSQ2E7VSSQ3F2VSSQ4F8
VSS0P9VSS1N1VSS2J3VSS3E3
VDDQ0 E9VDDQ1 G1VDDQ2 G9VDDQ3 G7VDDQ4 G3
VDD0 E1VDD1 J9VDD2 M9VDD3 R1
VDDL J1
VSSDL J7
VREF J2
ODT K9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
NC0 A1NC1 A2NC2 A8NC3 A9NC4 W1NC5 W2NC6 W8NC7 W9NC8 R7
+
CTB
3510
uF/6
.3V
+
CTB
3510
uF/6
.3V
CB52
100nF
CB52
100nF
CB51
100nF
CB51
100nF
CB53
1nF
CB53
1nF
R23810K/1%R23810K/1%
CB55
100nF
CB55
100nF
CB58
1nF
CB58
1nF
R24110K/NCR24110K/NC
R24010KR24010K
+
CTB
3610
uF/6
.3V
+
CTB
3610
uF/6
.3V
R23610K/1%R23610K/1%
U47
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
U47
K4T2G084QA-HCE6 or HCF7 (DDR2, 2Gb)
A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10/APM2A11P7A12R2A13R8A14R3
BA0L2BA1L3BA2L1
nDQSE8DQSF7
DM/RDQSF3NU/nRDQSE2
nCKK8CKJ8
nRASK7nCASL7
nCSL8CKEK2nWEK3
VSSQ0H8VSSQ1H2VSSQ2E7VSSQ3F2VSSQ4F8
VSS0P9VSS1N1VSS2J3VSS3E3
VDDQ0 E9VDDQ1 G1VDDQ2 G9VDDQ3 G7VDDQ4 G3
VDD0 E1VDD1 J9VDD2 M9VDD3 R1
VDDL J1
VSSDL J7
VREF J2
ODT K9
DQ0 G8DQ1 G2DQ2 H7DQ3 H3DQ4 H1DQ5 H9DQ6 F1DQ7 F9
NC0 A1NC1 A2NC2 A8NC3 A9NC4 W1NC5 W2NC6 W8NC7 W9NC8 R7
CB59
100nF
CB59
100nF
R23910K/1%R23910K/1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD_MPLL_AP
VDD_APLL_AP
VDD_EPLL_AP
VDD_VPLL_AP
VDD_M0_AP
VDD_MIPI_A
VDD_MIPI_A_AP
PVDD_MEM
VDD_RTC_AP
VDD_ARM_APPVDD_ARM
PVDD_RTC
VDD_INT_APPVDD_INT
VDD_ALIVE_AP
PVDD_LDO2
PVDD_LDO3
VDD_UOTG_D_AP
PVDD_LDO4
VDD_AUD
VDD_EXT0_AP
VDD_AUD_APPVDD_LDO5
VDD_EXT2_AP
VDD_MMC
PVDD_LDO6 VDD_LCD
VDD_UHOST_A_AP
PVDD_LDO8 VDD_UOTG_A_AP
VDD_ADC_AP
VDD_SYS0_AP
VDD_SYS1_AP
PVDD_LDO9
VDD_SYS
VDD_EXT1_AP
VDD_KEY_AP
VDD_KEY
VDD_UHOST_D_AP
VDD_MEM
VDD_EXT
VDD_CAM_AP
VDD_1V1
VDD_HDMI_AP
VDD_DAC_AP
VDD_DAC
VDD_DAC_A_AP
VDD_HDMI_PLL_AP
VDD_MIPI_D_AP
VDD_MIPI_PLL_AP
VDD_LCD_AP
VDD_CKO_AP
VDD_MODEM_AP PVDD_LDO7
VDD_MSM
VDD_CAM_IO_2V8
PVDD_LDO9
DC5V
VDD_CAM_IO_2V8
VDD_HDMI_OSC_AP
VDD_MEM1
VDD_MEM2
VDD_MEM_1V8
VDD_M1_AP
VDD_M2_AP
PWRRGTON_INV[13,16,17]
Title
Size Document Number Rev
Date: Sheet of
Power Jumper 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
10 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power Jumper 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
10 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power Jumper 0.0
SMDK_S5PV210_ CPU Board (Evaluation Board)
A3
10 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
(Pitch : 2.0mm)
1.1V 1A
1.1V 1A
1.8V 800mA
1.1V 10mA
1.1V 50mA
1.8V 450mA
2.8V 300mA
2.6V 150mA
3.3V 150mA
3.0V 450mA
LDO3 should be OFFin SLEEP mode
LDO8 should be OFF inSLEEP mode
LDO4 should beOFF in SLEEPmode
VDD_1V1 should be OFFin SLEEP mode
3.0V 150mA
Vout=1.242V(R2/R1+1)
R2
R1
2009.10.20. REV0.1 Change
2009.10.20. REV0.1 Change
R191 NC/R1608R191 NC/R1608
R204 NC/R1608R204 NC/R1608
R235 NC/R1608R235 NC/R1608
FB2
BLM18PG121SN1
FB2
BLM18PG121SN1
R211 0R211 0
R202 NC/R1608R202 NC/R1608
JP2A4B-2PA-2DSA
JP2A4B-2PA-2DSA
1 2
J5A4B-3PA-2DSA
J5A4B-3PA-2DSA
1 2 3
U46
MIC5219BM5
U46
MIC5219BM5
VIN1
GND2 VOUT 5
EN3 ADJ 4
R207 NC/R1608R207 NC/R1608
R185 0R185 0
R208 NC/R1608R208 NC/R1608
+CTB34
10uF/6.3V/T2012
+CTB34
10uF/6.3V/T2012
R195 NC/R1608R195 NC/R1608
JP3A4B-2PA-2DSA
JP3A4B-2PA-2DSA
1 2
R180 0R180 0
JP5A4B-2PA-2DSA
JP5A4B-2PA-2DSA
1 2
JP25A4B-2PA-2DSA
JP25A4B-2PA-2DSA
1 2
R197 0R197 0
R284 0/R1608R284 0/R1608
R222 NC/R1608R222 NC/R1608
R184 NC/R1608R184 NC/R1608
JP10A4B-2PA-2DSA
JP10A4B-2PA-2DSA
1 2
R226 NC/R1608R226 NC/R1608
+CT2
10uF/6.3V
+CT2
10uF/6.3V
R213 NC/R1608R213 NC/R1608
R229 NC/R1608R229 NC/R1608
R220 NC/R1608R220 NC/R1608
R223 0R223 0
JP15A4B-2PA-2DSA
JP15A4B-2PA-2DSA
1 2
R200 0R200 0
R210
1K
R210
1K
R193 NC/R1608R193 NC/R1608
JP19A4B-2PA-2DSA
JP19A4B-2PA-2DSA
1 2
R214 NCR214 NC
JP9A4B-2PA-2DSA
JP9A4B-2PA-2DSA
1 2
R209 NC/R1608R209 NC/R1608
FB1
BLM18PG121SN1
FB1
BLM18PG121SN1
JP12A4B-2PA-2DSA
JP12A4B-2PA-2DSA
1 2
JP18A4B-2PA-2DSA
JP18A4B-2PA-2DSA
1 2
CB50
100nF
CB50
100nF
JP24A4B-2PA-2DSA
JP24A4B-2PA-2DSA
1 2
JP7A4B-2PA-2DSA
JP7A4B-2PA-2DSA
1 2
R186 0R186 0
JP23A4B-2PA-2DSA
JP23A4B-2PA-2DSA
1 2
JP11A4B-2PA-2DSA
JP11A4B-2PA-2DSA
1 2
R231 NC/R1608R231 NC/R1608
R196 NC/R1608R196 NC/R1608
R219
1K
R219
1K
JP30A4B-2PA-2DSA
JP30A4B-2PA-2DSA
1 2
R203 NC/R1608R203 NC/R1608
R221 NC/R1608R221 NC/R1608
JP31A4B-2PA-2DSA
JP31A4B-2PA-2DSA
1 2
R233 0R233 0
Q5SI2333DS
Q5SI2333DS
3
1
2
JP35A4B-2PA-2DSA
JP35A4B-2PA-2DSA
1 2
U45
TPS2051BDBV
U45
TPS2051BDBV
OUT 1
GND 2
nOC 3nEN4
IN5
JP29A4B-2PA-2DSA
JP29A4B-2PA-2DSA
1 2
R201 NC/R1608R201 NC/R1608
JP17A4B-2PA-2DSA
JP17A4B-2PA-2DSA
1 2
R232
300K
R232
300K
R192 0R192 0
JP8A4B-2PA-2DSA
JP8A4B-2PA-2DSA
1 2
JP34A4B-2PA-2DSA
JP34A4B-2PA-2DSA
1 2
R199 NC/R1608R199 NC/R1608 JP21A4B-2PA-2DSA
JP21A4B-2PA-2DSA
1 2
R234 0/R1608R234 0/R1608
R224 NC/R1608R224 NC/R1608
R198 NC/R1608R198 NC/R1608
JP13A4B-2PA-2DSA
JP13A4B-2PA-2DSA
1 2
R228 NC/R1608R228 NC/R1608
JP28A4B-2PA-2DSA
JP28A4B-2PA-2DSA
1 2
C52
4.7u
F/X
5R
C52
4.7u
F/X
5R
R225 NC/R1608R225 NC/R1608JP32
A4B-2PA-2DSA
JP32A4B-2PA-2DSA
1 2
C54470pFC54470pF
JP27A4B-2PA-2DSA
JP27A4B-2PA-2DSA
1 2
R215 NC/R1608R215 NC/R1608
R230
240K
R230
240K
JP14A4B-2PA-2DSA
JP14A4B-2PA-2DSA
1 2
R189 NC/R1608R189 NC/R1608
R216 NC/R1608R216 NC/R1608R217 NC/R1608R217 NC/R1608
JP4A4B-2PA-2DSA
JP4A4B-2PA-2DSA
1 2
R227 0/R1608R227 0/R1608
JP16A4B-2PA-2DSA
JP16A4B-2PA-2DSA
1 2
JP22A4B-2PA-2DSA
JP22A4B-2PA-2DSA
1 2
R190 NC/R1608R190 NC/R1608
JP6A4B-2PA-2DSA
JP6A4B-2PA-2DSA
1 2
R205 NC/R1608R205 NC/R1608
JP33A4B-2PA-2DSA
JP33A4B-2PA-2DSA
1 2
R194 NC/R1608R194 NC/R1608
R188 0R188 0
R212 NC/R1608R212 NC/R1608
R181 NC/R1608R181 NC/R1608
C51
100nF
C51
100nF
R285NC/R1608R285NC/R1608
R182 NC/R1608R182 NC/R1608
R206 NC/R1608R206 NC/R1608
C53
4.7u
F/X
5R
C53
4.7u
F/X
5R
JP26A4B-2PA-2DSA
JP26A4B-2PA-2DSA
1 2FB3
BLM18PG121SN1
FB3
BLM18PG121SN1
R183 0R183 0
R187 NC/R1608R187 NC/R1608
R218NCR218NC
JP20A4B-2PA-2DSA
JP20A4B-2PA-2DSA
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DC5V
VDD_3V3DC5V
PVDD_LDO9
DC5V
VDD_3V3 VDD_1V8
VDD_SYS
PVDD_LDO9VDD_1V1DC5V
PVDD_INT
PVDD_LDO9
VDD_MEM_1V8DC5V
Title
Size Document Number Rev
Date: Sheet of
Power(DCjack&Regulator) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
11 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power(DCjack&Regulator) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
11 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power(DCjack&Regulator) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
11 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
R1
(3.3V)Vout=0.6(1+R2/R1)R2=R1(Vout/0.6V-1)
R2
R1
(1.1V)
<Silk>DC-IN
<Silk>5V/3A
(1.8V)Vout=1.25(1+R1/R2)R1=R2(Vout/1.25V-1)
R2
R1
<Silk>SYS_ON
Vout=0.2(1+R2/R1)-Iadj(R2)
R2
(1.8V)
Vout=0.60(1+R1/R2)R1=R2(Vout/0.60V-1)
R1
Vout = [email protected]
R2
2009.10.20. REV0.1 Change
CB49
100nF/C1608
CB49
100nF/C1608
+CTB3010uF/10V
+CTB3010uF/10V
U39LM2832XMY
U39LM2832XMY
VIND1VINA2GND3EN4 GND 5FB 6GND 7SW 8
DA
P9
C49 22pFC49 22pF
R173100K
R173100K
L12CDRH6D28 (10uH)
L12CDRH6D28 (10uH)
LED4LED-Red (SMD 2012)
LED4LED-Red (SMD 2012)
12
C48
22uF
,6.3
V
C48
22uF
,6.3
V
R165
44.2K,1%/R1608
R165
44.2K,1%/R1608
U43
SI4423DY
U43
SI4423DY
123
4
8765
R177
10K
R177
10K
U44
MAX6458
U44
MAX6458
VCC5
IN-4
OUT 1
GND 2
IN+ 3
ZD3Onsemi 1SMB5920BT3G (6.2V)ZD3
Onsemi 1SMB5920BT3G (6.2V)
12
R163
100K
R163
100K
R176
47K
R176
47K
R167
100K,1%/R1608
R167
100K,1%/R1608
L132.2uH (LQH32CN2R2M33)
L132.2uH (LQH32CN2R2M33)
+CTB33
10uF/10V
+CTB33
10uF/10V
+CTB31
10uF/6.3V
+CTB31
10uF/6.3V
+CTB32
10uF/6.3V
+CTB32
10uF/6.3V
+ CTB28
10uF/6.3V
+ CTB28
10uF/6.3V
R172330R172330
R178
12.7K
R178
12.7K
R166
100K
R166
100K
(1.5A, SMD, Poly Switch)
F1
MicroSMD150-2
(1.5A, SMD, Poly Switch)
F1
MicroSMD150-2
1 2
R1700
R1700
U42
LTC3406ES5
U42
LTC3406ES5
VIN4
RUN1
SW 3
VFB 5
GN
D2
+CTB29
10uF/6.3V
+CTB29
10uF/6.3V
R164
10K,1%
R164
10K,1%
R168 91K,1%/R1608R168 91K,1%/R1608
U41
LT3021ES8(ADJ)
U41
LT3021ES8(ADJ)
NC0 1
OUT 2
ADJ 3
AGND 4nSHDN5
PGND6
NC17
IN8
ZD2
MB
RS
320T
3
ZD2
MB
RS
320T
3
12
C50 100nFC50 100nF
U40
MAX1818EUT33
U40
MAX1818EUT33
IN1
POK2
nSHDN3 GND 4
SET 5
OUT 6
R16920K,1%/R1608R16920K,1%/R1608
R162
20K,1%
R162
20K,1%
R179
10K
R179
10K
R174
453K,1%/R1608
R174
453K,1%/R1608
C46
22uF,6.3V
C46
22uF,6.3V
LED5LED-GREEN (SMD 2012)
LED5LED-GREEN (SMD 2012)
12
R175100K,1%/R1608R175100K,1%/R1608
JACK1POWER JACK (DC-JACK, DC-003)
JACK1POWER JACK (DC-JACK, DC-003)
P 1
G2 2G3 3
R171510R171510
C47
22uF
,6.3
V
C47
22uF
,6.3
V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD_SYS
VDD_SYS
VDD_SYS
DC3V3DC3V3VDD_3V3
VDD_3V3
DC5V DC3V3
DC3V3
XrtcXTO [2]
XhdmiXTO [2]
XjTDO[2]XXTO [2]
XhdmiXTI [2]XrtcXTI [2]
XjTDI[2]XjTRSTn[2]
XjTMS[2]XjTCK[2]
XXTI [2]
XusbXTI [2]
XXTI [2]
XnRESET [2,21]
XusbXTO [2]
XusbXTI [2]
XnWRESET [2]
XuTXD2/UART_AUDIO_TXD[2,21]
XuRXD2/UART_AUDIO_RXD[2,21]
EXT_nRESET[21]
EXT_nRESET[21]
PMIC_nRST_OUT[13]
Title
Size Document Number Rev
Date: Sheet of
Reset / Clock source / JTAG 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
12 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Reset / Clock source / JTAG 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
12 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Reset / Clock source / JTAG 0.0
SMDK_S5PV210_POP CPU Board (Evaluation Board)
A3
12 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
JTAG<Silk>
X-Tal ClockSource
Reset Circuitry
<Silk>nRESET
For PLL
For RTCFor HDMI
JTAG
For USB
<Silk>nWRESET
UART2
R35: Close to X2
R39: Close to X1
*Pull-up, Pull-down resistors are embeded
(CL: 11pF)
(CL: 11pF)
(CL: 11pF)
(CL: 11pF)
2009.10.20. REV0.1 Change2009.10.20. REV0.1 Change
2009.10.20. REV0.1 Change
C40
20pF
C40
20pF
C43
4.7u
F/X
5R
C43
4.7u
F/X
5R
C36
14pF
C36
14pF
R147
100K
R147
100K
CON15
HIF3F-20PA-2.54DS (Box,Male,Right Angle)
CON15
HIF3F-20PA-2.54DS (Box,Male,Right Angle)
11 2 233 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 20
X224MHz (SMD,SX-8)
X224MHz (SMD,SX-8)
1
32
4
CB48
100nF
CB48
100nF
TP54TP54
R14
6N
CR
146
NC
R151
5.1M
R151
5.1M
CB47100nFCB47100nF
(HDR4-2.54-MALE)
J4
A2-4PA-2.54DSA(HDR4-2.54-MALE)
J4
A2-4PA-2.54DSA
1234
R153
NC
R153
NC
CB46
100nF
CB46
100nF
C41
20pF
C41
20pF
R14
5N
CR
145
NC
U37
MIC5319-3.3BD5
U37
MIC5319-3.3BD5
VIN1
GND2 VOUT 5
EN3 BYP 4
C38
14pF
C38
14pF
R14
4N
CR
144
NC
R161
100K
R161
100K
R15
50
R15
50
R160
NC
R160
NC
R148
NC
R148
NC
R158
5.1M
R158
5.1M
R156
10M
R156
10M
R159
100K
R159
100K U38
SN74LVC1G08DBV
U38
SN74LVC1G08DBV
1
24
35
C37
14pF
C37
14pF
C42
14pF
C42
14pF
R152
NC
R152
NC
R150
5.1M
R150
5.1M
SW2SW-TACT (Red)
SW2SW-TACT (Red)
3 41 2
SW3SW-TACT (Red)
SW3SW-TACT (Red)
3 41 2
C39
14pF
C39
14pF
X332.768KHz (CH-308)
X332.768KHz (CH-308)
12
3
C35
14pF
C35
14pF
R15
4N
CR
154
NC
R149
NC
R149
NC
C45
100nF
C45
100nF
X124MHz (SMD,SX-8)
X124MHz (SMD,SX-8)
1
32
4
R157
NC
R157
NC
OSC1
24MHz (SMD,SCO-103)
OSC1
24MHz (SMD,SCO-103)
OE1 GND 2
OUT 3VDD4
C44
4.7u
F/X
5R
C44
4.7u
F/X
5R
X427MHz (SMD,SX-8)
X427MHz (SMD,SX-8)
1
32
4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DC5V
DC5V
DC5V
DC5V
DC5V
PVDD_ARM PVDD_MEMPVDD_INT
PVDD_RTC
PVDD_LDO2 PVDD_LDO6
PVDD_LDO3
PVDD_LDO4
PVDD_LDO5 PVDD_LDO7
PVDD_LDO8
PVDD_LDO9
DC5V
VDD_3V3
VDD_3V3
PWRON
JIG_ON
PWRRGTONXPWRRGTON[2]
POWER_KEY
Xi2cSCL2/IEM_SPWI[2]
PWRRGTON
XEINT4[2,21]XEINT15[2,21]XEINT14[2,21]
XEINT0/PSHOLD[2]
Xi2cSDA2/IEM_SCLK[2]
POWER_KEY
PWRON
XEINT1[2,21]
PWROn_BOARD[15,18,20,21]
PMIC_nRST_OUT[12]
JIG_ON
PWRRGTON_INV [10,16,17]
Title
Size Document Number Rev
Date: Sheet of
Power - PMIC Socket 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
13 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power - PMIC Socket 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
13 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Power - PMIC Socket 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
13 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
<Silk>POWER
BAT1RB414_IV02N(NC)
BAT1RB414_IV02N(NC)
C20
4.7u
F/X
5R
C20
4.7u
F/X
5R
R141
0
R141
0
R136 0R136 0
SW1SW-TACT (Red)
SW1SW-TACT (Red)
3 41 2
C25
4.7u
F/X
5R
C25
4.7u
F/X
5R
C32
4.7u
F/X
5R
C32
4.7u
F/X
5R
U36
SN74LVC1G04DBV
U36
SN74LVC1G04DBV
2 4
531
R140
100K
R140
100K
TP52TP52
C27
4.7u
F/X
5R
C27
4.7u
F/X
5R
L10 2.2uH (LQH32C_53)L10 2.2uH (LQH32C_53)
L11 2.2uH (LQH32C_53)L11 2.2uH (LQH32C_53)
R135 0R135 0
C31
4.7u
F/X
5R
C31
4.7u
F/X
5R
R139
0
R139
0
CB44
100nF
CB44
100nF
TP53TP53
L92.2uH (LQH32C_53)
L92.2uH (LQH32C_53)
R138100KR138100K
R133 0R133 0
R14210K/R1005
R14210K/R1005
C29
4.7u
F/X
5R
C29
4.7u
F/X
5R
C28
4.7u
F/X
5R
C28
4.7u
F/X
5R
C23
4.7u
F/X
5R
C23
4.7u
F/X
5R
U33
MAX8698C
U33
MAX8698C
LX1 E1
LX2 G2
LX3 G5
SET1D4SET2D3SET3D2
PWRENB4
PWRONE3
PWRHOLDF3
MRnB5
ONOnC5
RSOnE4
SCLC3SDAC2SRADB3
LBOBC4
JIGONB2
REFBPA5
VCC_COIN F5
IN1F1IN2G1IN3G6IN4A2IN5C1IN6C6
BUCK1 E2
BUCK2 F2
BUCK3 F4
LDO1 F6
LDO2 B1LDO3 A1LDO4 A3LDO5 A4
LDO6 A6LDO7 B6LDO8 D6LDO9 E6
AGND1 D5AGND2 E5PGND1 D1PGND2 G3PGND3 G4
CB45
100nF
CB45
100nF
C30
4.7u
F/X
5R
C30
4.7u
F/X
5R
C18
4.7u
F/X
5R
C18
4.7u
F/X
5R
C24
100nF
C24
100nF
J3A4B-3PA-2DSA
J3A4B-3PA-2DSA
123
R143
0
R143
0
C26
4.7u
F/X
5R
C26
4.7u
F/X
5R
U34
SN74LVC1G04DBV
U34
SN74LVC1G04DBV
2 4
531
C22
4.7u
F/X
5R
C22
4.7u
F/X
5RC33
4.7u
F/X
5R
C33
4.7u
F/X
5R
C34
1nF
C34
1nF
JP1A4B-2PA-2DSA
JP1A4B-2PA-2DSA
1 2
U35
MAX16054AZT
U35
MAX16054AZT
IN1
GND2
CLEAR3 nOUT 4
OUT 5
VCC 6
R134 0R134 0
C21
4.7u
F/X
5R
C21
4.7u
F/X
5R
R1320 R1320
R137NC
R137NC
C19
4.7u
F/X
5R
C19
4.7u
F/X
5R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B_Xm0ADDR4
B_Xm0ADDR10B_Xm0ADDR9
Xm0ADDR15
Xm0ADDR0
Xm0ADDR13
Xm0ADDR2
B_Xm0ADDR5
B_Xm0ADDR0
Xm0ADDR9
Xm0ADDR3
Xm0ADDR1
B_Xm0ADDR8
Xm0ADDR10
B_Xm0ADDR14
Xm0ADDR4
B_Xm0ADDR13
Xm0ADDR11
Xm0ADDR14
Xm0ADDR8
Xm0ADDR12
B_Xm0ADDR1
B_Xm0ADDR6
B_Xm0ADDR15
B_Xm0ADDR7
B_Xm0ADDR12
Xm0ADDR5Xm0ADDR6Xm0ADDR7
B_Xm0ADDR11
B_Xm0ADDR2B_Xm0ADDR3
B_Xm0DATA9
Xm0DATA14
Xm0DATA4
Xm0DATA2
B_Xm0DATA8Xm0DATA8
B_Xm0DATA0
B_Xm0DATA6
Xm0DATA9
B_Xm0DATA3
B_Xm0DATA12
Xm0DATA0
Xm0DATA10
Xm0DATA12
Xm0DATA1
B_Xm0DATA14
Xm0DATA11
B_Xm0DATA13
B_Xm0DATA7
B_Xm0DATA10
B_Xm0DATA5
Xm0DATA13
B_Xm0DATA2
B_Xm0DATA15
B_Xm0DATA4Xm0DATA3
Xm0DATA15
B_Xm0DATA11
Xm0DATA5
B_Xm0DATA1
Xm0DATA7Xm0DATA6
VDD_3V3VDD_MEM
VDD_MEM
VDD_3V3VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_3V3VDD_MEM
VDD_MEM
VDD_MEM
B_Xm0WEn [21]
Xm0BE1[3]B_Xm0BE0 [21]
Xm0CSn1[3]
B_Xm0BE1 [21]
M0CSn4/NFCSn2
B_Xm0FREn [21]
Xm0ADDR[15:0][3,15]
Xm0CSn0[3]
Xm0FALE/ONDXL_SMCLK[3,15]
M0CSn5/NFCSn3
Xm0CSn3/NFCSn1[3]
Xm0CSn3/NFCSn1[3]
B_Xm0ADDR[15:0] [21]
Xm0OEn[3,15]
B_Xm0CSn3/NFCSn1 [21]B_Xm0CSn2/NFCSn0 [21]
B_Xm0FCLE/ONDAVD [21]
Xm0CSn2/NFCSn0[3,15]
B_M0CSn4/NFCSn2 [21]
Xm0CSn2/NFCSn0[3,15]
M0CSn5/NFCSn3M0CSn4/NFCSn2
B_M0CSn5/NFCSn3 [21]
B_Xm0OEn [21]
Xm0FCLE/ONDXL_AVD[3,15]
Xm0BE0[3]
B_Xm0CSn0 [21]B_Xm0CSn1 [21]
Xm0FWEn/ONDXL_RPn[3,15]Xm0FREn[3,15]
Xm0WEn[3,15]
B_Xm0FALE/ONDSMCLK [21]B_Xm0FWEn/ONDRPn [21]
Xm0CSn0[3]
Xm0FRnB1/ONDXL_INT1 [3,21]
Xm0FRnB0/ONDXL_INT0 [3,21]M0ONDINT [15]
Xm0CSn4/NFCSn2/ONANDXL_CSn0[3]
Xm0CSn5/NFCSn3/ONANDXL_CSn1[3]
M0CSn4/NFCSn2
M0CSn5/NFCSn3
M0ONDCSn [15]
Xm0DATA[15:0][3,15] B_Xm0DATA[15:0] [21]
Xm0DATA_RDn[3,21]
Xm0DATA_RDn [3,21]
Xm0CSn1[3]
Title
Size Document Number Rev
Date: Sheet of
Level Shifter & Buffer (SROM EBI IF) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
14 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Level Shifter & Buffer (SROM EBI IF) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
14 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Level Shifter & Buffer (SROM EBI IF) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
14 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
<Silk>ONDINT1
<Silk>ONDINT0
CS4 CS5
2 5
1 4
3 6 POP. OND
EXT. OND
Base B'd
<Silk>
R127
100K
R127
100K
TP48TP48CFG3
KHS06
CFG3
KHS06
1234
876
59101112
J2
A4B-3PA-2DSA
J2
A4B-3PA-2DSA
123
R128
100K
R128
100K
CB40 100nFCB40 100nF
CB36 100nFCB36 100nF
U32
SN74AVCA164245DGG
U32
SN74AVCA164245DGG
1A1471A2461A3441A4431A5411A6401A7381A837
2A1362A2352A3332A4322A5302A6292A7272A826
1DIR 12DIR 241OE48
2OE25
1B1 21B2 31B3 51B4 61B5 81B6 91B7 111B8 12
2B1 132B2 142B3 162B4 172B5 192B6 202B7 222B8 23
VCCA131 VCCA042 VCCB0 7VCCB1 18
GND045GND139GND234GND328
GND7 4GND6 10GND5 15GND4 21
CB35 100nFCB35 100nF
U30
SN74LVC1G08DBV
U30
SN74LVC1G08DBV
1
24
35
TP47TP47
U27
SN74AVCA164245DGG
U27
SN74AVCA164245DGG
1A1471A2461A3441A4431A5411A6401A7381A837
2A1362A2352A3332A4322A5302A6292A7272A826
1DIR 12DIR 241OE48
2OE25
1B1 21B2 31B3 51B4 61B5 81B6 91B7 111B8 12
2B1 132B2 142B3 162B4 172B5 192B6 202B7 222B8 23
VCCA131 VCCA042 VCCB0 7VCCB1 18
GND045GND139GND234GND328
GND7 4GND6 10GND5 15GND4 21
R129
100K
R129
100K
R1260
R1260
CB42 100nFCB42 100nF
U31
SN74LVC1G11DBV
U31
SN74LVC1G11DBV
13
25
46
R131
100K
R131
100K
R130
100K
R130
100KTP51TP51TP49TP49
U29
SN74LVC1G11DBV
U29
SN74LVC1G11DBV
13
25
46
CB37 100nFCB37 100nF CB38 100nFCB38 100nF
CB43 100nFCB43 100nF
TP50TP50
CB39 100nFCB39 100nF
R125
NC
R125
NC
U28
SN74AVCA164245DGG
U28
SN74AVCA164245DGG
1A1471A2461A3441A4431A5411A6401A7381A837
2A1362A2352A3332A4322A5302A6292A7272A826
1DIR 12DIR 241OE48
2OE25
1B1 21B2 31B3 51B4 61B5 81B6 91B7 111B8 12
2B1 132B2 142B3 162B4 172B5 192B6 202B7 222B8 23
VCCA131 VCCA042 VCCB0 7VCCB1 18
GND045GND139GND234GND328
GND7 4GND6 10GND5 15GND4 21
CB41 100nFCB41 100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Xm0DATA0
Xm0ADDR0
Xm0DATA14
Xm0ADDR10 Xm0ADDR11
Xm0DATA15Xm0DATA13
Xm0DATA8
Xm0ADDR8 Xm0ADDR9
Xm0DATA11
Xm0ADDR15
Xm0DATA9
Xm0ADDR6
Xm0DATA12
Xm0ADDR7
Xm0ADDR1
M0ONDCSn
Xm0DATA4 Xm0DATA5
Xm0ADDR5Xm0ADDR4
Xm0DATA6
Xm0ADDR13Xm0ADDR14
Xm0DATA7
Xm0ADDR3
Xm0DATA2Xm0DATA1
Xm0ADDR2
Xm0ADDR12
Xm0DATA3
Xm0DATA10
XvVD20XvVD19XvVD18
XvVD21
XvVD14
XvVD23
XvVD5
XvVD9
XvVD12
XvVD8
XvVD3
XvVD0
XvVD22
XvVD11
XvVD17
XvVD15XvVD16
XvVD7
XvVD7
XvVD1
XvVD4
XvVD6
XvVD10
XvVD13
XvVD2
XvVD15XvVD23
VDD_MEM VDD_MEM
VDD_LCD
DC5V
VDD_LCD
DC5V
VDD_LCD
VDD_3V3
Xm0WEn[3,14]Xm0FCLE/ONDXL_AVD[3,14]
Xm0FALE/ONDXL_SMCLK[3,14]Xm0DATA[15:0] [3,14]
Xm0FWEn/ONDXL_RPn[3,14]
Xm0DATA[15:0][3,14]
Xm0ADDR[15:0][3,14]
Xm0OEn [3,14]
Xm0ADDR[15:0] [3,14]
XvVSYNC/SYSCS1/VENVSYNC[4]
XvVD[23:0][4]
XvVDEN/SYSRC/VENHREF[4]
XvVCLK/SYSWE/V601CLK[4]XvHSYNC/SYSCS0/VENHSYNC[4]
Xi2cSDA0[2,18,21]
Xi2cSCL0[2,18,21]
TSXP0[4]
XvVDEN/SYSRC/VENHREF[4]
XvVCLK/SYSWE/V601CLK[4]
TSYP1[4]
XvVSYNC/SYSCS1/VENVSYNC[4]
TSYP0[4]
TSYM1[4]
XvHSYNC/SYSCS0/VENHSYNC[4]
TSXP1[4]TSXM1[4]
TSYM0[4]
TSXM0[4]
PWROn_BOARD[13,18,20,21]
SPI_CLK1[17,21]
SYS_OE/VEN_FIELD[4]
SPI_CSn1[17,21]
SPI_MOSI1[17,21]SPI_MISO1[17,21]
VSYNC_LDI[4]
XEINT6[2,20]
XpwmTOUT3/PWM_MIE[2,20,21]
M0ONDCSn[14]
M0ONDINT [14]Xm0FREn [3,14]Xm0CSn2/NFCSn0 [3,14]
Title
Size Document Number Rev
Date: Sheet of
OneNAND / LCD I/F(NonMIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
15 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
OneNAND / LCD I/F(NonMIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
15 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
OneNAND / LCD I/F(NonMIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
15 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
OneNAND Connector
TFT LCD FPC Cable Interface(MODULE Board)
LCD_NSS
LCD_SPICLKLCD_SPIMOSILCD_SPIMISO
LCD_BL
LCD_SUB_CLK
LCD_RESET
Place resistors on Top.
+CTB25
10uF/6.3V
+CTB25
10uF/6.3V
TP42TP42
CB33
100nF
CB33
100nF
TP40TP40TP41TP41
R123 0R123 0
R118 NCR118 NC
TP44TP44
CON14
QSH-030-01-F-D-A
CON14
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 6263 64
CB32
100nF
CB32
100nF
+CTB26
10uF
/10V +
CTB26
10uF
/10V
R122 0R122 0
TP46TP46
R121 0R121 0
R120 NCR120 NC12
+CTB27
10uF/10V
+CTB27
10uF/10V
TP45TP45
TP43TP43
CB31
100nF
CB31
100nF
CB34
100nF
CB34
100nF
R124 0R124 0
M1
GF056-60S-LSS-P2000
M1
GF056-60S-LSS-P2000
123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
R119 NCR119 NC12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SLOT0_SEL
SLOT0_SEL
SLOT0_SEL
VDD_MMC0
VDD_MMC
VDD_MMC
VDD_MMC0
VDD_MMC
VDD_MMC
VDD_MMC
VDD_MMC
VDD_MMC
XEINT7[2]
PWRRGTON_INV[10,13,17]
Xmmc1DATA2/MMC0_DATA6[2]
Xmmc0CMD[2]
slot0_CLK
slot0_DATA1
Xmmc1DATA0/MMC0_DATA4[2]
slot0_DATA2
Xmmc1CDn[2]
slot0_CMDslot0_DATA0
Xmmc1CMD[2]
Xmmc1DATA3/MMC0_DATA7[2]
Xmmc0DATA3[2]
Xmmc0DATA1[2]
Xmmc0CDn[2]
Xmmc0DATA0[2]
Xmmc0DATA2[2]
Xmmc1DATA1/MMC0_DATA5[2]slot0_CDn
Xmmc1CLK[2]
Xmmc0CLK[2]slot0_DATA3
slot0_DATA0
slot0_CLK
Xmmc1DATA1/MMC0_DATA5[2]
slot0_DATA3
slot0_DATA1
slot0_DATA2
Xmmc1DATA0/MMC0_DATA4[2]
slot0_CMD
Xmmc1DATA3/MMC0_DATA7[2]
Xmmc1DATA2/MMC0_DATA6[2]
slot0_CDn
HDMI_I2C_EN [19]
slot0_CDn
slot0_DATA0
slot0_DATA3
slot0_DATA1
slot0_DATA2Xmmc0DATA2[2]
Xmmc0DATA3[2]
Xmmc0DATA1[2]
Xmmc0DATA0[2]
Xmmc0CMD[2]
Xmmc0CLK[2]
Xmmc0CDn[2]
slot0_CMD
slot0_CLK
slot0_CDn
Title
Size Document Number Rev
Date: Sheet of
MMC#0 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
16 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#0 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
16 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#0 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
16 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
HS-MMC Slot 0
<Silk>MMC SLOT 0(mmc ch0,1)
S - L : B1 port, H : B2 portOE - L : Output enable H : all disconnect
ON: HDMI Disable
[1]
<Silk>
[2]
OFF:mmc0 ON: mmc1
SLOT0,HDMICFG2
CB27 100nFCB27 100nF
R110 100KR110 100K
R97
10K
R97
10K
U24
74LVC1G32DBV
U24
74LVC1G32DBV
1
24
53
R10
410
KR
104
10K
R111 NCR111 NC
LED3LED-Blue (SMD 2012)
LED3LED-Blue (SMD 2012)
12
CB28
100nF
CB28
100nF
CFG2
SW-DIP2
CFG2
SW-DIP2
12
43
+CTB23
1uF/6.3V
+CTB23
1uF/6.3V
R96
10K
R96
10K
R114 NCR114 NC
R10
110
KR
101
10K
CB30
100nF/C1608
CB30
100nF/C1608
R107
1K
R107
1K
+CTB24
10uF/6.3V
+CTB24
10uF/6.3V
R108
10K
R108
10K
Q4SI2333DS
Q4SI2333DS
3
1
2
R10
210
KR
102
10K
R10
310
KR
103
10K
CB29
100nF
CB29
100nF
R10
010
KR
100
10K
R115 NCR115 NC
U25
SN74CBTLV3257PWR
U25
SN74CBTLV3257PWR
1B122B153B1114B114
1B232B263B2104B213
nOE 15GND8 S 1
1A 42A 73A 94A 12
VCC 16
R113 NCR113 NC
R98
10K
R98
10K
U26
SN74CBTLV3257PWR
U26
SN74CBTLV3257PWR
1B122B153B1114B114
1B232B263B2104B213
nOE 15GND8 S 1
1A 42A 73A 94A 12
VCC 16
R106
330
R106
330
R117 NCR117 NC
CB26
100nF
CB26
100nF
R116 NCR116 NC
R109
0
R109
0
R99
10K
R99
10K CON13
SD/HSMMC Socket (BS178-0001-00)
CON13
SD/HSMMC Socket (BS178-0001-00)
NC2525DAT224
DAT323NC2222DAT421NC2020CMD19NC1818DAT517NC1616VSS1515NC1414
NC1313VDD12NC1111
NC1010CLK9NC88DAT67NC66VSS55NC44DAT73DAT02
DAT11
SD_CD26
SD_WP27
P29
/GN
D28
P30
/GN
D29
R112 NCR112 NC
R10
510
KR
105
10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VDD_MMC2
VDD_MMC
VDD_MMC
VDD_MMC
VDD_MMC
VDD_MMC1
VDD_MMC
VDD_MMC
VDD_MMC2
VDD_MMC1
VDD_MMC
VDD_MMC
XspiMISO1[2]XspiMOSI1[2]
XspiCSn1[2]
SPI_MOSI1 [15,21]
Xmmc2CDn/SPI_2_MISO[2]
XspiMOSI0[2]SPI_MISO0 [21]
Xmmc2DATA0/SPI_2_MOSI[2]
Xmmc2CLK/SPI_2_CLK[2]Xmmc2CMD/SPI_2_nSS[2]
SPI_CLK1 [15,21]
SPI_MOSI0 [21]
XspiCLK0[2]XspiCSn0[2]XspiMISO0[2]
SPI_CSn1 [15,21]
SPI_CSn0 [21]SPI_CLK0 [21]
XspiCLK1[2]
SPI_MISO1 [15,21]
PWRRGTON_INV[10,13,16]
PWRRGTON_INV[10,13,16]
Xmmc3DATA0/MMC2_DATA4[2]
XEINT8[2]
Xmmc3DATA2/MMC2_DATA6[2]
Xmmc3CLK[2]
Xmmc2DATA1[2]
Xmmc3DATA2/MMC2_DATA6[2]
Xmmc3DATA3/MMC2_DATA7[2]
Xmmc3DATA3/MMC2_DATA7[2]
Xmmc3DATA1/MMC2_DATA5[2]
Xmmc3CDn[2]
Xmmc2DATA3[2]
Xmmc3DATA0/MMC2_DATA4[2]
XEINT25/KP_ROW1[2,21]
Xmmc2DATA2[2]
Xmmc3CMD[2]
Xmmc3DATA1/MMC2_DATA5[2]
Xmmc2DATA0/SPI_2_MOSI[2]
Xmmc2CMD/SPI_2_nSS[2]
Xmmc2CLK/SPI_2_CLK[2]
Xmmc2CDn/SPI_2_MISO[2]
Xmmc2CDn/SPI_2_MISO[2]
Xmmc3CDn[2]
Title
Size Document Number Rev
Date: Sheet of
MMC#1/#2/ HS-SPI 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
17 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#1/#2/ HS-SPI 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
17 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#1/#2/ HS-SPI 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
17 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
HS-SPI
HS-SPI0<Silk> <Silk>
HS-SPI1<Silk>HS-SPI2
CON7,8,9 spacing : 2mm
HS-MMC Slot 2
MMC SLOT 2(mmc ch3) HS-MMC port 3(4bit)
<Silk>
<Silk>
HS-MMC port 2
HS-MMC Slot 1
MMC SLOT 1(mmc ch2)
R90
10K
R90
10K
R81
10K
R81
10K
R91
10K
R91
10K
R87
10K
R87
10K
R84
10K
R84
10K
U23
74LVC1G32DBV
U23
74LVC1G32DBV
1
24
53
CB22
100nF
CB22
100nF
RA3 0RA3 01357
2468
RA2 0RA2 01357
2468
CB24 100nFCB24 100nF
R79
10K
R79
10K
R77
10K
R77
10K
R94
1K
R94
1K
R92
330
R92
330
CB23
100nF
CB23
100nF
R74
10K
R74
10K
U22
74LVC1G32DBV
U22
74LVC1G32DBV
1
24
53
CB25
100nF
CB25
100nFR95
0
R95
0
CON11
A4B-5PA-2DSA(1x5, 2mm pitch)
CON11
A4B-5PA-2DSA(1x5, 2mm pitch)
1122334455
CB21 100nFCB21 100nF
CON9
A4B-5PA-2DSA(1x5, 2mm pitch)
CON9
A4B-5PA-2DSA(1x5, 2mm pitch)
1122334455
R88
10K
R88
10K
R850
R850
R75
10K
R75
10K
CON8
SD/HSMMC Socket (BS178-0001-00)
CON8
SD/HSMMC Socket (BS178-0001-00)
NC2525DAT224
DAT323NC2222DAT421NC2020CMD19NC1818DAT517NC1616VSS1515NC1414
NC1313VDD12NC1111
NC1010CLK9NC88DAT67NC66VSS55NC44DAT73DAT02
DAT11
SD_CD26
SD_WP27
P29
/GN
D28
P30
/GN
D29
CON12
SD/HSMMC Socket (BS178-0001-00)
CON12
SD/HSMMC Socket (BS178-0001-00)
NC2525DAT224
DAT323NC2222DAT421NC2020CMD19NC1818DAT517NC1616VSS1515NC1414
NC1313VDD12NC1111
NC1010CLK9NC88DAT67NC66VSS55NC44DAT73DAT02
DAT11
SD_CD26
SD_WP27
P29
/GN
D28
P30
/GN
D29
+CTB22
10uF/6.3V
+CTB22
10uF/6.3V
R93
10K
R93
10K
R73
10K
R73
10K
CB20
100nF
CB20
100nF
R78
10K
R78
10K
R82
10K
R82
10K
R72
330
R72
330
R86
10K
R86
10K
CON10
A4B-5PA-2DSA(1x5, 2mm pitch)
CON10
A4B-5PA-2DSA(1x5, 2mm pitch)
1122334455
Q2SI2333DS
Q2SI2333DS
3
1
2
LED2LED-Blue (SMD 2012)
LED2LED-Blue (SMD 2012)
12
RA10
RA101
357
2468
R83
1K
R83
1K
Q3SI2333DS
Q3SI2333DS
3
1
2
+CTB21
1uF/6.3V/T2012
+CTB21
1uF/6.3V/T2012
R76
10K
R76
10K
+CTB19
1uF/6.3V
+CTB19
1uF/6.3V
R89
10K
R89
10K
R80
10K
R80
10K
LED1LED-Blue (SMD 2012)
LED1LED-Blue (SMD 2012)
12
+CTB20
10uF/6.3V
+CTB20
10uF/6.3V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAM_SCL0
CAM_SDA0
CAM_SDA0CAM_SCL0
XciYDATA7
XciYDATA2
XciYDATA3
XciYDATA6
XciYDATA1
XciYDATA4XciYDATA5
XciYDATA0
VDD_CAM_2V8
VDD_CAM1V5
VDD_3V3
VDD_CAM_5V
VDD_CAM_3V3
VDD_CAM_1V2VDD_CAM_1V8
VDD_CAM_2V8
VDD_EXT
DC5V
VDD_CAM1V5
VDD_CAM_2V8
VDD_CAM_1V2DC5V
DC5V
DC5V VDD_CAM_3V3
VDD_CAM_IO_2V8
VDD_CAM_IO_2V8
VDD_CAM_1V8VDD_3V3
DC5VVDD_CAM_5V
CAM_A_CLK[4]
XciYDATA[7:0][4]
B_CAM_A_RSTXciVSYNC [4]
XciPCLK [4]
CAM_A_CLK [4]
XciHREF [4]
B_CAM_A_RST
CAM_SDA0[19]
CAM_SCL0[19] Xi2cSCL0 [2,15,21]
B_CAM_A_STBY
Xi2cSDA0 [2,15,21]
XciFIELD[4]
XciYDATA0[4]
XciPCLK[4]
XciVSYNC[4]
XciHREF[4]
XEINT2 [2,21]XEINT27/KP_ROW3 [2,21]
CAM_A_CLK[4]
XciYDATA2[4]
XciYDATA0[4]XciYDATA1[4]
XciYDATA4[4]XciYDATA3[4]
XciYDATA5[4]
XciPCLK[4]
XciYDATA6[4]
B_CAM_A_STBY B_CAM_A_RSTXciHREF [4]XciVSYNC [4]
Xi2cSCL0 [2,15,21]
CAM_SDA0[19]
CAM_SCL0[19]
Xi2cSDA0 [2,15,21]
XciYDATA7[4]
PWROn_BOARD[13,15,20,21]
XEINT10[2,21]
XEINT10[2,21]
XEINT5[2,21]
Title
Size Document Number Rev
Date: Sheet of
MMC#1 / HS-SPI / Camera I/F A Port(Non-MIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
18 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#1 / HS-SPI / Camera I/F A Port(Non-MIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
18 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MMC#1 / HS-SPI / Camera I/F A Port(Non-MIPI) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
18 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
Camera A I/F
<Silk>2M CAM
<Silk>
DIRL : B to AH : A to B
12MCAM
Place R285,R286 on U24(NC)
(1.5V)
R2
R2
R1
R1
(600mA)
Vout=0.2(1+R2/R1)-Iadj(R2)
Power for CAM
(1.2V)
Vout=0.6(1+R2/R1)R2=R1(Vout/0.6V-1)
R1
R2
(1.8V)Vout=1.25(1+R1/R2)R1=R2(Vout/1.25V-1)
(2.8V)
2009.10.20. REV0.1 Change
R620
R620
C6
1uF/
6VC
61u
F/6V
+ CTB15
10uF/6.3V
+ CTB15
10uF/6.3V
U21
LTC3406ES5
U21
LTC3406ES5
VIN4
RUN1
SW 3
VFB 5
GN
D2C17
4.7uF/X5R
C17
4.7uF/X5R
TP34 A_FIELDTP34 A_FIELD
R60 100K,1%/R1608R60 100K,1%/R1608
CB19100nFCB19100nF
R63
44.2K,1%/R1608
R63
44.2K,1%/R1608
L3 BLM
15H
D10
2SN
1L3 BLM
15H
D10
2SN
1
U15
SN74AVC4T245DGV
U15
SN74AVC4T245DGV
VCCA11DIR2
1A141A252A162A27
VCCB 161OEn 15
1B1 131B2 122B1 112B2 10
GND2 9GND18
2DIR3 2OEn 14
CB16
100nF
CB16
100nF
C13
4.7u
F/X
5R
C13
4.7u
F/X
5R
R57 NCR57 NC
C10
4.7u
F/X
5R
C10
4.7u
F/X
5R
L5 BLM
15H
D10
2SN
1L5 BLM
15H
D10
2SN
1
L6 2.2uH LQH32CN2R2M33L6 2.2uH LQH32CN2R2M33
+CTB1310uF/10V
+CTB1310uF/10V
C9
4.7u
F/X
5R
C9
4.7u
F/X
5R
C5
1uF/
6V
C5
1uF/
6V
L82.2uH (LQH32CN2R2M33)
L82.2uH (LQH32CN2R2M33)
TP36 A_CAMVSYNCTP36 A_CAMVSYNC
CON6
AXK8L24125B
CON6
AXK8L24125B
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 24
TP32TP32TP33TP33TP30TP30
CB18
100nF/C1608
CB18
100nF/C1608
+CTB16
10uF/6.3V
+CTB16
10uF/6.3V
R59 0R59 0
U16
LT3021ES8(ADJ)
U16
LT3021ES8(ADJ)
NC0 1
OUT 2
ADJ 3
AGND 4nSHDN5
PGND6
NC17
IN8
CB14
100nF
CB14
100nF
+CTB17
10uF/6.3V
+CTB17
10uF/6.3V
TP38 A_CAMDATA0TP38 A_CAMDATA0
R5210K
R5210K
CB17
100nF
CB17
100nF
U18
LTC3406ES5
U18
LTC3406ES5
RUN1GND2
SW3
VOUT 5
VIN 4
R71100K/1%R71100K/1%
TP37 A_CAMHREFTP37 A_CAMHREF
R6120K,1%/R1608R6120K,1%/R1608
TP31TP31
C7
4.7u
F/X
5R
C7
4.7u
F/X
5R
R50
1K
R50
1K
R54 0R54 0
U17
MAX1818EUT33
U17
MAX1818EUT33
IN1
POK2
nSHDN3 GND 4
SET 5
OUT 6
TP35 A_CAMPCLKTP35 A_CAMPCLK
+CTB18
10uF/6.3V
+CTB18
10uF/6.3V
R55 0R55 0
R65
100K,1%/R1608
R65
100K,1%/R1608
R68 0/1608R68 0/1608
R56 0R56 0
C16 22pFC16 22pF
R51
1K
R51
1K
CT1
100nF
CT1
100nF
12
CON7AXT634124AW1
CON7AXT634124AW1
1133557799111113131515171719192121232325252727292931313333
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 34
3535
3636
3737
3838
U19
MIC5319-3.3BD5
U19
MIC5319-3.3BD5
VIN1
GND2 VOUT 5
EN3 BYP 4
+CTB14
10uF/6.3V
+CTB14
10uF/6.3V
C11
4.7u
F/X
5R
C11
4.7u
F/X
5R
C8
4.7u
F/X
5R
C8
4.7u
F/X
5R
L4 BLM
15H
D10
2SN
1L4 BLM
15H
D10
2SN
1
R6768KR6768K
R66 249KR66 249K
+C14
10uF
/6.3
V
+C14
10uF
/6.3
V
CB15
100nF
CB15
100nF
R58 0R58 0
R64 0R64 0
TP39 FLASHTP39 FLASH
R70150K,1%R70150K,1%
U14
PCA9517DGK(NC)
U14
PCA9517DGK(NC)
VCCA1
SCLA2
SDAA3
GND4 EN 5
SDAB 6
SCLB 7
VCCB 8R53
0
R53
0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CBL_CEC
HDMI_SCLHDMI_SDA
CBL_CEC
HDMI_SDA
HDMI_SCL
VDD_CAM_2V8
VDD_MIPI_A
DC5V
VDD_SYS
DC5VDC5V
DC5V
VDD_EXT DC5V
VDD_CAM_2V8
VDD_MIPI_A
VDD_MIPI_A
VDD_3V3
DC5VDC5V
VDD_3V3
VDD_3V3
DC5V
XuoDRVVBUS[2]
XuoDP[2]
XuoVBUS[2]
XuoDM[2]
XuoREXT[2] XEINT24/KP_ROW0[2,21]
XuoID[2]
XhdmiREXT[4]
XhdmiTX1N[4]
XhdmiTXCN[4]
XhdmiTX1P[4]
XhdmiTX0N[4]XhdmiTXCP[4]
XhdmiTX2P[4]
XEINT13/HDMI_HPD[2]
XhdmiTX2N[4]
XhdmiTX0P[4]
XEINT12/HDMI_CEC[2]
XuhDN[2]
XuhPWREN[2]XuhDP[2]
XuhREXT[2]
Xi2cSCL1[2,20,21]
Xi2cSDA1[2,20,21]
XuhOVERCUR [2]
CAM_SCL0[18]
XEINT3 [2,21]
XmipiSDN1[4]XmipiSDP1[4]
XmipiSDP3[4]
CSI_CLK [4]CAM_SDA0[18]
XmipiSDP2[4]XmipiSDN2[4]
XmipiSDN3[4]
HDMI_I2C_EN [16]
XmipiSDP0[4]XmipiSDN0[4]
XmipiSDPCLK[4]XmipiSDNCLK[4]
Title
Size Document Number Rev
Date: Sheet of
HDMI/ MIPI-CSI/ MIPI-HSI/ USB 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
19 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
HDMI/ MIPI-CSI/ MIPI-HSI/ USB 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
19 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
HDMI/ MIPI-CSI/ MIPI-HSI/ USB 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
19 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
MIPI-CSI Camera Module Interface
USB OTG
Signal Name, Power Domain matching 필요
* locate as close aspossible to pin.
HDMI
MIPI-CSI<Silk>
CEC Isolation Circuit
USB HOST
DN and DP should be routed evenly
(4.7K)
(10K)
2009.10.26. REV0.1 Change
2009.10.20. REV0.1 Change
2009.10.20. REV0.1 Change
R20 0R20 0
Q1FDV301N
Q1FDV301N
R48 0R48 0
CB13
100nF
CB13
100nF
R33
4.7K
R33
4.7K
CB9
100nF
CB9
100nF
R36
NC
R36
NC
U10
SN74LVC1G04DBV
U10
SN74LVC1G04DBV
2 4
531
R21
4.7K
R21
4.7K
R37
0
R37
0
U9Rclamp0502B(N.C)U9Rclamp0502B(N.C)
123
R49
NC
R49
NC
R32
NC
R32
NC
U7Rclamp0502B(N.C)U7Rclamp0502B(N.C)
123
CON5
USB-MINIAB
CON5
USB-MINIAB
VBUS1D-2D+3ID4GND5 G9 9G8 8G7 7G6 6
C4
1uF
C4
1uF
Q-1
NDC7002N
Q-1
NDC7002N
11
22
334 4
5 5
6 6
TP29TP29
USB SINGLE Port - A Type (Host)
CON4
USB SINGLE Port - A Type (Host)
CON4VBUS1D-2D+3GND4
G5 5G6 6
C3
100nF
C3
100nF
R22
4.7K
R22
4.7K
R39
44.2/1%
R39
44.2/1%
U6Rclamp0502B(N.C)
U6Rclamp0502B(N.C)
123
R40
NC
R40
NC
R24 0R24 0
R35 0R35 0
U11
TPS2051BDBV
U11
TPS2051BDBV
OUT 1
GND 2
nOC 3nEN4
IN5R30
NC
R30
NC
U5
PCA9517DGK
U5
PCA9517DGK
VCCA1
SCLA2
SDAA3
GND4 EN 5
SDAB 6
SCLB 7
VCCB 8
R19 0R19 0
U12
SDMP0340LT
U12
SDMP0340LT
BB
CC
EE
CB10
100nF
CB10
100nF
R23 0R23 0
R45 0R45 0 R46 NCR46 NC
CB12100nFCB12100nF
R29
1K
R29
1K
HDMICON3
MD60-19P
HDMICON3
MD60-19P
GND020
TMDS_D0-9
TMDS_SHIELD15 TMDS_D1+4 TMDS_D2-3
TMDS_D2+1
TMDS_CLK+10TMDS_SHIELD311
CEC13
SCL15
DDC/CEC_GND17+5V18
TMDS_CLK-12
HOTPLUG19
GND4 21
TMDS_SHIELD28 TMDS_D0+7 TMDS_D1-6
TMDS_SHIELD02
NC14
SDA16
GND122 GND3 23
+CTB9
10uF/6.3V
+CTB9
10uF/6.3V
CON2
QSE-020-01-L-D-A
CON2
QSE-020-01-L-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 44
R28
1K
R28
1K
+CTB11
10uF/10V
+CTB11
10uF/10V
+CTB8
10uF/6.3V
+CTB8
10uF/6.3V
U13
TPS2051BDBV
U13
TPS2051BDBV
OUT 1
GND 2
nOC 3nEN4
IN5
R38
10K
R38
10K
CB11100nF
CB11100nF
+CTB10
10uF/10V
+CTB10
10uF/10V
R47
NC
R47
NC
R44 NCR44 NC
R26
100K
R26
100K
R43
1.8K
R43
1.8K
R31
10K
R31
10K
R4120KR4120K
+CTB12
10uF/10V
+CTB12
10uF/10V
R42NC
R42NC
R34
1K
R34
1K
U8Rclamp0502B(N.C)
U8Rclamp0502B(N.C)
123
R25
44.2/1%
R25
44.2/1%
R27
0
R27
0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SEL_TSI_BUF_EN
SEL_TSI_BUF_ENTSI_BUF_DIR
TSI_BUF_DIR
DC5V
DC5V
DC5V
VDD_LCD
MIPI_LCD_6V
VDD_MIPI_A
MIPI_LCD_LED
VDD_3V3VDD_MSM
MIPI_LCD_6V
VDD_MIPI_A
VDD_LCD
MIPI_LCD_LED
VDD_MIPI_A
VDD_MSM
DC5V DC5V
XpwmTOUT3/PWM_MIE [2,15,21]
PWROn_BOARD[13,15,18,21]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK [4,21]XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK [4,21]
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL[4,21]XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC[4,21]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK[4,21]
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR[4,21]XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA[4,21]
Xi2cSCL1[2,19,21]
XEINT17/KP_COL1 [2,21]
Xi2cSDA1[2,19,21]
XmipiMDP3[4]
XmipiMDN2[4]
XmipiMDN3[4]
XmipiMDP2[4]
XmipiMDN0[4]
XmipiMDPCLK[4]
XmipiMDN1[4]XmipiMDP1[4]
XmipiMDP0[4]
XmipiMDNCLK[4]
XEINT6 [2,15]XpwmTOUT3/PWM_MIE [2,15,21]
Title
Size Document Number Rev
Date: Sheet of
MIPI-DSI/TSI/24C0 IF 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
20 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MIPI-DSI/TSI/24C0 IF 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
20 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MIPI-DSI/TSI/24C0 IF 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
20 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
R1
R2
6.0V POWER
Vout=1.2(1+R2/R1)
LED drivers(Common)
For TSI test
MIPIMDPD1MIPIMDND1
MIPIMDPCLK
MIPI-DSI Connector
MIPIMDNCLK
MIPIMDPD0MIPIMDND0
MIPI-DSI<Silk>
ForCapacitiveSensorDevice I/F(I2C)
Note: XmipiM signals have same length.
Be placed TPs on eachlines.Not make stub.
OFF
RXON
[1] [2]
CFG3 : TSI
TX
<Silk>
TP17TP17
R14 NCR14 NC
R9 0R9 0
CB7
100nF
CB7
100nF
TP18TP18
R2
0
R2
0
TP19TP19
U2
LT3591EDDB
U2
LT3591EDDB
VIN1
GND2
NC33
SW4
CTRL 8
LED 7
NC6 6
CAP 5E_P
9
TP21TP21
TP14TP14
+CTB6
10uF/10V
+CTB6
10uF/10V
R3
100K
R3
100K
D1B320A
D1B320A
1 2
R6
100K
R6
100K
R10 0R10 0
CB3
100nF
CB3
100nF
CB8
100nF
CB8
100nF
TP28TP28
R18 NCR18 NC
TP20TP20
R13
10K/1%
R13
10K/1%
CB6
2.2uF/50V
CB6
2.2uF/50V
U3
LTC3872ETS8
U3
LTC3872ETS8
IPRG1
ITH2
SW 8
RU
N/S
S7
VIN 6
GND4
VFB3 NGATE 5
R17 NCR17 NC
TP16TP16
U4
Si4884DY
U4
Si4884DY
S22 S11
D6 6D7 7D8 8
S33G4 D5 5
R4
10
R4
10
U1
SN74AVC8T245-DGV
U1
SN74AVC8T245-DGV
VCCA1DIR2A13A24A35A46A57A68A79A810GND1111GND1212
VCCB24 24VCCB23 23
OEn 22B1 21B2 20B3 19B4 18B5 17B6 16B7 15B8 14
GND13 13
R8
17.4K, 1%
R8
17.4K, 1%
TP12TP12
+CTB5
10uF/6.3V
+CTB5
10uF/6.3V
TP26TP26
(HDR6-2.54-MALE)
J1
A2-6PA-2.54DSA(HDR6-2.54-MALE)
J1
A2-6PA-2.54DSA
123456
C2 47pFC2 47pF
R1
100K
R1
100K
R12 0R12 0
L1
22uH (LQH32CN220K23)
L1
22uH (LQH32CN220K23)
+CTB7
330uF/16V
+CTB7
330uF/16V
TP22TP22
TP15TP15
TP11TP11
TP23TP23
TP27TP27
CFG1
KHS02
CFG1
KHS02
12
43
TP24TP24
TP13TP13
R5
100K
R5
100K
C1
1.8nF
C1
1.8nF
L21uH (LQH32CN1R0M33)
L21uH (LQH32CN1R0M33)
R11 0R11 0
CB4
100nF
CB4
100nF
TP25TP25
R1640.2K/1%R1640.2K/1%
R7 0R7 0
+CTB3
10uF/10V
+CTB3
10uF/10V
+CTB4
10uF/6.3V
+CTB4
10uF/6.3V
R15 NCR15 NC
CB5
100nF
CB5
100nF
CON1
QSE-020-01-L-D-A
CON1
QSE-020-01-L-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 44
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B_Xm0ADDR7
B_Xm0DATA13
B_Xm0DATA9
B_Xm0DATA11
B_Xm0ADDR14
B_Xm0ADDR5B_Xm0DATA4B_Xm0DATA5
B_Xm0DATA14B_Xm0ADDR15
B_Xm0DATA0
B_Xm0ADDR2
B_Xm0ADDR12 B_Xm0DATA12
B_Xm0DATA7
B_Xm0DATA8
B_Xm0ADDR0
B_Xm0DATA15
B_Xm0ADDR1
B_Xm0DATA10
B_Xm0DATA6
B_Xm0DATA3
B_Xm0ADDR13
B_Xm0DATA2
B_Xm0ADDR6
B_Xm0ADDR4
B_Xm0ADDR8
B_Xm0ADDR10B_Xm0ADDR9
B_Xm0DATA1
B_Xm0ADDR3
B_Xm0ADDR11
VDD_MSM
VDD_KEY
VDD_EXT VDD_3V3
VDD_SYS
DC5V
VDD_AUD
VDD_3V3
VDD_MSM
VDD_EXT
VDD_DAC
VDD_AUD
VDD_3V3
DC5V
VDD_3V3
VDD_SYS
VDD_1V8 VDD_1V8
XuRTSn0[2]
B_Xm0FCLE/ONDAVD [14]
XEINT22/KP_COL6 [2]
Xi2sSDI0/PCM_SIN2[2]
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR[4,20]
Xi2cSCL1 [2,19,20]
XEINT21/KP_COL5 [2]
XuTXD3/RTSn2/UART_AUDIO_RTSn[2]
SPI_CLK1 [15,17]
XuTXD0[2]
XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0[4]
XEINT29/KP_ROW5 [2]
XEINT14[2,13]
XEINT31/KP_ROW7 [2]
B_Xm0FWEn/ONDRPn [14]
XuRXD3/CTSn2/UART_AUDIO_CTSn[2]
B_M0CSn5/NFCSn3[14]
XOM5[2]
XmsmREn/KP_ROW11/CF_IORN/MHL_IDCK [4]
Xi2cSDA0 [2,15,18]
B_Xm0CSn3/NFCSn1[14]
Xm0FRnB2 [3]
XmsmDATA10/KP_ROW3/CF_DATA10/MHL_D17 [4]
XpwmTOUT1 [2]
Xm0WAITn [3]
XmsmDATA9/KP_ROW2/CF_DATA9/MHL_D16 [4]
XuTXD2/UART_AUDIO_TXD[2,12]
Xi2cSCL0 [2,15,18]
XmsmDATA5/KP_COL6/CF_DATA5/MHL_D12 [4]
XEINT11[2]
XEINT28/KP_ROW4 [2]
XmsmWEn/KP_ROW10/CF_CSn1/MHL_HSYNC[4]
XmsmDATA13/KP_ROW6/CF_DATA13/MHL_D20 [4]
XmsmDATA11/KP_ROW4/CF_DATA11/MHL_D18 [4]
Xi2sSDO0_0/PCM_SOUT2[2]
XuRXD0[2]
XmsmDATA6/KP_COL7/CF_DATA6/MHL_D13 [4]
XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2[4]
XmsmDATA3/KP_COL4/CF_DATA3/MHL_D10 [4]
XuRTSn1[2]
XOM2[2]
XEINT24/KP_ROW0 [2,19]
XOM1[2]
Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[2]
XEINT27/KP_ROW3 [2,18]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 [2]
SPI_MISO1 [15,17]
XEINT16/KP_COL0 [2]
Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[2]
B_Xm0OEn [14]
B_Xm0CSn2/NFCSn0[14]B_Xm0CSn1[14]
XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4[4]
Xm0DATA_RDn[3,14]
XmsmDATA7/KP_ROW0/CF_DATA7/MHL_D14 [4]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK[4,20]
Xi2cSDA1 [2,19,20]
SPI_CSn0 [17]
XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC[4,20]
XmsmADDR13/KP_COL0/SROM_ADDR21/MHL_D6[4]
SPI_MOSI0 [17]
XEINT26/KP_ROW2 [2]
XuRXD2/UART_AUDIO_RXD[2,12]
XEINT25/KP_ROW1 [2,17]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 [2]
XpwmTOUT2 [2]
XmsmDATA15/KP_ROW8/CF_DATA15/MHL_D22 [4]
B_Xm0FREn [14]
B_Xm0WEn [14]
B_Xm0ADDR[15:0][14]
XEINT20/KP_COL4 [2]
Xi2sSDO1/PCM_SOUT1/AC97_SDO[2]
XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA[4,20]
XEINT1[2,13]
XOM0[2]
XEINT17/KP_COL1 [2,20]
XuTXD1[2]
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK[4,20]
Xi2sLRCK0/PCM_FSYNC2[2]
B_M0CSn4/NFCSn2[14]
XEINT10[2,18]
XEINT30/KP_ROW6 [2]
SPI_MISO0 [17]
SPI_MOSI1 [15,17]
Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[2]
XmsmCSn/KP_ROW9/CF_CSn0/MHL_D23[4]
Xi2sSDO0_2[2]
B_Xm0CSn0[14]
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1[4]
XmsmIRQn/KP_ROW12/CF_IOWN/MHL_VSYNC [4]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK[4,20]
B_Xm0BE1 [14]
PWROn_BOARD[13,15,18,20]
XmsmDATA8/KP_ROW1/CF_DATA8/MHL_D15 [4]
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL[4,20]
XpwmTOUT0 [2]
XuCTSn0[2]
XOM4[2]
XEINT15[2,13]
Xm0FRnB3 [3]
XEINT23/KP_COL7 [2]
EXT_nRESET [12]
XuCTSn1[2]
B_Xm0BE0 [14]
XEINT19/KP_COL3 [2]XEINT18/KP_COL2 [2] Xi2sSCLK0/PCM_SCLK2[2]
XpcmSOUT0/Xi2sSDO2 [2]
XmsmDATA2/KP_COL3/CF_DATA3/MHL_D9 [4]
XmsmDATA14/KP_ROW7/CF_DATA14/MHL_D21 [4]
B_Xm0DATA[15:0] [14]
Xi2sSDO0_1[2]
XOM3[2]
XmsmDATA1/KP_COL2/CF_DATA1/MHL_D8 [4]
XmsmDATA12/KP_ROW5/CF_DATA12/MHL_D19 [4]XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5[4]
XmsmADVN/KP_ROW13/SROM_ADDR22/MHL_DE[4]
XEINT3[2,19]
B_Xm0FALE/ONDSMCLK [14]
SPI_CSn1 [15,17]
XEINT9[2]
XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3[4]
Xm0FRnB1/ONDXL_INT1 [3,14]
XmsmDATA0/KP_COL1/CF_DATA0/MHL_D7 [4]
XuRXD1[2]
DACOUT0[4]
XpcmSIN0/Xi2sSDI2 [2]
Xm0FRnB0/ONDXL_INT0 [3,14]
XEINT5[2,18]
Xi2sSDI1/PCM_SIN1/AC97_SDI[2]
XmsmDATA4/KP_COL5/CF_DATA4/MHL_D11 [4]
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2 [2]
SPI_CLK0 [17]
Xi2sCDCLK0/PCM_EXTCLK2[2]
XEINT2[2,18]
XCLKOUT[2]
XnRESET [2,12]
XEINT4[2,13]
XpwmTOUT3/PWM_MIE [2,15,20]
Title
Size Document Number Rev
Date: Sheet of
B2B Connector(CPU) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
21 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
B2B Connector(CPU) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
21 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
B2B Connector(CPU) 0.0
SMDK_S5PV210_CPU Board (Evaluation Board)
A3
21 21Monday, October 26, 2009
SAMSUNG ELECTRONICS CO.,LTD
JB2(39,41) DACOUT1,2
MTH1GNDMTH1GND
JB1
QSS-075-01-F-D-A
JB1
QSS-075-01-F-D-A
11 2 233 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 202121 22 222323 24 242525 26 262727 28 282929 30 303131 32 323333 34 343535 36 363737 38 383939 40 404141 42 424343 44 444545 46 464747 48 484949 50 50
5151 52 525353 54 545555 56 565757 58 585959 60 606161 62 626363 64 646565 66 666767 68 686969 70 707171 72 727373 74 747575 76 767777 78 787979 80 808181 82 828383 84 848585 86 868787 88 888989 90 909191 92 929393 94 949595 96 969797 98 989999 100 100
101101 102 102103103 104 104105105 106 106107107 108 108109109 110 110111111 112 112113113 114 114115115 116 116117117 118 118119119 120 120121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150
151
151
152
152
153
153
154
154
155
155
156
156
157
157
158
158
159
159
160
160
161
161
162
162
CB1
100nF
CB1
100nF
TPH2TPH2
MTH3GNDMTH3GND
TP3TP3
MTH4GNDMTH4GND
TP5TP5
+CTB1
10uF/10V
+CTB1
10uF/10V
TPH1TPH1 TPH3TPH3
TP1TP1
JB2
QSS-075-01-F-D-A
JB2
QSS-075-01-F-D-A
11 2 233 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 202121 22 222323 24 242525 26 262727 28 282929 30 303131 32 323333 34 343535 36 363737 38 383939 40 404141 42 424343 44 444545 46 464747 48 484949 50 50
5151 52 525353 54 545555 56 565757 58 585959 60 606161 62 626363 64 646565 66 666767 68 686969 70 707171 72 727373 74 747575 76 767777 78 787979 80 808181 82 828383 84 848585 86 868787 88 888989 90 909191 92 929393 94 949595 96 969797 98 989999 100 100
101101 102 102103103 104 104105105 106 106107107 108 108109109 110 110111111 112 112113113 114 114115115 116 116117117 118 118119119 120 120121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150
151
151
152
152
153
153
154
154
155
155
156
156
157
157
158
158
159
159
160
160
161
161
162
162
TP4TP4
TP6TP6
TP2TP2
CB2
100nF
CB2
100nF
TP9TP9
+CTB2
10uF/10V
+CTB2
10uF/10V
MTH2GNDMTH2GND
TP7TP7
TP10TP10
TP8TP8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Table of Contents
Description
SMDK_S5PC110_Base B'd (S5PC110 Evaluation Board) SchematicsDateRevision
Rev 0.0 2009. 04. Preliminary Version
Part Reference<Component><Number>---------------------------------------------------U : Component or Regurator ICC : CapacitorCB : Capacitor BypassCT : Capacitor TantalCTB : Capacitor Tantal BypassJ : JumperJB : CPU To Base connectorJP : Jumper PowerR : ResistorRA : Resistor ArrayRP : Resistor PowerVR : Variable ResistorL : InductorFB : Ferrite BeadOSC : OscillatorX : X-tal (Crystal)Q : Transistor or FETD : DiodeZD : Zener DiodeLED : LED DiodeSW : SWitch Tact/PushCON : CONnectorCFGB : ConFiGure switch onBaseb'd(DIP/Slide)TP : Test Point (SMD)TPH : Test Point Hole (Through Hole)MTH: Mount Through HoleM (MOD) : MODule Interface connector
Page Function-------------------------------------------------------01 Revision History02 B2B Connector&power(Base Board)03 NOR/NAND/SRAM/ChipSel04 CF Modem Key signal swiching05 Compact Flash Socket06 Ext.ROM Bus/ Host_Modem IF07 Camera B-Port Interface08 Audio Switch 09 Audio(WM9713_AC97)10 Audio(WM8580_IIS_5.1CH)11 SPDIF OUT / IIC EEPROM Interface12 Audio Jack13 External Keypad14 UART/ IrDA15 Ethernet 100Mbp(LAN9115)16. Module Connector1_217 Module Connector3_418 TV Interface/PWM/EINT/LED19 RMB board interface(for SMDK b'd test)
2009. 08.Rev 0.1
Revision History 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
1 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B2B Connector(Base) 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
2 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
B_Xm0ADDR2
B_Xm0ADDR12
B_Xm0ADDR0
B_Xm0ADDR15
B_Xm0ADDR5B_Xm0ADDR4
B_Xm0ADDR13
B_Xm0ADDR8
B_Xm0ADDR1
B_Xm0ADDR7
B_Xm0ADDR3
B_Xm0ADDR9B_Xm0ADDR10
B_Xm0ADDR6
B_Xm0ADDR11
B_Xm0ADDR14
B_Xm0DATA6
B_Xm0DATA4
B_Xm0DATA11
B_Xm0DATA7
B_Xm0DATA8
B_Xm0DATA3
B_Xm0DATA10
B_Xm0DATA14B_Xm0DATA15
B_Xm0DATA9
B_Xm0DATA5
B_Xm0DATA13
B_Xm0DATA0B_Xm0DATA1
B_Xm0DATA12
B_Xm0DATA2
PWROn_BOARD[7,16,17]
XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA[4,7]
XOM5[19]
XuCTSn1[14]
XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5[4,7]
XmsmWEn/KP_ROW10/CF_CSn1/MHL_HSYNC[4]
XuTXD1[14]
XOM0[19]XOM1[19]
XuTXD3/RTSn2/UART_AUDIO_RTSn[14,16,17]
XuTXD2/UART_AUDIO_TXD[14,16,17]
XEINT1
XEINT10
XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4[4,7]
XOM3[19]
XEINT14
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL[4,7]
XmsmADDR13/KP_COL0/SROM_ADDR21/MHL_D6[4]
XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2[4,7]
XEINT9[15]
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1[4,7]
XuRTSn0[14]
XuRXD2/UART_AUDIO_RXD[14,16,17]
XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0[4,7]
XOM2[19]
XuRXD3/CTSn2/UART_AUDIO_CTSn[14,16,17]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK[4,7]
XuRTSn1[14]
XEINT11
XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC[4,7]
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK[4,7]
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR[4,7]
XmsmCSn/KP_ROW9/CF_CSn0/MHL_D23[4]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK[4,7]
XEINT5
XmsmADVN/KP_ROW13/SROM_ADDR22/MHL_DE[4]
XuRXD1[14]
XuRXD0[14]
XEINT15
XuCTSn0[14]
XEINT3[7]
XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3[4,7]
XuTXD0[14]
XOM4[19]
XmsmDATA9/KP_ROW2/CF_DATA9/MHL_D16 [4]
XEINT24/KP_ROW0 [13,16,17]
XmsmIRQn/KP_ROW12/CF_IOWN/MHL_VSYNC [4]
XmsmDATA15/KP_ROW8/CF_DATA15/MHL_D22 [4]
XEINT29/KP_ROW5 [13,16]
EXT_nRESET [6,19]
XEINT17/KP_COL1 [13]
XEINT19/KP_COL3 [10,13]
SPI_CLK1 [16,17]
XmsmDATA2/KP_COL3/CF_DATA3/MHL_D9 [4]
SPI_MISO1 [16,17]
XEINT18/KP_COL2 [6,13]
XEINT22/KP_COL6 [13,18]
XmsmDATA14/KP_ROW7/CF_DATA14/MHL_D21 [4]
XmsmDATA11/KP_ROW4/CF_DATA11/MHL_D18 [4]
Xi2cSCL0 [6,7,10,11,16,17]
XmsmDATA7/KP_ROW0/CF_DATA7/MHL_D14 [4]
XEINT31/KP_ROW7 [13,16,18]
XEINT16/KP_COL0 [13]
XEINT28/KP_ROW4 [6,13,16]
XmsmDATA10/KP_ROW3/CF_DATA10/MHL_D17 [4]
SPI_CSn1 [16,17]
SPI_CLK0 [16]
XEINT27/KP_ROW3 [7,13,16,17]
SPI_MOSI0 [16]
XEINT25/KP_ROW1 [13,16,17]
XmsmDATA0/KP_COL1/CF_DATA0/MHL_D7 [4]
XmsmDATA5/KP_COL6/CF_DATA5/MHL_D12 [4]
SPI_MISO0 [16]
Xi2cSDA0 [6,7,10,11,16,17]
XEINT20/KP_COL4 [13,18]
SPI_CSn0 [16]
XmsmDATA8/KP_ROW1/CF_DATA8/MHL_D15 [4]
XEINT23/KP_COL7 [13,18]
XEINT21/KP_COL5 [13,18]
XmsmDATA1/KP_COL2/CF_DATA1/MHL_D8 [4]
XmsmREn/KP_ROW11/CF_IORN/MHL_IDCK [4]
Xi2cSCL1 [11]
XEINT26/KP_ROW2 [13,16,17]
XmsmDATA12/KP_ROW5/CF_DATA12/MHL_D19 [4]
XEINT30/KP_ROW6 [6,13,16]
SPI_MOSI1 [16,17]
XmsmDATA6/KP_COL7/CF_DATA6/MHL_D13 [4]
XmsmDATA4/KP_COL5/CF_DATA4/MHL_D11 [4]
Xi2cSDA1 [11]
XmsmDATA3/KP_COL4/CF_DATA3/MHL_D10 [4]
XmsmDATA13/KP_ROW6/CF_DATA13/MHL_D20 [4]
B_Xm0ADDR[15:0][3,6,15]
Xi2sSDO0_1[6,10]
Xi2sSCLK0/PCM_SCLK2[6,10]
Xi2sSDO0_0/PCM_SOUT2[6,10]
DACOUT0[18]
Xm0DATA_RDn
Xi2sLRCK0/PCM_FSYNC2[6,10]Xi2sCDCLK0/PCM_EXTCLK2[6,10]
DACOUT2
Xi2sSDI0/PCM_SIN2[10]
Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[8]
B_Xm0CSn2/NFCSn0[3]
Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[8]
Xi2sSDO1/PCM_SOUT1/AC97_SDO[8]
B_M0CSn5/NFCSn3[3]
Xi2sSDO0_2[10]
B_M0CSn4/NFCSn2[3]B_Xm0CSn3/NFCSn1[3]
B_Xm0CSn0[3]B_Xm0CSn1[3]
Xi2sSDI1/PCM_SIN1/AC97_SDI[8]Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[8]
DACOUT1
B_Xm0FALE/ONDSMCLK [3]B_Xm0FCLE/ONDAVD [3,6]
Xm0FRnB3 [3]
Xm0FRnB1/ONDXL_INT1 [3]
Xm0WAITn [3,6]
B_Xm0BE0 [3]
XpwmTOUT1 [6,14,16,18]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 [6,8]
Xm0FRnB2 [3]
XpcmSOUT0/Xi2sSDO2 [8]
B_Xm0FREn [3]
B_Xm0OEn [3,6,15]
Xm0FRnB0/ONDXL_INT0 [3]
XpwmTOUT0 [5,18]
XpcmSIN0/Xi2sSDI2 [8]
B_Xm0BE1 [3]
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2 [8]
B_Xm0DATA[15:0] [3,6,15]
B_Xm0FWEn/ONDRPn [3]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 [6,8]
B_Xm0WEn [3,6,15]
XpwmTOUT2 [6,14,16,18]
XEINT2
XCLKOUT[10]
XnRESET [3,7,13,15,16,17]
XEINT4[18]
XpwmTOUT3/PWM_MIE [18]
DC5V DC5VVDD_MSM
VDD_DAC
VDD_EXT
VDD_SYS
VDD_AUD
VDD_KEY
VDD_3V3
VDD_SYS
VDD_EXT
VDD_MSM
VDD_EXT
VDD_SYS
VDD_KEY
VDD_MSM
VDD_3V3
VDD_AUD
VDD_DAC
VDD_3V3 VDD_3V3
VDD_AUD
VDD_3V3
VDD_1V8VDD_1V8
CB1
100nF
TP6TP5
CB10
100nF
+ CTB1
10uF/6.3V
CB6
100nF
+ CTB3
10uF/6.3V
CB9
100nF
TP2
+ CTB9
10uF/6.3V
CB2
100nF
TP1
JB1
QTS-075-03-F-D-A
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
51 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100
101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121123125127129131133135137139141143145147149
122124126128130132134136138140142144146148150
151
152
153
154
155
156
157
158
159
160
161
162
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
51 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100
101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121123125127129131133135137139141143145147149
122124126128130132134136138140142144146148150
151
152
153
154
155
156
157
158
159
160
161
162
CB4
100nF
+ CTB5
10uF/6.3V
+ CTB2
10uF/6.3V
TP4
CB7
100nF
+CTB7
10uF/10V
+CTB8
10uF/10V
TP9
TP3
CB3
100nF
+ CTB6
10uF/6.3V
TP8
JB2
QTS-075-03-F-D-A
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
51 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100
101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121123125127129131133135137139141143145147149
122124126128130132134136138140142144146148150
151
152
153
154
155
156
157
158
159
160
161
162
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
51 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100
101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121123125127129131133135137139141143145147149
122124126128130132134136138140142144146148150
151
152
153
154
155
156
157
158
159
160
161
162
CB5
100nF
+ CTB4
10uF/6.3V
CB8
100nF
TP7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AMD NOR-FlashMemory(SOCKET) SRAM
Memory
Samsung NAND-Flash memory(SOCKET )
<Silk>
<Silk>NAND
AM29LV800BB,1MB
<Silk>SRAM
NOR
No WriteProtection
ADDR for SRAM is usingbyte base addressing
K9MCG08U5M
[2]External
NAND CS0
CFGB3:nCS2NAND CS2
[1]
[1]
[4]
[4]
SRAM[1]
CFGB4:nCS3
[1]
SRAM
[2]
CFGB5:nCS4
NAND CS1
[2]
[1]
CFGB1:nCS0
SRAM[2]
SRAMSRAM
<Silk>
[3]
NAND CS3
[3]
CFGB2:nCS1
CFGB6:nCS5
External
[2]
Ethernet
Ethernet
NOR
NOR/NAND/SRAM/xD Card/Chip Selection 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
3 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
nCS_SRAM
B_Xm0DATA11
B_Xm0DATA1
B_Xm0DATA15B_Xm0DATA14
B_Xm0DATA3B_Xm0DATA4
B_Xm0DATA8
nCS_NAND0
B_Xm0DATA0
B_Xm0DATA6
B_Xm0DATA10
B_Xm0DATA5
nCS_NAND1
nCS_AMD
B_Xm0DATA13
B_Xm0DATA7
B_Xm0DATA2
B_Xm0DATA12
nCS_AMD
B_Xm0DATA9
nCS_NAND2nCS_NAND3
B_Xm0ADDR10
B_Xm0ADDR6
B_Xm0ADDR15
B_Xm0ADDR13
B_Xm0ADDR9
B_Xm0ADDR1
B_Xm0ADDR7
B_Xm0ADDR3
B_Xm0ADDR5
B_Xm0ADDR8
B_Xm0ADDR2
B_Xm0ADDR11
B_Xm0ADDR4
B_Xm0ADDR12
B_Xm0ADDR14
B_Xm0ADDR0
B_Xm0ADDR15B_Xm0ADDR14
B_Xm0ADDR2
B_Xm0ADDR13
B_Xm0ADDR1
B_Xm0ADDR6B_Xm0ADDR5
B_Xm0ADDR11
B_Xm0ADDR7
B_Xm0ADDR3B_Xm0ADDR4
B_Xm0ADDR12
B_Xm0ADDR10
B_Xm0ADDR8B_Xm0ADDR9
B_Xm0DATA4
B_Xm0DATA0
B_Xm0DATA3B_Xm0DATA2
B_Xm0DATA5B_Xm0DATA6B_Xm0DATA7
B_Xm0DATA1
nCS_NAND3
nCS_NAND1nCS_NAND2
nCS_NAND0nCS_SRAMnCS_AMD
B_Xm0DATA10
B_Xm0DATA2
B_Xm0DATA14
B_Xm0DATA5
B_Xm0DATA9
B_Xm0DATA0
B_Xm0DATA15
B_Xm0DATA13
B_Xm0DATA3
B_Xm0DATA12
B_Xm0DATA8
B_Xm0DATA11
B_Xm0DATA4
B_Xm0DATA7
B_Xm0DATA1
B_Xm0DATA6
nCS_SRAM
nCS_NAND1
nCS_SRAMnCS_NAND2
nCS_NAND3nCS_SRAM
nCS_NAND0nCS_SRAM
nCS_SRAM
nCS_AMDnCS_SRAM
B_M0CSn4/NFCSn2[2]
B_Xm0CSn0[2]
B_Xm0CSn2/NFCSn0[2]
B_M0CSn5/NFCSn3[2]
B_Xm0ADDR[15:0] [2,6,15]
B_Xm0CSn3/NFCSn1[2]
B_Xm0ADDR[15:0] [2,6,15]
B_Xm0DATA[15:0][2,6,15]
B_Xm0FALE/ONDSMCLK[2]
B_Xm0FREn[2]
B_Xm0FCLE/ONDAVD[2,6]
B_Xm0OEn [2,6,15]B_Xm0WEn [2,6,15]
B_Xm0FWEn/ONDRPn[2]
B_Xm0FREn[2]
B_Xm0WEn[2,6,15]
B_Xm0BE1[2]B_Xm0BE0[2]
B_Xm0OEn[2,6,15]
B_Xm0FWEn/ONDRPn[2]B_Xm0FALE/ONDSMCLK[2]
B_Xm0FCLE/ONDAVD[2,6]
B_Xm0OEn[2,6,15]
B_Xm0BE0[2]B_Xm0BE1[2]
B_Xm0WEn[2,6,15]nCS_ETH [15]
nCS_ETH [15]
B_Xm0DATA[15:0][2,6,15]
nCS_EXT [6]
nCS_EXT [6]
nCS_ETH [15]nCS_EXT [6]
B_Xm0DATA[15:0][2,6,15]
Xm0FRnB2[2]Xm0FRnB1/ONDXL_INT1[2]Xm0FRnB0/ONDXL_INT0[2]
Xm0FRnB3[2]
Xm0FRnB0/ONDXL_INT0[2]
Xm0WAITn[2,6]
B_Xm0CSn1[2]
XnRESET [2,7,13,15,16,17]
XnRESET[2,7,13,15,16,17]
SROM_ADDR16[4,6]SROM_ADDR17[4,6]SROM_ADDR18[4,6]SROM_ADDR19[4,6]SROM_ADDR20[4,6]
SROM_ADDR20[4,6]
SROM_ADDR16[4,6]SROM_ADDR17[4,6]SROM_ADDR18[4,6]SROM_ADDR19[4,6]
VDD_3V3
VDD_3V3VDD_3V3VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
CFGB1
KHS02
12
43
TP14 M0WAITn
R12 100K
+CTB14
10uF/6.3V
R9 100K
CFGB2
KHS02
12
43
CB11
100nF
U3
Socket S-TSO-SM-048-A
2524232221201918
87654321
481716
9
2746
26281115124737
29313335384042443032343639414345
1013
14
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19
VSS0VSS1
nCEnOEnWE
nRY/BYnRESET
nBYTEVDD0
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9
DQ10DQ11DQ12DQ13DQ14
DQ15/A-1
A2013
14
CB12
100nF
R11 100K
U2
K6F1616U6A_EF55
A3A4A5
B1
B3B4
B6
C1C2
C3C4
C5C6
D2
D3
D4
D5
E2
E4
E5
F1F2
F3F4
F5F6
G1
G2
G3G4
G6
H1
H2H3H4H5
H6
A1B2A2G5B5A6
D6E1
D1
E6E3
A0A1A2
IO9
A3A4
IO1
IO10IO11
A5A6
IO2IO3
IO12
A17
A7
IO4
IO13
A16
IO5
IO15IO14
A14A15
IO6IO7
IO16
A19
A12A13
IO8
A18
A8A9A10A11
NC
nLBnUBnOEnWEnCS1CS2
VCCVCC
VSS
VSSVSS
TP19 M0FCLE
CFGB3
KHS02
12
43
CB13
100nF
CB14
100nF
TP12 M0OEn
CFGB4
KHS02
12
43
R13 100K
+CTB13
10uF/6.3V
CFGB5
KHS04
1234
8765
R6 100K
TP11 M0BE1
TP16 M0FREn
U4
Socket S-TSO-SM-048-A
123456789
101112131415161718192021222324
484746454443424140393837363534333231302928272625
NC0NC1NC2R/nB4R/nB3R/nB2R/nB1nREnCE1nCE2NC7VCC0VSS0nCE3nCE4CLEALEnWEnWPNC10NC11NC12NC13NC14
NC29NC28NC27NC26
IO7IO6IO5IO4
NC25NC24NC23VCC1
VSSNC21NC20NC19
IO3IO2IO1IO0
NC18NC17NC16NC15
TP17 M0FWEn
TP13 M0WEn
R14 100K
+CTB12
10uF/6.3V
R7 100K
CFGB6
KHS04
1234
8765
TP10 M0BE0
R10NC
R8 100K
R150
TP15 M0FRnB0
TP18 M0FALE
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S2 S1 S0
L L L Disconnect
L L H A1 = B1
L H H A2 = B1
<Silk>
CFGB7
CF
SROM
KEY(INT)
KEY(MSM)
MHL
CAM
MSM
1 2
CFGB8
1 2
OFF
21
CFGB9
OFF ON ON
OFFOFF ONOFF ON
OFFOFF ON ON ON
OFF ON ON OFF OFF
OFFOFF
OFF
OFF
ON
ON OFF
OFFOFF ON OFF OFF OFF
ON OFF OFF OFF OFF OFF
*KEY(MSM) case: Remove CF card & don't access SROM.
*To use MSM,CAM,CF, CFG3.1 on CPU b'd should be OFF.
CF,modem,key switching 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
4 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
msm_sel1
msm_sel1
msm_sel2
msm_sel2
msm_sel2
msm_sel2
msm_sel1
msm_sel1
KP_COL0/SROM_ADDR21[6,13]
msmADDR9/MHL_D2[6]
XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA [2,7]
msmADDR8/MHL_D1[6]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK [2,7]
KP_ROW4/CF_DATA11[5,13]
KP_COL4/CF_DATA3[5,13]
XmsmDATA9/KP_ROW2/CF_DATA9/MHL_D16 [2]
msmADDR10/MHL_D3[6]
XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL [2,7]
XmsmDATA14/KP_ROW7/CF_DATA14/MHL_D21 [2]
KP_ROW6/CF_DATA13[5,13]
XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0 [2,7]
XmsmDATA1/KP_COL2/CF_DATA1/MHL_D8 [2]
KP_ROW5/CF_DATA12[5,13]
KP_ROW1/CF_DATA8[5,13]
XmsmWEn/KP_ROW10/CF_CSn1/MHL_HSYNC [2]
KP_COL7/CF_DATA6[5,13]
XmsmDATA15/KP_ROW8/CF_DATA15/MHL_D22 [2]
KP_ROW7/CF_DATA14[5,13]
XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5 [2,7]
XmsmDATA4/KP_COL5/CF_DATA4/MHL_D11 [2]
KP_ROW0/CF_DATA7[5,13]
SROM_ADDR17[3,6]
KP_ROW2/CF_DATA9[5,13]
XmsmCSn/KP_ROW9/CF_CSn0/MHL_D23 [2]
SROM_ADDR20[3,6]
KP_COL3/CF_DATA2[5,13]
KP_ROW13/SROM_ADDR22[6,13]
XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2 [2,7]
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK [2,7]
XmsmDATA2/KP_COL3/CF_DATA3/MHL_D9 [2]
XmsmDATA10/KP_ROW3/CF_DATA10/MHL_D17 [2]
XmsmDATA7/KP_ROW0/CF_DATA7/MHL_D14 [2]
XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4 [2,7]
KP_ROW3/CF_DATA10[5,13]
XmsmREn/KP_ROW11/CF_IORN/MHL_IDCK [2]
XmsmDATA0/KP_COL1/CF_DATA0/MHL_D7 [2]
XmsmADDR13/KP_COL0/SROM_ADDR21/MHL_D6 [2]
SROM_ADDR19[3,6]
SROM_ADDR16[3,6]
XmsmDATA5/KP_COL6/CF_DATA5/MHL_D12 [2]
msmADDR11/MHL_D4[6]
KP_COL6/CF_DATA5[5,13]
XmsmDATA11/KP_ROW4/CF_DATA11/MHL_D18 [2]
XmsmDATA12/KP_ROW5/CF_DATA12/MHL_D19 [2]
XmsmDATA3/KP_COL4/CF_DATA3/MHL_D10 [2]
KP_ROW8/CF_DATA15[5,13]
XmsmADVN/KP_ROW13/SROM_ADDR22/MHL_DE [2]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK [2,7]
XmsmDATA6/KP_COL7/CF_DATA6/MHL_D13 [2]
XmsmIRQn/KP_ROW12/CF_IOWN/MHL_VSYNC [2]
XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC [2,7]
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR [2,7]
SROM_ADDR18[3,6]
XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3 [2,7]
XmsmDATA13/KP_ROW6/CF_DATA13/MHL_D20 [2]
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1 [2,7]
XmsmDATA8/KP_ROW1/CF_DATA8/MHL_D15 [2]
KP_COL2/CF_DATA1[5,13]
msmADDR0[6]msmADDR1[6]msmADDR2[6]msmADDR3[6]msmADDR4[6]msmADDR5[6]
msmADDR7/MHL_D0[6]msmADDR6[6]
CF_ADDR0[5]CF_ADDR1[5]CF_ADDR2[5]CF_IORDY[5]CF_INTRQ[5]CF_DMARQ[5]CF_DRESETN[5]CF_DMACKN[5]
msm_sel1msm_sel2
msmDATA13/MHL_D20[6]msmDATA14/MHL_D21[6]msmDATA15/MHL_D22[6]msmCSn/MHL_D23[6]msmWEn/MHL_HSYNC[6]msmREn/MHL_IDCK[6]
msmDATA12/MHL_D19[6]
msmDATA2/MHL_D9[6]
msmDATA6/MHL_D13[6]
msmDATA3/MHL_D10[6]
msmDATA1/MHL_D8[6]
msmDATA5/MHL_D12[6]msmDATA4/MHL_D11[6]
msmDATA7/MHL_D14[6]
msmDATA0/MHL_D7[6]
msmDATA10/MHL_D17[6]msmDATA9/MHL_D16[6]msmDATA8/MHL_D15[6]
msmDATA11/MHL_D18[6]
msmIRQn/MHL_VSYNC[6]
KP_COL1/CF_DATA0[5,13]
KP_COL5/CF_DATA4[5,13]KP_ROW11/CF_IORN[5,13]KP_ROW10/CF_CSn1[5,13]KP_ROW9/CF_CSn0[5,13]
KP_ROW12/CF_IOWN[5,13]
msmADDR13/MHL_D6[6]msmADDR12/MHL_D5[6]
msmADVN/MHL_DE[6]
SEL_CAM_BUF_EN[7]
KEY_SEL0 [13]KEY_SEL1 [13]
SEL_MHL_BUF_ENb[6]SEL_MHL_BUF_EN[6]
VDD_MSM
VDD_MSM
VDD_MSM
VDD_MSM
VDD_CAM_B
VDD_KEY
VDD_MSM
VDD_EXTR18100K
TP22
R16100K
CFGB8
SW-DIP2
12
43
R24
100K
CB16
100nFU7
SN74CB3T16212-DGV
56
542
3 53
524
5 51
506
8
17
4412
11 45
4610
9 47
487
1
43413936343230
42403735333129
13151821232527
14162022242628
55193849
S1
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND1
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
S0
6B17B18B19B1
10B111B112B1
6B27B28B29B2
10B211B212B2
6A17A18A19A110A111A112A1
6A27A28A29A210A211A212A2
S2GND2GND3GND4
U8
SN74CB3T16212-DGV
56
542
3 53
524
5 51
506
8
17
4412
11 45
4610
9 47
487
1
43413936343230
42403735333129
13151821232527
14162022242628
55193849
S1
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND1
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
S0
6B17B18B19B1
10B111B112B1
6B27B28B29B2
10B211B212B2
6A17A18A19A110A111A112A1
6A27A28A29A210A211A212A2
S2GND2GND3GND4
CFGB9
SW-DIP2
12
43
R17
100K
CFGB7
KHS02
12
43
CB17 100nF
CB15 100nF
U5
SN74CB3T16212-DGV
56
542
3 53
524
5 51
506
8
17
4412
11 45
4610
9 47
487
1
43413936343230
42403735333129
13151821232527
14162022242628
55193849
S1
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND1
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
S0
6B17B18B19B1
10B111B112B1
6B27B28B29B2
10B211B212B2
6A17A18A19A110A111A112A1
6A27A28A29A210A211A212A2
S2GND2GND3GND4
TP21
R25
100K
TP20
R19100K
TP23
U6
SN74LVC1G04DBV
24
531
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CompactFlash Card Socket
CompactFlash Card Socket
<Silk>CF
<GPIO Controll>ON : LowOFF : Input & Pull up disable
Compact Flash Card Socket 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
5 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
CF_nREGCF_nINPACK
CF_IORDY
CF_IREQ
CF_nREG
CF_CE0
nCSEL_0
CF_CE0
CF_ADDR1
CF_ADDR2
CF_nIORD
CF_nIORD
CF_nIOWR
CF_ADDR0
CF_IREQ
nCSEL_1
nCSEL_1
CF_ADDR1
CF_CE1
CF_ADDR0
CF_nINPACK
nCSEL_0
CF_nIOWR
CF_CE1
CF_IORDY
CF_ADDR2
CF_RESET
CF_RESET
nDASP_0_1
nDASP_0_1
nPDIAG_0_1
nPDIAG_0_1
XpwmTOUT0[2,18]
CF_DMARQ[4]
CF_DRESETN[4]
KP_ROW12/CF_IOWN[4,13]
KP_ROW9/CF_CSn0[4,13]
KP_ROW11/CF_IORN[4,13]KP_ROW10/CF_CSn1[4,13]
KP_COL4/CF_DATA3 [4,13]
KP_COL1/CF_DATA0 [4,13]KP_COL2/CF_DATA1 [4,13]
KP_COL6/CF_DATA5 [4,13]
KP_COL3/CF_DATA2 [4,13]
KP_COL5/CF_DATA4 [4,13]
KP_ROW0/CF_DATA7 [4,13]KP_COL7/CF_DATA6 [4,13]
KP_ROW3/CF_DATA10 [4,13]KP_ROW4/CF_DATA11 [4,13]
KP_ROW2/CF_DATA9 [4,13]KP_ROW1/CF_DATA8 [4,13]
KP_ROW7/CF_DATA14 [4,13]KP_ROW6/CF_DATA13 [4,13]
KP_ROW8/CF_DATA15 [4,13]
KP_ROW5/CF_DATA12 [4,13]
CF_IORDY[4]
CF_INTRQ[4]
KP_ROW8/CF_DATA15 [4,13]
KP_COL2/CF_DATA1 [4,13]
KP_COL6/CF_DATA5 [4,13]
KP_COL4/CF_DATA3 [4,13]
KP_COL1/CF_DATA0 [4,13]
KP_ROW5/CF_DATA12 [4,13]
KP_ROW0/CF_DATA7 [4,13]
KP_COL3/CF_DATA2 [4,13]
KP_ROW2/CF_DATA9 [4,13]
KP_ROW6/CF_DATA13 [4,13]
KP_COL7/CF_DATA6 [4,13]
KP_ROW3/CF_DATA10 [4,13]
KP_ROW1/CF_DATA8 [4,13]
KP_COL5/CF_DATA4 [4,13]
KP_ROW4/CF_DATA11 [4,13]
KP_ROW7/CF_DATA14 [4,13]
CF_ADDR2 [4]CF_ADDR1 [4]CF_ADDR0 [4]
KP_ROW12/CF_IOWN[4,13]
KP_ROW9/CF_CSn0[4,13]
CF_IORDY[4]
KP_ROW11/CF_IORN[4,13]
CF_INTRQ[4]
KP_ROW10/CF_CSn1[4,13]
CF_DRESETN[4]
CF_DMARQ[4]CF_DMACKN[4]
CF_ADDR2 [4]CF_ADDR1 [4]CF_ADDR0 [4]
CF_DMACKN[4]
VDD_CF
VDD_CF
VDD_CF
VDD_3V3VDD_CF
VDD_CF
VDD_CF
+
CTB15
10uF/6.3V
R37 0
R34
10K
R35 NC
R32 10K
R221
100K
CON1
CompactFlash (55358-5021)
212223234564748492728293031501214151617181920
732343542
137383940412443444546
91333362625
81011
51 52 53 54 55 56
D0D1D2D3D4D5D6D7D8D9
D10D11D12D13D14D15
GND2A7A6A5A4A3A2A1A0
nCS0nCS1nIORDnIOWRnIORDYGND1INTRQVCC2nCSELnVS2/OPENnRESETnIOCS16nDMARQnDMACKnDASPnPDIAGnATA_SELVCC1nVS1/GNDnWEnCD1nCD2A10A9A8
51 52 53 54 55 56
CB20
100nF
R29
10K
CON21
CompactFlash (55358-5021)
212223234564748492728293031501214151617181920
732343542
137383940412443444546
91333362625
81011
51 52 53 54 55 56
D0D1D2D3D4D5D6D7D8D9
D10D11D12D13D14D15
GND2A7A6A5A4A3A2A1A0
nCS0nCS1nIORDnIOWRnIORDYGND1INTRQVCC2nCSELnVS2/OPENnRESETnIOCS16nDMARQnDMACKnDASPnPDIAGnATA_SELVCC1nVS1/GNDnWEnCD1nCD2A10A9A8
51 52 53 54 55 56
R41
1K
CB18
100nF
LED1LTST-C150BKT (SMD3216 Blue)
12
R31 10K
R30 NC
R40 10K
R330
R39 10KR38
330
CB19
100nF
+CTB16
10uF/6.3V
Q1SI2333DS
3
1
2R36 0
R42NC
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ROM BUS
JF2
2
SMDK_S5PC110Base B/DJF1
QTE-040-01-L-D-EM2
JF1
External ROM Bus
2
MODEM&MHL I/F
QS
E-0
40-0
1-L-
D-E
M2
1
Mod
em I/
F
2
place resistors near to JB2
*LOGIC_pwr:B
*LOGIC_pwr:A
Ext. ROM Bus/ Host_Modem IF/MHL 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
6 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MHL_SCL0
MHL_CI2CA
MHL_I2S_SCKMHL_I2S_MCLK
MHL_SDA0
MHL_I2S_SDO1MHL_I2S_SDO0/SPDIFMHL_I2S_WS
MHL_SDA0
MHL_SCL0
MHL_I2S_SDO1
R_MCLK
MHL_I2S_SDO0/SPDIF
MHL_I2S_SCK
MHL_I2S_MCLK
MHL_I2S_WS
R_SDO0/SPDIF
R_SDO0/SPDIF
R_MCLK
B_Xm0DATA3
B_Xm0ADDR5
B_Xm0ADDR12
B_Xm0DATA7
B_Xm0ADDR10
B_Xm0ADDR0
B_Xm0DATA5
B_Xm0ADDR14
B_Xm0DATA11
B_Xm0ADDR7
B_Xm0DATA10
B_Xm0DATA0
B_Xm0DATA14
B_Xm0DATA2
B_Xm0ADDR8
B_Xm0ADDR4B_Xm0ADDR2
B_Xm0DATA4
B_Xm0DATA9
B_Xm0ADDR13
B_Xm0ADDR9
B_Xm0DATA12
B_Xm0DATA8
B_Xm0ADDR15
B_Xm0DATA15
B_Xm0ADDR11
B_Xm0ADDR1
B_Xm0DATA6
B_Xm0DATA1
B_Xm0DATA13
B_Xm0ADDR3
B_Xm0ADDR6
XpwmTOUT1[2,14,16,18]
msmDATA15/MHL_D22 [4]
B_Xm0ADDR[15:0] [2,3,15]
Xi2cSCL0 [2,7,10,11,16,17]
EXT_nRESET[2,19]
msmADDR3 [4]msmADDR0[4]
msmDATA5/MHL_D12 [4]
B_Xm0WEn[2,3,15]
msmDATA11/MHL_D18 [4]
msmDATA1/MHL_D8 [4]
msmDATA7/MHL_D14 [4]
Xi2cSDA0 [2,7,10,11,16,17]
msmDATA6/MHL_D13[4]
XEINT18/KP_COL2[2,13]
msmDATA12/MHL_D19[4] msmDATA13/MHL_D20 [4]
msmDATA2/MHL_D9[4] msmDATA3/MHL_D10 [4]
msmDATA8/MHL_D15[4]
B_Xm0ADDR[15:0][2,3,15]
B_Xm0DATA[15:0][2,3,15]
nCS_EXT[3]
msmDATA14/MHL_D21[4]
XEINT28/KP_ROW4[2,13,16]
msmDATA4/MHL_D11[4]
XEINT30/KP_ROW6 [2,13,16]
XpwmTOUT2[2,14,16,18]
B_Xm0OEn [2,3,15]
msmDATA9/MHL_D16 [4]
msmADDR2[4]msmADDR5 [4]
EXT_nRESET [2,19]
msmDATA10/MHL_D17[4]
XEINT30/KP_ROW6[2,13,16]
XpwmTOUT2 [2,14,16,18]
B_Xm0DATA[15:0] [2,3,15]
msmDATA0/MHL_D7[4]
XpwmTOUT1 [2,14,16,18]
msmADDR7/MHL_D0 [4]
msmADDR1 [4]
msmADDR6[4]msmADDR4[4]
SROM_ADDR17 [3,4]SROM_ADDR16[3,4]SROM_ADDR18[3,4]SROM_ADDR20[3,4]
KP_ROW13/SROM_ADDR22[4,13]
SROM_ADDR19 [3,4]KP_COL0/SROM_ADDR21 [4,13]
msmADDR10/MHL_D3[4]msmADDR8/MHL_D1[4]
msmADVN/MHL_DE[4]
msmADDR12/MHL_D5[4]
msmADDR9/MHL_D2 [4]msmADDR11/MHL_D4 [4]msmADDR13/MHL_D6 [4]
msmIRQn/MHL_VSYNC[4]
msmCSn/MHL_D23[4]msmWEn/MHL_HSYNC[4] msmREn/MHL_IDCK [4]
B_Xm0FCLE/ONDAVD[2,3]
Xi2sSDO0_0/PCM_SOUT2 [2,10]
Xi2sCDCLK0/PCM_EXTCLK2 [2,10]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 [2,8]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 [2,8]
Xi2sLRCK0/PCM_FSYNC2 [2,10]Xi2sSCLK0/PCM_SCLK2 [2,10]
Xi2sSDO0_1 [2,10]
SEL_MHL_BUF_EN [4]
SEL_MHL_BUF_ENb [4]
Xm0WAITn [2,3]
Xm0WAITn [2,3]
VDD_AUD
VDD_MSM
VDD_MSM
VDD_MSM
VDD_EXT
VDD_MSM
VDD_3V3
VDD_MSM
VDD_MSMVDD_3V3
VDD_MSM
CB23
100nF
TP32
R48
10K
R59 NC
R56 0
R66
1K
R57
0
R50
10K
R52 NC
TP29
R53 4.7K
+CTB18
10uF/6.3V
JF1QTE-040-01-L-D-EM2
135791113151719212325272931333537394143454749515355575961636567697173757779
2468
101214161820222426283032343638404244464850525456586062646668707274767880
8182
JF2QSE-040-01-L-D-EM2
135791113151719212325272931333537394143454749515355575961636567697173757779
2468
101214161820222426283032343638404244464850525456586062646668707274767880
8182
CB22
100nF
R222 NC
TP30
R54 NC
TP33
R61 NCCB24
100nF
+CTB17
10uF/6.3V
R67 0
CB21
100nF
TP28
U10
PCA9517DGK
1
2
3
4 5
6
7
8VCCA
SCLA
SDAA
GND EN
SDAB
SCLB
VCCB
R44
NC
TP24
TP31
TP25
R62 NC
R65
1K
CB26
100nF
R55 NC
R58 NCU9
SN74AVC8T245-DGV
123456789
101112
242322212019181716151413
VCCADIRA1A2A3A4A5A6A7A8GND1GND2
VCCB2VCCB1
OEnB1B2B3B4B5B6B7B8
GND3
R60 NC
R49
10K
R47
10K
R64 NC
R63 NC
R430
R45
NC
CB25
100nF
TP26
R460
TP27
R51 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAM B
CAMIF B port<Silk>
L : B to AH : A to B
R1
R2
(2.8V)Vout=0.6(1+R2/R1)R2=R1(Vout/0.6V-1)
DIRL : B to AH : A to B
Camera I/F B Port 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
7 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
B_CAM_B_D4
B_CAM_B_D1
B_CAM_B_D3
B_CAM_B_VSYNCB_CAM_B_CLK
B_CAM_B_D6
B_CAM_B_FIELD
B_CAM_B_D0
B_CAM_B_D5
B_CAM_B_D7
B_CAM_B_D2
B_CAM_B_D3
B_CAM_B_D6
B_CAM_B_D4
B_CAM_B_PCLK
B_CAM_B_D7
B_CAM_B_HREF
B_CAM_B_CLK
B_CAM_B_VSYNC
SEL_CAM_BUF_EN
B_CAM_B_D0B_CAM_B_D1
B_CAM_B_FIELD
B_CAM_B_D2
B_CAM_B_D5
B_CAM_B_HREFB_CAM_B_PCLK
B_CAM_B_RST
B_CAM_B_RSTB_CAM_B_STBY
B_CAM_B_STBY
B_CAM_B_CLK
B_CAM_B_FIELD
B_CAM_B_PCLK
B_CAM_B_D0
B_CAM_B_HREF
B_CAM_B_VSYNC
PWROn_BOARD[2,16,17]
Xi2cSCL0[2,6,10,11,16,17]Xi2cSDA0[2,6,10,11,16,17]
XmsmADDR7/CAM_B_D7/CF_DMACKN/MHL_D0 [2,4]
XmsmADDR8/CAM_B_PCLK/SROM_ADDR16/MHL_D1 [2,4]
XmsmADDR1/CAM_B_D1/CF_ADDR1/MIPI_ESC_CLK [2,4]
XmsmADDR3/CAM_B_D3/CF_IORDY/TS_SYNC [2,4]
XmsmADDR0/CAM_B_D0/CF_ADDR0/MIPI_BYTE_CLK [2,4]
XmsmADDR12/CAM_B_CLKOUT/SROM_ADDR20/MHL_D5 [2,4]
XmsmADDR2/CAM_B_D2/CF_ADDR2/TS_CLK [2,4]
XmsmADDR6/CAM_B_D6/CF_DRESETN/TS_ERROR [2,4]
XmsmADDR11/CAM_B_FIELD/SROM_ADDR19/MHL_D4 [2,4]
XmsmADDR5/CAM_B_D5/CF_DMARQ/TS_DATA [2,4]XmsmADDR4/CAM_B_D4/CF_INTRQ/TS_VAL [2,4]
XmsmADDR10/CAM_B_HREF/SROM_ADDR18/MHL_D3 [2,4]XmsmADDR9/CAM_B_VSYNC/SROM_ADDR17/MHL_D2 [2,4]
PWROn_BOARD[2,16,17]
SEL_CAM_BUF_EN [4]
XEINT27/KP_ROW3 [2,13,16,17]XEINT3 [2]
XnRESET[2,3,13,15,16,17]DC5V
VDD_MSM
VDD_CAM_EXT
VDD_MSM
VDD_CAM_B VDD_CAM_B
VDD_CAM_B
VDD_CAM_B
VDD_CAM_BVDD_CAM_EXT
VDD_CAM_EXT
DC5V
R75100K/1%
TP46
TP35 B_CAMPCLK
R72 0
U12
SN74AVC4T245DGV
12
4567
1615
1312111098
3 14
VCCA1DIR
1A11A22A12A2
VCCB1OEn
1B11B22B12B2
GND2GND1
2DIR 2OEn
CON2
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 62 63 64
+CTB23
10uF/10V
CB29
100nF
TP39
R690
TP34 B_FIELD
TP41 B_CAMMCLK
TP48
C1 22pF
TP45
L12.2uH (LQH32CN2R2M33)
1 2
+CTB22
10uF/6.3V
TP50
TP37 B_CAMHREF
TP47
TP36 B_CAMVSYNC
CB30
100nF
CB27
100nFU11
SN74AVCA164245DGG
4746444341403837
3635333230292726
124
4825
2356891112
1314161719202223
3142 7
18
45393428
4101521
1A11A21A31A41A51A61A71A8
2A12A22A32A42A52A62A72A8
1DIR2DIR
1OE2OE
1B11B21B31B41B51B61B71B8
2B12B22B32B42B52B62B72B8
VCCA1VCCA0 VCCB0
VCCB1
GND0GND1GND2GND3
GND7GND6GND5GND4
CB33
100nF
TP40
TP38 B_CAMDATA0
CB28100nF
R74
365K/1%
U13
LTC3406ES5
4
1
3
5
2
VIN
RUN
SW
VFB
GN
D
TP43
CB32
100nF
JP1A2-2PA-2.54DSA
1 2
R73 10K
+CTB19
10uF/6.3V
R70 10K
R68 0
TP42
CB31
100nF
+CTB21
10uF/10V
+CTB20
10uF/6.3V
TP44
R71
0
TP49
TP51
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
[SPDIF OUT]
- Since these are shared with other module[For isolate purpose only]
place resistors near to JB2
SCLK, LRCLK, SDO should havesame routing length!!!CDCLK(max 24MHz) should beguarded by ground!!!
[WM9713 AC97]
SCLK, LRCLK, SDO should havesame routing length!!!CDCLK(max 24MHz) should beguarded by ground!!!
GPIO I2S Audio Port 1
SCLK, LRCLK, SDO should have samerouting length!!!CDCLK(max 24MHz)should be guarded byground!!!
[WM8580 Pri I2S/PCM]GPIO I2S Audio Port 0
[Module2/3/4]
[I2S2/PCM0/SPDIF]
[I2S1/PCM1/AC97]
GPIO I2S Audio Port 2
[I2S0/PCM2]
[WM8580 Sec.Interface I2S/PCM]
[WM8580 Sec.Interface I2S/PCM]
[2]CFGB10
Audio1:WM9713AC97
Audio2:SPDIFOUt
Off
Audio2:WM8580IIS/PCM
[1]
<Silk>
Audio1:WM8580IIS/PCM
On
Place U14,U15 closeto U16,U17
Audio Switch 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
8 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
AUDIO2_En
AUDIO1_SELAUDIO1_En
AUDIO2_SEL
AUDIO1_SELAUDIO2_SEL
T_Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK [16,17]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2[2,6]
T_Xi2sCDCLK0/PCM_EXTCLK2 [2,6,10]
T_XpcmSOUT0/Xi2sSDO2 [17]
Xi2sSDO0_2[2,10]
Xi2sSDI1/PCM_SIN1/AC97_SDI[2]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2[2,6]
B_WM8580_I2S_SCLK/PCM_SCLK [10]
Xi2sSDO0_1[2,6,10]
B_SPDIF_EXTCLK0 [11]
B_WM9713_AC97_SYNC [9]
T_Xi2sSDO0_2 [2,10]
B_WM8580_I2S_DI/PCM_SIN [10]B_WM8580_I2S_DO/PCM_SOUT [10]
B_WM8580_I2S_DI/PCM_SIN [10]
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2[2]
T_XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 [17]
Xi2sSDO0_0/PCM_SOUT2[2,6,10]
B_WM8580_I2S_DO/PCM_SOUT [10]
Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[2]
Xi2sCDCLK0/PCM_EXTCLK2[2,6,10]
B_WM8580_I2S_LRCLK/PCM_FSYNC [10]
T_Xi2sSDO0_0/PCM_SOUT2 [2,6,10]
Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[2]
B_WM9713_AC97_RSTn [9]
Xi2sSDO1/PCM_SOUT1/AC97_SDO[2]
B_WM9713_AC97_SDO [9]
Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[2]
XpcmSOUT0/Xi2sSDO2[2]
B_WM8580_I2S_CDCLK/PCM_EXTCLK [10]
Xi2sSCLK0/PCM_SCLK2[2,6,10] T_Xi2sSCLK0/PCM_SCLK2 [2,6,10]
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2[2,6]
B_SPDIF_OUT0 [11]
Xi2sSDI1/PCM_SIN1/AC97_SDI[2]Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[2]
B_WM8580_I2S_CDCLK/PCM_EXTCLK [10]
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2[2,6]
T_Xi2sSDI0/PCM_SIN2 [2,10]
T_XpcmSIN0/Xi2sSDI2 [17]
Xi2sSDI0/PCM_SIN2[2,10]
B_WM8580_I2S_LRCLK/PCM_FSYNC [10]
T_Xi2sSDI1/PCM_SIN1/AC97_SDI [16,17]
T_XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 [17]
T_Xi2sLRCK0/PCM_FSYNC2 [2,6,10]Xi2sLRCK0/PCM_FSYNC2[2,6,10]
XpcmSOUT0/Xi2sSDO2[2]
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2[2]
T_Xi2sSDO1/PCM_SOUT1/AC97_SDO [16,17]
XpcmSIN0/Xi2sSDI2[2]
B_WM9713_AC97_BITCLK [9]
XpcmSIN0/Xi2sSDI2[2]
Xi2sSDO1/PCM_SOUT1/AC97_SDO[2]
Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[2]
B_WM8580_I2S_SCLK/PCM_SCLK [10]
T_Xi2sSDO0_1 [2,6,10]
T_XpcmFSYNC0/LCD_FRM/Xi2sLRCK2 [17]
B_WM9713_AC97_SDI [9]
T_Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn [16,17]Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[2]T_Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC [16,17]
VDD_AUD
VDD_AUD
VDD_AUD
R88 NC
R217
100K
R90 NC
CFGB10
KHS02
12
43
R220
0
R76 NC
R86 NC
R89 NC
R77 NC
R83 NC
R218
100K
R87 NC
CB34
100nF
U15
SN74CBTLV3383DGVRE4
1
23
4 5
67
8 9
1011
12
24
2322
21 20
1918
17 16
1514
13nBE
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
BX
U14
SN74CBTLV3383DGVRE4
1
23
4 5
67
8 9
1011
12
24
2322
21 20
1918
17 16
1514
13nBE
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
BX
CB35
100nF
R81 NCR79 NC
R219
0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(Headphone L/R OUT)
Audio(WM9713_AC97)
(MIC In)
(Line L/R In)
(47K)
Audio(WM9713_AC97) 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
9 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
B_WM9713_AC97_SDI [8]B_WM9713_AC97_BITCLK [8]
B_WM9713_LINE_R [12]
WM9713_OUT_L[12]
B_WM9713_AC97_RSTn [8]
B_WM9713_AC97_SDO [8]
WM9713_OUT_R[12]
B_WM9713_MIC [12]
B_WM9713_LINE_L [12]
B_WM9713_AC97_SYNC [8]
VDD_AUD
VDD_AUD
VDD_AUD
VDD_AUD
VDD_AUDVDD_1V8
R928.2K
C12220pF
C10
220pF
CB40
100nF
C13
1uF
+CTB25
4.7uF,6.3V
R1000
C2
1uF
CB39
100nF
CB46
100nF
+CTB24
4.7uF,6.3V
R93
8.2K
R9647K
R98 0/R1608C11
1uF
WM9713LGEFL/RV
U16
WM9713LGEFL/RV1 2 3 4 5 6 7 8 9 10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
4849
DB
VD
D
MC
LKA
MC
LKB
DG
ND
1
SD
ATA
OU
T
BIT
CLK
DG
ND
2
SD
ATA
IN
DC
VDD
SY
NC
RE
SE
TB
WIP
ER
LINER
LINEL
MICOM
MIC1
MONOIN
PCBEEP
TPGND
Y-
X-
Y+
X+
TPVDD
SP
KR
SP
KL
SPKG
ND
OU
T4
CA
P2
MO
NO
MIC
2B
MIC
2A
MIC
BIA
S
VR
EF
AGN
D
AV
DD
OUT3
SPKVDD
HPL
HPGND
HPR
AGND2
HPVDD
GPIO1/PCMCLK
GPIO2/IRQ
GPIO3/PCMFS
GPIO4/PCMDAC
GPIO5/PCMADCGND
R101100K
C6
220pF
CB45100nF
C9
220pF
R232
0
C4
1uF
OSC1
ISXO-5 (SMD 24.576MHz)_3.3V
1 2
34
OE GND
OUTVDD
CB38100nF
CB44100nF
R91
8.2K
+CTB29
4.7uF/6.3V
R958.2K
C3
1uFCB41
1uF
+
CTB26
100uF/6.3V
R233
0
CB42
100nF
+
CTB27100uF/6.3V
R236
0
CB37100nF
C8
220pF
C5
1uF
C7
1uF
R234
0
R99NC
CB36
100nF
R97100K
CB43100nF
+CTB28
4.7uF/6.3V
R235
0
R9447K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
2-Wire ModeSW mode
Manufacturer : GolledgeDescription : SM Crystal 12pFPackage : HC49-4H SMD (12.9 x 4.8 x 4.3 mm)
WM8580A
NC for Ext. clock
Audio(WM8580_PCM/IIS & 5.1CH)
* Note:CTB19 ~ 24 should be placed as close as possible to thecodec chip
MultiCh. L/R AudioOUT
WM8580_MasterCLKSelection
IIC slaveaddr=0x36(W)
to test I2S0 5.1ch(extraly can testI2S1 2ch)
24MHz for Codec master
<Silk>
Voice Ext. CLK
External CLK
AUDIO MCLK SEL
AP_CLKOUTtoXTI
I2S0 CDCLK
[6]
CFGB11
[4]
I2S1,2 CDCLK
[5]
[2]
[1]
HDMI Audio ExtCLK
[3]
Audio(WM8580_PCM/IIS & 5.1CH) 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
10 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
I2SMCLK_WM8580
EXTCLKIN_WM8580
I2SMCLK_WM8580
EXTCLKIN_WM8580
T_Xi2sLRCK0/PCM_FSYNC2[2,6]
EXT_AUD_CLK
T_Xi2sSDO0_2[2]
T_Xi2sSCLK0/PCM_SCLK2[2,6]
BB_WM8580_LINEIN_L[12]
SPDIFIN_WM8580[11]
WM8580_OUT_RL [12]
BB_WM8580_LINEIN_R[12]
XEINT19/KP_COL3[2,13]
WM8580_OUT_FL [12]
T_Xi2sSDO0_0/PCM_SOUT2[2,6]
EXT_VOICE_CLK
Xi2cSCL0[2,6,7,11,16,17]
B_WM8580_I2S_DO/PCM_SOUT[8]
Xi2cSDA0[2,6,7,11,16,17]
WM8580_OUT_RR [12]
B_WM8580_I2S_LRCLK/PCM_FSYNC[8]
WM8580_OUT_Sub [12]
B_WM8580_I2S_SCLK/PCM_SCLK[8]
WM8580_OUT_FR [12]
T_Xi2sSDO0_1[2,6]
B_WM8580_I2S_DI/PCM_SIN[8]
WM8580_OUT_Center [12]
T_Xi2sSDI0/PCM_SIN2[2]
EXT_SPDIF_CLK [11]
EXT_HDMI_AUDIO_CLK [11]
EXT_AUD_CLK
T_Xi2sCDCLK0/PCM_EXTCLK2[2,6]B_WM8580_I2S_CDCLK/PCM_EXTCLK[8]
XCLKOUT[2]EXT_HDMI_AUDIO_CLK[11]
EXT_VOICE_CLK
VDD_AUD
VDD_AUD
DC5VVDD_AUDVDD_AUD
VDD_AUD
VDD_AUD
CB51
100nF
R103 NC
CB48
100nF
R102 0
R238 0
U17
WM8580A
162
171
34
14
242223192021
28262725
32333431
131211
5
9876
18
36
35
4045
3946
10
15
30
29
41
42
43
44
47
48
3738
DVDDPVDD
DGNDPGND
XTIXTO
SPDIFIN1
MCLKPAIFRX_LRCLKPAIFRX_BCLKDIN1DIN2DIN3
MFP2PAIFTX_LRCLKMFP1DOUT
SDINSCLKCSBSDO
MFP3MFP4MFP5MFP10
MFP6MFP7MFP8MFP9
MUTE
AINL
AINR
AVDDVREFP
AGNDVREFN
SPDIFOP
CLKOUT
SWMODE
HWMODE
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
ADCREFPVMID
C15
15pF
R241 0
C18
1uF
R247 0
C42
NC
+CTB30
10uF/6.3VC14
15pF
+
CTB36
10uF/6.3V
R249 0
OSC4
2.048MHz (SMD,SCO-103)
1 2
34
OE GND
OUTVDD
R243 0
+
CTB39
10uF/6.3V
C41
100pF
+
CTB35
10uF/6.3V
+CTB40
10uF/6.3V
R248 0
R107 0
R106 10K
CB49
100nF
+
CTB34
10uF/6.3V
R109
NC
JP2A2-2PA-2.54DSA
1 2
+
CTB37
10uF/6.3V
+
CTB38
10uF/6.3V
R239 0
R250 0
X1
12MHz (SMD, GSX49-4/351BF)
R105 10K
C171uF
CFGB11
KHS06
1234
876
59101112
R111 0
R110 0
CB47
100nF
R240 0
CB52100nF
+CTB3210uF/6.3V
OSC3
16.9344MHz (SMD,SCO-103)
1 2
34
OE GND
OUTVDD
R104 NC
R237 0
C16 0.1uF
R245 0
CB50
100nF
R242 0
+CTB31
10uF/6.3V
+
CTB33
10uF/6.3V
OSC2
ISXO-5 (SMD 24.576MHz)
1 2
34
OE GND
OUTVDD
R246 0
R244 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For Multi_Master I2C
IIC E2PROM
<Silk>I2C Header
termination resistors
[TOSLINK]
[WM8580 spdif input]
S/PDIF Audio Out
8-TSSOP package
SPDIF Out / IIC EEPROM 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
11 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
Xi2cSDA1 [2]Xi2cSCL0[2,6,7,10,16,17]Xi2cSDA0[2,6,7,10,16,17]
Xi2cSCL1 [2]
B_SPDIF_EXTCLK0[8]
SPDIFIN_WM8580 [10]
B_SPDIF_OUT0[8]
Xi2cSDA0 [2,6,7,10,16,17]Xi2cSCL0 [2,6,7,10,16,17]
EXT_SPDIF_CLK [10]
VDD_AUD
VDD_EXT
R112 NC
U18
S524AD0XD1
1234 5
678A0
A1A2VSS SDA
SCLWP
VDD
(HDR8-2.54-MALE)
CON6
A1-8PA-2.54DSA
68
3
7
24
5
1
CB54
100nF
S.PDIF
CON5
GP1FM313TZ
1
32
4 5
R124
0
R125
0
FB1
BLM18PG121SN1
R123 0
CB53
100nF
R114
22
R122 0
R126
0
R113
22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Silk>
<Silk>
Headphone/Front LR
Line In Right
<Silk>
(Recording)
<Silk>
[1] : Speaker
0 : NC ON1 : NO ON
Line In Left
Center/Sub
[3] : LineIn
Off: LINEIN On: MIC[4] : 8580 sel
<Silk>
[2] : Mic
Selector
Line In
Mic In
Off: WM8580(IIS)
On: WM9713(AC97)
<Silk>
CFGB12:Audio Connector
Rear LR
Audio Jack 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
12 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
WM8580_nLineIn/Mic inLineIn_nWM8580/WM9713Mic_nWM8580/WM9713
Speaker_nWM8580/WM9713
LineIn_nWM8580/WM9713
Mic_nWM8580/WM9713
WM8580_nLineIn/Mic in
Speaker_nWM8580/WM9713
WM8580_OUT_Center[10]
BB_WM8580_LINEIN_L[10]
WM9713_OUT_L[9]
B_WM9713_LINE_L[9]
B_WM8580_LINEIN_R
B_WM9713_MIC[9]
WM8580_OUT_RR[10]
B_WM8580_LINEIN_L
WM8580_OUT_FL[10]
B_WM8580_MIC
B_WM8580_LINEIN_L
WM8580_OUT_RL[10]
B_WM8580_MIC
B_WM8580_LINEIN_R
WM8580_OUT_Sub[10]
WM8580_OUT_FR[10]
B_WM9713_LINE_R[9]
WM9713_OUT_R[9]
BB_WM8580_LINEIN_R[10]
VDD_AUD
VDD_AUD
VDD_AUD
VDD_AUD
VDD_AUD
VDD_AUD
CB57100nF
+
CTB4410uF/6.3V
Gnd
L
R
CON8PJ-327-2
3 2 14
CB56100nF
CB58100nF
CFGB12
KHS04
1234
8765
Gnd
L
R
CON10PJ-327-2
3 2 14
+
CTB4210uF/6.3V
+CTB45
10uF/6.3VU22
MAX4764ETB
4
8
2
10
6 7
5
3
9
1
11
NC1
NC2
NO1
NO2
GND IN2
IN1
COM1
COM2
VCC
11
+
CTB4310uF/6.3V
Gnd
L
R
CON7PJ-327-2
3 2 14
R128
2K
C19
220pF
R129 0
R127
0
U21
MAX4764ETB
4
8
2
10
6 7
5
3
9
1
11
NC1
NC2
NO1
NO2
GND IN2
IN1
COM1
COM2
VCC
11
Gnd
L
R
CON9PJ-327-2
3 2 14
CB55100nF
Gnd
L
R
CON11PJ-327-2
3 2 14
U20
MAX4764ETB
4
8
2
10
6 7
5
3
9
1
11
NC1
NC2
NO1
NO2
GND IN2
IN1
COM1
COM2
VCC
11
RA2
100K
1 2 3 4
8 7 6 5
+CTB4110uF/6.3V
U19
MAX4764ETB
4
8
2
10
67
5
3
9
1
11
NC1
NC2
NO1
NO2
GNDIN2
IN1
COM1
COM2
VCC
11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Silk>
Qwerty keypad
QWERT_KEY
<Silk>Extended_KEY
Extra Keypad(14X8)
External Keypad 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
13 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
kp_ROW0kp_ROW1
kp_COL4
kp_COL3
kp_COL5
kp_COL6
kp_COL7
kp_ROW10
kp_COL4
kp_COL4
kp_COL6kp_ROW1
kp_ROW1
kp_ROW7
kp_ROW5
kp_ROW2
kp_COL6
kp_ROW12
kp_COL1
kp_ROW8
kp_ROW3
kp_ROW11
kp_COL6
kp_ROW4
kp_ROW8
kp_ROW9
kp_COL3
kp_ROW4
kp_ROW11
kp_COL2
kp_ROW7
kp_COL3
kp_ROW13
kp_ROW3
kp_ROW5
kp_ROW10
kp_COL7
kp_ROW0
kp_COL3
kp_COL1
kp_ROW6
kp_COL1
kp_ROW9
kp_COL0
kp_COL5
kp_ROW6
kp_COL0
kp_COL7
kp_COL7
kp_COL2
kp_ROW2
kp_COL5
kp_ROW12kp_ROW0
kp_COL0
kp_COL4
kp_ROW13
kp_COL2
kp_COL5
XEINT24/KP_ROW0[2,16,17]
XEINT19/KP_COL3[2,10]XEINT20/KP_COL4[2,18]
XnRESET[2,3,7,15,16,17]
XEINT21/KP_COL5[2,18]
XEINT29/KP_ROW5[2,16]XEINT16/KP_COL0[2]
XEINT27/KP_ROW3[2,7,16,17]
XEINT23/KP_COL7[2,18]
XEINT26/KP_ROW2[2,16,17]
XnRESET[2,3,7,15,16,17]
XEINT18/KP_COL2[2,6]
XEINT28/KP_ROW4[2,6,16]
XEINT25/KP_ROW1[2,16,17]
XEINT22/KP_COL6[2,18]
XEINT30/KP_ROW6[2,6,16]XEINT31/KP_ROW7[2,16,18]
XEINT17/KP_COL1[2]
KP_COL2/CF_DATA1[4,5]
KP_ROW4/CF_DATA11[4,5]KP_COL1/CF_DATA0[4,5]
KP_ROW3/CF_DATA10[4,5]
KP_COL4/CF_DATA3[4,5]
KP_ROW2/CF_DATA9[4,5]
KP_COL7/CF_DATA6[4,5]KP_COL6/CF_DATA5[4,5]KP_COL5/CF_DATA4[4,5]
KP_COL3/CF_DATA2[4,5]
KP_ROW0/CF_DATA7[4,5]KP_ROW1/CF_DATA8[4,5]
KP_COL0/SROM_ADDR21[4,6]
KP_ROW12/CF_IOWN[4,5]KP_ROW13/SROM_ADDR22[4,6]
KP_ROW9/CF_CSn0[4,5]
KP_ROW6/CF_DATA13[4,5]
KP_ROW11/CF_IORN[4,5]
KP_ROW5/CF_DATA12[4,5]
KP_ROW7/CF_DATA14[4,5]
KP_ROW10/CF_CSn1[4,5]
KP_ROW8/CF_DATA15[4,5]
KEY_SEL1[4]KEY_SEL0[4]
VDD_KEY VDD_KEYVDD_KEY
VDD_KEY
VDD_KEY
TP56
D9 MM
BD
101L
T1
13
2
RA322
1234
8765
R135 1K
D5 MM
BD
101L
T1
13
2
R130
100K
SW1SKQYPCE010
SW3SKQYPCE010
C20
NC
TP54
D6 MM
BD
101L
T1
13
2
SW5SKQYPCE010
TP52
TP53
U24
SN74CB3T16212-DGV
56
542
3 53
524
5 51
506
8
17
4412
11 45
4610
9 47
487
1
43413936343230
42403735333129
13151821232527
14162022242628
55193849
S1
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND1
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
S0
6B17B18B19B1
10B111B112B1
6B27B28B29B2
10B211B212B2
6A17A18A19A110A111A112A1
6A27A28A29A210A211A212A2
S2GND2GND3GND4
D1 MM
BD
101L
T1
13
2
R132 1K
D10 M
MB
D10
1LT1
13
2
CB60100nF
R131 1K
JOG1
SKRHAAE010
1 4
3 6
2 5
A B
C D
Center Common
U23
SN74CB3T16212-DGV
56
542
3 53
524
5 51
506
8
17
4412
11 45
4610
9 47
487
1
43413936343230
42403735333129
13151821232527
14162022242628
55193849
S1
1B11A1
1A2 1B2
2B12A1
2A2 2B2
3B13A1
GND1
VCC
5B25A2
5A1 5B1
4B24A2
4A1 4B1
3B23A2
S0
6B17B18B19B1
10B111B112B1
6B27B28B29B2
10B211B212B2
6A17A18A19A110A111A112A1
6A27A28A29A210A211A212A2
S2GND2GND3GND4
C21
NC
CON13
GF056-30S-LSS-P2000
123456789
101112131415161718192021222324252627282930
31 32
R133 1K
D8 MM
BD
101L
T1
13
2
TP57
SW2SKQYPCE010
D2 MM
BD
101L
T1
13
2
R134 1K
D7 MM
BD
101L
T1
13
2
CON12
GF056-30S-LSS-P2000
123456789
101112131415161718192021222324252627282930
31 32
CB59100nF
D3 MM
BD
101L
T1
13
2
TP55
SW4SKQYPCE010
D4 MM
BD
101L
T1
13
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART3
UART2
IrDA
UART1
S - L : B1 port, H : B2 portOE - L : Output enable H : all disconnect
CTS2RTS2
TXD3RXD3
UART / IrDA Interface
SDBW
IRDA_TXD
IRDA_RXD
COM2 portUART1/2/3
<Silk>
<Silk>COM1 portUART0 Only
UART Headerfor Highspeed Test
IrDA(U2)
PIN1
OFF
CFGB13:COM2
X
X X
ON ON
OFF
PIN2 PIN3
UART3
ON
<Silk>
OFF
UART2
UART1
XX
ON
(DTR)
(DSR)
<Silk>UART Header
default: ON ON ON
PIN4
OFF
OFF
OFF
OFF
UART/IrDA 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
14 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
SEL_U3_IR
SEL_U1_U2
SEL_U1_U2
SEL_U2_U3
SEL_U2_U3
nEN_COM2
SEL_U3_IRnEN_COM2
nEN_COM2
nEN_COM2
XuTXD3/RTSn2/UART_AUDIO_RTSn[2,16,17]
XuRTSn0[2]XuTXD0[2]
XuTXD1[2]
XuRTSn1[2]
XpwmTOUT1[2,6,16,18]
XuRXD0[2]XuTXD0[2]
XuTXD2/UART_AUDIO_TXD [2,16,17]XuTXD1[2]
XuRXD3/CTSn2/UART_AUDIO_CTSn[2,16,17]
XuRXD0[2]XuCTSn0[2]
XpwmTOUT2[2,6,16,18]
XuCTSn1[2]
XuRXD1[2]
XuRXD2/UART_AUDIO_RXD [2,16,17]
XuRXD1[2]XuRXD3/CTSn2/UART_AUDIO_CTSn [2,16,17]
XuRXD2/UART_AUDIO_RXD[2,16,17]XuTXD2/UART_AUDIO_TXD[2,16,17]
XuTXD3/RTSn2/UART_AUDIO_RTSn [2,16,17]XuRTSn0[2]XuCTSn0[2]
XuRTSn1 [2]XuCTSn1 [2]
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
+ CT2
0.1uF/16V
CFGB13
KHS04
1234
8765
C22
330pF
CON14
BOXCONN_DB9(female)
594837261
1011
CB62
100nF
R141100K
+CT6
0.1uF/16V
R143
NC
U28
SN74CBTLV3257PWR
25
1114
36
1013
1581
47912
161B12B13B14B1
1B22B23B24B2
nOEGNDS
1A2A3A4A
VCC
+CT5
0.1uF/16V
U30
HSDL-3602
1
2
3
45
6
7
8
9
10
11
VC
C
AGN
D
FIR_SEL
MD0MD1
NC
GN
D
RXD
TXD
LED
A
11
R137 0
CB64
100nF
R138 10K
+
CT10.1uF/16V
CB63
100nF
RA4
100K
1 2 3 4
8 7 6 5
CB61
100nF
R251 0
+CT3
0.1uF/16V
(HDR8-2.54-MALE)
CON22
A1-8PA-2.54DSA
68
3
7
24
5
1
+CT8
0.1uF/16V
U29
SN74CBTLV3257PWR
251114
361013
15 81
479
12
16 1B12B13B14B1
1B22B23B24B2
nOE GNDS
1A2A3A4A
VCC
C24
330pF
C28
330pF
C29
330pF
R136 0
(HDR12-2.54-MALE)
CON16
A1-12PA-2.54DSA
345
8
1011
12
9
7
6 12
C23
330pF
C27
330pF
R144
100K
R252 0
R140 0
+CT7
0.1uF/16V
C25
330pF
C26
330pF
R253 0
R139 10K
U26
MAX3232CSE
1
3
4
5
141378
16
2
6
15
111210
9
C1+
C1-
C2+
C2-
T1OUTR1IN
T2OUTR2IN
VCC
V+
V-
GND
T1INR1OUTT2INR2OUT
CON15
BOXCONN_DB9(female)
594837261
1011
U25
MAX3243CAI
28
241
2
27
3
1413
22 21
1918171615
25
54
23
20
26
678
9101112
C1+
C1-C2+
C2-
V+
V-
T1INT2IN
nFORCEOFF nINVALID
R1OUTR2OUTR3OUTR4OUTR5OUT
GND
R2INR1IN
FORCEON
R2OUTB
VCC
R3INR4INR5IN
T1OUTT2OUTT3OUTT3IN
R145
100K
+CTB46
6.8uF/6.3V
CB66
100nF
U27
SN74CBTLV3257PWR
25
1114
36
1013
1581
47912
161B12B13B14B1
1B22B23B24B2
nOEGNDS
1A2A3A4A
VCC
R254 0
R142
2.7
+ CT4
0.1uF,16V/T2012
CB65
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(XFMRS / XFATM9A-COMBO1-4S 0548)
microchip_93LC46A_DIP8
100Mbps<Silk>FDPLX
<Silk>LINK
<Silk>
J1 - ON : Use 8bit mode(&remove r224-r231) OFF : Use 16bit mode(&mount r224-r231&removeR152)J2 - ON : Use EEPROM OFF : Not Use EEPROM
(Transformer embeded)
Ethernet 100Mbp(DM9000) 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
15 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
TX_PTX_N
RX_NRX_P
nSPD_100
RX_P
nLINK_ACK
RX_N
TX_P
B_Xm0ADDR0
TX_N
nLINK_ACKnSPD_100
nFDUPLEX
B_Xm0DATA14
B_Xm0DATA8
B_Xm0DATA6B_Xm0DATA7
B_Xm0DATA3
B_Xm0DATA9
B_Xm0DATA11
B_Xm0DATA13
B_Xm0DATA15
B_Xm0DATA0
B_Xm0DATA5
B_Xm0DATA12
B_Xm0DATA10
B_Xm0DATA1B_Xm0DATA2
B_Xm0DATA4
nFDUPLEX
B_Xm0DATA[15:0][2,3,6]
B_Xm0WEn[2,3,6]
nCS_ETH[3]
B_Xm0OEn[2,3,6]
XEINT9[2]
B_Xm0ADDR0[2,3,6]
XnRESET[2,3,7,13,16,17]
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
ETH_AVDD_1V8
VDD_3V3
ETH_AVDD_1V8
VDD_3V3
C36
100nFR155
49.9/1%
J11 2
R225 0
C37
100nF
R157
49.9/1%
R151
330
R226 0
U32
DM9000B-8/16
121110987654321
24 23 22 21 20 19 18 17 16 15 14 13
37 38 39 40 41 42 43 44 45 46 47 48
252627282930313233343536
SD5SD6SD7
AVDD18TX-TX+
AGND3AGND2
RX-RX+
AVDD18BGRES
LED
3/S
D14
VDD
2W
AK
E/S
D15
EE
DC
SE
ED
CK
EE
DIO
SD
0S
D1
SD
2G
ND
2S
D3
SD
4
CS
#LE
D2(
IOW
AIT
/WA
KE
UP
for e
epro
m)
LED
1(IO
16 fo
r eep
rom
)P
WR
ST#
TES
TVD
D1
X2
X1
GN
D1
SD
AGN
D1
BGG
ND
GP6/SD13GP5/SD12GP4/SD11GP3/SD10GP2/SD9VDD3GP1/SD8CMDGND3INTIOR#IOW#
R227 0R228 0R229 0
C3422pF
R230 0R231 0
U31
DIP 8P IC SOCKET(microchip_93LC46A_DIP8)
1234 5
678
Y1
25MHz_22pF_50ppm
LED2
LED-Green (SMD 3216)
12C31
100nF
R223 0
R152
NC
R156
49.9/1%
R150
330
+ C351uF
12
+CTB47
10uF/6.3V
CON17
Single_Ports_Combo_0
12345678
910
GNDTX_CTTX-TX+XRX_CTRX-RX+
ShieldShield
LED4
LED-Green (SMD 3216)
12
C38
100nF
C3322pF
+ C32
220uF/16V
12
R1534.7k
CB67
100nF
R148
4.7k
J21 2
LED3
LED-Yellow (SMD 3216)
12
R224 0
R14610k
C30100nF
R154
49.9/1%
R147 10k
R149
6.8k/1%
CB68
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MODEM_WAKEUP
MODULE 1
MODEM_RST
SPI
GPS (UART2, SPI0)
MODEM_PWR_ONMODEM_RI
HD Radio (SPI1, IIS for Module 4)MODULE 2
Mobile TV (SPI1, IIC)
Module Connector1&2 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
16 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XuTXD3/RTSn2/UART_AUDIO_RTSn[2,14,17]
XuTXD2/UART_AUDIO_TXD[2,14,17]
SPI_MOSI1 [2,17]
SPI_CSn1 [2,17]
SPI_CLK1 [2,17]
SPI_MISO1 [2,17]
Xi2cSDA0 [2,6,7,10,11,17]Xi2cSCL0 [2,6,7,10,11,17]
XpwmTOUT1[2,6,14,18]
PWROn_BOARD[2,7,17]
XEINT30/KP_ROW6[2,6,13]XEINT28/KP_ROW4[2,6,13]
XpwmTOUT2[2,6,14,18]
PWROn_BOARD[2,7,17]
XEINT30/KP_ROW6[2,6,13]
XEINT28/KP_ROW4[2,6,13]
XEINT31/KP_ROW7[2,13,18]
XEINT29/KP_ROW5[2,13]
XEINT24/KP_ROW0[2,13,17]
XEINT27/KP_ROW3[2,7,13,17]
XEINT25/KP_ROW1[2,13,17]XEINT26/KP_ROW2[2,13,17]
XuRXD2/UART_AUDIO_RXD[2,14,17]
XuRXD3/CTSn2/UART_AUDIO_CTSn[2,14,17]
SPI_MISO0 [2]SPI_MOSI0 [2]
SPI_CSn0 [2]
SPI_CLK0 [2]
T_Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[8,17]
T_Xi2sSDI1/PCM_SIN1/AC97_SDI[8,17]T_Xi2sSDO1/PCM_SOUT1/AC97_SDO[8,17]
T_Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[8,17]T_Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[8,17]
XnRESET[2,3,7,13,15,17]
XnRESET[2,3,7,13,15,17]
VDD_3V3
VDD_3V3
DC5V
VDD_EXT
DC5V
VDD_EXT
CB70
100nF
TP58
R161 NC
+CTB52
10uF/6.3V
CB74
100nF
TP62
R163 NC
R159 0
TP60
TP74
TP63RA5
01234
8765
+CTB51
10uF/6.3V
MTH6GND
TPH1GND
TP83
CB69
100nF MTH1GND
+CTB48
10uF/6.3V
TP65
MTH7GND
CB72
100nF
TP66
TPH5GND
MTH3GND
TP61
TP72
TP67
R162 NC
RA7NC 1
234
8765
TP77
TP68
RA110
1234
8765
TP73
MTH8GND
TP78
+CTB49
10uF/6.3V
RA6
NC1234
8765
TP69RA80
1234
8765
TP76
R158 0
RA9NC
1234
8765
TPH2GND
TP75
M2
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 62 63 64
R160 NC
MTH4GND
MTH5GND
TPH4GND+CTB50
10uF/10V
TP81
TP64
TP82
CB71
100nF
R164 NC
CB73
100nF
TP70
MTH2GND
TPH6GND
TP80
+CTB53
10uF/10V
TP71
RA10NC
1234
8765
TPH3GND
M1
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 62 63 64
TP79
TP59
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BT (UART2, PCM)
BT_PCM_CLK
WP_SD0
Disable audio partMUXs using thismodule
PCM BT_PCM_SDI
UARTSPI
MODULE 4
I2S/AC97
MODULE 3
Audio (AC97, IIS, IIC)
SD_PWR_EN
GPIO
BT_PCM_FSYNCBT_PCM_SDO
PCM
NCD_SD0
Disable audio part MUXsusing this module
INT_JACK_DETGPIO_MUTE
GPIO_PWRENGPIO_AMP_EN
0 ohm : I2S
Open :AC97 RESETnBITCLKSYNC
SCLK1LRCK1CDCLK1
Module Connector3&4 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
17 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XuTXD3/RTSn2/UART_AUDIO_RTSn[2,14,16]
XuTXD2/UART_AUDIO_TXD[2,14,16]
SPI_MOSI1[2,16]SPI_MISO1[2,16]
XEINT24/KP_ROW0 [2,13,16]
SPI_CLK1[2,16]
SPI_CSn1[2,16]
T_Xi2sSDO1/PCM_SOUT1/AC97_SDO[8,16]
Xi2cSDA0[2,6,7,10,11,16]Xi2cSCL0[2,6,7,10,11,16]
PWROn_BOARD[2,7,16]
PWROn_BOARD[2,7,16]
XEINT24/KP_ROW0[2,13,16]XEINT25/KP_ROW1[2,13,16]
XEINT26/KP_ROW2[2,13,16]XEINT27/KP_ROW3[2,7,13,16]
XuRXD3/CTSn2/UART_AUDIO_CTSn[2,14,16]
XuRXD2/UART_AUDIO_RXD[2,14,16]
T_Xi2sSDI1/PCM_SIN1/AC97_SDI[8,16]
T_XpcmFSYNC0/LCD_FRM/Xi2sLRCK2[8]T_XpcmSOUT0/Xi2sSDO2[8] T_XpcmSIN0/Xi2sSDI2 [8]
T_XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2 [8]T_XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2 [8]
T_Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[8,16]
T_Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[8,16]T_Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn[8,16]
T_Xi2sSCLK1/PCM_SCLK1/AC97_BITCLK[8,16]
T_Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[8,16]
T_Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC[8,16]
T_XpcmSOUT0/Xi2sSDO2[8]
T_XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2[8]T_XpcmFSYNC0/LCD_FRM/Xi2sLRCK2[8]
T_XpcmSIN0/Xi2sSDI2[8]
XnRESET[2,3,7,13,15,16]
XnRESET[2,3,7,13,15,16]
VDD_3V3
VDD_AUD
DC5V
VDD_EXT
DC5V
VDD_3V3
TP84
TP116
TP98
R182 NC
R174 0TP99
R186 NC
R184 NC
CB78
100nF
+CTB59
10uF/10V
TP96
R192 NC
R171 0R170 0
R177 0
R187 NC
R178 0
+CTB58
10uF/6.3V
R188 NC
+CTB55
10uF/6.3V
CB79
100nF
R165 0
R168 0
R190 NC
R166 0
R172 0
R176 NC
TP104
TP105
M4
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 62 63 64
R183 NC
CB77
100nF
TP100
TP106
CB76
100nF
CB80
100nF
TP88
TP108
R191 NC
TP103
TP109TP110
TP90
TP85
R180 NC TP101
+CTB56
10uF/10V
TP111
TP107
TP92
CB75
100nF
R173 NC
R181 0
TP87
TP102
R189 NC TP112
TP93
R175 0
M3
QSH-030-01-F-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 4243 4445 4647 4849 5051 5253 5455 5657 5859 60
61 62 63 64
TP91
R169 0
TP94
R179 0
TP113
TP89
R185 NC
+CTB54
10uF/6.3V
TP114
+CTB57
10uF/6.3V
TP95
TP115
TP86
R167 0
TP97
TP117
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Silk>
GPH2_7
GPH2_5
GPH2_4
GPH2_6
<Silk> <Silk>
External IRQTest
XEINT31XEINT4
<Silk>PWM Header
<Silk>DC_IN
TV Interface
TV Interface/ PWM/ LED/ EINT 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
A3
18 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XpwmTOUT2[2,6,14,16]XpwmTOUT1[2,6,14,16]
XpwmTOUT0[2,5]
XEINT4 [2] XEINT31/KP_ROW7 [2,13,16]
XEINT22/KP_COL6[2,13]
XEINT23/KP_COL7[2,13]
XEINT20/KP_COL4[2,13]
XEINT21/KP_COL5[2,13]
DACOUT0[2]
XpwmTOUT3/PWM_MIE[2]
DC5V
VDD_SYS
VDD_KEYVDD_SYS
VDD_DAC
R195 0R194 330
R211
330
R199 330
R200 330
SW6TL1105A-BLACK (DIP)
3 41 2
CON19
COMPOSITE RCA
12
VIDEOGND
JP3A2-2PA-2.54DSA
1 2
JP4A2-2PA-2.54DSA
1 2
R209 0
SW7TL1105A-BLACK (DIP)
3 41 2
Q3
MMBT3904LT1
1
2 3
LED8
LTST-C150BKT (SMD3216 Blue)
1 2
U33
BAV99LT1
32
1
CB82
100pF
JP5A2-2PA-2.54DSA
1 2
R207
100K
CB81
100pF
R198 330
JP6A2-2PA-2.54DSA
1 2
R208
100K
LED7
LTST-C150BKT (SMD3216 Blue)
1 2
LED9
LTST-C150BKT (SMD3216 Blue)
1 2
LED6
LTST-C150BKT (SMD3216 Blue)
1 2
Q2
MMBT3904LT1
1
2 3
LED10LTST-C150CKT (SMD3216 Red)
12
Q5
MMBT3904LT1
1
2 3
Q4
MMBT3904LT1
1
2 3
R210
0
(HDR4-2.54-MALE)
J3
A2-4PA-2.54DSA
1234
RA12
1K
1234
8765
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AFor RMB Board I/F Connector
RMB b'd IF(for SMDK b'd test) 0.1
SMDK_S5PC110_Base Board (S5PC110 Evaluation Board)
B
19 19Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
RMB_nRESET
RMB_OM5
RMB_nRESET
RMB_CTRL1
EXT_nRESET[2,6]
RMB_CTRL2
XOM0[2]
XOM2[2]
XOM4[2]XOM3[2]
XOM1[2]
XOM5[2]
RMB_OM1
RMB_OM3
RMB_OM0
RMB_OM2
RMB_OM4RMB_OM5
RMB_OM3RMB_OM2
RMB_OM0RMB_OM1
RMB_OM4RMB_CTRL2RMB_CTRL1
DC5V VDD_3V3
VDD_3V3
DC5VVDD_3V3
VDD_3V3
CB85 100nF
TP121
+
CTB6110uF/6.3V
R216100K
TP123
TP118
CB83
100nF
TP125
TP120
TP126
TP122
+
CTB6010uF/6.3V
TP128
CB86 100nF
TP124
TP130
R213 0
TP119
TP127
CON20
QSE-020-01-L-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
41 42 43 44 45 46
TP129
U36
SN74AVCA164245DGG
4746444341403837
3635333230292726
124
4825
2356891112
1314161719202223
3142 7
18
45393428
4101521
1A11A21A31A41A51A61A71A8
2A12A22A32A42A52A62A72A8
1DIR2DIR
1OE2OE
1B11B21B31B41B51B61B71B8
2B12B22B32B42B52B62B72B8
VCCA1VCCA0 VCCB0
VCCB1
GND0GND1GND2GND3
GND7GND6GND5GND4
R212 NC
R214 100K
R215100K
CB84
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Part Reference<Component><Number>---------------------------------------------------U : Component or Regurator ICC : CapacitorCB : Capacitor BypassCT : Capacitor TantalCTB : Capacitor Tantal BypassJ : JumperJB : CPU To Base connectorJP : Jumper PowerR : ResistorRA : Resistor ArrayRP : Resistor PowerVR : Variable ResistorL : InductorFB : Ferrite BeadOSC : OscillatorX : X-tal (Crystal)Q : Transistor or FETD : DiodeZD : Zener DiodeLED : LED DiodeSW : SWitch Tact/PushCON : CONnectorCFG : ConFiGure switch (DIP/Slide)TP : Test Point (SMD)TPH : Test Point Hole (Through Hole)MTH: Mount Through HoleM (MOD) : MODule Interfaceconnector
Preliminary Version
SMDK_S5PC110_LCD B'd (S5PC110 Evaluation Board) Schematics
Rev 0.0 2009. 05.12
Revision Date
Rev 0.2
Table of Contents
Description
Rev 0.1
Page Function-------------------------------------------------------01 Revision History02 Connector To SMDK03 4.8" WVGA(800 X 480) & BL04 3.1" WVGA(480 X 800)
Revision History 0.1
SMDK_S5PC110 LCD Board (S5PC110 Evaluation Board)
A3
1 4Thursday, October 01, 2009
Title
Size Document Number Rev
Date: Sheet of
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TFT LCD FPC Cable InterfaceFrom SMDK
Connector to SMDK 0.1
SMDK_S5PC110 LCD Board (S5PC110 Evaluation Board)
A3
2 4Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
LCD_DATA9
LCD_DATA11
LCD_DATA14
LCD_DATA8
LCD_DATA3
LCD_DATA15
LCD_DATA22
LCD_DATA12
LCD_DATA17
LCD_DATA2LCD_DATA1
LCD_DATA18
LCD_DATA20
LCD_DATA16
LCD_DATA21
LCD_DATA7
LCD_DATA0
LCD_DATA10
LCD_DATA6LCD_DATA5LCD_DATA4
LCD_DATA13
LCD_DATA19
LCD_DATA23
TSYM0[3,5,6,7]TSYP0[3,5,6,7]TSXM0[3,5,6,7]TSXP0[3,5,6,7]
LCD_DATA[23:0][3,4,5,6,7]
IIC_SDA[6]
IIC_SCL[6]LCD_VCLK[3,4,5,6,7]
LCD_HSYNC[3,4,5,6,7]LCD_VSYNC[3,4,5,6,7]
LCD_VDEN[3,4,5,6,7]
LCD_BL[3]
LCD_RESET[3,4,5,7]
SPI_CSn[4,5,7]
SPI_CLK[4,5,7]SPI_MOSI[4,5,7]
LCD_VCLK_SUB[4,7]
SPI_MISO[7]
LCD_OE[4]
TSYM1[7]TSYP1[7]
TSXM1[7]TSXP1[7]
PWROn_BOARD[7]
SYS_POWERSYS_POWER
VDD_LCD
VDD_LCD
VDD_LCD
+CTB1
10uF/6.3V/T2012
CB3
100nF/C1608
R1
10K/R1608
CB1
100nF/C1608
CB2
100nF/C1608
+CTB2
10uF/10V/T2012
CON1
GF056-60S-LSS-P2000
123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
61 62
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.8inch WVGA(800x480)LMS480KF02
RGB(24Bit) Parallel Interface
(7 LED x2, 20mA per LED)
(3.3V)
LED drivers(Common)
<Silk>
4.8 WVGA MAIN
4.8inch WVGA(800x480) 0.1
SMDK_S5PC110 LCD Board (S5PC110 Evaluation Board)
A3
3 4Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
LCD_DATA1
LCD_DATA19LCD_DATA18
LCD_DATA4
LCD_DATA10LCD_DATA11
LCD_DATA17
LCD_DATA0
LCD_DATA13
LCD_DATA22LCD_DATA23
LCD_DATA14
LCD_DATA8
LCD_DATA2
LCD_DATA15
LCD_DATA5
LCD_DATA12
LCD_DATA7LCD_DATA6
LCD_DATA21
LCD_DATA16
LCD_DATA9
LCD_DATA3
LCD_DATA20
LCD_DATA[23:0][2,4,5,6,7]
LCD_RESET[2,4,5,7]LCD_HSYNC[2,4,5,6,7]
LCD_VDEN[2,4,5,6,7]
LCD_VCLK[2,4,5,6,7]
LCD_VSYNC[2,4,5,6,7]
TSYM0[2,5,6,7]
TSYP0[2,5,6,7]
TSXM0[2,5,6,7]
TSXP0[2,5,6,7]
LCD_BL [2]
LCD_BL [2]
VDD_LCD
VDD_LED1
VDD_LED2
SYS_POWER
VDD_LED2
VDD_LED1
SYS_POWER
+CTB5
10uF/10V/T2012 L2
22uH (LQH32CN220K23)
1 2
1 2
R7 0/R1608R6 0/R1608
R4
10/R1608
R5 0/R1608CB7
100nF/C1608
L1
22uH (LQH32CN220K23)
1 2
1 2
CB4
100nF/C1608
+CTB3
10uF/10V/T2012 CON2
molex: 51296-4593
789
101112131415161718192021222324252627282930313233343536373839404142434445
6543
12
46 47
PD18(R2)PD19(R3)PD20(R4)PD21(R5)PD22(R6)PD23(R7)PD8(G0)PD9(G1)PD10(G2)PD11(G3)PD12(G4)PD13(G5)PD14(G6)PD15(G7)PD0(B0)PD1(B1)PD2(B2)PD3(B3)PD4(B4)PD5(B5)PD6(B6)PD7(B7)GND3DOTCLKPCIHSYNCVSYNCDEGND4GND5Y2X2Y1X1GND6LED1-LED1+LED2-LED2+
PD17(R1)PD16(R0)VCC2VCC1
GND1GND2
46 47
R2
10/R1608
U1
LT3591EDDB
1
2
3
4
8
7
6
5
9VIN
GND1
NC1
SW
CTRL
LED
NC2
CAPGN
D2
U2
LT3591EDDB
1
2
3
4
8
7
6
5
9
VIN
GND1
NC1
SW
CTRL
LED
NC2
CAPGN
D2
CB5
100nF/C1608
R3 0/R1608
+CTB4
10uF/10V/T2012
CB8
2.2uF/50V/C3216
CB6
2.2uF/50V/C3216
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Vout=0.60(1+R1/R2)R1=R2(Vout/0.60V-1)
R1
Vout = [email protected]
R2
Portrait WVGA(800x480) 0.1
SMDK_S5PC110 LCD Board (S5PC110 Evaluation Board)
A3
4 4Thursday, October 01, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
LCD_DATA22LCD_DATA20LCD_DATA18LCD_DATA16LCD_DATA14LCD_DATA12LCD_DATA10LCD_DATA8LCD_DATA6LCD_DATA4LCD_DATA2LCD_DATA0
LCD_DATA23LCD_DATA21LCD_DATA19LCD_DATA17LCD_DATA15LCD_DATA13LCD_DATA11LCD_DATA9LCD_DATA7LCD_DATA5LCD_DATA3LCD_DATA1
LCD_DATA23
LCD_DATA7LCD_DATA15
TSXM0[2,3,5,6]TSXP0[2,3,5,6]
TSYP0 [2,3,5,6]TSYM0 [2,3,5,6]
LCD_RESET [2,3,4,5]
SPI_CLK [2,4,5]LCD_VCLK [2,3,4,5,6]
LCD_VSYNC [2,3,4,5,6]
LCD_VDEN [2,3,4,5,6]
LCD_HSYNC[2,3,4,5,6]
LCD_DATA[23:0][2,3,4,5,6]LCD_DATA[23:0] [2,3,4,5,6]
SPI_CSn[2,4,5]SPI_MOSI[2,4,5]SPI_MISO[2]
PWROn_BOARD[2]
LCD_RESET[2,3,4,5]
LCD_VDEN[2,3,4,5,6]
LCD_HSYNC[2,3,4,5,6]
LCD_VSYNC[2,3,4,5,6]
LCD_VCLK_SUB[2,4]
LCD_VCLK[2,3,4,5,6]
SPI_CSn[2,4,5]SPI_CLK[2,4,5]SPI_MOSI[2,4,5]SPI_MISO[2]
LCD_DATA[23:0][2,3,4,5,6]
TSXM1[2]TSXP1[2]
TSYP1 [2]TSYM1 [2]
LCD_VCLK_SUB [2,4]
LCD_OE[2,3,4,5]
VDD_LCD
VDD_4VSYS_POWER
VDD_4V
VDD_LCD
TP14 TPTP15 TP
R27 0/R1608
R24 0/R1608
TP13 TP
R15 0/R1608R18 0/R1608
TP4 TP
U3LM2832XMY1234 5
678
9
VINDVINAGNDEN GND
FBGNDSW
DA
P
TP3 LCD_ID
TP1 TP
R10220K/R1608
TP5 TP
R17 0/R1608
C1
22uF,6.3V
TP9 TP
CB9
1000nF/C1608
R20 0/R1608
TP11 TPTP12 TP R25 NC/R1608TP10 TP
R12 NC/R1608
C2
22uF
,6.3
V
R26 0/R1608
TP7 TP
R23 0/R1608
R21 0/R1608
CON3
14-5805-050-000-829
13579
1113151719212325272931333537394143
2468101214161820222426283032343638404244
45 4647 4849 50
C3
22uF
,6.3
VTP6 TP
L3CDRH6D28 (10uH)
R11 NC/R1608
TP8 TP
R14 NC/R1608
R8
56K,1%
R22 0/R1608
R9
10K,1%
TP2 TP
R13 NC/R1608
R19 0/R1608
R16 0/R1608
ZD1
MB
RS
320T
3
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Mux OneNAND<Silk>
QTH/QSH Series ( 0.5mm)
(Sync : R2, R3, R5 )(Async: R4, R6 )
Ext. Mux OneNAND Pre
SMDK2443 Evaluation Board
A3
E2Wednesday, August 02, 2006
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XrDATA11
XrDATA9
Xsm_nRP
XrDATA10
Ext_sm_INT
XrDATA12
XrDATA8
XrDATA15
XrOEn
XrDATA14XrDATA13
XrDATA7
Xsm_nRP Ext_sm_RDYXsm_nAVD Ext_sm_INTXrWEn XrOEn
Xsm_CLK
XrDATA[15:0]
XrDATA2
XrDATA14
XrDATA[15:0]
XrDATA15
XrDATA7XrDATA4
XrDATA3XrDATA1
XrDATA2
XrDATA8
XrDATA[15:0]
XrDATA10
XrDATA4
XrDATA11
XrDATA5XrDATA6
XrDATA0
XrDATA0
XrDATA9
XrDATA3
XrDATA5XrDATA6
XrDATA1
XrDATA12 XrDATA13
XrWEn
Ext_OneNand_CSnExt_OneNand_CSn
sm_CLK
sm_RDY
sm_nAVD
Ext_OneNand_CSn
Xsm_CLK
Xsm_nAVD
sm_CLK
sm_nAVD
Ext_sm_RDY sm_RDY
VDD_mem
VDD_mem
VDD_mem
RM20
+CTM1
10uF
JM1
QSH-030-01-F-D-A
24681012141618202224262830323436384042444648505254565860
13579
11131517192123252729313335373941434547495153555759
RM30
RM50
RM40(NC)
RM6 0(NC)
UM1
KFN2G16Q2M-DEB6
D1A3A6B1C3C4B5B2C1D6D5C2C5E3B3D3
E1A1E2B4
F3A2
A4A5
H1G1
B6C6
ADQ0ADQ1ADQ2ADQ3ADQ4ADQ5ADQ6ADQ7ADQ8ADQ9ADQ10ADQ11ADQ12ADQ13ADQ14ADQ15
CLKnWEnCEnOE
nAVDnRP
VSS0VSS1
RDYINT
VCCcoreVCCIO
RM1
100K(NC)
C508
100nF
CM1
100nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Silk>
DeMux OneNAND
QTH/QSH Series ( 0.5mm)
(Sync : R2, R3, R5 )(Async: R4, R6 )
Ext. DeMux OneNAND Pre
SMDK2443 Evaluation Board
A3
E1Wednesday, August 02, 2006
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XrDATA5
XrADDR7
XrADDR3
XrDATA1
XrADDR13
Xsm_nRP
XrADDR4XrDATA3
XrADDR8
XrDATA0
XrADDR14
XrDATA9XrADDR9
XrADDR5
XrADDR15XrDATA14
XrDATA7XrADDR6
XrDATA8
XrADDR10
XrDATA4
XrDATA2
XrDATA13
XrADDR11 XrDATA11
XrDATA15
XrDATA6
XrADDR12
XrWEn
XrDATA10
XrOEn
XrADDR1
XrDATA12
XrADDR2
XrADDR0
XrADDR12
XrADDR5XrADDR2
XrADDR9
XrADDR14
XrADDR4
XrADDR1
Xsm_nRP Ext_sm_RDY
XrADDR6
Xsm_nAVD Ext_sm_INT
XrADDR8
XrWEn
XrADDR3
XrOEn
XrADDR10
XrADDR0
XrADDR7
Xsm_CLK
XrADDR11
XrADDR15XrADDR13
XrADDR[15:0] XrADDR[15:0]
XrDATA14
XrDATA[15:0]
XrDATA15
XrDATA7XrDATA4
XrDATA3XrDATA1
XrDATA2
XrDATA8
XrDATA[15:0]
XrDATA10 XrDATA11
XrDATA0
XrDATA9
XrDATA5XrDATA6
XrDATA12 XrDATA13
XrADDR[15:0] XrDATA[15:0]
Ext_sm_INT
Ext_OneNand_CSn
Ext_OneNand_CSn
Ext_OneNand_CSn
Xsm_CLK
Xsm_nAVD
sm_CLK
sm_nAVD
Ext_sm_RDY sm_RDY
sm_RDYsm_CLK
sm_nAVD
VDD_mem
VDD_mem
VDD_mem
R2 0
R5 0
R3 0
R1
100K(NC)
R4 0(NC)
C1
100nF
J1
QSH-030-01-F-D-A
24681012141618202224262830323436384042444648505254565860
13579
11131517192123252729313335373941434547495153555759
R6 0(NC)
U1
KFH2G16Q2M-DEB6
G2G3H4H5H2H3G6F4F6E6G5F5D2F2F1D4
E1
A1
F3
E2B4
A2
A4A5
D3B3E3
C2D5D6C1B2B5C4C3B1A6A3D1
H1
C5
G1
B6C6
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
CLK
nWE
nAVD
nCEnOE
nRP
VSS0VSS1
DQ0DQ1DQ2
DQ4DQ5DQ6DQ7DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15
RDY
DQ3
INT
VCCcoreVCCIO
+CT1
10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<Silk>
DeMux OneNAND
QTH/QSH Series ( 0.5mm)
(Sync : R2, R3, R5 )(Async: R4, R6 )
Ext. DeMux OneNAND Pre
SMDK2443 Evaluation Board
A3
E1Wednesday, August 02, 2006
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XrDATA5
XrADDR7
XrADDR3
XrDATA1
XrADDR13
Xsm_nRP
XrADDR4XrDATA3
XrADDR8
XrDATA0
XrADDR14
XrDATA9XrADDR9
XrADDR5
XrADDR15XrDATA14
XrDATA7XrADDR6
XrDATA8
XrADDR10
XrDATA4
XrDATA2
XrDATA13
XrADDR11 XrDATA11
XrDATA15
XrDATA6
XrADDR12
XrWEn
XrDATA10
XrOEn
XrADDR1
XrDATA12
XrADDR2
XrADDR0
XrADDR12
XrADDR5XrADDR2
XrADDR9
XrADDR14
XrADDR4
XrADDR1
Xsm_nRP Ext_sm_RDY
XrADDR6
Xsm_nAVD Ext_sm_INT
XrADDR8
XrWEn
XrADDR3
XrOEn
XrADDR10
XrADDR0
XrADDR7
Xsm_CLK
XrADDR11
XrADDR15XrADDR13
XrADDR[15:0] XrADDR[15:0]
XrDATA14
XrDATA[15:0]
XrDATA15
XrDATA7XrDATA4
XrDATA3XrDATA1
XrDATA2
XrDATA8
XrDATA[15:0]
XrDATA10 XrDATA11
XrDATA0
XrDATA9
XrDATA5XrDATA6
XrDATA12 XrDATA13
XrADDR[15:0] XrDATA[15:0]
Ext_sm_INT
Ext_OneNand_CSn
Ext_OneNand_CSn
Ext_OneNand_CSn
Xsm_CLK
Xsm_nAVD
sm_CLK
sm_nAVD
Ext_sm_RDY sm_RDY
sm_RDYsm_CLK
sm_nAVD
XrADDR6
XrADDR0
XrADDR4XrADDR2
XrADDR12XrADDR10
XrADDR14
XrADDR8XrADDR7
XrADDR3XrADDR5
XrADDR1
XrADDR15
XrADDR11XrADDR13
XrADDR9
XrOEn
Ext_sm_RDYExt_sm_INT
Ext_OneNand_CSn
Xsm_nRPXsm_nAVDXrWEn
Xsm_CLK
XrDATA2XrDATA0
XrDATA4XrDATA6
XrDATA12XrDATA14
XrDATA8XrDATA10
XrDATA7XrDATA5XrDATA3XrDATA1
XrDATA9
XrDATA15XrDATA13XrDATA11
VDD_mem
VDD_mem
VDD_mem
+CT1
10uF
R1
100K(NC)
R4 0(NC)
C1
100nF
J2
2mm Surface Mount Header (TMM)
2468101214161820222426283032343638404244
13579
1113151719212325272931333537394143
R2 0
J1
QSH-030-01-F-D-A
24681012141618202224262830323436384042444648505254565860
13579
11131517192123252729313335373941434547495153555759
R5 0
U1
KFH2G16Q2M-DEB6
G2G3H4H5H2H3G6F4F6E6G5F5D2F2F1D4
E1
A1
F3
E2B4
A2
A4A5
D3B3E3
C2D5D6C1B2B5C4C3B1A6A3D1
H1
C5
G1
B6C6
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15
CLK
nWE
nAVD
nCEnOE
nRP
VSS0VSS1
DQ0DQ1DQ2
DQ4DQ5DQ6DQ7DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15
RDY
DQ3
INT
VCCcoreVCCIO
R6 0(NC)
R3 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Mux OneNAND<Silk>
QTH/QSH Series ( 0.5mm)
(Sync : R2, R3, R5 )(Async: R4, R6 )
Ext. Mux OneNAND Pre
SMDK2443 Evaluation Board
A3
E2Wednesday, August 02, 2006
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XrDATA11
XrDATA9
Xsm_nRP
XrDATA10
Ext_sm_INT
XrDATA12
XrDATA8
XrDATA15
XrOEn
XrDATA14XrDATA13
XrDATA7
Xsm_nRP Ext_sm_RDYXsm_nAVD Ext_sm_INTXrWEn XrOEn
Xsm_CLK
XrDATA[15:0]
XrDATA2
XrDATA14
XrDATA[15:0]
XrDATA15
XrDATA7XrDATA4
XrDATA3XrDATA1
XrDATA2
XrDATA8
XrDATA[15:0]
XrDATA10
XrDATA4
XrDATA11
XrDATA5XrDATA6
XrDATA0
XrDATA0
XrDATA9
XrDATA3
XrDATA5XrDATA6
XrDATA1
XrDATA12 XrDATA13
XrWEn
Ext_OneNand_CSnExt_OneNand_CSn
sm_CLK
sm_RDY
sm_nAVD
Ext_OneNand_CSn
Xsm_CLK
Xsm_nAVD
sm_CLK
sm_nAVD
Ext_sm_RDY sm_RDY
XrDATA15
Xsm_nAVD
XrDATA7
XrOEn
XrDATA6
XrWEn
XrDATA13
XrDATA5
Ext_sm_RDY
XrDATA12
Xsm_CLK
XrDATA11
XrDATA3
Ext_sm_INT
XrDATA14
XrDATA2XrDATA1
Ext_OneNand_CSn
XrDATA8
XrDATA0
XrDATA9
Xsm_nRP
XrDATA10
XrDATA4
VDD_mem
VDD_mem
VDD_mem
RM40(NC)
RM1
100K(NC)
RM20
RM6 0(NC)
C508
100nF
+CTM1
10uF
CM1
100nF
JM1
QSH-030-01-F-D-A
24681012141618202224262830323436384042444648505254565860
13579
11131517192123252729313335373941434547495153555759
JM2
2mm Surface Mount Header (TMM)
246810121416182022242628
13579
111315171921232527
RM30
RM50
UM1
KFN2G16Q2M-DEB6
D1A3A6B1C3C4B5B2C1D6D5C2C5E3B3D3
E1A1E2B4
F3A2
A4A5
H1G1
B6C6
ADQ0ADQ1ADQ2ADQ3ADQ4ADQ5ADQ6ADQ7ADQ8ADQ9ADQ10ADQ11ADQ12ADQ13ADQ14ADQ15
CLKnWEnCEnOE
nAVDnRP
VSS0VSS1
RDYINT
VCCcoreVCCIO
1
1
A A
<Silk>
PROBE
CON2
<Silk>
POWER
Be placed TPs oneach lines.Notmake stub.
<Silk>
TP
<Silk>
TP
PROBE
POWER(REG/LED)
PROBE
TOP
<Silk>
4EA 5M CAM MODULE
SYS_PWR
XmipiCLK_RX_N,XmipiCLK_RX_P,XmipiSDN0,XmipiSDP0,XmipiSDP1,XmipiSDN1
signal 위 은 직선으로 연결(500Mhz differentialsignal)
SW ON : CAM STANDBY
1.5V REG
CON2CON1
BOTTOM
CON1
Replacement Diagram
0.0
SMDK_S5PC110_4EA Board (Daughter Board)
A3
1 1Thursday, May 21, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XmipiSDP0
XciMCLK
Xi2cSDA0
VGA_CAM_nSTBY
XciMCLK
XciRESET
XmipiSDN0
Xi2cSDA0
Xi2cSCL0
XciRESET
5M_VCM_GND
XmipiSDN1XmipiSDP1
XmipiCLK_RX_P
Xi2cSCL0
XmipiCLK_RX_N
XmipiCLK_RX_P
XmipiSDP1
Xi2cSCL0
VGA_CAM_nSTBY
XmipiSDN1
XmipiCLK_RX_NXmipiCLK_RX_P
Xi2cSDA0
5M_AGND
XmipiSDN0
XmipiSDP1
XmipiSDP0
XmipiCLK_RX_N
XmipiSDN0XmipiSDP0
XciMCLK
XciRESET
XmipiSDN1
CAM_DVDD28
CAM_DVDD28
CAM_DVDD15
CAM_VDD28_AF
CAM_DVDD18CAM_AVDD28
CAM_DVDD18
CAM_DVDD28
CAM_DVDD28
CAM_AVDD28
REG_IN
CAM_DVDD15
CAM_DVDD28
CAM_VDD28_AF
CAM_DVDD28
CON2
FH19SC-24S-0.5SH
1234567891011121314151617181920212223242526
C80.1uF/10V
LED1LED-Red (SMD 2012)
12
R12 0/R1005
C1
2200
nF/1
0V
C3
2200
nF/1
0V
R212 0
R60/R1608
R11100K/R1005
TP21
JP1A4B-2PA-2DSA
1 2
R50R/1005
R910K/R1005
C4
2200
nF/1
0V
C101000nF/10V
TP31
R20R/1005
R10
0/R1005
R40R/1005
C111000nF/10V
TP61
J1
HEADER
2468
1357
R216 0
R80/R1608
TP51
C6
2200
nF/1
0V
C5
2200
nF/1
0V
TP41
C90.1uF/10V
TP11
C2
2200
nF/1
0V
CFG1
SW-DIP2
12
43
CON1
QTE-020-01-L-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
U1MIC5365-1.5YMT
4
3
1
2
5
VIN
EN
VOUT
GND
GN
D
R10R/1005
C70.1uF/10V
R7680/R1005
R30R/1005
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Table of Contents
Description
MIPI-LCM&LAN Module B'd Schematics (for SMDK6440)DateRevision
Page Function-------------------------------------------------------01 Revision History02 MIPI-LCM03 LAN DM9000
Rev 0.0 2009.03.06 (2009.02.17) First Version
Part Reference<Component><Number>---------------------------------------------------U : Component or Regurator ICC : CapacitorCB : Capacitor BypassCT : Capacitor TantalCTB : Capacitor Tantal BypassCP : Capacitor return Path on power planeJ : JumperJB : CPU or Base connectorJP : Jumper PowerR : ResistorRA : Resistor ArrayRP : Resistor PowerVR : Variable ResistorL : InductorFB : Ferrite BeadOSC : OscillatorX : X-tal (Crystal)Q : Transistor or FETD : DiodeZD : Zener DiodeLED : LED DiodeSW : SWitch Tact/PushCON : CONnectorCFG : ConFiGure switch (DIP/Slide)
<Component><Number>---------------------------------------------------TP : Test Point (SMD)TPH : Test Point Hole (Through Hole)MTH: Mount Through HoleMOD : MODule Interface connector
Revision History 0.0
MIPI-LCM&LAN Module B'd (for SMDK6440)
A3
1 3Friday, March 06, 2009
SAMSUNG ELECTRONICS CO., LTDTitle
Size Document Number Rev
Date: Sheet of
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
B_SYNCMCSE_TE
EXTSDB
MIPI-DSI ConnectorMIPI-DSI<Silk>
(VDD_MIPI18)
For MIPI R03 Syrah
MIPI-R03 Syrah<Silk>
(VDD_MIPI18)
EXTSDBB_SYNCMCSE_TE
2009.03.06
MIPI-LCM 0.0
MIPI-LCM&LAN Module B'd (for SMDK6440)
A3
2 3Friday, March 06, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
XMIPIMDND0XMIPIMDPD0
XMIPIMDNCLKXMIPIMDPCLK
XMIPIMDND1XMIPIMDPD1
XEINT6 XEINT6
XMIPIMDND0
XMIPIMDPCLK
XMIPIMDPD1
XMIPIMDNCLK
XMIPIMDND1
XMIPIMDPD0
MIPIGND
PVDD_SS
PVDD_LCD
MIPI_LCD_LED
PVDD_SS
MIPIGND
MIPI_LCD_6V
PVDD_LCD
MIPI_LCD_LED
PVDD_SS
MIPI_LCD_6V
MIPIGNDMIPIGND
PVDD_SS
MIPI_LCD_LED MIPI_LCD_6V
MIPIGND MIPIGND
PVDD_LCD PVDD_SS
MIPIGNDMIPIGND
MIPIGND
TP11
R1 0/R1005
TP1
R2 0/R1005
MTH1GND
MTH3GND
MTH4GND
TP9
TP2
TP4
MTH2GND
TP10
R3 0/R1005
+CTB2
10uF,6.3V/T2012
R5 0/R1005
CON1
QTE-020-01-L-D-A
13579
111315171921232527293133353739
246810121416182022242628303234363840
TP8
TP3
TP5
+CTB3
10uF,6.3V/T2012
FB4
BLM18PG121SN1
CON2
JAE AA03-P020VA2
13579
1113151719
2468101214161820
CB1
100nF/C1608
TP7
CB4
100nF/C1608
R4 0/R1005
+ CTB1
330uF/16V/T6032
TP6
CB3
100nF/C1608
CB5
100nF/C1608
CB2
2.2uF/50V/C3216
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XVD7
LCD_SPIMISO
WHITE_LED
TP
XPWM_TOUT0
XVD5
XVD13
XVD1
LCD_SPIMOSI
XVDEN
XVD15
* Note : 1. Use decal on SMDK6410 Base board. 2. Placement on Bottom Side.
XVD21
TP
LCD_RESETn
GPJ5
TSYM
XVD23
XVD17
XVD8
XVD14
XVD16
XVD20
XHSYNC
XVD4
TSYP
XVD9
LCD_CSn
TSXP
XPWM_TOUT1
XVCLK
XVD10
XVD3
XVSYNC
XVD0
XVD6
LCD_SPICLK
TSXM
XVD22
XVD12
WLED_OUT1
XVD18
XVD11
XVD2
XVD19
LCD_PANNEL_ON
<Silk>LINK
<Silk>100Mbps
16-bit Mode
UseEEPROM
Not UseEEPROM
8-bit Mode
SW?
1
2
ON OFF
XEINT4/GPN4
[ Note (CMD) ]High: DATA PortLow: INDEX Port
LAN DM9000 0.0
MIPI-LCM&LAN Module B'd (for SMDK6440)
A3
3 3Tuesday, February 17, 2009
SAMSUNG ELECTRONICS CO.,LTDTitle
Size Document Number Rev
Date: Sheet of
MAC_DATA1
MAC_DATA3
MAC_DATA7
MAC_DATA11
MAC_DATA6
MAC_DATA2
MAC_DATA13MAC_DATA14
MAC_DATA10MAC_DATA9
MAC_DATA15
MAC_DATA4
MAC_DATA12
MAC_DATA5
MAC_DATA0
MAC_DATA8
MAC_DATA0MAC_DATA1MAC_DATA2MAC_DATA3MAC_DATA4MAC_DATA5MAC_DATA6MAC_DATA7
MAC_DATA12MAC_DATA11
MAC_DATA8
MAC_DATA10
MAC_DATA14MAC_DATA15
MAC_DATA9
MAC_DATA13
MAX_CMD
MAC_RESETn
MAX_nWE
MAC_DATA[15:0]
MAX_nOEMAX_nCS
EEP_CLK
EEP_DIO
EEP_CS
TX_M
TX_P
RX_M
RX_P
TX_PTX_M
RX_PRX_M
X2
X1
X1X2
EEP_CSEEP_CLKEEP_DIO
MAC_RESETn
MAC_DATA[15:0]
MAX_CMD
MAX_nWEMAX_nOE
MAX_nCS MAC_IRQ
MAC_IRQ
nSPD_100nLINK_ACK
nLINK_ACKnSPD_100
VDD3.3V
PWR_5V
VDD3.3V
VDD3.3V
DVDD3.3V
DVDD3.3V
VDD_A
E-GND
E-GND
A-GND
VDD_A
A-GND
A-GND
DVDD3.3V
A-GND
DVDD3.3V
VDD_A
A-GND
DVDD3.3V
A-GND
VDD3.3V DVDD3.3V
A-GNDE-GND
C3
10nF/C1608
U3
93LC46 (EEPROM)
1234
65
87CS
CLKDIDO
ORGGND
VCCNC
SW1
KHS02
12
43
TP22
+ CTB6
10uF,6.3V/T2012
C4
NC (0.1uF,2KV)
R21
510/R1608
CB11
100nF/C1608
R17 0/R1608
R6
49.9
,1%
/R16
08
R9
75,1
%/R
1608
U2DM9000AEP (DAVICOM)
121110
09
0807
0605
0403
02
01
24
23
22
212019
181716
15
1413
37
3839
4041
42
4344
45
46
47 48
2526272829
30
31
32
33
34
3536
SD5SD6SD7
TXV
DD
25
TX-TX+
TXG
ND
RXG
ND
RX-RX+
RX
VD
D25
BGRES
LED3/SD14
VD
D
WAKE/SD15
EECSEECK
EEDIO
SD0SD1SD2
GN
D
SD3SD4
CS#
LED2(IOWAIT/WAKEUP for eeprom)LED1(IO16 for eeprom)
PWRST#TEST
VD
D
X2X1
GN
D
SD
RXG
ND
BGG
ND
GP6/SD13GP5/SD12GP4/SD11GP3/SD10GP2/SD9
VD
D
GP1/SD8
CMD
GN
D
INT
IOR#IOW#
+CTB7
10uF,6.3V/T2012
C7 1uF/C1608
TP20
JACK1
RJHS-5380
12345678
1615
1211
1413
109
+CTB4
10uF,6.3V/T2012
CON3
GF056-60S-LSS-P2000
123456789
101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
R23
1K,1%/R1608
R7
49.9
,1%
/R16
08
CB9100nF/C1608
R8
75,1
%/R
1608
CB6
100nF/C1608
TP23
TP12
TP21
R24
0/R1608
R20
510/R1608
R12
49.9
,1%
/R16
08
R18 100K/R1608
R10
75,1
%/R
1608
U1
BEL S558-5999-46
161415
75
1210
4 8
132
9 13
6
11
TD+TCTTD-
RX+RCMT
TCMTTX+
NC
NC
RD+RCTRD-
NC
NC
RX-
TX-
TP13
R15 0/R1608
TP17
R14 0/R1608
C110nF/C1608
TP18
TP16
LED2
LED-Yellow (SMD 3216)
12
X1
25MHz (SMD,SX-8)
1
3
2
4
R19 0/R1608
+CTB8
10uF,6.3V/T2012
R22 10K/R1608
TP14
C5
22pF,5%/C1608
C6
22pF,5%/C1608
R13 6.8K,1%/R1608
CB7
100nF/C1608
LED1
LED-Green (SMD 3216)
12
C2
10nF/C1608
R11
49.9
,1%
/R16
08
R16 0/R1608
R250/R1608
TP19
FB2
BLM18PG121SN1
CB8
100nF/C1608
FB3
BLM18PG121SN1
TP15
+CTB5
10uF,6.3V/T2012
FB1
BLM18PG121SN1
CB10
100nF/C1608
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