Saverio Minutoli INFN Genova
1
Saverio Minutoli
INFN Genova
27 September 2006
T1status overview:
Electronic cardsAFEC – CFECVFAT emulator mezzanines
Totem Collaboration meeting
CablingFibersH.V.
Saverio Minutoli INFN Genova
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T1 electronics system
6xCFEC = 2x192chs
AFEC 220chs
50cm
CSC Plane_n
CSC
Pl
ane_n
+1
DOHM-CCU
SLOW CONTROL RING
boards shielded with faraday cages.
Saverio Minutoli INFN Genova
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Anode Front End Card (1)
Adapted to the CSC plane type 5P We have had some problem with the first design New PCB Design almost completed.
Major modifications: Shielding – cross talk – lines length equalization
Ready to produce the prototype next week. Components procurement completed. Pcb production need 2 weeks Components loading 1 week Ready to mount on the CSC-5P, end of October
Saverio Minutoli INFN Genova
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AFEC (2)
Layout first prototype
top
bottom
Saverio Minutoli INFN Genova
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CFEC (1)
Design completed. PCB prototypes produced. Components procurement completed. Ready to load the components on the boards:
External firm This week, mounting tools production. Next week we will have the board on the desk.
Saverio Minutoli INFN Genova
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CFEC LAYOUT - TOP
Saverio Minutoli INFN Genova
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CFEC (2)
Saverio Minutoli INFN Genova
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CFEC (3)
with VFAT digital
with VFAT digital emulator
Saverio Minutoli INFN Genova
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CFEC box (4)
Shielding
Heat dissipation
Saverio Minutoli INFN Genova
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CFEC 2nd version (5)
Cathode with VFAT analog
Cathode signal shared in two VFAT Two thresholds
Saverio Minutoli INFN Genova
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VFAT digital emulator mezzanine
Top
Bottom
CFEC with mezzanine
Saverio Minutoli INFN Genova
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VFAT analog emulator mezzanine (1)
We have had some problem with the first pcb design: Blind hole - Ratio diameter/#layers 1/12, not possible to produce
New PCB Design completed. Ready to produce the prototype next week. Components procurement completed. Pcb production need 1 weeks Components loading 1 week Ready to mount on the CSC-5P, middle of October
Saverio Minutoli INFN Genova
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VFAT analog emulator mezzanine (2)
Saverio Minutoli INFN Genova
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Mezzanines firmware
VFAT verilog code have been synthesized, routed and placed in the FPGA designed for the mezzanines (Xilinx Spartan 3.)
Need to link the physical pin out of the device with the code.
Need to write the USB driver: Probably we can adopt the driver written for the FED
mezzanine? We can “play” with the firmware, soon. Need to get the new VFAT datasheet, in particular I2C
registers mapping.
Saverio Minutoli INFN Genova
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T1 Detector cable routing (1)
Saverio Minutoli INFN Genova
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T1 Detector cable routing (2)
Saverio Minutoli INFN Genova
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T1 Detector cable routing (1)
L1=50cm
L2=12m
Optic FibersPatch Panel8 MPO
T1 RackGOL/DOHM
GOL/DOHM
MPO in line adapter
Fan-out Box onT1 6th frame
Multi ribbon cable (8x12)
Ribbon fiber cable (12x1)
Single fiber
SMU in line adapter
12
8
L3=2.3m
L4=3m L6=2m
L5=2m
T1 internal distribution
Platform Side
Cable Tray side T1 quarter side
#2
#1
#3
#4
T1 ¼ Optic Distribution Scheme
Saverio Minutoli INFN Genova
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H.V. architecture
Patch -Panel
DCSSCADAOPCServer
A1733B28 Channels 3 kV/3 mA or 4 kV/2 mA
15SHV
R.M.
R.M.= 52 Radiall Multipin
Patch -Panel
Patch -Panel
Patch -Panel
Patch -Panel
R.M.
15SHV
15SHV
15SHV
R.M.
R.M.
3 x R.M.
2
2
GROUNDING & SHIELDING ??
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