VLSI Testing Yield Analysis & Fault Modeling
VLSI Testing Yield Analysis & Fault Modeling
Virendra SinghIndian Institute of Science
E0 286: Test & Verification of SoC Design
Lecture - 2
Jan 18, 2008 E0-286@SERC 2
VLSI Chip YieldVLSI Chip Yield
A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.
A chip with no manufacturing defect is called a good chip.
Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y.
Cost of a chip:Cost of fabricating and testing a wafer
-------------------------------------------------------------------- Yield x Number of chip sites on the wafer
Jan 18, 2008 E0-286@SERC 3
Clustered VLSI DefectsClustered VLSI Defects
WaferDefects
Faulty chips
Good chips
Unclustered
defectsWafer yield = 12/22 = 0.55
Clustered defects (VLSI)Wafer yield = 17/22 = 0.77
Jan 18, 2008 E0-286@SERC 4
Yield ParametersYield Parameters Defect density (d ) = Average number of defects per
unit of chip area Chip area (A) Clustering parameter () Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
(+x ) (Ad /) x= -------------
. ----------------------
x ! () (1+Ad /) +xwhere
is the gamma function
= 0, p (x
)
is a delta function (maximum clustering) =
, p
(x
)
is Poisson distribution (no clustering)
Jan 18, 2008 E0-286@SERC 5
Yield EquationYield Equation
Y
= Prob
( zero defect on a chip ) = p
(0)
Y = ( 1 + Ad /
)
Example: Ad
= 1.0,
= 0.5, Y
= 0.58
Unclustered
defects:
= , Y
= e -
Ad
Example: Ad
= 1.0,
= ,
Y
= 0.37too pessimistic !
Jan 18, 2008 E0-286@SERC 6
Defect Level or Reject RatioDefect Level or Reject Ratio
Defect level (DL) is the ratio of faulty chips among the chips that pass tests.
DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured
product quality. For commercial VLSI chips a DLgreater than 500 ppm is considered unacceptable.
Jan 18, 2008 E0-286@SERC 7
Determination of DLDetermination of DL
From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL.
From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.
Jan 18, 2008 E0-286@SERC 8
Modified Yield EquationModified Yield Equation Three parameters:
Fault density, f = average number of stuck-at faults per unit chip areaFault clustering parameter, Stuck-at fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / ) -
Assuming that tests with 100% fault coverage(T
=1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / ) -
Jan 18, 2008 E0-286@SERC 9
Defect LevelDefect Level
Y (T ) -
Y (1)DL (T ) = --------------------
Y (T )
(
+ TAf
) = 1 -
--------------------(
+ Af
)
Where T
is the fault coverage of tests, Af
is the average number of faults on the chip of area A,
is the fault clustering parameter. Af
and
are determined by test data analysis.
Jan 18, 2008 E0-286@SERC 10
05
101520
2530
0 10 20 30 40 50 60 70 80 90 100Fault Coverage
D
e
f
e
c
t
L
e
v
e
l
Yield and Fault CoverageYield and Fault Coverage
Jan 18, 2008 E0-286@SERC 11
Computed DLComputed DL
Stuck-at fault coverage (%)
D
e
f
e
c
t
l
e
v
e
l
i
n
p
p
m
237,700 ppm
(Y
= 76.23%)
SEMATECH Chip (Courtesy: IBM)
Jan 18, 2008 E0-286@SERC 12
Time in Months
R
e
v
e
n
u
e
s
TTime toMarket
Loss ofRevenues
Time to MarketTime to Market
Jan 18, 2008 E0-286@SERC 13
Failure Rate Vs Product Lifetime
Product Life Time
F
a
i
l
u
r
e
R
a
t
e
InfantMortality Working Life Span Wearout
1-20 weeks 10-20 years
Jan 18, 2008 E0-286@SERC 14
DefinitionsDefinitions
Defect: A defect in an electronic system is the unintended difference between the implemented hardware and its intended design
Error: A wrong output signal produced by defective system is called error. An error is an effect whose cause is some defect
Fault: A representation of a defect at the abstracted function level is called a fault
Jan 18, 2008 E0-286@SERC 15
Why Model Faults?Why Model Faults?
I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing)
Real defects (often mechanical) too numerous and often not analyzable
A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments
Jan 18, 2008 E0-286@SERC 16
Some Real Defects in ChipsSome Real Defects in Chips Processing defects
Missing contact windows Parasitic transistors Oxide breakdown . . .
Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) . . .
Time-dependent failures Dielectric breakdown Electromigration . . .
Packaging failures Contact degradation Seal leaks . . .
Ref.: M. J. Howes
and D. V. Morgan, Reliability and Degradation -Semiconductor Devices and Circuits, Wiley, 1981.
Jan 18, 2008 E0-286@SERC 17
Electromigration
(a)
(b)
(c)
(a) Open in a line(b) Short between two lines (whisker)(c) Short between lines on different layers (hillock)
Jan 18, 2008 E0-286@SERC 18
Mapping Physical Defect into Faults 1
B
R1
R2
RL
BA
Z(a) (b)
ZA
A Z
Z
A
Both the defective resistance in bipolar and a the oxide breakdown in oxide between the source and drain of the NMOS transistor form a short failure mode
Both cases are mapped into a stuck-atfault
Jan 18, 2008 E0-286@SERC 19
Mapping Physical Defect into Faults 2
A
ZA
Z
A
Z
Poly Metal Diffusion
Physical defect: A missing metalo
NMOS is missing the gate Failure mode: an open Fault: open A possible circuit representation is shown
Jan 18, 2008 E0-286@SERC 20
Mapping Physical Defect into Faults 3
(a) (b)
(d)
L1
L2 L2
L1
Bridging Fault
(c)GND
Stuck-at 0Stuck-at 1Vdd
Jan 18, 2008 E0-286@SERC 21
Observed PCB DefectsObserved PCB Defects
Defect classes
ShortsOpensMissing componentsWrong componentsReversed componentsBent leadsAnalog specificationsDigital logicPerformance (timing)
Occurrence frequency (%)
5116
1368555
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand
Reinhold, 1985.
Jan 18, 2008 E0-286@SERC 22
Failure Classification
IC Failures
Parameter Degradation
Incorrect Design
TemporatySoft
PermanantHard
Mode Duration
Transient
Intermittent
Jan 18, 2008 E0-286@SERC 23
Common Fault ModelsCommon Fault Models
Single stuck-at faultsTransistor open and short faultsMemory faultsPLA faults (stuck-at, cross-point, bridging)Functional faults (processors)Delay faults (transition, path)Analog faults
Jan 18, 2008 E0-286@SERC 24
Single Stuck-at FaultSingle Stuck-at Fault Three properties define a single stuck-at fault
Only one line
is faultyThe faulty line is permanently set to 0
or 1The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults
a
b
cd
e
f
10
g h i 1
s-a-0j
k
z
0(1)1(0)
1
Test vector for h s-a-0 fault
Good circuit valueFaulty circuit value
VLSI Testing Yield Analysis & Fault ModelingVLSI Chip YieldClustered VLSI DefectsYield ParametersYield Equation Defect Level or Reject RatioDetermination of DLModified Yield EquationDefect LevelYield and Fault CoverageComputed DLTime to MarketFailure Rate Vs Product LifetimeDefinitionsWhy Model Faults?Some Real Defects in ChipsElectromigration Mapping Physical Defect into Faults 1Mapping Physical Defect into Faults 2Mapping Physical Defect into Faults 3Observed PCB DefectsFailure ClassificationCommon Fault ModelsSingle Stuck-at Fault
Top Related