TDC With Hit Rate Limiter 96 Ch
TDC
T1T0
DV
Counter
Hit RateLimiter
(7/256CK212)
DVLDCLR
CK212L/S
LD
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
CC[5..2]
4hits/256CK212,4hits/1.2s3.3MHz
CLRHITLD
CLRCNT
TDC Data Concentration 96 Ch
L1 Buffer1xM4K16x256
4hits/CH/1.2s16hits/4CH/1.2s1hit: 16bitsBuffer Length:(256/16)x1.2s=19.2s
ZeroSupp.
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
EV Buffer2xM4K
16x256x2
SDRAM16x6M/spill12MB/spill
EV Window 2 x 1.2s128hits/16CH/EV16 Ch Output Time:128CK106=64RF=1.2s48 Ch Store Time:=3.6s
SDRAM WR Time:256RF<4.8s
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
L1 Buffer1xM4K16x256
ZeroSupp.
L1 Buffer1xM4K16x256
L1 Buffer1xM4K16x256
FPGA(DCC)
Truncating at EV Buffer123+5 words/48CH/EV48 Ch Send Out Time:128x2RF=4.8s
Useful Numbers: for 96 Channel Board
RF 53.102MHz, 18.8ns
CK212 212.4MHz, 4.708ns
LSB 1.18ns
Hit Rate Limiter Setting 4hits/256CK212 4hits/64RF 4hits/1.2s, 3.3MHz
Double Hit Min. Separation 4xCK106, 37.7ns
Event Window 2 x 1.2s
Absolute Maximum Hits/event/48ch 123hits+5header/trailers 128 x 2Bytes
Event Maximum Size/96ch 256 x 2Bytes
SDRAM port data rate 53MHz x 2Bytes 4.8s/event
Number of events/spill <32K
Absolute Maximum data/spill/FE card 8M words 16MB
Absolute Maximum data/spill/8 FE 128MB 1280Mbits
Readout Chain Data Rate 26.5Mbits/s
Absolute Maximum Spill Readout Time 48.3sec
Readout Timing
G0B=0
G4B=0
G0B=1
G4B=1
G8B=1
G12B=1
G24B=1
G8B=0
G12B=0
G16B=0
G20B=0
G16B=1
G20B=1
G24B=0
G28B=0
G28B=1
0 1 2 3 4 5 6
0,1
7
6.6us
1.2us
8 9 a b c
0,1
WR
RD
G32B=0
G32B=1
G44B=1
0,1
1.2us
Data Format
1 CH[3..0] CC[10..2] T1 T0
BD_CHGRP[4..0]
CNT[7..0]
EV[13..0]=1, 2, .. 16K-1
EHID[5..0]
Reserved Header/Ender
EV Header 0
EV Header 1
Hit Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 01617
0
1
1 P
1 P
1 P
0 0
00 0 No Data
1 P CHGRP Header
00 0
0
TS[7..0]0 1 0
1 0 1 P
Ender
Data Block
CHGRP Header CHGRP=0
EV Header 0
EV Header 1
No Data
Hit Data
Hit Data
CHGRP Header CHGRP=1
Hit Data
CHGRP Header CHGRP=2
CHGRP Header CHGRP=3
Hit Data
CHGRP Header CHGRP=4
CHGRP Header CHGRP=5
Ender (=No Data)
CHGRP Header CHGRP=0
EV Header 0
EV Header 1
No Data
Hit Data
Hit Data
CHGRP Header CHGRP=1
CHGRP Header CHGRP=2
Ender (=No Data)
EV Header 0
EV Header 1
No Data
CHGRP Header CHGRP=3
Hit Data
CHGRP Header CHGRP=4
CHGRP Header CHGRP=5
Ender (=No Data)
Hit Data
TDC Description• The TDC FE card has three FPGA devices: two named MIPP_TDC and one named MIPP_DCC. Each
MIPP_TDC digitizes 48 channels of inputs and sends data to MIPP_DCC which interfaces with a 16MB SDRAM and the daisy-chained interface to ship data back to the controller. A TDC_FE card supports 96 input channels.
• Each channel in the MIPP_TDC has a hit limiter. The time is split into 1.2us (or 64RF, RF=1/53MHz) periods which are counted after the reset at the start of each spill. In each of the 1.2us, the number of hits in each channel is limited to 4 hits.
• A channel group contains 4 channels. Every 4 cycles of CK106 (106MHz), hit data in each channel is written to the hold-shift register. The hold-shift register then shift data of the 4 channels, one in each CK106 cycle, to the zero suppression block. Therefore, the hit separation in each channel is 4 x 1/106MHz = 37.7 ns.
• The zero-suppressed data from the 4-channel groups, i.e., only the valid hits are stored in the L1 pipeline buffers. A pipeline buffer is organized as 16 blocks of 16 words with 16-bit/word which uses a M4K RAM. Each hit is stored as a 16-bit word, each channel can have maximum 4 hits in 1.2us. Therefore, a 16 words block holds data of 4 channels in 1.2us. The entire L1 pipeline length is 16x1.2us = 19.3us.
• Up to about 18us trigger latency are supported. For each trigger, data in 2 x 1.2us time window are readout, which corresponding to 2 16-word blocks in the L1 pipeline buffer. Data from 16 channels are grouped together, taking 1.2us to transfer from the L1 pipeline buffer to the EV buffer. Data of 48 channels are transferred in 3.6us.
• Truncating happens while storing data into EV buffer if too many channels are hot. The data for an event stored in the EV buffer contains 2 headers and 3 enders, one at the end of each 16-channel group. The total number of hits allowed in 48 channels is 123. The truncated data block is not good for experiment data, however, it contains all necessary header and enders to avoid hanging up the remaining readout system.
• Up to 256 16-bit words/event for 96 channels are stored in the 16MB SDRAM. A total of 32K events can be held in the SDRAM.
• Daisy chained 8 TDC_FE cards are readout through a 26.5Mbit/s data link to the controller. The total time to readout 8 x 16 MB is about 48.3 sec.
TDC With Hit Rate Limiter
TDC
T1T0
DV
Counter
Hit RateLimiter
(7/256CK212)
DVLDCLR
CK212L/S
LD
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
CC[5..2]
7hits/256CK212,7hits/1.2s5.8MHz
CLRHITLD
CLRCNT
Reset Timing
0 1 2 3 4 5 6 7 8 9 a b c d e f
0 1 2 3 0 1 2 3
0 1 2 3 0 1 2 3
CC[9..2]
CC[4..3]
CK106
SCLR
SCLRQ
SCLRCC
CCQ[4..3]=CH
10CLRHIT
LDT=7TCQ
VTQ CH=0 CH=1 CH=2 CH=3
ff 00
CLRCNT
Trigger Timing
7F 0 1 2 3
CC[9..2]
CC[9..3]
CK106
CCQ[9..3]
FF 00
CLRCNT
FE 01
7F 0 1 2 37E
TM1us
MGQ[]
WBK[2..0] BK1 BK1+1, BK1+4
TM1us
EVPRQ[7..3],[2..0] N,7 N+1,0
Trig
TrigReq
N+1,7
N,7 N+1,0EVPR4Q[7..3],[2..0]
PUSHOK=!EVPR5Q[2]
7F 0 1 2 37ECC3Q[9..3]
(7F) (0) (1) (2)(7E)TMQQ[]
(7F) (0) (1)(7E) (7F)
N+1,3N,7 N+1,0EVPR5Q[7..3],[2..0]
TDC Data Concentration
L1 Buffer1xM4K16x256
7hits/CH/1.2s28hits/4CH/1.2s1hit: 16bitsBuffer Length:(256/32)x1.2s=9.6s
ZeroSupp.
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
EV Buffer4xM4K
16x512x2
SDRAM16x6M/spill12MB/spill
EV Window 2 x 1.2s448hits/32CH/EVBuffer Input Time:448CK106=224RF=4.2s
SDRAM WR Time:448RF<9.6s
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
L1 Buffer1xM4K16x256
ZeroSupp.
L1 Buffer1xM4K16x256
L1 Buffer1xM4K16x256
L1 Buffer
L1 Buffer1xM4K16x256
ZeroSupp.
L1 Buffer1xM4K16x256
ZeroSupp.
CCQ[13..10]WA0x[4..0]
VTQ0x
0
WA1x[4..0]
VTQ1x
CCP1Q[12..10],CCQ[7..3]
CCMLQ[12..10],CCQ[7..3]
CCQ[8]=1
0
CCP1Q[12..10],CCQ[7..3]
CCMLQ[12..10],CCQ[7..3]
CCQ[8]=0
EventWindow
Readout Timing
G0B=0
G4B=0
G0B=0
G4B=0
G0B=1
G4B=1
G0B=1
G4B=1
G8B=0
G12B=0
G8B=1
G12B=1
G16B=0
G20B=0
G16B=1
G20B=1
G24B=0
G28B=0
G24B=1
G28B=1
G8B=0
G12B=0
G8B=1
G12B=1
G16B=0
G20B=0
G16B=1
G20B=1
G24B=0
G28B=0
G24B=1
G28B=1
0 1 2 3 4 5 6
1
2
16.6us
1.2us
0
12
3
7
65
4
3 4 5 6 7
00
WR
RD
Useful Numbers
RF 53.102MHz, 18.8ns
CK212 212.4MHz, 4.708ns
LSB 1.18ns
Hit Rate Limiter Setting 7hits/256CK212 7hits/64RF 7hits/1.2s, 5.8MHz
Double Hit Min. Separation 8xCK106, 75.5ns
Event Window 2 x 1.2s
Absolute Maximum Hits/event/32ch 448hits 448 x 2Bytes
Event Interval >512RF >9.64s
SDRAM port data rate 53MHz x 2Bytes 512 x 2Bytes
Number of events/spill 12K
Absolute Maximum data/spill/FE card 5.37M hits 10.75MB
Absolute Maximum data/spill/8 FE 86MB 860Mbits
Readout Chain Data Rate 26.5Mbits/s
Absolute Maximum Spill Readout Time 32.5sec
Data Format
D/H=1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH[4..0] CC[9..2] T1 T0
256 x CK212 = 1.2s1024 x 1.18 ns
BD[2..0] CNT[8..0]0 0 1
EV[13..0]=1, 2, .. 16K-1
TS[9..0]
0
0 1
0 010
0 110 Reserved Header/Trailer
PR[1..0]
Zero Suppression
L1 BufferM4K9x512
ZeroSupp.
TDC/HRL
TDC/HRL
TDC/HRL
TDC/HRL
DV
CH1
CH0
CC5
CC4
CC3
CC2
T1
T0
0
0
0
X
X
X
X
X
X
1
CH1
CH0
T1
T0
Data Roll-overMarker1/16CK2121/4RF
Counter
CH[3..0]
CK212
A==0 PUSH
DV
CC5
CC4
CC3
CC2
L1 Buffer Contents
0
0
0
X
X
X
X
X
X
1
CH1
CH0
T1
T0
TS=n
0
0
0
X
X
X
X
X
X
1
CH1
CH0
T1
T0
1
0
0
T1
T0
0
0
0
X
X
X
X
X
X
n+1
0
0
0
X
X
X
X
X
X
n+2n+4 n+3
CC5
CC4
CC3
CC2
CC5
CC4
CC3
CC2
CC5
CC4
CC3
CC2
Hold-Shift Timing
TDC
T1T0
DV
Counter
Hit RateLimiter
(8/256CK212)
DVLDCLR
CK212L/S
LD13
CC[5..2]
SCLRTCQ
0 1
SCLRQQ
CC[]
SCLRTCQ
LD53
Counter
CH[3..0]A==0 PUSH
DV
PUSH
1 77 0654
2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 e f 0
3210 0CH[]
POP Logic L1 BufferM4K9x512
POPLogic
EV Buffer2xM4K16x512
DV
CH1
CH0
CC3
CC2
CC1
CC0
T1
T0
(A==0)&POPQ
Counter
TP[11..4]
CK212
Counter
TS[11..0]
CK212
INC
TL
POP
L1
TS-TP>TLTPL1-TP<TW
etc.
TW
TL: 256 RF = 4.8sTW: 16 x 4 RF = 1.2s
S0. After Reset: No POP until TS-TP>TLS1. Before L1: Popping until TS-TP==TLS2. L1 Arrives: Stop popping, keep TPL1S3. DLSEL: Resume popping
PUSHEV if TPL1-TP<TW
PUSHEVDLSEL
DLSEL: 64 CK212 for each group.
POP Logic L1 BufferM4K9x512
POPLogic
EV Buffer2xM4K16x512
DV
CH1
CH0
CC3
CC2
CC1
CC0
T1
T0
(A==0)&POPQ
Counter
TP[11..4]
CK212
Counter
TS[11..0]
CK212
INC
TS-TP>TL
TL
POP
DL Ctrl
L1
DL Token In
DL Token Out
TPL1-TP<TW
TW
TL: 256RF = 4.8sTW: 16x4RF = 1.2s
S0. After Reset: No POP until TS-TP>TLS1. Before L1: Popping until TS-TP==TLS2. L1 Arrives: Stop popping, keep TPL1S3. DL Token in: Popping until TPL1-TP==TW
Output DL Token, go to S1.
Hit Rate Limiter
CK212
+/-
NE0
NE7
0
0
DVDVLD
• For each incoming hit, the accumulator is added by:
– 32 most of time
– (-1) when >=224 (i.e., 7*32).
• For each clock cycle with no hit, the accumulator counts down by:
– 1 most of time
– 0 if the accumulator is empty.
• Long term dead-time-free hit rate:– < 1/33*212MHz = 6.4 MHz.
• Instantaneous dead-time-free hit rate:– < 6hit in any 256+6 time window.
• Absolute maximum number of hits in any 256 cycle (1.2s):
– 15 hits
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