Standard buses
Buses 2/47
System buses
Communication buses
Buses 3/47
control panel
other systems measure & control devices.
timersRTC
decodersMM serv.devices
interruptcontrollers
secondarymemories
processor
programmememory(ROM)
datamemory(RAM)
operatordevices
communi-cation
devices
processdevices
systembus
communicationbuses
System buses - MUBUS 4/47
D0..D15 - 16 data lines;A0..A15 - 16 address lines;ADMEMLOW, ADPERLOW - memory & I/O access pulsesREFRESHLOW - refresh address pulseNOTREADYLOW - not readyWRITELOW - write pulseNODALOW - data valid on D0..D15RESETLOW - system resetINTREQLOW, INTACKLOW - maskable interrupt request & interrupt acknowledgeINTIN, INTOUT - interrupt daisy chain signalsNMILOW - non-maskable interruptHOLDREQLOW, HOLDACKLOW - bus request & bus release acknowledgeHOLDIN, HOLDOUT - bus request daisy chain signalsPROCREQLOW - bus request in multi-processors systemSYSTEMCLOCK, USERCLOCK - clocks;-12V,-5V,0V,5V,12V - „internal” supplying lines;-15V,0V,15V & 0V,5V - „external” supplying lines, isolated from „internal” supplying lines.
MUBUS
System buses - MUBUS 5/47
memory read cycle
A15..A0
ADMEMLOW
NOTREADYLOW
WRITELOW
D15..D0
memory write cycle
A15..A0
ADMEMLOW
NOTREADYLOW
WRITELOW
D15..D0
A15..A0
ADPERLOW
NOTREADYLOW
WRITELOW
D15..D0
I/O device read cycle
I/O device write cycle
A15..A0
ADPERLOW
NOTREADYLOW
WRITELOW
D15..D0
System buses - MULTIBUS 6/47
MULTIBUS (Intel’s)
DAT0..DAT15 - data lines;ADR0..ADR15 - address lines;MRDC, MWTC - memory read & write pulses;IORC, IOWC - I/O read & write pulses;XACK, AACK - read/write acknowledge signals for memory & I/OINH1 - inhibit signal for RAM INH2 - inhibit signal for ROMINIT - system resetINT0..INT7 - interrupt request inputsBREQ - bus request BUSY - bus busyBPRN, BPRO - bus request daisy chain signalsBCLK, CCLK - constant & variable clocks (max.10MHz);-12V,-10V,-5V,0V,5V,12V - supply
System buses - MULTIBUS 7/47
memory read cycle
ADR15..ADR0
MRDC
XACK
D15..D0
I/O device read cycle
ADR15..ADR0
IORC
XACK
D15..D0
memory write cycle
ADR15..ADR0
MWTC
XACK
D15..D0
I/O device write cycle
ADR15..ADR0
IOWC
XACK
D15..D0
System buses - MULTIBUS II 8/47
MULTIBUS II (Intel)
for any microprocessor, also for multiprocessors systems,
transfer speed up to 40MB/s
MULITIBUS II - standard of the whole multiprocessors system:
architecture, buses, electrical, mechanical
Standard defines 5 buses:
multichannel DMA bus;
iSBX - Intel IO expansion bus;
iLBX - Intel local bus extension;
iSSB - Intel serial system bus;
iPSB - Intel parallel system bus.
System buses - MULTIBUS II 9/47
iPSB
consists of 5 sub-buses:data & address bus:
multiplexed AD0..AD31 & PAR0..PAR3
(parity bit for each 8 ADx lines);arbitrage bus: BREQ i 6 lines ARBx for priority level;system control bus: lines SC0..SC9,
which means depends on bus cycle;error line bus: BUSRER - parity error on ADx or SCx bus,
TIMEOUT - transfer time limit exhausted;general control bus: RST, RSTNC, DCLOW, PROT,
BCLK, CCLK, LACHn
System buses - MULTIBUS II 10/47
iPSB bus protocol consists of 3 cycles:
arbitrage cycle = arbitrage phase
+ switching bus to selected processor phase;
transfer cycle = request phase (address & order transmitting)
+ answer phase (data & strobes)
error message cycle = message phase
+ return phase
System buses - VME 11/47
VME bus (Versa Module Eurocard - Mostek, Motorola, Signetics)
1981 - ver. A: union of two standards VERSAbus & Eurocard1982 - ver. B1985 - ver. C: by IEC i IEEE commissionsnow ver. D: extension for 64-bit processors
VME modular systems dominate on industrial and military applications market.
Features: asynchronous, 32 data lines (ver. C), 64 (ver. D); 32 address lines (ver. C), 64 (ver. D); non-multiplexed (ver. A-C), multiplexed (ver. D); 7 interrupt levels; possible multiprocessor applications; wide offer of VME cases and modules, from many manufacturers;
System buses - VME 12/47
Features cont.:
2 types of modules: master - transfer initiator & slave - subordinate; many masters can be connected to one bus - their bus access requests
are handled by priority arbiter included in bus controller,
placed in most-left socket of the system case;
bus controller contains following blocks:
systemclock
transmitter
bustimer
IACK*signal
transmitterarbiter
supplymonitor
VME bus controller
VMEbus
System buses - VME 13/47
Features c.d.
max. transfer speed 40MB/s; max. bus length 50cm; number of sockets 2 .. 21; bus signals are divided into 4 sub-busses:
data transfer bus (data, address and handshake);arbitrage bus (used by masters and interrupt service modules for accessing to data transfer bus);priority interrupt bus (7 interrupt request lines, interrupt acknowledge, interrupt chain system lines);additional lines bus (system reset, clocks, supply +5V, +12V, -12V, etc.);
two connectors J1 i J2 (optional), each 32x3 pins, J2 contains: 8 most sensing address bits, 16 most sensing data bits, additional supply lines, 64 user-defined lines; VME modules are height of 3U with only J1 connector or 6U with both J1 & J2;
System buses - VME 14/47
Example of VME CPU module:
CPU module
addressmonitor
mastermodule
busrequestmodule
interrupthandlermodule
interruptrequestmodule
VMEbus
CPU
System buses - VME 15/47
Example of VME I/O or memory module:
slave module
slavemodule
interruptrequestmodule
VMEbus
I/O devices or memory
System buses - PC 16/47
PC standard buses 8086/88
286
386 386 386 386
486 486 486 486 486
P5 P5 P5
P6 (Pro) MCA EISA ISA PCI VLB 20Mb/s 33Mb/s 12,5Mb/s 132/264Mb/s 120Mb/s
ISA - Industry Standard ArchitectureEISA - Extended Industry Standard ArchitectureMCA - Micro Channel ArchitectureVLB - VESA Local Bus (Video Electronic Standards Association)PCI - Peripheral Component Interconnect
System buses - MCA i VLB 17/47
MCA- invited by IBM for PS/2; 32 data lines & 32 address lines;
for multitasking O.S. & 386/486 processors;
up to 16 microprocessors placed on extension cards; 32-bit DMA channels;
expanded configuration memory; extension cards have identifiers;
cards configured only by software; software switching on/off ;
max. transfer speed 20MB/s.
VLB - 32-bit local bus designed for disk & video controllers;
based on 386/486 local bus;
VLB socket placed behind standard ISA socket;
max. transfer rate 120MB/s.
System buses - ISA 18/47
D1 C1
D10 C10
D18 C18
/MEMCS16/IOCS16
IRQ10IRQ11IRQ12IRQ15IRQ14
/DACK0DRQ0
/DACK5DRQ5
/DACK6DRQ6
/DACK7DRQ7
Vcc/MASTER
GND
SBHELA23LA22LA21LA20LA19LA18LA17/MEMR/MEMWSD08SD09SD10SD11SD12SD13SD14SD15
tył obudowy
B1 A1
B10 A10
B20 A20
B31 A31
GNDRESET
+5VIRQ2
-5VDRQ2
-12V/0WS+12VGND
/SMEMW/SMEMR
/IOW/IOR
/DACK3DRQ3
/DACK1DRQ1/REFCLKIRQ7IRQ6IRQ5IRQ4IRQ3
/DACK2T/C
ALE+5V
OSCGND
/IOCHKD7D6D5D4D3D2D1D0IOCHRDYAENA19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
ISAtransfer speed up to 10MB/s
System buses - EISA 19/47
EISA (Extended Industry Standard Architecture)
EISA differs from ISA:
32 data &32 address lines;
new 90 signals;
full application of 32-bit processors;
electrical and mechanical ISA compatibility;
for multiprocessor systems with priority accessing to common resources,
additional processors - on extension cards;
extended DMA:
blocks up to 4GB (ISA up to 64/128kB);
7 channels 8/16/32-bits wide (with automatic width selection);
rotated instead fixed device assignment system;
level ISA
level EISA
System buses - EISA 20/47
EISA differs from ISA, cont.:
level active interrupt, instead slope like in ISA - more jamproof;
4kB configuration memory (for main-board and extension cards);
extension cards configured only by software;
extended bus controller;
transfer speed up to 33MB/s.
Applications:
industrial computers;
System buses - PCI 21/47
PCI
Invited by Intel as processor independent, 32-bit local bus.
Allows building very big systems:
up to 256 PCI buses in one system;
up to 32 devices per one bus;
up to 8 functions per one device.
Standard PC main board have 1 PCI bus servicing up to 10 devices.
Clocking frequency: 33MHz (66MHz) transfer speed 132MB/s (264MB/s).
64-bit extension has doubled transfer speed.
System buses - PCI 22/47
extensioncards
ISAEISAMCA
SCSIbus
P
cache
memory controller
PCI controller
RAM
sound card graphic card video card
network card HDC/FDCexternalbus
bridge
SCSIbridge
SCSIdevices
PCI
Typical PCI bus structure in PC:
System buses - PCI 23/47
PCI configuration memory
Each device has 256B configuration memory, containing:
• 64B standard header:
manufacturer and device identifiers, version of device,
command register, status register,
device class, minimal transfer time, etc.
• 192B device-specific bytes.
Bus and device configuration - automatic/software
System buses - PCI 24/47
There are 2 types of PCI devices:
initiators (I), which can control the bus;
slaves (S), only answer to transfer requests.
Transfer can be conducted between: I I else I S.
There are 4 types of PCI sockets,
due to data bus width and
supply voltage:
rear of the case
3,3V 5V32b
3,3V 5V64b
basic120 contacts
64 extensioncontacts
System buses - PCI 25/47
PCI interrupts
There are 4 interrupt channels, shared by many devices. PCI bus arbiter contains
programmable interrupt router (PIR), which matches PCI interrupts to standard
PC-AT interrupt controllers.
PIR
8259Aslave
8259Amaster
IRQ8
IRQ15
IRQ0
IRQ7
INTA
INTB
INTC
INTD
dev.X
dev.Y
dev.Z
System buses – AGP 26/47
AGP (Accelerated Graphics Port) - modified PCI:
• introduced in 1997r.;
• 32-bit bus for servicing a single graphic card;
• optimized for fast data block transfer between main memory and graphic card;
• transfer rate up to 2133MB/s;
System buses – PCIe 27/47
PCIe (Peripheral Component Interconnect Express):
• introduced in 2004r. (v1.0);
• replaces firstly AGP and then PCI;
• designed for servicing a single (one slot = one driver PCIe) extension card –
mainly graphic card;
• slot size depends on transfer rate
and transfer rate depends on number of transferring lanes;
• transfer rate in full-duplex from 250MB/s (v1.0 x1) to 16GB/s (v3.0 x16);
Communication buses - I2C 28/47
I2C - Philips’s inter-chip synchronous serial bus (I2C = IIC = Inter-Integrated Circuit)
Applications: communication in dissipated data acquisition and control systems; peripheral device service; consumer electronics.
Features:
SCL - clock line fMAX=100kHz (standard), 400kHz (extension),
now up to 1MHz;
SDA - data line;
common ground;
SCL & SDA are driven by OC (OD) outputs
- pulling-up (to Vcc) resistors are needed;
up to 32 devices per one bus.
Communication buses - I2C 29/47
Standard I2C bits:
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
“S”start bit
“D”data bit
“A”acknowledge bit
“E”stop bit
Serial transmission of byte:
SCL
SDA D7 D6 D5 D4 D3 D2 D1 D0 A
Communication buses - I2C 30/47
Transfer is realized between superior device (master), which drives both SDA & SCL lines and inferior (slave), which can drive only SDA line.
Devices connected to one I2C branch may be different:
SCLSDA
Vcc
mastertr/rec
slavetr/ rec
slaverec
mastertr/ rec
slavetr/ rec
slavetr/ rec
Communication buses - I2C 31/47
During transfer master slave “A”-bit is sent by slave, after correct addressing
and data receiving.
Transfer starts “S”-bit sent by master.
Transfer ends “E”-bit either new “S”-bit from master.
SCLmaster
SDAmaster S D7 D6 D5 D4 D3 D2 D1 D0 E S D7 D6 D5
SDAslave
A
Communication buses - I2C 32/47
During transfer slave master “A”-bit is sent by master if after receiving data, it
is going to read following bytes from slave. The absence of “A”-bit from master
makes slave to stop transmitting.
Transfer ends “E”-bit either new “S”-bit from master.
SCLmaster
SDAslave D0 D7 D6 D5 D4 D3 D2 D1 D0
SDAmaster A
acknowledge from master S D7 D6 D5no acknowledge from master
Communication buses - I2C 33/47
Device addressing
Standard addressing allows to address up to 128 devices connected to single bus.
Each device should have individual 7-bit hardware-defined address.
Device may master either slave type and work as: transmitters, receivers or
transmitters/receivers.
Before data transfer slave should be addressed by active master.
After “S”-bit master transmits 7-bit slave address together with R/W-bit,
which determines transfer direction of the following bytes.
Examples of typical transfer frames: 1. master slave with one internal register
2. slave with one internal register master
S slave address 0 A data byte A X
slave
master master
slave
R/W master
S slave address 1 A data byte 1 X
slave
master masterR/W
slave
Communication buses - I2C 34/47
Communication buses - I2C 35/47
3. master slave with many internal registers
S slave address 0 A internal slave address A data byte A X
slave
master x N master
slave +slave
R/W
4. slave with many internal registers master
S slave address 1 A data byte A data byte 1 X
slave
master
N
mastermaster
+slave
R/W
x (N-1)+
slave
Communication buses - I2C 36/47
Example of I2C-bus branch:
100n10k
VCC
VCCVCCVCC
SCL
SDA
VCCPCF8583RTC+240BCMOSRAM
32768
OSCI
OSCO
1 2 3
A0
5 6 7
SDA
TEST
SCL
PCF8570256BCMOSRAM
A0
A1
A2
4k7
4k7
1 2 3
5 6 7
PCF8570256BCMOSRAM 1 2 3
5 6 7
PCF8582256BEEPROM 1 2 3
5 6 7
SDA
TEST
SCL
SDA
RC
SCL
SDA
_INT
SCL
A0
A1
A2
A0
A1
A2
ADR=1010000 ADR=1010101 ADR=1010001 ADR=1010011
Communication buses - D2BUS 37/47
D2BUS (D2BUS = DDBUS = Digital Data Bus)
Features:
transfer speed up to 100kb/s;
range: 150m;
12 bit addresses (4096 devices);
up to 50 devices connected to single branch;
carrier: usually twisted pair;
bus control can be accessed by any D2BUS master device;
removing or switching off doesn’t disturb the communication;
to communication between devices, inside which I2C bus is applied.
Communication buses - D2BUS 38/47
Example of D2BUS frame:
S - start bit, P - parity bit, A - acknowledge bit, E - stop bit
D2BUS applications:
connecting few devices placed on local area
(dissipated control equipment, audio-video equipment).
Communication buses - D2BUS 39/47
Example of D2BUS application:
Communication buses - CAN 40/47
CAN (Controller Area Network)
invented by Bosch & Intel
Features:
asynchronous, huge number of transmitter and receiver
(up to 2032 version 2.0A; up to 500mln version 2.0B);
removing or switching off doesn’t disturb the communication;
transfer rate 1Mb/s at distance 40m;
range 1000m at transfer rate 40kb/s;
carrier: twisted pair;
bit coding by differential voltages;
electromagnetic jamproof.
Communication buses - CAN 41/47
CAN branch:
Standard CAN frame:
Communication buses - CAN 42/47
Applications:
automotive (fuel injection, ABS, airbags, lighting, air-condition, security),
aviation, robotics, industry controllers (Siemens).
J1850 - American version, no electric compatibility to CAN, applied by Chrysler, General Motors, Ford
ABUS - like CAN system from Volkswagen
VAN - like CAN system from Peugeot i Renault
Communication buses - SPI 43/47
SPI (Serial Peripheral Interface)
invented by Motorola
Features:
synchronous, full duplex;
speed rate typically 1,5Mb/s, max. 6..10Mb/s;
3 lines + slave selection line;
4 transfer modes, depending on clock polarity and active clock edge;
two types of devices: master & slave;
master should control clock and slave selection lines;
many masters and slaves can be connected to single bus;
no addressing.
Applications of SPI:
serial configuration memories, A/D & D/A converters, multiprocessor communication.
Communication buses - SPI 44/47
Example of SPI bus:
Example of transfer frame between master and slave-EEPROM:
Communication buses - SMBUS 45/47
SMBUS (System Management Bus)
designed by Intel in 80th years
Features:
• like I2C;
• two lines: SMBDAT i SMBCLK;
• I2C compatible at 100kHz transfer rate;
• transfer time-limit defined - 25ms;
• transfer rate: 10kHz-100kHz.
Communication buses - Microwire 46/47
Microwire
invented by National Semiconductor
Features:
• like SPI;
• synchronous, full duplex, compatible to SPI mode 0;
• max. transfer rate 650kb/s;
• three lines: SI (data input), SO (data output) i SC (clock);
• absence of slave-select line.
Applications :
serial EEPROMs, A/D & D/A converters,
specific chips for radio circuits, telecommunications and audio equipment.
Communication buses - 1-Wire 47/47
1-Wire
invented by Dallas Semiconductor/Maxim
Features:
• only single active line - supplying & transfer;
• synchronous, half duplex;
• fixed transfer rate 16,3kb/s (standard mode) & 115,2kb/s (overdrive mode);
• limited bit transmitting time (60s);
• two types of devices: master & slave;
• devices have unique identifiers - possibility of device addressing.
Applications:
iButton family, temperature meters, RAM , ROM, EPROM
i EEPROM, RTC chips, A/D converters, bridges to other serial interfaces
(RSxxx, USB), power supply supervisors, digital potentiometers.
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