External Use
TM
QorIQ Qonverge
SoC Solutions in HetNet Covering a wide range of wireless base station deployments
FTF-NET-F0033
A P R . 2 0 1 4
Barry Stern | Macro/Micro/Metrocell Product Line,
Sr. Marketing Manager
TM
External Use 1
Agenda
Explosion in Demand for Wireless Data Traffic and
Operators Challenges
Trends in Wireless Networks
Wireless Base Station Sites and Types
Silicon Vendors Challenges
Complete SoC Portfolio for Base Stations
SoC Portfolio Architectures
Complete Portfolio for HetNet from Freescale
Freescale Software Solutions
Rich Ecosystem of Partners
TM
External Use 2
Explosion of Traffic on Wireless Networks
Source: Ericsson (2013)
Global mobile penetration is at 92% and growing at >100M subs per quarter
EMEA, LAMEX, NAM & APAC* all > 100% penetration (*excluding China)
Mobile broadband subscribers will grow 4x to reach 9.3B by 2019, 5.6B Smart Phone, 2.6B LTE
Smart phone traffic will grow 10x driven by an average user monthly data traffic growth from 600 MB to 2.2 GB
LTE global population coverage will be 65% by 2019, North America will be 95%
TM
External Use 3
Mobile GPS
Touchpad
Notebook
Appliance
Addressing the Mobile Data Tsunami
Multiple parallel approaches required
New network topologies Cloud-RAN, small cells, DAS, HetNet
More efficient use of spectrum: LTE/OFDM, massive/high-order MiMO
New technologies: wireless backhaul (relay), carrier Wi-Fi offload
Regulatory innovation with new spectrum (e.g. 5G), white spaces, spectrum re-farming (e.g 2G/3G reuse)
TM
External Use 4
Operators Facing Multiple Challenges
Move from voice to data-centric usage
driving 18x increase in bandwidth
demand
User density in urban areas - by
2016, 60% of mobile traffic will be
generated in metro areas
Limited, higher frequency spectrum
with poor building penetration
Current deployments have large
footprints and high running costs
resulting in high OPEX
Current deployments lead to over
provisioning and poor load balancing
resulting in high CAPEX
Source: Ericsson (2012/2013)
Month
ly P
eta
Byr
es (
10
15B
)
2010 2011 2012 2013 2014 2015 2016 2017 2018
0
3,000
6,000
9,000
12,000
Data: mobile PCs, tablets and mobile routers
Data: mobile phones
Voice
15,000
TM
External Use 5
Small Cells Help
3G small cell volumes have peaked
LTE small cell deployments have started Freescale has more than 50 customer engagements
2014 will see volume LTE small cell shipments on FDD-LTE and initial TDD-LTE shipments
Trials and deployments in every region Freescale involved in NAM, LAMEX, EMEA & APAC
No longer coverage only but part of deployment strategies for capacity, QoS and in-building penetration
Source: Infonetics (2013)
TM
External Use 6
Pico and RRH
Dedicated Backhauls
Relay RF Backhaul
Core
Network
Femto
Internet Backhaul
Internet
Wi-Fi
Femto
Wi-Fi Offload
Metro/Pico RRH
Relay
Macro
Wireless Access Market Dynamics
Two major wireless infrastructure trends are dominant:
Rapid growth in small cells as Heterogeneous Networks (HetNet)
deployments leveraged to address coverage and capacity issues
Macro Cells driving for higher density and more centralization
TM
External Use 7
Heterogeneous Networks
Combination of different cell types (Femto, Pico, Metro, Macro)
With a large deployment of a network small cells
Offers solution to both end user and service provider
TM
External Use 8
Macro RAN Solution Trends
Higher density solutions
Doubling in throughputs/capacity and
greater
Centralized base stations with
large resource pools Layer 1, MAC scheduler, Layer 2,
transport and control
Cloud-RAN with virtualized,
pooled resources Specialized Layer 1, virtualized GPP for
higher level functions
RRH - Remote Radio Heads
CPRI Fiber
Connections
BBU Pool/Hotel
TM
External Use 9
High bandwidth optical transport
network: Adaptable for dynamic network load
Cloud-RAN Trend
Reduced OPEX: Fewer sites, easier maintenance
Baseband pooling/load balancing: Maximize equipment loading, reduced redundancy
Centralized baseband: Collaborative multipoint, inter-cell interference coordination
Baseband Pool
BB Pool BB Pool
PHY/MAC PHY/MAC PHY/MAC PHY/MAC
Optical Transport Network
x2+
CPRI switch
Real-time Cloud for centralized
baseband processing: Reduce BS sites, lower power
consumption and CAPEX/OPEX cost
High bandwidth optical transport
network: Adaptable for dynamic network load
Distributed RRU: Cooperative multi-point processing,
improve SE
RRU
RRU
RRU
RRU
RRU
RRU
RRU
Virtualized Control & Transport
Network load balancing. Server Pool
TM
External Use 10
Wireless Base Station Deployments and Types
Indoor Outdoor
Home Femtocell
SOHO Femtocell
Public Venue Picocell Enterprise Pico/Metrocell
Macrocell
Urban Area Metrocells
Cloud RAN
TM
External Use 11
Characteristics of Base Station Types
Cell Installed # Active
Users
Max Radius
(Km)
Bandwidth
(MHz)
Sectors MiMO
Femto Indoor 4 - 16 0.1 10 1 2x2
Pico Indoor/
Outdoor 32 - 100 0.3 10 - 20 1 2x2
Metro Outdoor 100 - 250 < 3 20 - 40 1-2
2x2
&
4x4
Macro/
CRAN/
Centralized base stations
Outdoor 250 - 1000
1000 - 10,000 < 20 60-80
3
>30
4x4
&
8x8
TM
External Use 12
Silicon Vendors Challenges
TM
External Use 13
Challenges for Semiconductor Solutions
Complex mix of IP: DSP, CPU,
Acceleration
High levels of integration:
Balanced resources for use case,
power consumption and efficiency
Complete solutions including
entire processing chain, hardware
and software
Multiple target price/performance
points driving need for scalable
architecture, software
compatibility/ease of use and reuse
Relentless focus on reduction in
total cost of ownership
TM
External Use 14
Silicon Vendor Software Requirements
Additional Services
Operation & Maintenance
LTE & WCDMA
Layer 1 PY
Operator/OEM
HW Independent
HW Dependent
Payload
RRC
Signali
ng/ST
CP PCDP RTP/GTP
UDP
RLC
MAC
L1 Control
IPv4/v6
IPSEC
Ethernet Control
Closely coupled software
and hardware
Hardware specific Layer 1,
performance optimized
Intelligent software partitioning
Balanced resources for use case
System integration and testing
End to end testing of complete stack
Intelligent design
Scalable architecture + software
compatibility and reuse
TM
External Use 15
Freescales Base Station Solutions Portfolio
TM
External Use 16
NEW
Femto
BSC9131/0 (45 nm) 8-16 users
Pico
BSC9132 (45 nm) 32-100 users
Metro
B3421 (28 nm) 100-256 users
Macro/CRAN
B4860 (28 nm) 1000+ users
Broad portfolio from femtocell to macrocell with on-time, on-specification release track record
Common architecture and software tool sets including CodeWarrior Development Suite and operating systems
Software and tools ecosystem catering for Tier-1 wireless OEMs and broad market customers
Rich third-party ecosystem for tools, operating system and application software
Freescales Complete SoC Portfolio for Wireless Base Stations Addressing All Market Trends
QorIQ Qonverge Base Station-on-Chip SoC Series
Advanced core and acceleration technologies, highly-balanced architectures for baseband processing integration, advanced process technologies
Freescale delivers industrys first complete SoC portfolio from home femto to multi-sector macro base stations
Software compatibility across different devices
Layer 1 and transport software stacks for small cell solutions to further expedite time to market
Adopted by industry-leading base station OEMs
TM
External Use 17
QorIQ Qonverge B4860 SoC for Macrocell
and Cloud-RAN
TM
External Use 18
New Level of Performance in Mobile
Wireless Infrastructure
Three 20 MHz sectors 8T/8R LTE in a single
SoC, supporting multiple standards and multimode
operation for macrocell base stations
Future proof, provides full support and scalability
for LTE-Advanced R.11 and HSPA R.10 standards
Complete baseband solution, integrates L1, L2,
control and transport baseband processing from
backhaul network to antenna Interface
Competitive system cost, helps OEMs to meet
operators demand for lower CAPEX/OPEX
Freescales R&D scale and unique ownership
of fundamental IP, combined with systems
knowledge drives competitive differentiation
World-class silicon, 28 nm process
execution and beyond
TM
External Use 19
QorIQ Qonverge B4860: Block Diagram and Benefits
Includes 64-bit e6500 dual-threaded cores, built on Power Architecture technology, offering industry-leading DMIP/MHz performance with AltiVec technology for dramatic L2 scheduling acceleration
Includes SC3900FP fixed/floating-point StarCore DSP cores providing 2x DSP performance compared to competitive offerings
20 GHz of programmable performance
Smart hardware acceleration for Layer 1, 2, control and transport allows for best in class performance, power and cost
Large-scale SoC integration allows for simpler programming models and easier load balancing
Rich I/O mix including backhaul and antenna interfaces provide flexibility, interoperability and reduces overall system cost
TM
External Use 20
Smart Acceleration for Optimal Performance
MAPLE-B
Innovative Layer-1
Acceleration Work distribution between cores
and accelerators
MAPLE-B Layer-1 Hardware Accelerators
Standards support LTE, WCDMA, WiMAX, GSM and
LTE-Advanced
Throughputs Very high throughputs enabling low
processing latencies
Programming Simple API
Multimode operations LTE, LTE-A, WCDMA
Advanced MiMO
Innovative MiMO Equalizer for
improved spectral efficiency and
reduce processing latencies compared
to conventional techniques
Streaming Direct streaming to/from antenna
without core intervention
Internal Embedded
Flows
Internal embedded flows for
PUSCH/PDSCH Uplink/Downlink
processing without core intervention
Completely offloads extensive Baseband algorithms
Security acceleration for offload of
Transport functionality
Integrated vector processing unit for
accelerating L2 scheduling DPAA Control/Transport Hardware Accelerators
FMAN
Frame Manager
>20 Gbps aggregate throughput,
Parse, Classify, Distribute
BMAN
Buffer Manager
Manages buffer pools for accelerators
and network interfaces
QMAN
Queue Manager
Simplified sharing of network
interfaces and hardware accelerators
by multiple cores
RMAN
Rapid IO Manager Seamless mapping sRIO to DPAA
SEC
Security
SNOW-3G, Kasumi, ZUC, IPSec,
AES, DES, MD5, SHA-1/2.
Saving CPU Cycles for higher value work
TM
External Use 21
Advanced Interfaces for Macro Deployments
sRIO & PCIe for multichip
connectivity
Advance I/O
Glueless Interfaces to Antenna
& Backhaul
2x 10 GbE XFI/KR Classify-Parse-Distribute
Timing Synchronization 4x 1 GbE/2.5 GbE
iEEE1588v2
8x CPRI v4.2 High-speed, industry-
standard Antenna
Interfaces at 9.8G
2x sRIO V2.1 2 controllers with 8 lanes
5G
PCIe v2.0 Quad lanes at 5G
IFC Modern NOR/NAND flash
controller & Legacy ASIC
connectivity
Other Peripherals SPI, I2C, USB, UART,
MMC, etc
Advanced
Debug/Tracing
JTAG, Aurora
(debug/trace)
Advanced Real-time
Tracing and Monitoring
Standard, High Speed
Antenna Interfaces
Backhaul networking,
delivering line-rate at
smallest packet sizes
TM
External Use 22
Traditional Approach
3-sector 20 MHz LTE Macrocell
with 5 major components
New Approach
3-sector 20 MHz LTE Macrocell
using Single SoC
Benefit of Intelligent Integration vs. Traditional Discrete
Solution
Multicore
MPU sRIO
Switch
Layer-1
Layer-2/3
Transport
& Control
DSP
CP
RI
I2C
UART
SPI
GE
sRIO
CPRI
Flas
h DDR2 DDR1
Flas
h
Antenna
10 Gbps
1Gbps
DDR
3 DDR3
Back Haul
Maint.
PHY
PHY Antenna
DSP
DSP
CPRI
B4860
POWER
4x Cost Reduction
3x Power Reduction
B4860 SoC
TM
External Use 23
Cloud-RAN with BBU Pooling and Control Pooling
Expense to deploy fiber creates a practical limit on number and
distance of connections to BBU pool
QorIQ Qonverge (B4860) processor addresses needs unique to
BBU
More efficient (silicon size and power) for L1 processing
compared to a GPP
Hardware-based accelerators for standard and repetitive
algorithms
Low latency and deterministic behavior with L1 and L2
processed on same device
10 GbE connections for BBU balancing within the pool
The base station-on-a-chip approach provides scalable solution
to suit varying capacity needs
10G backhaul connectivity is required
QorIQ (T4240) ideal for Cloud-RAN, data-centric servers
Lower power than competitors GPP
SoC mimics cloud compute system architecture
Strong processing assist technology for security,
compression and packet processing
Ideal for virtualization of core, RNC, gateway, etc.
Power Architecture technology leads wireless market
share
Ecosystem and virtualization solutions exist
Remote Radio Heads
CPRI Fiber
Connections
B4860-Based BBU Pool/Hotel
Mobile Core Infrastructure QorIQ T4240-based Servers
10Gb 10Gb
TM
External Use 24
Based on advanced Power Architecture, StarCore, CoreNet and MAPLE technologies
First SoC in 28 nm technology node for wireless infrastructure
Supports the most advanced mobile wireless standards
High-Density Baseband Solution
LTE-Advanced SOLUTION
60 MHz sector on a chip
1.8 Gbps Aggregated Throughput
LTE/LTE-A SOLUTION
Base station on a chip
3-sector, 20 MHz, 8T8R Ant.
1.4 Gbps Aggregated Throughput
LTE, LTE-A,
WCDMA, TD-
SCDMA, GSM
Simultaneous
Multi-mode
LTE+WCDMA
Supports
Macrocells
Supports
Multi-RAT:
WCDMA SOLUTION
Base station on a chip
up to 6 cells, 5 MHz, 2T2R ant.
318 Mbps Aggregated Throughput
QorIQ Qonverge B4860 SoC - Industry Leading
Throughputs/Capacity
TD-SCDMA SOLUTION
Base station on a chip
30 carriers with a single device
TM
External Use 25
QorIQ Qonverge B3421 Solution for
Metrocell and Large Enterprises
TM
External Use 26
QorIQ Qonverge B3421: Block Diagram and Benefits
CoreNet Cache Coherency Switch Fabric
8-Lanes 10G SERDES
Banked L2 Cache
StarCore
SC3900FP DSP
Banked L2 Cache
512KB
CoreNet
Platform
Cache
64-bit
DDR3/3L
Memory
Controlle
r
USB 2.0
IFC
USIM
6x SPI
SD/MMC
Security Monitor
GPIOs
Timers
4x I2C
2x P
CIe
5
G
2x C
PR
I 9
.8G
4x J
ES
D2
04
A/B
SA
TA
5x J
ES
D20
7
DF
E
Watchpoint
s
Perf.
Monitor
Trace
Aurora
T1 T2
Power
e6501
T1 T2
Power
e6501
StarCore
SC3900FP DSP
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-
Cache
32 KB
I-Cache
32 KB
D-
Cache
32 KB
I-Cache
MAPLE-B FMAN/DPAA
Turbo/
Viterbi
Dec.
FFT/
DFT
MiMO
Equ.
Turbo
Enc.
PDSCH
RISCs
PUSCH
MAPLE-B3
Security
Engine
Queu
e
Mgr.
Buffer
Mgr.
Parse, Classify,
Distribute
iEEE1588v2
2.5
G/1
G
1G
1G
2.5
G/1
G
Single Chip - Metrocell Base Station Standards support: LTE/LTE-A (Rel. 10/11)
Dual 20 MHz or 40 MHz w/ CA
LTE-Advanced Carrier Aggregation, CoMP, eICIC
Wi-Fi offload - 802.11ac/n hosting (IPSec-CAPWAP / DTLS)
Active users - 256 LTE
Aggregated throughputs -
LTE/LTE-A : 450 Mbps
Processing layers: Transport-PDCP-RLC/MAC-PHY-DFE
Architecture and Features Dual e6501 dual-thread cores, built on Power Architecture
technology, with AltiVec SIMD
Dual SC3900FP StarCore Fixed & Floating-point DSP
MAPLE-B3 Baseband Accelerator Platform
FEC - Turbo Decode/Encode, Viterbi
Fourier Transforms
MMSE MiMO equalization (IRC/SIC/PIC), Matrix Inversion
LTE PDSCH/PUSCH embedded data path flows
DFE (Digital Front End) CFR, DPD, DUC/DDC
DPAA enabled - Fman, Qman, Bman
Sec. engine - Kasumi, Snow-3G, ZUC, IPsec, DTLS
Trust architecture/secured boot
L3-cache/shared memory 512 KB
DDR3/3L Controller 64-bit up 1.866 GHz (w/ ECC)
CoreNet full cache coherent fabric
2G/3G/LTE sniffing
USB 2.0
8x 10GG SerDes lanes , combining:
4x Ethernet SGMII + MACSec + IEEE 1588
2x CPRI v4.2 @ 9.8G antenna interfaces
4x JESD204A/B 9.8G RFIC interfaces
2x PCIe @ 5G, x2 lanes
SATA
2x Aurora
5x JESD207 RFIC interfaces
IFC, 4x I2C, DUART, 6x SPI, eSDHC, USIM
Package - 33mmx33mm, FCPBGA, Pb-free
TM
External Use 27
Performance with Industry-Leading Cores
e6501 High-Performance CPU 64-bit Power Architecture core
with Altivec 128-bit SIMD engine Dual threads provide x1.9 times the
performance of a single e6501 thread
Hardware support for cache coherency
Tightly-coupled, low-latency clustered level-2 cache allowing full sharing or strict allocation
SC3900 High-Performance DSP *Step function in DSP performance
over competition Fixed/Floating-point support State-of-the-art support for high-
performance control code with branch prediction
MMU and address translation support
Tightly-coupled, low-latency clustered level-2 cache allowing full sharing or strict allocation
Hardware support for cache coherency
High-throughput Memory Accesses
BDTI
Highest
Speed Score
Texas
Instruments
C66x
1.5 GHz
Freescale SC3900
1.2 GHz
BDTIsimMark2000 BDTImark2000
Core Performance: CoreMark
2.4x
e500 core
processor
e6500
processor
(2 thread)
BDTi Speed Score
CoreNet Coherency Fabric CoreNet Coherency Fabric
CoreNet Interface 256-bit Rd & Wr Data Busses
DSP Core Cluster CPU Core Cluster
High Speed
Baseband
Accelerators
Interface
SC3900
FVP Core SC3900
FVP Core
32K 32K 32K 32K
16-way Shared L2 Cache 16-way Shared L2 Cache,
PM
C
PM
C
AltiVec AltiVec
32K 32K 32K 32K
T T T T
e6501 e6501
CoreNet Interface 256-bit Rd & Wr Data Busses
* In benchmarking performed by independent analysis firm BDTI, the 1.2
GHz SC3900 achieved the highest fixed-point BDTIsimMark2000 score
ever recorded. See www.BDTI.com for details. BDTI has not evaluated
the floating-point performance of the SC3900.
http://www.bdti.com/
TM
External Use 28
CoreNet Cache Coherency Switch Fabric
8-Lanes 10G SERDES
Banked L2 Cache
StarCore
SC3900FP DSP
Banked L2 Cache
512KB
CoreNet
Platform
Cache
64-bit
DDR3/3L
Memory
Controller
USB 2.0
IFC
USIM
6x SPI
SD/MMC
Security Monitor
GPIOs
Timers
4x I2C
2x P
CIe
5
G
2x C
PR
I 9
.8G
4x J
ES
D20
4A
/B
SA
TA
5x J
ES
D20
7
2.5
G/1
G
1G
1G
2.5
G/1
G
Parse, Classify,
Distribute
iEEE1588v2
Security
Engine
Queue
Mgr.
Buffer
Mgr.
Turbo
Dec.
FFT/
DFT
MiMO
EQ.
Turbo
Enc.
PUSCH
RISCs
DF
E
Watchpoints
Perf.
Monitor
Trace
Aurora
T1 T2
Power
e6501
T1 T2
Power
e6501
StarCore
SC3900FP DSP
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
MAPLE-B FMAN
PUSCH
Security Monitor
USB 2.0
IFC
2x DUART
4x I2C
eSPI
GPIOs
512KB
CoreNet
Platform
Cache
64-bit
DDR3
Memory
Controller
SD/MMC
Smart Acceleration for Optimal Performance Integrated SIMD vector processing unit
for Layer 2 scheduler acceleration IP packet acceleration Layer 2 Hardware Accelerators
FMAN
Frame Manager
7 Gbps aggregate throughput, parse,
classify, distribute at smallest packet
sizes
BMAN
Buffer Manager
Manages buffer pools for cores,
accelerators and network interfaces
QMAN
Queue Manager
Simplified sharing of network
interfaces and hardware accelerators
by multiple cores
Security algorithms SNOW-3G, Kasumi, ZUC, AES, DES,
MD5, SHA-1/2.
Security Protocols Autonomous IPsec, DTLS/CAPWAP
Saving CPU cycles for higher value work
Sharing data between
cores, accelerators, I/Os CFR, DPD, DUC/DDC, IQ
acceleration
IPSec, DTLS, Kasumi,
ZUC, SNOW-3G
L1 Baseband acceleration
Layer 1 & DFE Hardware Accelerators
Standards support LTE, LTE-Advanced
Throughputs Very high throughputs enabling low
processing latencies
Programming Simple API under SDOS
Advanced MiMO
Innovative MMSE based MiMO
equalizer for improved spectral
efficiency and reduce processing
latencies compared to conventional
techniques
Streaming Direct streaming to/from antenna
interfaces, without core intervention
Internal Embedded
Flows
Internal embedded processing for
PUSCH/PDSCH uplink/downlink
processing without core intervention
DFE Programmable to adapt for different
choices of PA and for OEMs to
leverage their IP
Completely offloads extensive baseband & linearization
algorithms
TM
External Use 29
Metrocell Concurrent LTE with Wi-Fi and Content Caching
FDD-LTE
Dual cell 20 MHz 2T2R, or
Single cell 20 MHz 4T4R
Wi-Fi offloading
802.11ac Wi-Fi chipset
Local content caching -
saving backhaul traffic
Third party RFIC and Wi-Fi chipset
B3421
LTE, LTE-A
SGMII
SGMII
PCIe
FLASH
O&M
SATA SSD
JESD204B
JESD204B
PMIC Power
Supply
DDR
SGMII
WiFi
3x3
GPS
RFIC
2T/2R
RFIC
2T/2R
UART
LTE/WiFi
Backhaul
SGMII
http://www.google.co.il/url?sa=i&rct=j&q=&esrc=s&frm=1&source=images&cd=&cad=rja&docid=Br_gJYPhs73XxM&tbnid=1KFWt7wWUu1t7M:&ved=0CAUQjRw&url=http://www.compositiontoday.com/blog/default.asp?archive=3&ei=nfP5Uoa2NLHG7AbkooGwDw&bvm=bv.61190604,d.ZGU&psig=AFQjCNHaCFJk7ECAwYPmuFi5tau0UJ3uLA&ust=1392198933891685
TM
External Use 30
QorIQ Qonverge B3421 SoC 2x 20 MHz
Software Partitioning
Freescale SW
Partners SW
Linux SMP, RT Patch, Core Affinity
e6501 dual-
thread core
SC3900FP core +
MAPLE-B3 LTE L1-L2 FAPI
UL Processing
(Estimations,
PUCCH, SRS,
RACH)
PHY Controller
Sec 0
DL Control Ch
Infra Services
SDOS
SC3900FP core +
MAPLE-B3 LTE L1-L2 FAPI
UL Processing
(Estimations,
PUCCH, SRS,
RACH)
PHY Controller
Sec 1
DL Control Ch
Infra Services
DL, UL
Scheduler
Infra
services
DL+UL RLC
DL+UL MAC
LTE L1-L2 FAPI
e6501 dual-
thread core
DDR3
DDR Memory
JESD
204B/
207
Ethernet
1G/2.5G
IFC
FLASH
Ethernet
1G
GPIO
I2C/
eSPI
Clocking POR Config. Power Circuit
UART /
USB GPS
Receiver
Ethernet
1G/2.5G
Backhaul Chaining
Ethernet
/ PCIe
WiFi
Chipset
Optional
Freescale HW
LTE
RF PA
System
OAM
Backhaul
RFIC
JESD
204B/
207
LTE
RF PA
System RFIC
Infra
services
PDCP
RRC
OAM eGTP-U
UDP
S1-AP X2-AP SCTP
IP (IPsec)
Ethernet
(Backhaul
QoS)
ROHC
IKEv2 RRM
Ciphering
DFE
TM
External Use 31
QorIQ Qonverge BSC9132 Picocell Solution
TM
External Use 32
QorIQ Qonverge: BSC9132 Block Diagram
Multicore Fabric
4-Lanes SERDES
512KB Shared L2 Cache
StarCore
SC3850 DSP
512KB L2 Cache
USB 2.0
IFC
USIM
1x SPI
SD/MMC
GPIOs
Timers
2x I2C
2x P
CIe
5G
2x C
PR
I 6
.1G
4x J
ES
D20
7
Power
e500mc
Power
e500mc
StarCore
SC3850 DSP
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
Security
Engine
512KB L2 Cache
32-bit
DDR3
Memory
Controller
32-bit
DDR3
Memory
Controller
2x S
GM
II +
15
88
v2
MAPLE-B2P
LTE WCDMA
32 KB
Shared
Memory
TDM
Single Chip Picocell Base Station
Standards support: LTE (Rel. 8/9), WCDMA (Rel.
99/7/8/9), 802.16e
Bandwidth: 20 MHz or 2x 10 MHz
100 LTE or 32 HSPA active users
Multimode support
LTE throughputs: 150 Mbps DL / 75 Mbps UL with 2x4 ant.
HSPA+ throughputs: 84 MbpsDL /23 Mbps UL
WiMAX 802.16e: up to 50 Mbps DL/13 Mbps UL
2G/3G Sniffing and GPS support
Secured boot and trust architecture support
Proc. layers: PHY-MAC-RLC-PDCP-Transport
Architecture
Dual e500mc cores, built on Power Architecture
technology (1 GHz/1.2 GHz)
Dual StarCore SC3850 DSPs (1 GHz/1.2 GHz)
MAPLE-B2P Baseband Accelerators Platform
Security engine - IPsec, Kasumi, Snow-3G
Dual DDR3/3L, 32-bit,1.333 GHz, w/ ECC
IEEE 1588 v2, NTP
USB 2.0
4 SerDes lanes, combining:
2x Ethernet 1G SGMII
2x CPRI v4.1 @ 6.144G antenna interface
1x PCIe @ 5G x2 lanes
Quad JESD207 RF transceiver interfaces
NAND/NOR Flash controller, eSDHC, USIM
I2C, eSPI
Package FCPBGA, 23mmx23mm, 0.8mm
TM
External Use 33
QorIQ Qonverge BSC9131 Femtocell
Solution
TM
External Use 34
QorIQ Qonverge: BSC9131 Block Diagram
Multicore Fabric
USB 2.0
IFC
USIM
1x SPI
SD/MMC
GPIOs
TDM
2x I2C
Power
e500mc
256KB L2 Cache
StarCore
SC3850 DSP
512KB L2 Cache
Power
e500mc
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32-bit DDR3
Memory
Controller
3x J
ES
D207/M
AX
PH
Y
Security
Engine
2x
RG
MII +
1588v2
MAPLE-B2F
LTE WCDMA
Timers
Single Chip Femtocell Base Station
SMB Femtocell up to 16 users BSC9131
Multimode
SoC Architecture
e500 core, built on Power Architecture technology (800 Mhz 1 GHz)
StarCore SC3850 core subsystem (800 MHz 1 GHz)
MAPLE-B2F Baseband Accelerators Platform
eTVPE Turbo/Viterbi Decoder
DEPE Turbo Encoder w/ rate match
CRCPE CRC check & insertion
FTPE FFT/DFT
PDPE, PUPE
UMTS Chiprate
Security engine IPsec, Kasumi, Snow-3G
Secured boot
Single DDR3 Controller 32-bit 800 MHz
IEEE 1588 v2, NTP
USB 2.0
2x Ethernet RGMII and IEEE1588v2
3x JESD207/MAXPHY RF transceiver interfaces
Multi-standard Architecture
Standards support: LTE (Rel. 9), WCDMA (Rel. 99/7/8)
LTE 20 MHz single sector -10 0Mbps / DL 50 Mbps UL
HSPA 5 MHz single sector 42 Mbps / DL 11 Mbps UL
Processing Layers: PHY-MAC-RLC-PDCP-NTP
Enabled with 2x2 MiMO
2G/3G sniffing and GPS support
TM
External Use 35
Freescale Provides Complete Portfolio for
HetNet
TM
External Use 36
Freescale Solutions for HetNet
Cloud-RAN Baseband processing centralization, reduced
number of cell sites, load balancing
Remote Radio Heads
CPRI Fiber
Links
GigE
Links
Picocells
Femtocells
Macrocells
Metrocells
Flexible Architecture Supports scalable solutions for all cell types
HetNet enabled solution for best user experience
SoCPeerless levels of integration
provide best-in-class cost and power
VortiQa software solutionse2e
solutions focus for rapid deployment
Solution is evolving to:
HetNets underlay with small cells
Low-cost, SoC-based software solution with SON
capability to effectively deploy and manage these
networks
Multi RAT solutions, integration of 3G/4G with WiFi
TM
External Use 37
Software Solutions from Freescale and
Partners
TM
External Use 38
Freescale Small Cell Software Solution
Comprehensive, commercial grade
L1, L2, L3 and Transport Software
solution for small cells integrated
and tested
LTE-FDD/TDD and LTE-Advanced L1
software stack (licensed by Freescale)
L2/L3 software for LTE-FDD/TDD and
LTE-Advanced (licensed by partners)
Transport software, including IPsec,
QoS backhaul, etc. (licensed by
Freescale and partners)
Development tools and operating
system software (available through
Freescale and partners)
RRC
L1 Control
MAC
RLC
PDCP
Ethernet Control
IPSEC
IPv4/v6
UDP
GTP Signalin
g
/ STCP
Payload
Operation & Maintenance
LTE & LTE-A
Layer-1 PHY
Additional services
SD
OS
OS
L
inu
x O
S
Freescale OEM/Partners SP/OEM
TM
External Use 39
Hardware Abstract Layer
Hardware & OS Abstract Layer
Freescale - LTE/LTE-A Software Libraries for Macrocell
SC3900 e6500
SDOS
MA
PL
E
LTE/LTE-A Library
LTE L2-L1 API
Linux Kernel Space
Standard, FSL API
Linux User Space
Std
Libs
FMAN
Network
Stacks
QoS
pthreads
Drivers
Eth-Net
Custom
er Libs
Sockets
ASFIPSEC
File
Systems
Rman
Driver
SRIO
Driver
Qman
Driver
USDPA
A LibSEC Lib
Bman
Driver
Std Libs
Applications L2 L3
Std
Apps
Customer
Apps
Optimized and compliance tested reference Layer-1 software
components library for FDD & TDD LTE/LTE-A processing chains
DP
AA
DL Ctrl
PDSCH
PUSCH PRACH
PUCCH
SRS MBSFN
L 1 FWK
ANT IF L 2 - L 1 IF Debug
RT Sch
TM
External Use 40
Comprehensive IDEs that provide
a visual, automated framework,
with optimizing compilers to
accelerate development of
complex applications
Leading providers for LTE
commercial Layer 2/3 and
Layer 1 software stacks as
well as system integration
services
Leading providers of
commercial operating systems,
middleware and development
tools
Operating systems with
optimized drivers for CPU, DSP,
accelerators, interfaces
Freescale provides complete
LTE & LTE-A software stacks
for Layer-1 PHY and
Transport
RF boards and test equipment
hardware partners
Platform developed by
Freescale, integrated with RF,
to enable end-to-end system,
introduced with silicon samples
Modular, cost-effective
development platform pertinent
to software and system
development
Reference
Design
Linux SDK
SmartDSP-OS
Complete Solution, Rich Ecosystem
http://www.google.co.il/url?sa=i&rct=j&q=&esrc=s&frm=1&source=images&cd=&cad=rja&docid=djH_N86yaWwv2M&tbnid=W8fX3Mwr5tSn5M:&ved=0CAUQjRw&url=http://www.satellite-evolution.com/group/site/?p=11779&ei=m-T5Uo3jLaiN7AaC2IDwDw&bvm=bv.61190604,d.ZGU&psig=AFQjCNHvPjG8jIyg0bqGpsyP90PnEc5OzA&ust=1392195069020039http://www.google.co.il/url?sa=i&rct=j&q=&esrc=s&frm=1&source=images&cd=&cad=rja&docid=9PEYSQy89icXIM&tbnid=Z2VuBF1A2KiNiM:&ved=0CAUQjRw&url=http://www.tmcnet.com/webinar/unicom/unicom-06-19-13.htm&ei=u-T5UvazH6qJ7AbZwoAQ&bvm=bv.61190604,d.ZGU&psig=AFQjCNHvPjG8jIyg0bqGpsyP90PnEc5OzA&ust=1392195069020039
TM
External Use 41
Introducing The
QorIQ LS2 Family
Breakthrough,
software-defined
approach to advance
the worlds new
virtualized networks
New, high-performance architecture built with ease-of-use in mind Groundbreaking, flexible architecture that abstracts hardware complexity and
enables customers to focus their resources on innovation at the application level
Optimized for software-defined networking applications Balanced integration of CPU performance with network I/O and C-programmable
datapath acceleration that is right-sized (power/performance/cost) to deliver
advanced SoC technology for the SDN era
Extending the industrys broadest portfolio of 64-bit multicore SoCs Built on the ARM Cortex-A57 architecture with integrated L2 switch enabling
interconnect and peripherals to provide a complete system-on-chip solution
TM
External Use 42
QorIQ LS2 Family Key Features
Unprecedented performance and
ease of use for smarter, more
capable networks
High performance cores with leading
interconnect and memory bandwidth
8x ARM Cortex-A57 cores, 2.0GHz, 4MB L2
cache, w Neon SIMD
1MB L3 platform cache w/ECC
2x 64b DDR4 up to 2.4GT/s
A high performance datapath designed
with software developers in mind
New datapath hardware and abstracted
acceleration that is called via standard Linux
objects
40 Gbps Packet processing performance with
20Gbps acceleration (crypto, Pattern
Match/RegEx, Data Compression)
Management complex provides all
init/setup/teardown tasks
Leading network I/O integration
8x1/10GbE + 8x1G, MACSec on up to 4x 1/10GbE
Integrated L2 switching capability for cost savings
4 PCIe Gen3 controllers, 1 with SR-IOV support
2 x SATA 3.0, 2 x USB 3.0 with PHY
SDN/NFV
Switching
Data
Center
Wireless
Access
TM
External Use 43
See the LS2 Family First in the Tech Lab!
4 new demos built on QorIQ LS2 processors:
Performance Analysis Made Easy
Leave the Packet Processing To Us
Combining Ease of Use with Performance
Tools for Every Step of Your Design
TM
2014 Freescale Semiconductor, Inc. | External Use
www.Freescale.com
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