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Analog Electronic Circuits
Lesson 9 JFET Amplifier
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Outline
JFET Amplifier Biasing Conditions
Self Biased JFET
JFET Load Line
Amplifier Biasing
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JFET Biasing Conditions
VGS
is Reverse Biased!
JFET used in Saturation for amplifier
Therefore VDS > VP
Commonly IDS
set to approximately 0.5IDSS
When VGS
= VP
/3.4 then IDS
= 0.5IDSS
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JFET Fixed Bias
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JFET Fixed Bias
RG
sets input impedance - rgs
very high
Separate negative supply on Gate
Impractical in most cases
Used at times
Common at low VDD
supply voltages
Self Biased config provides -ve VGS
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Self Biased Configuration
Add resistor between Source and Ground
VDD
must be higher than Fixed Bias
ID through RS elevates VS above GroundV
Gheld at Gnd through R
G
Sets up a -ive VGS
Thus VGS
= - ID
x RS
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Self Biased Configuration
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JFET Load Line Self Bias
Provides a graphical method to visualizebiasing characteristics and Q point
Transfer curve at saturation is quadratic
JFET operation predictable given VGS(OFF)
and IDSS
(datasheet)
Drawing Load-Line identifies Q point
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JFET Load Line Self Bias
ID
VGS
ID= I
DSS(1
VGS
VP
)2
VGS(OFF)
VGS(OFF)
2
IDSS
IDSS
2
IDSS
4
VGS(OFF)
3.4
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JFET Load Line Self Bias
ID
VGS
IDSS
VGS
= IDR
D
ID
Q point IDQ
VGSQ
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Load Line Changing RS
ID
VGS
IDSS
VGS
= IDR
D2
ID
IDQ
VGSQ
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Load Line Changing RS
ID
VGS
IDSS
VGS
= IDR
D3
ID
IDQ
VGSQ
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Amplifier Biasing
Quadratic curve tricky biasing, take yourtime with the math...
Useful shortcuts:
Solving: use substitution and quadratic formula
Designing: IDS
= 0.5IDSS
when VGS
= VP
/3.4
Amplifier in saturation Ensure VDS
> VP
Remember RS
sets Q point for Self Bias!
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Amplifier Biasing
ID = IDSS(1 VGS
VP)2
VGS = VP(1 ID
IDSS)
VGS = IDR S
substitute ID = IDSS(1 IDRS
VP)2
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Amplifier Biasing
ID = IDSS(1 VGS
VP)2
VGS = IDR S
ID =bb24ac
2awhere 0 = aID
2 + bID + c
substitute ID = IDSS(1 IDRS
VP)2
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Amplifier Biasing
ID = IDSS(1 VGS
VP)2
VGS = IDR S
substitute ID = IDSS(1 ID RSVP)
2
= IDSS(1 IDR SVP)(1 ID RSVP
)
therefore ID = IDSS 2 IDSS RS
VP
ID + IDSS(RS
VP
)2
ID2
and 0 = IDSS(RS
VP)2
ID2 (
2 IDSS RS
VP1)ID + IDSS
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Amplifier Biasing
ID = IDSS(1 VGS
VP)2
VGS = IDR S
substitute ID = IDSS(1 ID RSVP )
2
= IDSS(1 IDR SVP )(1 ID RSVP )
therefore ID = IDSS 2 IDSS RS
VP
ID + IDSS(RS
VP
)2
ID2
and 0 = IDSS(RS
VP)2
ID2 (
2 IDSS RS
VP1)ID + IDSS
a b c
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Amplifier Biasing
ID = IDSS(1 VGS
VP)2
VGS = VP(1 ID
IDSS)
VGS = IDR S
KVL : 0 = VDDIDRDVDSIDRS
therefore : VDS = VDDID(RD+RS)saturation... ensure that VDS > VP
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Credits and Attributions
Reference Texts:
Boylestad, R.L., Nashelsky, L., (2009). Electronic Devicesand Circuit Theory (10th ed.)
Floyd, T.L., (2012). Electronic Devices: conventional currentversion (9th ed.)
Images:
All images as individually attributed courtesy of
FreeDigitalPhotos.net user(s); anankkml listed in order ofaperance.
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Copyright (c) 2012 by Mladen Hruska. This work is made availableunder the terms of the Creative Commons Attribution-ShareAlike 2.5Canada license
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