8/13/2019 Session 1 Sig Rev
1/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Session 1 : Introduction to
Digital Signal Processing
Session delivered by:
Chandan N.
8/13/2019 Session 1 Sig Rev
2/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Session Objective
To understand the basic concept of signals and digital signal
processing
To review on the basic architectures
To understand the concept of sampling
To understand the effects of under sampling and over sampling
2
8/13/2019 Session 1 Sig Rev
3/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Session Topics
DSP Architecture evolution Types of Signals
Discrete time Systems
Sampling
3
8/13/2019 Session 1 Sig Rev
4/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Three Markets Three Chips
General purpose
wide range of applications
performance matters
Microcontroller
one small app runs forever
possible real-time constraints
Digital Signal Processing
complicated processing of signals real-time constraints
4
8/13/2019 Session 1 Sig Rev
5/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Hardware Differences
Microprocessor - processor datapath, register file, ALU,caches
Microcontroller microprocessor plus other peripherals, on-
chip memory
Digital Signal Processor microprocessor with ALUsoptimized for digital signal processing (MAC)
5
8/13/2019 Session 1 Sig Rev
6/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Introduction to DSP Processors
Hardware
Algorithms
Image processing
Digital systems
Logical design
Control systems
Digital signal processing
DSP VLSI
Analog circuits
6
8/13/2019 Session 1 Sig Rev
7/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Introduction
Digital Signal Processing: application of mathematicaloperations to digitally represented signals
Signals represented digitally as sequences of samples
Digital signals obtained from physical signals via tranducers
(e.g., microphones) and analog-to-digital converters (ADC) Digital signals converted back to physical signals via digital-to-
analog converters (DAC)
Digital Signal Processor (DSP):
electronic system that processes digital signals
7
8/13/2019 Session 1 Sig Rev
8/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Definitions
In DSP, digital signals often represent signals from physicalsystems, which are in relation to physical time
DSP systems are related to physical time
Systems where the correctness of the system behavior depends
not only an the logical results of the computations, but also onthe physical instant at which these results are produced, are real-
time systems
Real-time DSP system is a DSP system, where signal mapping
is performed in real-time and the real-time constraint is
determined by the repetition period of the algorithm
8
8/13/2019 Session 1 Sig Rev
9/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
What is DSP
Changing or analyzing information that is measured as discretesequences of numbers
The representation, transformation, and manipulation of signals
and the information they contain
9
8/13/2019 Session 1 Sig Rev
10/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Unique Features of DSP
Signals come from the real world Need to react in real time
Need to measure signals and convert them to digital
numbers
Signals are discrete Information in between discrete samples is lost
10
8/13/2019 Session 1 Sig Rev
11/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Processing Real Signals
Most of the signals in our environment are analog such as
sound, temperature and light To processes these signals with a computer, we must:
1. Convert the analog signals into electrical signals, e.g., usinga transducer such as a microphone to convert sound into
electrical signal2. Digitize these signals, or convert them from analog todigital, using an ADC (Analog to Digital Converter)
In digital form, signal can be manipulated
Processed signal may need to be converted back to an analogsignal before being passed to an actuator (e.g., a loudspeaker)
Digital to analog conversion can be done by a DAC (Digitalto Analog Converter)
11
8/13/2019 Session 1 Sig Rev
12/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Typical DSP Components
Input lowpass filter (anti-aliasing filter) Analog to digital converter (ADC)
Digital computer or digital signal processor
Digital to analog converter (DAC)
Output lowpass filter (anti-imaging filter)
12
8/13/2019 Session 1 Sig Rev
13/68
PEMP
8/13/2019 Session 1 Sig Rev
14/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Advantage of DSP Versatility
Digital systems can be reprogrammed for other applications Digital systems can be ported to different hardware
Repeatability and stability
Digital systems can be easily duplicated
Digital systems do not depend on strict component tolerances
Digital system responses do not drift with temperature
Simplicity
Some things can be done more easily digitally than with analog systems
(e.g., linear phase filters)
Security can be introduced by encryption/scrambling Digital signals easily stored on magnetic media without deterioration
14
PEMP
8/13/2019 Session 1 Sig Rev
15/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Disadvantages of DSP
DSP techniques are limited to signals with relatively low bandwidths
The point at which DSP becomes too expensive will depend on theapplication and the current state of conversion and digital processingtechnology
Currently DSP systems are used for signals up to video bandwidths(about 10 MHz)
The cost of high-speed ADCs and DACs and the amount of digitalcircuitry required to implement very high-speed designs (> 100 MHz)makes them impractical for many applications
As conversion and digital technology improve, the bandwidths forwhich DSP is economical continue to increase
The need for an ADC and DAC makes DSP not economical for simpleapplications (e.g., a simple filter)
Higher power consumption and size of a DSP implementation can makeit unsuitable for simple very low-power or small size applications
15
PEMP
8/13/2019 Session 1 Sig Rev
16/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Applications of DSP
Noise Filtering
Coding 64 kbps-narrowband, 64 kbps-wideband
32 kbps-narrowband, 32 kbps-wideband
16 kbps-narrowband, 16 kbps-wideband
Compression
64 kbpsMu-Law PCM 32 kbps CCITT G.721 ADPCM
16 kbps LD-CELP
8 kbps CELP
4.8 kbps CELP for STU-3
2.4 kbps LPC-10E for STU-3 Recognition
Synthesis
Sampling Rate changes
16
PEMP
8/13/2019 Session 1 Sig Rev
17/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Applications of DSP Image Processing: enhancement, coding, compression, pattern recognition
Multimedia: transmission of sound, still images, motion pictures, digital TV,video conferencing
Music: recording, playback and manipulation (mixing, special effects),
synthesis
Communication: encoding and decoding of digital communication signals,
detection, equalization, filtering, direction finding, echo cancellation Radar and Sonar: target detection, position and velocity estimation, tracking
Biomedical Engineering: analysis of biomedical signals, diagnosis, patient
monitoring, preventive health care, artificial organs
17
PEMP
8/13/2019 Session 1 Sig Rev
18/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Real Time DSP System
18
PEMP
8/13/2019 Session 1 Sig Rev
19/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Real Time DSP System
19
PEMP
8/13/2019 Session 1 Sig Rev
20/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Why Go Digital?
Digital signal processing techniques are now so powerful that
sometimes it is extremely difficult, if not impossible, for analoguesignal processing to achieve similar performance.
Examples:
FIR filter with linear phase.
Adaptive filters.
Analogue signal processing is achieved by using analogue componentssuch as:
Resistors.
Capacitors.
Inductors.
The inherent tolerances associated with these components,temperature, voltage changes and mechanical vibrations candramatically affect the effectiveness of the analogue circuitry
20
PEMP
8/13/2019 Session 1 Sig Rev
21/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Why Go Digital?
With DSP it is easy to: Change applications.
Correct applications.
Update applications.
Additionally DSP reduces:
Noise susceptibility.
Chip count.
Development time.
Cost.
Power consumption.
21
PEMP
8/13/2019 Session 1 Sig Rev
22/68
PEMP
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Why NOT Go Digital?
High frequency signals cannot be processed digitallybecause of two reasons:
Analog to Digital Converters, ADC cannot work fast
enough.
The application can be too complex to be performedin Real-time
22
PEMP
8/13/2019 Session 1 Sig Rev
23/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Use a DSP processor when the following are required: Cost saving.
Smaller size.
Low power consumption.
Processing of many high frequency signals in real-time.
Use a GPP processor when the following are required:
Large memory.
Advanced operating systems.
Need For DSP Processors
25
PEMP
8/13/2019 Session 1 Sig Rev
24/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Typical DSP Algorithms
Algorithm Equation
Finite Impulse Response Filter =
=M
k
k knxany
0
)()(
Infinite Impulse Response Filter ==
+=N
k
k
M
k
k knybknxany
10
)()()(
Convolution =
=N
k
knhkxny
0
)()()(
Discrete Fourier Transform
=
=1
0
])/2(exp[)()(
N
n
nkNjnxkX
Discrete Cosine Transform ( ) ( )
=
+=
1
0
122
cos).().(
N
x
xuN
xfucuF
The Sum of Products (SOP) is the key element in most
DSP algorithms:
26
PEMP
8/13/2019 Session 1 Sig Rev
25/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Hardware vs. Microcode Multiplication
DSP processors are optimised to perform multiplication andaddition operations.
Multiplication and addition are done in hardware and in one
cycle.
Example: 4-bit multiply (unsigned).
1011x 1110
1011x 1110
Hardware Mi cr ocode
10011010 00001011.
1011. .
1011. . .
10011010
Cycl e 1Cycl e 2
Cycl e 3Cycl e 4
Cycl e 5
27
PEMP
8/13/2019 Session 1 Sig Rev
26/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Floating vs. Fixed Point processors
Applications which require: High precision.
Wide dynamic range.
High signal-to-noise ratio.
Ease of use.Need a floating point processor.
Drawback of floating point processors:
Higher power consumption.
Can be higher cost. Can be slower than fixed-point counterparts and larger
in size.
28
PEMP
8/13/2019 Session 1 Sig Rev
27/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Floating vs. Fixed Point Processors
It is the application that dictates which device and platform touse in order to achieve optimum performance at a low cost.
For educational purposes, use the floating-point device
(C6711) as it can support both fixed and floating point
operations.
29
PEMP
8/13/2019 Session 1 Sig Rev
28/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
General Purpose DSP vs. DSP in ASIC
Application Specific Integrated Circuits (ASICs) are
semiconductors designed for dedicated functions.
The advantages and disadvantages of using ASICs are
listed below:
Advantages
High throughput
Lower silicon area
Lower power consumption Improved reliability
Reduction in system noise
Low overall system cost
Disadvantages
High investment cost
Less flexibility
Long time from design tomarket
30
PEMP
8/13/2019 Session 1 Sig Rev
29/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Texas Instruments TMS320 Family
Different families and sub-families exist tosupport different markets.
Lowest CostControl Systems
Motor Control
Storage
Digital Ctrl Systems
C2000 C5000
EfficiencyBest MIPS per
Watt / Dollar / Size
Wireless phones
Internet audio players
Digital still cameras
Modems
Telephony
VoIP
C6000
Multi Channel and Multi
Function App's
Comm Infrastructure Wireless Base-stations
DSL
Imaging
Multi-media Servers
Video
Performance &Best Ease-of-Use
31
PEMP
8/13/2019 Session 1 Sig Rev
30/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Architectures Evolution
Objective: fast computation of Z = X * Y
(one instruction and two operands)
Methods:
Von NeumannHarvard Architecture
Super Harvard Architecture
Modified Harvard Architecture
Cost Speed
32
PEMP
8/13/2019 Session 1 Sig Rev
31/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Architectures Evolution:
Von Neumann
Data and instructions are stored in the same single bank.
One access to memory (1 piece of data or instruction) is
performed during each instruction cycle.
33
PEMP
8/13/2019 Session 1 Sig Rev
32/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Architectures Evolution:
Harvard Architecture
Data and instructions are stored in two different memory
banks. One access to each of the banks is performed
simultaneously during each instruction cycle.
34
PEMP
8/13/2019 Session 1 Sig Rev
33/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Architectures Evolution:Super Harvard Architecture
Data can be stored in the instructions block also. One access toeach of the banks is performed simultaneously to fetch
instruction+data or data+data. An instruction cache mechanism
is involved in the second option.
35
PEMP
8/13/2019 Session 1 Sig Rev
34/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Architectures Evolution:Modified Harvard Architecture
One single-ported instruction block and one dual-ported data block
enable single-cycle Access of 2 Pieces of Data and 1 Instruction.
36
PEMP
8/13/2019 Session 1 Sig Rev
35/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Speed
MIPS million instructions per second
MOPS million (mathematical) operation per second
MFLOPS million floating-point operation per second
MMACS million MACs per second
37
PEMP
8/13/2019 Session 1 Sig Rev
36/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Development Flow
Simulation target (without a physical processor) enables you tobuild, edit, and debug your program, even before a processor is
manufactured. Your PC connects to the EZ-KIT Lite evaluation system via acable, enabling you to monitor processor behavior.
JTAG emulator enables application software to be downloadedand debugged from within VisualDSP++ or CCS
38
PEMP
8/13/2019 Session 1 Sig Rev
37/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
DSP Development Flow
Mathematical algorithm
MATLAB code for Simulation/Validation
RT format MATLAB code + Validation with the former stage
DSP Simulation + Validation with the former stage
DSP Evaluation + Validation with the former stage DSP Emulation + Validation with the former stage
39
PEMP
8/13/2019 Session 1 Sig Rev
38/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
C or Assembler
Assembler
Pros: Maximal efficiencyCons: Required core architecture knowledge Complicated for reading Complicated for writing Long development time Expensive development HR
CPros: Core architecture knowledge is not
required Easy for reading Easy for writing Short development time Cheap development HR Maximal efficiency
Cons: Limited efficiency (depends on the
optimizer)
40
PEMP
S 2 21
8/13/2019 Session 1 Sig Rev
39/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
C or Assembler
Intensive code parts Assembler
Bureaucracy C/C++
Algorithms analysis by assembler expert.
41
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
40/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
C and C++ Language Programming
Motivation: Portability, maintainability, time to market Full ANSI Language
plus: // C++ style comments
other general programmability extensions
Full-featured library full standard math function support
additional DSP functions
basic I/O: printf, simple file I/O
Extensions tailored for DSP
Highly effective optimizer
Fully integrated into programming environment
edit, build support runtime system in place
source-language debugging
42
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
41/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Types of Signals
Analog Signals (Continuous-Time Signals): Signals that are
continuous in both the dependant and independent variable(e.g., amplitude and time). Most environmental signals are
continuous-time signals.
Discrete Sequences (Discrete-Time Signals): Signals that are
continuous in the dependant variable (e.g., amplitude) butdiscrete in the independent variable (e.g., time). They are
typically associated with sampling of continuous-time signals.
Digital Signals: Signals that are discrete in both the dependant
and independent variable (e.g., amplitude and time) are digitalsignals. These are created by quantizing and sampling
continuous-time signals or as data signals (e.g., stock market
price fluctuations).
43
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
42/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Types of Signal
44
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
43/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Discrete Time Signals:Time-Domain Representation
Signals represented as sequences of numbers, called samples
Sample value of a typical signal or sequence denoted asx[n] with nbeing
an integer in the range
x[n] defined only for integer values of nand undefined for non-integer
values of n
Discrete-time signal represented by {x[n]}
n
45
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
44/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Discrete-time signal may also be written as a
sequence of numbers inside braces:
In the above,
The arrow is placed under the sample at time
index n= 0
},9.2,7.3,2.0,1.1,2.2,2.0,{]}[{ =
nx
,2.0]1[ =x ,2.2]0[ =x ,1.1]1[ =x
Discrete Time Signals:Time-Domain Representation
46
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
45/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Graphical representation of a discrete-time signal with
real-valued samples:
Discrete Time Signals:Time-Domain Representation
47
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
46/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Discrete Time Signals:
Time-Domain Representation
In some applications, a discrete-time sequence {x[n]} may
be generated by periodically sampling a continuous-time
signal at uniform intervals of time)(txa
48
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
47/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Here, nthsample is given by
The spacing Tbetween two consecutive samples is called the
sampling intervalor sampling period
Reciprocal of sampling interval T, denoted as , is called
the sampling frequency:
),()(][ nTxtxnx anTta == =
TF
TFT1
=
g
Time-Domain Representation
49
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
48/68
ESD2521
M.S. Ramaiah School of Advanced Studies, Bengaluru
Discrete Time Signals:
Time-Domain Representation
Unit of sampling frequency is cycles per second, or Hertz
(Hz), if Tis in seconds
Whether or not the sequence {x[n]} has been obtained by
sampling, the quantityx[n] is called the n-th sample of the
sequence
{x[n]} is a real sequence, if the n-th samplex[n] is real for
all values of n
Otherwise, {x[n]} is a complex sequence
50
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
49/68
S 5
M.S. Ramaiah School of Advanced Studies, Bengaluru
g
Time-Domain Representation
A complex sequence {x[n]} can be written as
where
and are the real and imaginary parts ofx[n]
The complex conjugate sequence of {x[n]} is given by
Often the braces are ignored to denote a sequence if there is no ambiguity
][nxre
][nxim
]}[{]}[{]}[{ nxjnxnximre
+=
]}[{]}[{]}[*{ nxjnxnx imre =
51
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
50/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
gTime-Domain Representation
Example - is a real sequence
is a complex sequence
We can write
where
}.{cos]}[{ nnx 250=
}{]}[{ . njeny 30=
}.sin.{cos]}[{ njnny 3030 +=
}.{sin}.{cos njn 3030 +=
}.{cos]}[{ nnyre 30=
}.{sin]}[{ nnyim 30=
52
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
51/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
g
Time-Domain Representation
Example -
is the complex conjugate sequence of {y[n]}
That is,
}{}.{sin}.{cos]}[{ . njenjnnw 303030 ==
]}[*{]}[{ nynw =
53
8/13/2019 Session 1 Sig Rev
52/68
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
53/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
gTime-Domain Representation
A discrete-time signal may be a finite-length or an infinite-
length sequence
Finite-length (also called finite-duration or finite-extent)
sequence is defined only for a finite time interval:
where and with
Lengthor durationof the above finite-length sequence is
21 NnN
1N
8/13/2019 Session 1 Sig Rev
54/68
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
55/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
g
Time-Domain Representation
Example -
is a finite-length sequence of length 12 obtained by zero-
padding with 4 zero-valued samples
= 850 432
nnnnxe ,,][
432 = nnnx ,][
57
PEMP
ESD2521Discrete-Time Signals:
8/13/2019 Session 1 Sig Rev
56/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
gTime-Domain Representation
A right-sided sequencex[n] has zero-valued samples for
If a right-sided sequence is called a causal sequence
,01 N
1Nn
,02N
2Nn
A left-sided sequence
59
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
58/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Operations On Sequences
A single-input, single-output discrete-time system operates on a
sequence, called the input sequence, according to some prescribed
rules and develops another sequence, called the output sequence, with
more desirable properties
x[n] y[n]
Input sequence Output sequence
Discrete-time
system
60
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
59/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Operations On Sequences
For example, the input may be a signal corrupted with
additive noise Discrete-time system is designed to generate an output by
removing the noise component from the input
In most cases, the operation defining a particular discrete-
time system is composed of some basic operations
61
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
60/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Basic Operations
Product(modulation) operation:
Modulator
An application is in forming a finite-length sequence from
an infinite-length sequence by multiplying the latter with a
finite-length sequence called an window sequence
Process called windowing
x[n] y[n]
w[n]
][][][ nwnxny =
62
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
61/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Basic Operations
Additionoperation:
Adder
Multiplicationoperation
Multiplier
][][][ nwnxny +=
Ax[n] y[n] ][][ nxAny =
x[n] y[n]
w[n]
+
63
PEMP
ESD2521
B i O ti
8/13/2019 Session 1 Sig Rev
62/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Basic Operations
Time-shiftingoperation:
whereNis an integer
IfN> 0, it is delayingoperation Unit delay
IfN< 0, it is an advanceoperation
][][ Nnxny =
y[n]x[n]z
1z y[n]x[n] ][][ 1= nxny
][][ 1+= nxny
64
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
63/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Basic Operations
Time-reversal(folding) operation:
Branchingoperation: Used to providemultiple copies of a sequence
][][ nxny =
x[n] x[n]
x[n]
65
PEMP
ESD2521
Sampling Rate Alteration
8/13/2019 Session 1 Sig Rev
64/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Sampling Rate Alteration
Employed to generate a new sequence y[n] with a sampling
rate higher or lower than that of the sampling rate of
a given sequencex[n]
Sampling rate alteration ratiois
IfR> 1, the process called interpolation
IfR< 1, the process called decimation
TF'TF
T
T
F
FR
'
=
66
PEMP
ESD2521
S li R t Alt ti
8/13/2019 Session 1 Sig Rev
65/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Sampling Rate Alteration
In up-samplingby an integer factorL> 1,equidistant zero-valued samples are inserted by the up-sampler
between each two consecutive samples of the input sequencex[n]:1L
=
=otherwise,0
,2,,0],/[][
LLnLnxnxu
L][nx ][nxu
67
PEMP
ESD2521
8/13/2019 Session 1 Sig Rev
66/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Sampling Rate Alteration
An example of the up-sampling operation
0 10 20 30 40 50-1
-0.5
0
0.5
1Output sequence up-sampled by 3
Time index n
Amplitude
0 10 20 30 40 50-1
-0.5
0
0.5
1Input Sequence
Time index n
Amplitude
68
PEMP
ESD2521
S i A i
8/13/2019 Session 1 Sig Rev
67/68
M.S. Ramaiah School of Advanced Studies, Bengaluru
Sampling Rate Alteration
An example of the down-sampling
operation
0 10 20 30 40 50-1
-0.5
0
0.5
1Output sequence down-sampled by 3
Amplitude
Time index n
0 10 20 30 40 50-1
-0.5
0
0.5
1Input Sequence
Time index n
Amplitude
69
PEMP
ESD2521
S i S
8/13/2019 Session 1 Sig Rev
68/68
Session Summary
An Embedded system is a special-purpose computer that
interacts with the real world through sensing and/or actuation
Embedded Systems are also extremely and diversely applied
in various areas Digital Signal Processing is an application ofmathematical operations to digitally represented signals
Top Related