8/10/2019 Scan 1120002
1/3
'pol
eql
ssoJcB
on_asr
elrnb
sI
(uD
U
+
"u
aq
plnoqs
or
Pue
on
^\Jp
aroJaraql
llrlvt
p
'
(ot,trrA),
_urs
=
7)
Jo
t31Y=D
uls
d%
: slt\olloJ
s
Pe
a8ellon
aleF
>1ead
uaa^qaq
drqsuoqelary
'asrnoc;o
'uec 1r
I
aq,{eur
d81yeflrc1
rolaifi
ueql \'"06
ur{l
ssal
salSue
Suug
1e
ucs
aql
Suua8
aq.l
sv',1
'3lg
^
aq;,
ulrg
'.06
>
p
(e)
.06
=
n
(q)
UCS
Jo
3uua33g1o11
(o)
pBoI
cP
qlr/la
lrncrrc
a^B/ t\-JIeq
;
;i
i5s
ire
1o'8uug
orulstsau
'99'7
'8Id
(r)
rr+r .
+1..'*:-
-------
rr
.
(S)
(D)
sA
Jo
anIB^
aql
sarrr;
slq.Ii
''1
=
d%
teqt
q'"'
p"-t-':lp*'^:l:-"":?:?;,,:t*:l
"f::t;;
il1;'T'';;
::iln"}il:::;.Y'";\;J:'"'*="'-r"1"'r=-i:ilT:'^'ff
Til;:1f
".S::?"H::"]
seqd
III
aroJalaql
sr
"n
AIuo
saauclsrsd{
J\
ud\oqs
sE
ucs
ssorre
rn
sL
sreadde
sn
aae11o"-ittil'.::
:::'":;::;".",:t::l#1""#::i"rq
:#:il$?tr:ffi:.
'(a'e11on
raFB'1
ai":i
-r
uqr
ssal
sr
1'n
a'ellorr
a1e3;o
4ead)
d'1
'
IIIAJINi
#;;;;il;i,i;o'
sE
Ireus
osIB
sr
*i=':'-'-''1::"i:":::::::"i:"::,:t:,H::'ffi"*
L"rr;'::+
""*ln";nu;
a'el1or,
ale'
arlr
saurrrrarap
g
Buqlas rarauoquatod
aq;,
"zg,8uriCre.r
f,q
pelo4uoc
aq
uc
aslnd
cp
s-nll
Jo
apnlqdure
aq;
'aspd
cP
e^eff\-Jler{
sr
tn
e8elloa
;lpl
'a'7
'(1uo
alcfc;pq
arrl+5od
3u:r;.n'
:::::::rt"""l3
"Ut
:1ffi;il^;;""r:",
IIBrrs
e
s,yr'rp
lFcr.rc
ra3gul
a4e3
'a3re1
etezg
'rU
saculslsar
sv
srolqr,tqtr
L6I
lrt't't.tvl
"06=D
8/10/2019 Scan 1120002
2/3
Thvristors
[Art.
4.14]
r99
In
the range
of
power
freguencies, it may
be
empirically
shown
[3]
that
RC for
zero output
voltage is
given by
ncr_ff=l
T
=Lf =period
of ac
line
frequency
in
seconds.
The
SCR
will
trigger when
u"
=Vrr+
u4,
where
ua is
the voltage
drop
across
diode
Dl.
At the
instant
of
triggering,
lf
u"
is
assumed constant,
the
current.Ir,
must
be supplied
by
voltage
source
through R,
Dl and
gate
to
cathode circuit.
Hence
the
maximum
value
of
R is
given
by
...(4.25)
where
where
u"
is the
source voltage
at
which thyristor turns
can
be obtained
from
Eqs.
(4.25)
and
(4.26).
...(4.26)
on. Approximate
values
of
lR and
C
us
-lt
12
0
V6 sin
rrrt
_+
|/"
*'a
I
I
Fq
I
I
2r
I
ift
(a)
(b)
Fig.
4.67.
Waveforms for RC half-wave
trigger circuit
of
Fig.
4.66
(o)
high
value of
E
(b)
low value
of R.
When
SCR
triggers,
voltage drop
acro.ss
it
falls to 1 to
1.5 V. This,
in turn,
lowers
the
voltage
across.R
and C to
this low value
of
1
to
1.5 V.
Low
voltage across SCR
during
conduction
period
keeps
C
discharged
in
positive
half
cycle until
negative
voltage cycle
across
C
appears.
This
charges
C
to maximum
negative
voltage
-V^as
shown
in
Fig. 4.67
by dotted
line.
In
Fig.4.67
(a),
F
is more,
the
time
taken for
C
to charge
from
-
oa
to
(Vs1+
u)
=
V",
is
more,
frring
angle is
more and therefore
average
output
voltage is
low. In
Fig.
4.67
(b),
R is
less, frring
angle
is
low
and
therefore
average
output
voltage
is more.
(ii)
RC
fult-wave
trigger
circuit.
A
simple
RC trigger
circuit
giving
full-wave
output
voltage
is
shown
in Fig,
4.68. Diodes
D1-D4 form
a
full-wave
diode
bridge.
In
this
circuit,
the
initial
8/10/2019 Scan 1120002
3/3
206
[Art.
4.14]
Power
Flectrorb
Rr
DI
ir.f .
,l:
.,
vc
..=
\
''i
,^
f--
Pulse
Tt
R2
/
D4
L.
t;-
t:
a
G
c
v.
Vd.
.
vd.
Fig. 4.73. Synchronised
UJT trigger circuit.
on. As soon
as
the capacitor
discharges,
it starts to
recharge as shown.
Rate ofrise
ofcapacitor
voltage
can
be
controlled
by
varying
,R. The
frring
angle
can be controlled
up
to
about
150".
This
method
of
controlling the output
power
by varying charging
resistor.R
is
called ramp
control,
qpm'Joop
control or
manual
control.
As
the
zener diode
voltage
V"
goes
to
zero
at
the
end of each half cycle,
the synchronization
of
the
trigger circuit
with
the
supply voltage
across SCRs
is
achieved.
Thus the time
f,
equal
to
crlo,
when
the
pulse
is
applied
to
SCR
for the
frrst time,
will
remain
constant for t\e same
value
of
R.
Small variations
in
the
supply
voltage
and
frequency
are
not
going
to
effect
the circuit
operation.
Pulse
voltog8
-lfit
J,fL
(a)
(b)
Fig.
4.74.
Generation
of
output
pulses
for the
circuit
of Fig.
4.73. Here,
t
=
a/a.
In case
R
is reduced
so
that
u" reaches
UJT threshold
voltage
twice
in each half
cycle
as
shown in
Fig.
4.74
(b\,
then
there
will
be
two
pulses
in each
half
cycle.
As
the
first
pulse
will
be
able
to turn-on
the
SCR,
second
pulse
in
each cycle
is redundant.
Ramp-and'pedestal
triggering.
Ramp
and
pedestal
triggering
is
an
improved
version
of
synchronized-UJT-oscillator
triggering.
Fig.
4.75
shows
the
circuit for ramp-and-pedestal
triggering
oftwo
SCRs
connected
in antiparallel
for
controlling
power
in
an ac load.
This
trigger
circuit
can
also
be used
for
triggering
the
thyristors
in
a
single-phase
semicohverter
or
a
single-phase
full converter.
The
various
voltage
waveforms
are
shown in
Fig.
4.26.
Zener diode
voltage V, is constant at
its
thresh-hold
voltage.
R,
acts as
a
potential
divider.
Wiper
of
.R2 controls
the
value
of
pedestal
voltage
Voa.
Diode
D allows
C
to
be
quickly
chdrged
to
Voa
through
the low
resistance
of the
upper
portion
of
Rr. The setting
of
wiper
on
R, is
such
...Y
d,
o.
q
D
Top Related