Reducing SSD Read Latency via NAND Flash Program and Erase Suspension
Guanying Wu and Xubin He
{wug, xhe2}@vcu.edu Department of Electrical and Computer Engineering
Virginia Commonwealth University
Richmond, VA
1 2/20/2012
This research is sponsored in part by the U.S. National Science Foundation (NSF) under grants CCF-1102605 and CCF-1102624.
Suspend Program and Erase to make Read faster?
2
Motivation
• P/E (Program/Erase) are about 10x/100x slower than read.
• P/E are non-suspendable in current NAND products
– Once committed to NAND flash, no preemptions.
• If apps write and read at the same time & Intensive workloads
– Read latency suffers from queuing delay.
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A Simple Demo
RD3 wouldn’t benefit from RPS
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Further Investigation
• Simulation with disk I/O traces.
– MS SSD-add-on simulator
– 6 popular traces
• Comparing:
– FIFO
– Read Priority Scheduling
– Optimistic cases:
• Equal latencies: PER
• 0 P/E latencies: PE0
0
0.2
0.4
0.6
0.8
1
F1
F2
DA
P
MSN
C3
C8
F1
F2
DA
P
MSN
C3
C8
No
rmal
ize
d R
ead
Lat
en
cy
FIFO RPS PER PE0
SLC MLC
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We are expecting:
Our Idea: Make NAND Flash P/E Suspendable
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Outline
• Background:
– Why can we suspend P/E?
• Design:
– How do we do it?
• Evaluation:
– Compare to the optimistic cases
• Conclusion
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Background: NAND Flash Erase
• NAND Flash Erase:
– Reset cells via a long pulse of Erase Voltage to expel the electrons.
– Plus a verify operation.
1.5/3ms
4us
Guarantee the duration
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8us
Background: NAND Flash Program
• NAND Flash Program:
– Incremental Step Pulse Programming
9 ARASE, K. Semiconductor NAND Type Flash Memory with Incremental Step Pulse Programming, Sept. 22 1998. U.S. Patent 5,812,457.
Background: NAND Flash Program
NAND Flash Program: Timeline
• Program pulse and verify are considered atomic • Suspend in the interval between program pulse and verify
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20us 8/24us
Background: NAND Flash P/E
• Correct Timing
– Program: what is the last phase? what is the value of Vpp?
– Erase: how much job have we done/how much is left?
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BREWER, J.; GILL, M. Nonvolatile Memory Technologies with Emphasis on Flash.
Design: Suspend/Resume Erase
• Case 1: Read arrives when resetting wire voltage
• Case 2: Read in the middle of Erase Pulse or Verify (cancelled)
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Design: Suspend/Resume Erase
• Case 1: Suspension happens in Verify phase
– Redo Verify phase. (overhead to erase latency)
• Case 2: Suspension happens in Erase phase
– Finish what is left before suspension.
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Design: Suspend/Resume Program
• Program pulse and Verify are considered atomic, intuitively:
– Choice 1: Suspend in the intervals – Inter-Phase-Suspension
– Choice 2: Cancel the current phase – Intra-Phase-Cancellation
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Design: Suspend/Resume Program
• Need to retain the page buffer first.
• Resume from IPS
• Resume from IPC
Overhead
Overhead Overhead
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Evaluation: Read Latency
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0
0.2
0.4
0.6
0.8
1
F1 F2 DAP MSN C3 C8 F1 F2 DAP MSN C3 C8
No
rmal
ize
d R
ead
Lat
en
cy
RPS PER PE0 PES_IPC
SLC MLC
0.9
0.95
1
1.05
1.1
1.15
F1 F2 DAP MSN C3 C8 F1 F2 DAP MSN C3 C8 No
rmal
ize
d R
ead
Lat
en
cy
PES_IPC PES_IPS
SLC MLC
Evaluation: Write Latency Overhead
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0.8
0.85
0.9
0.95
1
1.05
1.1
No
rmal
ize
d W
rite
Lat
en
cy
FIFO RPS PES_IPS PES_IPC
SLC MLC
Conclusion
• Suspending P/E for read is a feasible solution:
– Significant read performance gain.
– Low overhead on write latency.
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