Reduced-code test methodusing sub-histograms forpipelined ADCs
Hyeonuk Son, Jaewon Jang, Heetae Kim, and Sungho Kanga)
School of Electrical and Electronic Engineering, Yonsei University,
50 Yonsei-ro, Seodaemum-gu, Seoul 120–749, Korea
Abstract: The measurement of static test parameters for an analog-to-
digital converter (ADC) requires a large volume of test data, especially for
a high-resolution ADC. This paper proposes a reduced-code test method for
pipelined ADCs that does not compromise test accuracy. The proposed
method calculates fault information at each stage by using sub-histograms.
The simulation results based on 12-bit pipelined ADCs show a maximum
integral nonlinearity error of 0.590 LSB with only 3.92% of the codes
required for the conventional histogram-based method.
Keywords: analog-to-digital converter (ADC), pipelined ADC, histogram-
based test, reduced-code test
Classification: Integrated circuits
References
[1] A. Gines and G. Leger: Proc. Design, Automation and Test in EuropeConference and Exhibition (2014) 1. DOI:10.7873/DATE.2014.384
[2] S. M. Hamed, A. H. Khalil, M. B. Abdelhalim, H. H. Amer and A. H. Madian:Proc. Communication and Information Technology (2013) 366.
[3] C. A. Schmidt, O. Lifschitz, J. E. Cousseau, J. L. Figueroa and P. Julian: IEEETrans. Instrum. Meas. 63 (2014) 658. DOI:10.1109/TIM.2013.2295877
[4] V. Pálfi and I. Kollár: IEEE Trans. Instrum. Meas. 62 (2013) 880. DOI:10.1109/TIM.2013.2243500
[5] J. Blair: IEEE Trans. Instrum. Meas. 43 (1994) 373. DOI:10.1109/19.293454[6] K. S. Chan, N. F. Nordin, K. C. Chan, T. Z. Lok and C. W. Yong: Proc. Asian
Test Symposium (2013) 213. DOI:10.1109/ATS.2013.47[7] J. F. Lin, S. J. Chang and C. H. Huang: Proc. Asian Test Symposium (2009) 57.
DOI:10.1109/ATS.2009.18[8] J. Lin, S. Chang, T. Kung, H. Ting and C. Huang: IEEE Trans. Very Large
Scale Integr. (VLSI) Syst. 19 (2011) 2158. DOI:10.1109/TVLSI.2010.2089543[9] A. Laraba, H. G. Stratigopoulos, S. Mir, H. Naudet and G. Bret: Proc. VLSI
Test Symposium (2013) 1. DOI:10.1109/VTS.2013.6548913[10] T. B. Cho and P. R. Gray: IEEE J. Solid-State Circuits 30 (1995) 166. DOI:10.
1109/4.364429
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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LETTER IEICE Electronics Express, Vol.12, No.12, 1–10
1 Introduction
Analog-to-digital converters (ADCs) are widely used in systems-on-chips (SoCs)
as devices that transfer signals between analog and digital domains [1, 2]. In
general, ADCs should be tested strictly because they are the largest bottleneck in
the data transmission process [3]. The most representative method for measuring
the linearity of ADCs is the histogram-based test method [4, 5], which determines
test parameters by applying test samples with a known probability density function
(PDF) and by measuring the output PDF. This test method can precisely measure
test performance through the large code bin width. However, its disadvantages
include a long test time and the necessity of large amounts of test data [6, 7]. To
solve these problems, many reduced-code test methods have been proposed. In [8],
a transition-code-based method that measures a few specific transition codes was
proposed to reduce test data. Transition codes, which refer to specific codes that
include a large nonlinearity in the presence of a gain fault, are measured for the
reduction of test samples. However, the previous studies are less accurate because
the results are estimated by specific codes.
This paper proposes a reduced-code test method that utilizes fault information
of each stage for pipelined ADCs. The proposed method creates sub-histograms
and collects samples at each pipeline stage. After the enough samples are collected,
static parameters including differential nonlinearity (DNL) and integral nonlinearity
(INL) are determined through the results of sub-histograms. The proposed method
has the advantage of accomplishing high test accuracy with fewer test data than the
existing histogram-based methods.
2 Faults in pipelined ADC
The general structure of a 1.5-bit/stage pipelined ADC is shown in Fig. 1. The
proposed method is explained for the 1.5-bit/stage structure, although it can be
extended to other multiple-bit/stage structures by using the same principle. The
pipelined ADC in Fig. 1 includes front-end sample-and-hold (S/H) circuits and N
stages arranged in series. Each stage consists of an S/H circuit, sub-ADC, sub-
DAC, subtractor, and gain stage. The output (Vi) of the previous stage is passed
through the sub-ADC, which generates the pipeline stage outputs. Simultaneously,
the residues are determined through the sub-DAC, subtractor, and gain stage, and
they are delivered to the next stage. The outputs at each stage are stored in the
pipeline latches and passed through the digital error correction (DEC) circuits, after
which the final outputs are determined by eliminating errors including a large
amount of comparator offsets [8].
The function of the rest of the design, except for the sub-ADC, is generally
implemented by multiplying-DAC (MDAC) circuits [9]. Because MDAC circuits
induce gain and offset faults that have a large impact on residues, many previous
studies have proposed test methods that target MDAC circuits. In this letter, we
target the gain fault and op-amp offset fault in MDAC which directly affect the
linearity of pipelined ADCs. The fault effects caused by comparator offsets are not
considered, because pipelined ADCs with DEC circuits can tolerate large com-
parator offset faults, especially in the 1.5-bit/stage pipelined structure [8, 10].
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
3 Proposed method
The proposed method calculates the offset and gain faults included in MDAC
circuits at each stage by analyzing the proposed sub-histograms. Fig. 2 shows the
structure of the proposed sub-histograms. The sub-histograms are inserted at the
end of the pipeline latches. Each sub-histogram consists of several gates and N-bit
counters to distinguish the “00,” “01,” and “10” values of the pipeline latches.
When data are inserted into the sub-histograms, the enable signal of the relevant
line is generated. This signal activates the counter and updates the results. When the
enough test samples are applied, the frequency of each output is stored, then the
stage faults can be calculated by the collected data in the sub-histograms. The
proportion of “00,” “01,” and “10” values are different from the ideal values
because of the included faults, so we can determine the faults inspecting the
difference.
Fig. 2. Structure of the proposed sub-histograms
Fig. 1. Structure of a 1.5-bit/stage pipelined ADC
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
3.1 Calculation of pipeline stage faults
To determine the inserted faults through the proposed sub-histograms, the fault
effects on the distributions of stage outputs are calculated. Fig. 3 represents the
transfer curve of the 1.5-bit/stage pipeline stage, which includes the op-amp offset
and gain faults. The transfer function at the jth stage including the offset fault
(offsetj) is determined as (1). To determine the effects of offsetj on the sub-
histograms, the changes between sections where the output values are 00, 01,
and 10 are calculated. The transition points, where the output value changes, are
obtained by measuring x when substituting �Vref =4 for y in (1) and the results are
shown in (2). The values of x1, x3, and x5 indicate the values where the output
changes from “00” to “01”; the others (x2, x4 and x6) indicate the values where the
output changes from “01” to “10.”
y ¼ 2 x þ Vref
2
� �þ offsetj x � � Vref
4
� �
y ¼ 2x þ offsetj jxj < Vref
4
� �
y ¼ 2 x � Vref
2
� �þ offsetj x � Vref
4
� �ð1Þ
x1 ¼ � 5
8Vref � 1
2offsetj x2 ¼ � 3
8Vref � 1
2offsetj
x3 ¼ � 1
8Vref � 1
2offsetj x4 ¼ 1
8Vref � 1
2offsetj
x5 ¼ � 3
8Vref � 1
2offsetj x6 ¼ � 5
8Vref � 1
2offsetj
ð2Þ
The length of each section ðl00; l01; l10Þ where the values are “00,” “01,” and
“10” meaning the distribution of sub-histogram data can be calculated using (2), the
results of which are shown in (3). From (3), the offsetj evidently affects the
occurrence of “00” and “10.” Therefore, offsetj is determined by subtracting l00
from l10 as shown in (4).
l00 ¼ j � Vref � x1j þ j � Vref
4� x3j þ j Vref
4� x5j ¼ 5
8Vref � 4
3offsetj
l01 ¼ jx1 � x2j þ jx3 � x4j þ jx5 � x6j ¼ 3
4Vref
l10 ¼ jx2 � � Vref
4
� �j þ jx4 � Vref
4j þ jx6 � Vref j ¼ 5
8Vref þ 4
3offsetj
ð3Þ
offsetj ¼3
8ðl10 � l00Þ ð4Þ
The graph in Fig. 3(b) represents the transfer curve including gain faults. The
transfer function at the jth stage with the gain fault (gainj) is determined as in (5).
As in the process for calculating the offset fault, we can identify six transition
points at which the output changes. They are determined by the expressions in (6).
The length of each section where the values are “00,” “01,” and “10” representing
the results of sub-histogram are calculated mathematically as shown in (7). A
simple method to find gainj is to use l01, the results of which are shown in (8).© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
y ¼ ð2 þ gainjÞ x þ Vref
2
� �x � � Vref
4
� �
y ¼ ð2 þ gainjÞx jxj < Vref
4
� �
y ¼ ð2 þ gainjÞ x � Vref
2
� �x � Vref
4
� �ð5Þ
x1 ¼ � 5 þ 2gainj8 þ 4gainj
Vref x2 ¼ � 3 þ 2gainj8 þ 4gainj
Vref
x3 ¼ � 1
8 þ 4gainjVref x4 ¼ 1
8 þ 4gainjVref
x5 ¼3 þ 2gainj8 þ 4gainj
Vref x6 ¼5 þ 2gainj8 þ 4gainj
Vref
ð6Þ
Fig. 3. Transfer curves of a 1.5-bit/stage pipeline ADC including (a)offset faults (b) gain faults in MDAC
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
l00 ¼5 þ 4gainj8 þ 4gainj
Vref l01 ¼ 6
8 þ 4gainjVref l10 ¼
5 þ 4gainj8 þ 4gainj
Vref ð7Þ
gainj ¼1:5Vref
l01� 2 ð8Þ
Fig. 4 shows sub-histogram data including offset and gain fatults in stage 1.
Test samples are applied for 1,000 periods and the sub-histograms collect 4,096,000
samples for the fault detection. From the results of (8), the gain fault can be
calculated by substituting 0.5 for Vref and 0.3731 (1,528,359/4,096,000) for l01.
The solution is determined to about 0.01018. The gain fault does not affect offset
faults because it raises the proportion of “00” and “10” in the same ratio. To
determine the offset fault, the proportion of “00” (0:2384 ¼ 976; 625=4; 096; 000)
is subtracted from that of “10” (0:3884 ¼ 1; 591; 016=4; 096; 000) and multiplied
by 0.375 by (4). The calculated offset fault is determined to 0.05625.
3.2 Applying the stage faults
After the offset and gain faults of each stage are calculated from the sub-histo-
grams, we estimate the transfer curve for the static test parameters including DNL
and INL. For the accurate estimation, we apply the offset error, transition error and
slope to estimate the accurate transfer curve. The offset error is determined by the
stage offsets. The impact of the offset faults on the outputs decreases as the pipeline
stage progresses. For example, the offset fault that occurs at the ðj þ 1Þth stage hashalf the impact of a fault at the jth stage. The mathematical formula for the offset
effects that occur at each stage is shown in (9).
offset error ¼Xnj¼1
offsetj � 2�j ð9Þ
The gain faults of each stage change the slope of the transfer curve and cause
transition errors in certain output positions. Transition errors generated by the
changed slope induce large discontinuous jumps in the transfer curve. Fig. 5 shows
the transfer curve affected by the gain faults at stage 1 and stage 2. For the eight
Fig. 4. Sub-histogram data including offset and gain fatults in stage 1
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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total transition errors in Fig. 5, the third and sixth errors (TE1) occur because of
faults in stage 1, whereas the others (TE2) occur because of faults in stage 2.
Theoretically, the gain faults of stage 1 cause transition errors at the 3/8 and 5/8
points [8]. On the same principle, the gain faults at the jth stage generate transition
points at 3=2jþ2; 5=2jþ2; . . . ; 2jþ2 � 3=2jþ2. The amplitude of the transition errors
is determined through the pipelined structure according to (10).
The entire slope of the transfer curve is determined by (11). The slope in (11)
determines the sign of the transition errors; the transition error is negative if the
slope is greater than 1 and positive if the slope is less than 1. In addition, in contrast
to the ideal transfer curve, fault effects do not occur at the 1/4, 1/2, or 3/4 points.
These fixed points are used as the initial points in determining the transfer curve.
After determining these errors, the transfer curve can be estimated. The process
of estimating the transfer curve is as follows. First, a straight line with a slope of
(11) is drawn based on a fixed point. If transition errors appear in the process, they
are added or subtracted from the results determining their values by (10). After all
outputs are determined through this process, the offset error in (9) is applied.
Through the estimated transfer curve, DNL and INL can be determined.
transition errorj ¼ 1
2j� gainj ð10Þ
slope ¼ 1
2j�Ynj¼1
ð2 þ gainjÞ ð11Þ
4 Simulation results
Simulations were performed with C++ and MATLAB for 12-bit pipelined ADCs
having a 2-V peak-to-peak operating voltage to demonstrate the effectiveness of the
proposed test method. A ramp signal with additive white Gaussian noise (AWGN)
was used as the test samples, and the linearity of the ramp signal was assumed to be
ideal. AWGN was generated with an average of 0 and standard deviation of 0.001.
Fig. 5. Transfer curve affected by gain faults at the first and secondstages
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
The op-amp offset and gain faults in the MDAC were inserted as target faults.
Offset faults having a maximum value of �0:3 LSB and gain faults having a
maximum value of �0:2 were randomly included in each stage. Comparator offsets
were inserted in each stage with an average of 0 and standard deviation of 0.0625.
To demonstrate the accuracy of the proposed stage fault calculation method, we
applied the test samples for 5, 10 and 100 periods and collected the data for the sub-
histograms. In this procedure, the faults at stage 11 and stage 12 were excluded
from the estimation because the impacts on the outputs were negligible and hardly
influenced the test accuracy. Table I presents the error ratios for the calculated
offset and gain faults compared with the ideal ones. In the results for offset faults,
errors occurred in approximately 8.0% when the test inputs were inserted for five
period, but the errors are decreased to 4.2% with 100 simulation periods. In the case
of gain faults, the average error rate was approximately 2.72% when the test inputs
were inserted for five periods, and they were reduced to approximately 0.35% with
100 simulation periods.
To demonstrate the accuracy of the proposed method, the results were com-
pared with those obtained by the conventional histogram-based method. Fig. 6
depicts the DNL and INL errors (differences from ideal values) of the proposed
method and the conventional histogram-based method. The average DNL error was
0.025 LSB for the proposed method, which is less than that obtained with the
conventional histogram method. Moreover, the peak INL error was 1.446 LSB for
the conventional histogram-based method and 0.590 LSB for the proposed method.
In ADC testing, it is important to achieve test accuracy with fewer test samples.
To examine the reduction in the number of test samples, the proposed method was
compared with previous methods. Fig. 7 shows the number of test samples required
by the conventional histogram method, the previous method [8], and the proposed
method. In the conventional histogram, the required test samples increased ex-
ponentially with the resolution of ADCs. In [8], a method was proposed to reduce
the number of test samples through the transition-code-based test technique, and the
Table I. Error ratios for calculated offset and gain faults
5 periods 10 periods 100 periods
stageoffset gain offset gain offset gainfaults faults faults faults faults faults
1 0.046 0.002 0.042 0.002 0.040 0.001
2 0.052 0.002 0.049 0.002 0.047 0.001
3 0.048 0.003 0.049 0.003 0.045 0.001
4 0.061 0.003 0.052 0.003 0.051 0.001
5 0.058 0.008 0.049 0.008 0.038 0.002
6 0.282 0.019 0.050 0.018 0.037 0.003
7 0.067 0.024 0.046 0.022 0.037 0.002
8 0.064 0.042 0.049 0.038 0.049 0.004
9 0.058 0.065 0.048 0.062 0.026 0.008
10 0.066 0.104 0.062 0.082 0.052 0.012© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
test was conducted with approximately 7% of test samples of the histogram-based
method. Because the proposed method calculates the faults by using a sub-histo-
gram at each stage, it requires far fewer test samples than the previous method. The
proposed method required 56.7% of test samples needed in [8] and 3.92% of those
required by the histogram method. The rate of reduction increased as the resolution
of the ADC increased. For 15-bit ADCs, only 16.68% of the number of samples
used in [8] was required.
Fig. 6. Test results compared with the conventional histogram-basedmethod for (a) DNL and (b) INL
Fig. 7. Required number of test samples for the conventional histo-gram-based method, previous work [8] and proposed method
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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IEICE Electronics Express, Vol.12, No.12, 1–10
5 Conclusion
A reduced-code test method for a pipelined ADC was proposed to reduce the
required number of test samples without a loss of accuracy. The proposed method
creates sub-histograms by using the data from pipeline latches and determines the
faults of each pipeline stage. A mathematical approach is then used to produce a
transfer curve by using the results of the sub-histogram. The proposed method
requires fewer data samples compared with the previous histogram based-test
method. Simulation results based on a 12-bit pipelined ADC showed improved
test accuracy and a reduction in the number of test samples required compared with
previous test methods.
Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF)
grant funded by the Korea government (MSIP) (No. 2015R1A2A1A13001751).
© IEICE 2015DOI: 10.1587/elex.12.20150417Received May 6, 2015Accepted May 26, 2015Publicized June 9, 2015Copyedited June 25, 2015
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