© V. Angelov IKP Uni-Köln 05.08.2013 1
Physikalisches InstitutUNI-Heidelberg
Venelin AngelovElektronikwerkstatt
© V. Angelov IKP Uni-Köln 05.08.2013 2
Digital system design withFPGA
• Logic Box• SUbmodules available• Some Designs
• 7x100 MHz ADC• Dual MALU• TDC
• The new DL711 Logic Box• The new ADC SUBmodule
© V. Angelov IKP Uni-Köln 05.08.2013 3
Logic Box
• Block Diagram
• USB Interface
• User Design
• Top & Contraints Generator
• Design Flow
© V. Angelov IKP Uni-Köln 05.08.2013 4
Block Diagram of DL701/6/9
bytes
ProgramFlash
CWR
4 or 8 SU7xx
DMA_req
CRdy
i/o
16
DMA_Ainc
USBInterface
32
CRD
USBconnector
CDin
CReset
32
CWR
32
Optional
Optional
CReset
FTDI or Cypress
2
. . .
CRdy
CLK
o
Caddr
SU 1
SU 0
JTAG
o
+
+
CDout
CLK
o
CDin
100 MHz
Activity
SU 3|7
o
32
FPGA
DMA_Nwords
RES_n32
o
Top oftheuserdesign DMA_Addr
i
SerProg
USB Controller
DMA_dsize
32
i
RESET
QuartzOscillator
LED_back
DMA_ena
i/o
CDout 32
Caddr
Digital ClockManager (DCM)
i/o
JTAGconnector
CRD
DMA_ack
DL701/6: xc3s400DL709/10: xc3s4000DL711: xc6slx150t
© V. Angelov IKP Uni-Köln 05.08.2013 5
User Design
MS bits of CAddrwrite port
read port
CDin
CDout CWR
MS bits of CAddr
User I/Os
© V. Angelov IKP Uni-Köln 05.08.2013 6
Generate Top and UCF files
gen_lb DL709 -s2 SU704 -s3 SU736 -t ../../SRC/TOP/DL709.vhd -o top.vhd-u top.ucf
specifiy the DL7xx type
specifiy the SU7xx cards
specifiy the template file
specifiy the VHDL output file
specifiy the UCF output file
This program supports now:
DL701, 706, 709, 710, 711
SU701, 702, 703, 704, 706, 707, 709, 710, 711, 712, 713, 714, 715, 717, 720, 721, 722, 724, 725, 726, 727, 728, 730, 731, 733, 734, 736, 737
© V. Angelov IKP Uni-Köln 05.08.2013 7
SUbmodules overviewSU701 TTL I/O 16 channels in two groupsSU702 8 channel 14-bit ADC (MAX1149)SU703 4 channel fast dicriminator with 2xMAX9601 (dual PECL comparator) +
2xMAX537 (4x serial DAC)SU704 5 channel TTL or NIM I/OSU705 4M x 16-bit RAMSU706 100 MS/s 14-bit ADC (ADS5500)SU707 8 channel LVDS I/OSU709 8 temperature sensors SMT160-30 / HY-LINE #16092SU710 2 channel 14-bit DACSU711 DelaySU712 Dual 8 channel 14-bit ADC (MAX1149), like SU720 but without isolationSU713 Dual 8 channel 14-bit DACSU714 ADC ADS5500SU715 2 channel audio preamplifierSU716 16M x 32-bit RAMSU717 Gated integrator with ADS5500SU720 Dual 8 channel 14-bit ADC (MAX1149), like SU712 but with isolation
© V. Angelov IKP Uni-Köln 05.08.2013 8
SUbmodules overviewSU721 Dual 8 channel 14-bit DAC, like SU713 but with isolationSU722 5 channel TTL I/O, like SU700 but with isolationSU724 Toslink interfaceSU725 8 channel ECL inputSU726 32 LEDsSU727 Toslink interfaceSU728 16-bit ADC and DACSU730 PSRAM 8M x 16 bitSU731 4 x H-Bridge, 36V 2ASU733 Optical In/OutSU734 DDS Modul with AD9910SU735 100 MS/s 14-bit ADCSU736 2 channel fast dicriminator with programmable threshold &
hysteresis and direct NIM outputs (1xMAX9600 dual ECL comparator + AD5624 4x serial DAC)
SU737 Optical Gigabit Ethernet with TLK2201 (SerDes) and SFP Module
© V. Angelov IKP Uni-Köln 05.08.2013 9
7x100 MHz ADC Design7 x 100 MHz 14-bit ADC SUbmodules
1 x 5 TTL/NIM IO Submodule
Multievent buffering:
4 events @ 2048 samples …512 events @ 16 samples
Programmablepresample length
USB2.0 InterfaceC, C++ or LabView
© V. Angelov IKP Uni-Köln 05.08.2013 10
TOP BLOCK DIAGRAM
INVTS
3
DIS/INV
BUSY_OUT
1
DISTRG
14
4
EVENT BUFFER
2
ADC SPI
3
TIMESYNC_IN
INVBUSY
7x
TRIGG_IN
SU706
ADC CLK
INVTRG
ADC_CLK_IN
CONTROL
INTERFACETO USB CHIP
USB CHIPFX2 (CYPRESS)
5
ADC_DATA_OUT
0
CONFIGURATION_REGISTER at 0x1000C
SPI
INV
DIS/INV
CBUS
ADCITP
DISTS
ANALOG_IN
© V. Angelov IKP Uni-Köln 05.08.2013 11
ADC CLOCK
0
CLK
Enable
CLK 100 MHz
1
div ratio
7x
SYNC
Output DDR
DR
CLK
QDF
CLKn
ENA
ADC CLK 50 MHz
do one DCM phase step when no reset
Discrete phase of theSYNC signal relative tothe ADCCLK
SYNC dPhase=1
2
dPhaseDCM reset when 1
Rst
SYNC dPhase=0
CLK 100 MHz
11..10DCM Phase-255..+255
ADCCLK14
State machine
SU706ADS5500
2
100 MHz
set ratio/dphase when 1
15
dPhase
Note: Set the ratio and
dphase again after changing
the DCM phase even if ratio
and dphase remained
unchanged!!!
Ratio Freq [MHz] dPhase
0 100 0
1 50 0..1
2 33 0..2
3 25 0..3
Ratio
7
Input DFF
D
CLK
Q
ENA
DCMCLK
9..8
14
DCM CLK
7
ADC DATA
ADC Data
UP/DN one step when bit7=1
DCM
RST
CLK
Q
QINC/DEC
CLK
© V. Angelov IKP Uni-Köln 05.08.2013 12
ADC SPI INTERFACE
10..9
15..12
1101
SPI DATA
0 - normal
1 - all 0
2 - all 1
3 - test pattern
Write to ADC_SPI+8 anything to reset all ADCs.Recommended before setting the ADCs.
1
PD
15..12
0
0
15..12
0..0
11
0..0 DLL
0
0
0 - DLL on (for 100 MHz)1 - DLL off (for < 60 MHz)
0..0
TP1110
1111
Write to ADC_SPI+Channel the 16-bit SPIData word for the corresponding function inADC[Channel]
0
In test pattern mode the ADCs send1010...100101...01(the bits toggle after each ADC clock)
This is useful for adjusting thetiming in the data transfer.
0 - normal1 - power down
© V. Angelov IKP Uni-Köln 05.08.2013 13
ADC CLOCK ADJUST 100 MHz
0
100000
200000
300000
400000
500000
600000
700000
800000
900000
1e+006
-200 -100 0 100 200 300
Bit
err
ors
for
4096 s
yste
m c
locks
DCM delay
100 MHz, dphase 0, dll 1
0123456
© V. Angelov IKP Uni-Köln 05.08.2013 14
ADC DATA PATH
AIN
clear &start
00
AIN
9..2 bits
DUAL PORT RAM
4..11 bits
ch=0..6
err counter 0
sample+1
Addr (relative to the BA_EV_BUFFER)
err counter 2
sample
test patternchecker
even
EVENT_SIZE_REGISTER at 0x1000D
00
0
odd
1
Address Counter AIN, AOUT
err counter 3
even/odd memoryselect
err counter 1
WE_e
2
busy
REG
32
0
WE_o
Data
31
31
Counter
13..4
REGAOUT_e
0
Bit 3 inCOMMAND_REGISTER at0x1000B
MUX
AOUT_o
EVENT
14
TestPatternGenerator
SAMPLE
327x14
ADC[ch]
ch2..0
Addr=0x10 (relative to theBA_EV_BUFFER)
Addr
Bit 5 inCONFIGURATION_REGISTERat 0x1000C
SIM_MODE
13 bits
SWAP
. . .
© V. Angelov IKP Uni-Köln 05.08.2013 15
EVENT DATA FORMAT
r0
sample 1
00
30
r1
Event Id
00
r6
20
ch=r3
r5
00
adc6..0
. . .
The unused ADCs are automatically turned off,the active ADCs can be read back
sample 3
0
ch=r1
00
4
24
sample 0
31
00
ch=r0
RDCLR
sample 0
sample 2
sample 0
READ_ORDER_REGISTERat 0x1000F
sample 1
1. i=0
2. Send r[i]
3. i=i+1
4. if r[i]=7 or i=7 exit
else goto 2
2
sample 0
r2
sample 0
Event Buffer Clear
Readout order
sample 1
evsize
Software Trigger
sample 1
0
. . .
ch=r0
r3
Test Pattern Check(toggle bits)
SFTTRG
31
Ev. in Buffer
EVENT_SIZE_REGISTERat 0x1000D
Read StateMachine Clear
00
adc_maskread-only
00
Timestamp with 10 ns resolution
sample 10
3
r4
EBCLR
ch=r<n-1>
00
00
1. Clear the event buffer at the beginning
and after setting the event size! All
events stored are lost!
2. Clear the read state machine in case of
unexpected data from the event buffer - no
events are lost!
ch=r2
TPCHK
Time Stamp Clear
0 16
1 32
2 64
3 128
4 256
5 512
6 1024
7 2048
00
00
00
TSCLR
COMMAND_REGISTER at 0x1000B
© V. Angelov IKP Uni-Köln 05.08.2013 16
OPERATION
Presamples: 10 bit register at 0x1000E,
automatically wrapped to ensure the
trigger is inside the event.
Start value 8
Presamples
0 16 5121 32 2562 64 1283 128 644 256 325 512 166 1024 87 2048 4
ADC
Event size
event stored
Busy
Trigger
EventSize Number of Number of EventsRegister Samples in the Buffer
© V. Angelov IKP Uni-Köln 05.08.2013 17
Dual MALU• 32 inputs, NIM or TTL (selectable at eachinput)• Two logical groups consisting of userprogrammable subset of the 32 inputs• In each group:
• Delay gate generators at each input(100 MHz)• Four outputs
• 3 of them just discriminators withprogrammable thresholds• one implemented as pattern checker
• Counters at each input and output fordebugging
© V. Angelov IKP Uni-Köln 05.08.2013 18
Block Diagram
TTLDIS3R
EDGE_C
SOFT_P
DIS1..4L
DELAYS
NIMDIS4R
32
0
DIS1..4R
5
DOWNSCALE
INP_DIS_R
DIS3L
32
31
4
32
WIDTH
INP_DIS_L
DIS4L
32
CNT_CTRL
DIS1..4L
32
OR_MASK
DIS1L
32
31
4
DATA
THRESHOLDS
DIS2L
32
TMAX
INPUTS
DATA
DISCR1
DISCR3
INP_NIM
TTL
x
OUTPUTS
USB Controller
DISCR2
DISCR4
CT
ADDR
Configuration
32 counters
DISCR2
CC
ADDR
Count
DISCR1
DISCR3
E
3Count
DOWNSCALE DISCR4
CT - clear timer, CC - clear counters, E - enableNote: clear commands are automaticallydeactivated after 1 clock period
IN
WIDTHDELAYS
max time for counting in 10 ns steps, write 0 for continuous
8 x SU704 IN
OR_MASK
8 counters
0
EDGE_R
INP_SHAPER
THRESHOLDS
4
ICNT0..31
EDGE_L
DIS1R
MALU
4
DCNT 1..4R, 1..4L
INP_INV
DIS2R
INP_DIS_CMALU
DIS1..4R
NIM
© V. Angelov IKP Uni-Köln 05.08.2013 19
Input edge detection and mask32 channels, i=0..31
Disable the channel in the left group when 1
EDGE_C[i]
INP_NIM
AND2
EDGE_R[i]
1Input DFF
D
CLK
Q
Send a pulse by software (writing 1 to the corresponding bit(s) in this register)
0
0
SOFT_P
31
AND2
MUXTTL[i]
31
NIM[i]
INP_DIS_R
D
CLK
Q
Note: this is not exactly the real design
0
D
CLK
Q
0
SOFT_P[i]
Disable the channel in the counter group when 1
EDGE_I[i]
Input DFF
D
CLK
Q
31
INP_NIM[i]
used for the fron LEDs
INP_DIS_L
D
CLK
Q
right group
0
INP_INV[i]
left group
31
AND2
INP_DIS_R[i]
counters
INP_DIS_C
INP_DIS_L[i]
AND2
0
INP_DIS_C[i]
Note the bits in SOFT_P are automatically cleared 1 clock period after activating
XOR2
0
Invert input when 1INP_INV
OR2
EDGE_L[i]
Select the NIM input when 1
31
Disable the channel in the right group when 1
31
D
CLK
Q
© V. Angelov IKP Uni-Köln 05.08.2013 20
DGG, Discriminator & Pattern Cheker
DISCR1
DOWNSC2
DELAY[4*n+3]
WIDTH[7..0]
WIDTH_R
THRESH2[4..0]
DWNSC3T_L/RDELAY[4*n+2]
DG3
32 x
31
COMPARATOR 2
0
DELAY[4*n+1]
DISCR2
IN2
modulo
0
THRESH3[4..0]
15
DELAY[4*n]
DG2
modulo
WIDTH_L
COMPARATOR 3
PATT_TRGn=0..7
Pattern Checker
DISCR3
modulo
ORMASKL
DOWN COUNTER 1
DOWNSC3
PULSER_R/L
MUX
DELAY
RESERVED
AND2
=0
16
1
WIDTH
IN[31..0] =0
31
0
AND2
SUM
DOWN COUNTER 2
THRESH3
OR_MASK2
uses ch0..24 only,see p.4
AND2
IN1
DOWNSC2[15..0]
THRESH2
OR_MASK1
DWNSC12_L/R
DG
=0
THRESH1
DISCR3
DISCR1
0
16
DG1
DOWN COUNTER 3
PATT_TRG
OR_MASK4
DISCR2
15
DELAY4*n..4n+3
IN3
DOWNSC3[15..0]
ORMASKR
AND2
6
OR_MASK3
16
15
SUM
32
DISCR4
16
THRESH1[4..0]
31
31
Delay-GateGenerators
PWIDTH
DOWNSC1[15..0]
DOWNSC1
0
OR4
DELAY[7..0]
15
COMPARATOR 1
© V. Angelov IKP Uni-Köln 05.08.2013 21
Pattern Cheker
10
15
20
9
14
19
AND any of
24
25 Terms
then OR all together
Pattern Checker
0 1 32 4
5
© V. Angelov IKP Uni-Köln 05.08.2013 22
TDC
Based on DL709 + 2 x SU704 (5xNIM/TTL)- 7 channels (start 0..6) and stop, TTL/NIM- 2.5 ns resolution- Event builder with timestamp- Multievent buffering- USB2.0 readout, C, C++ or LabView (Windows)
© V. Angelov IKP Uni-Köln 05.08.2013 23
DL711
As DL709 +- Spartan 6 FPGA XC6SLX150t with SerDes- Two SFPs- DRAM- SDCARD slot- Interface (now USB2.0) as mezzanine card- 8 slots for SUbmodule Cards
© V. Angelov IKP Uni-Köln 05.08.2013 24
SU735
Clock In
LatticeXO2 FPGAwith bootflash
SE/DIff IN toDiff OUT
very cleanclock
Data Out
I2C
A
SPI
LVDS orLVCMOS
LTC2261 orcompatible
D
LVDS orLVCMOS
diff CLK
I2C
ClockCleanerSi5338
© V. Angelov IKP Uni-Köln 05.08.2013 25
SU735 Prototype
© V. Angelov IKP Uni-Köln 05.08.2013 26
SU735 Ver1
© V. Angelov IKP Uni-Köln 05.08.2013 27
EW @ PI UNI-HD (2009)
© V. Angelov IKP Uni-Köln 05.08.2013 28
EW @ PI UNI-HD (2013)
© V. Angelov IKP Uni-Köln 05.08.2013 29
Thank You
© V. Angelov IKP Uni-Köln 05.08.2013 30
SPARESAusstattung
… at KIP
© V. Angelov IKP Uni-Köln 05.08.2013 31
Generate Top and UCF files
library IEEE;
use IEEE.std_LOGIC_1164.ALL;
use work.LogicBox_pkg.all;
entity DL709 is
Port (
CLK : in std_logic;
RES_n : in std_logic;
LED_Back : out std_logic;
-- put here the signals to the SUxxx modules
-- Slot 0 is empty
-- Slot 1 is empty
-- SU704 on slot 2
SU2_INTTL : in std_logic_vector( 5 downto 1);
SU2_OUTP : out std_logic_vector( 5 downto 1);
SU2_INECL : in std_logic_vector( 5 downto 1);
SU2_OE_n : out std_logic_vector( 5 downto 1);
SU2_LED_n : out std_logic_vector( 5 downto 1);
SU2_TERM : out std_logic_vector( 5 downto 1);
Clock, Resetand LED
SU7xx boards
DMA_Addr32
DMA_req
i/oTop oftheuserdesign
32
o
CReset
i/oCDin
DMA_Ainc
CRdy
CWR
DMA_Nwords
CDout
2
Caddr
Optional
i/oCRD
CDout
DMA_ena
32
o
o
USB Controller
Caddr
CRD
CLK
CDin
i
DMA_dsize
DMA_ack
CWR
o
16
CReset
CRdy
32
CLKi
o
DL709.vhd
top_core
usb2cbus_fx2
© V. Angelov IKP Uni-Köln 05.08.2013 32
Generate Top and UCF files
-- SU736 on slot 3
SU3_CMP_SE : in std_logic_vector( 2 downto 1);
...
SU3_SDO_DAC : in std_logic;
SU3_SCLK_DAC : out std_logic;
SU3_CS_DACn : out std_logic;
...
-- end of the SUxxx section
-- FX2
FXClk : out std_logic;
FXAddr : out std_logic_vector( 1 downto 0);
FXData : inout std_logic_vector( 7 downto 0);
FXRD_n : out std_logic;
...
FXPEnd_n : out std_logic);
end DL709;
SU7xx boards
USB Interface
© V. Angelov IKP Uni-Köln 05.08.2013 33
Generate Top and UCF filescomponent top_core is
Generic(ClkMHz : integer := 100);
Port (
CLK : in std_logic;
Reset : in std_logic;
-- put here the signals to the SUxxx modules
-- Slot 0 is empty
-- Slot 1 is empty
-- SU704 on slot 2
SU2_INTTL : in std_logic_vector( 5 downto 1);
...
SU2_TERM : out std_logic_vector( 5 downto 1);
-- SU736 on slot 3
SU3_CMP_SE : in std_logic_vector( 2 downto 1);
...
SU3_LED_NIMn : out std_logic_vector( 2 downto 1);
…
-- IF
CAddr : in std_logic_vector(31 downto 0);
CWR : in std_logic;
CRD : in std_logic;
CDIn : in std_logic_vector(31 downto 0);
CDOut : out std_logic_vector(31 downto 0);
CRdy : out std_logic);
end component;
Component declaration
CB
us
signals
SU
7xx
sig
nals
DMA_Addr32
DMA_req
i/oTop oftheuserdesign
32
o
CReset
i/oCDin
DMA_Ainc
CRdy
CWR
DMA_Nwords
CDout
2
Caddr
Optional
i/oCRD
CDout
DMA_ena
32
o
o
USB Controller
Caddr
CRD
CLK
CDin
i
DMA_dsize
DMA_ack
CWR
o
16
CReset
CRdy
32
CLKi
o
DL709.vhd
top_core
usb2cbus_fx2
© V. Angelov IKP Uni-Köln 05.08.2013 34
Generate Top and UCF files# DL709
NET "CLK" LOC = "AF14" | IOSTANDARD = LVTTL ;
NET "LED_Back" LOC = "K26" | IOSTANDARD = LVTTL ;
NET "RES_n" LOC = "G26" | IOSTANDARD = LVTTL | PULLUP ;
NET "FXRD_n" LOC = "W26" | IOSTANDARD = LVTTL ;
NET "FXWR_n" LOC = "AC14" | IOSTANDARD = LVTTL ;
NET "FXEmpty" LOC = "M26" | IOSTANDARD = LVTTL ;
NET "FXFull" LOC = "L26" | IOSTANDARD = LVTTL ;
NET "FXClk" LOC = "R26" | IOSTANDARD = LVTTL ;
NET "FXAddr<0>" LOC = "Y26" | IOSTANDARD = LVTTL ;
NET "FXAddr<1>" LOC = "AC25" | IOSTANDARD = LVTTL ;
NET "FXSLOE_n" LOC = "Y25" | IOSTANDARD = LVTTL ;
NET "FXPEnd_n" LOC = "AC26" | IOSTANDARD = LVTTL ;
NET "FXData<0>" LOC = "Y15" | IOSTANDARD = LVTTL ;
…
NET "FXData<7>" LOC = "AA12" | IOSTANDARD = LVTTL ;
# Empty slot 0
# Empty slot 1
# SU704 on slot 2
NET "SU2_INTTL<5>" LOC = "P1" | IOSTANDARD = LVTTL ;
NET "SU2_OUTP<5>" LOC = "P2" | IOSTANDARD = LVTTL ;
NET "SU2_INECL<5>" LOC = "P3" | IOSTANDARD = LVTTL ;
NET "SU2_OE_n<5>" LOC = "P4" | IOSTANDARD = LVTTL ;
…
© V. Angelov IKP Uni-Köln 05.08.2013 35
Directory tree|\_ C
|\_ SIM
| \_ USB2CBUS
| |\_ SRC
| \_ DATA
|\_ SRC
| |\_ COMMON (led.vhd, ticker.vhd, LogicBox_pkg.vhd, svn_extract.vhd …)
| |\_ USB2CBUS
| \_ TOP
|
\_ PROJECTS
|\_ DL709_2xSU704_TDC
|\_ DL709_7xSU706
|\_ DL709_8xSU704_MALU
\_ DL709_SU737_GbEth (Makefile)
|\_ C
|\_ SCRIPTS
|\_ SRC (DL709.vhd …)
|\_ SIM_TOP_CORE (Makefile)
| |\_ SRC
| \_ DATA
|
|\_ REPORTS (cleared before compilation)
\_ other temporary…
(controller_va.vhd, FX2.vhd, FTDI245n.vhd, usb2cbus_fx2.vhdusb2cbus_ftdi.vhd, VME2CBUS.vhd)(Templates DL7xx.vhd)
(DL709.ucf|.xst, DL709_files.txt, bitgen.ut,xprog.cmd, xprog_flash.cmd)
Top Related