[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]] [My Notes on CH-13[OP-AMP]-> PHASE-LOCKED-LOOP[PLL] OR ANALOG-PHASE-LOCKED-LOOP[A-PLL]] PHASE-LOCKED-LOOP = DIGITAL-PHASE-LOCKED-LOOP[D-PLL] + ANALOG-PHASE-LOCKED-LOOP[A-PLL] , its an important course for bio-medical instrumentations , MY BLOG ON BIO-MEDICAL ENGINEERING COURSES IS HERE --> www.medical-image-processing.blogspot.com , Operational-Amplifiers Text Book--> Fundamentals-Of-Operational-Amplifiers And Linear Integrated Circuits By Howard M. Berlin And Frank C. Getz, Jr. MAXWELL MACMILLAN , INTERNATIONAL EDITIONS .
2013
MUHAMMAD-SIKANDAR-KHAN-LODHI BIO-MEDICAL ENGINEERING GUIDE.INC
1/11/2013
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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PHASE-LOCKED-LOOP[PLL] OR ANALOG-PHASE-LOCKED-LOOP[A-PLL]:-
INTRODUCTION: the Phase-locked-loop is now a very sophisticated electronic network, which will
used for such following applications,
1. Motor-speed control,
2. Touch-Tone[DTMF] DECODER’S ,
3. MODULATION/De-Modulation[MODEM],
4. Filtering,
5. Frequency-scaling,
6. Frequency-control of electronic-communication-equipment,
7. Measuring frequency of Physiological-events such as Respiration or Heart-rate.
13-1 ) THE BASIC PRINCIPAL OF PLL:
VCO=> voltage controlled oscillators [VCO].
i. THE PHASE-DETECTOR {MIXER OR PHASE-COMPARATOR}:-
{V0 = ERROR-VOLTAGE}
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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V0= its an average [DC] o/p voltage that is proportional to the difference in frequency [ fin-f0 ]
and phase-difference [ ] between [b/w] the i/p-signal [Vin] of PLL and the O/P of the VCO-
SIGNAL [ Vo’ ] with frequency [ fo ] . so
{V0 = ERROR-VOLTAGE= }
{
}
[
]
VOLTAGE-CONTROLLED-OSCILLATOR [VCO] :
[KVCO = VCO-Conversion- gain [Hz/V] ].
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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[fmin = out put frequency when [ Vin=0] ] ;
Well we study the VCO in Ch # 12 , Op-Amp course is as a “Voltage to frequency Converter”,
VCO convertes the controlled-voltage into a frequency [Pulsed-wave form]
VCO out-put frequency fo is proportional to the magnitude of the in-put voltage of VCO;
VCO conversion gain KVCO relates fo to input voltage of VCO as followed equation; [i-e]
[ ]
THE LOOP-FILTER=LOW-PASS-FILTER[LPF]:
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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LPF [low pass filter] remove any noise and high frequency components from the out-put
voltage Vo of the “Phase-detector”, resulting in an average DC control voltage, that drives the
VCO.
It’s the primary building blog that determines the dynamic performance of the loop-covering
the following factors,
a. Capture and lock ranges;
b. Band-width;
c. Transient-response;
Key-> the complete [PLL] system exhibits the characteristics of a second-order system [ Analogous to
the transient behavior of a swinging pendulum or vibrating string;
[ Radian-frequency-> [ ] ];
[ ]; it’s a decibel-response of a
second-order-system .
[ ]
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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If [ ], then we have a sinusoidal-oscillator;
-------------------
[new-topic]
BASIC-OPERATION-OF-“PHASE-LOCKED-LOOP [PLL]”:
In operation, the “”Phase-Locked-Loop” is in any one of the following three distinct states:
1. Free-running-state;
2. Capture-state.
3. Phase-Lock-state.
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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If we assume that initially the “Phase-locked-Loop” has no input signal, the VCO then runs at
its “Free-running-frequency”, which is set by either an external RC-filter or LC-filter network ,
here the loop is said to be un-locked.
When an input signal is applied to the phase-detector and the VCO frequency starts to change
in a direction that reduces the frequency difference b/w the VCO-freq [fVCO ] input freq [fin ] ,
then the loop is said to have Acquired-capture and is now in the “capture-state”.
The fin and fo are not equal [ ] , but in time they will be equal [ ].
In order for a “Phase-Locked-Loop” that is initially un-locked to respond to an input signal and
then be in capture state.
The frequency of the input signal must be with in a narrow frequency-range called the
“capture-range” , which is set by the response-parameters of loop circuit , if fin is out-side this
capture-range, the loop will never acquire-capture and the fo of the VCO will equal its free-
running frequency.
On the other hand, if the fin is within the loops capture-range, then the VCO frequency [ fo =
fVCO ] start to change in a direction that reduces the frequency difference between the VCO-
frequency [ fo = fVCO ] and input frequency[fin].
The capture-range is often specified as percentage of VCO free-running frequency so, that the
free running frequency is within this capture-range.
For-example: consider a system-> [ fin{PLL}fo ] , [Capture-range=Cr ] Given:-> [ Capture-range[ Cr’
] = ± 2 % = ± 0.02 = ± Cr’ ]; of a [ free-running-frequency = 1250 Hz = ffR ]; so,
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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[
]
[ ];
So,
[ ];
[ ]
[ ] its for “Loop” will Acquire Capture .
[ ] then the
loop will Acquire-Capture.
If the [
], then the loop will Acquire-Capture, and the VCO-Frequency fo will then shift to
equal that of the input frequency fin [ fo = fin ] .
Otherwise, the output frequency fo of VCO will remain at 1250 Hz for those [ fin < 1225 Hz ]
and [ fin > 1275 Hz ].
In general-case:-
[
];
When the loop Acquire capture, the fin and fo of PLL are not equal, however, the process is
repeated many times going around the loop, the fin and [ fo=fVCO ] are comparedby phase-
detector, its DC-output voltage is proportional tothis frequency difference, after filtering
through [ LPF =low pass filter ] , this frequency-difference drives the VCO whose output
frequency tries to get closer to input frequency.
PHASE-LOCKED: Eventually the loop will reach the situation where the VCO’s frequency fo
and the loops input frequency fin are exactly equal [ fin = fo ] except for a possible phase-shift,
when the input[Vin] and output [Vo] signal have exactly the same frequency, except for a
given phase-shift, the loop is then said to be locked or “Phase-locked”.
The Phase-shift, if any occers because the Vco is Asynchronous with the input-signal if there is
no input signal , the VCO runs along at its own pace [ i-e, its free-running frequency ] , when
the loop receives an input signal, its then Asynchronous with the VCO-signal.
SETTLING-TIME: Because of the loops transient-behavior, it takes a finite Amount of time for
the loop , once it acquires capture, to become locked, this is known as “Settling-Time”.
In a well designed “Phase-Locked-Loop-System” this may be on the order of several milli-
seconds, hence the transition from being an unlocked loop to acquiring capture and becoming
locked may appear as a virtually instantaneous-process.
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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Once locked, the input frequency fin can change with in certain limits, and the VCO’s output
frequencies fo will follow this change.-> [ ].
When fin changes even slightly, the phase-detector, then senses this frequency-difference and
the shifting process starts all over again until the [ ] and fin are exactly the same [
except for a possible-phase-difference ] .
LOCK [ OR HOLD-IN ] RANGE :- Once locked, the input frequency range over which the VCO
can track is called as “Lock [or hold-in ] Range ”.
As with the loops “Capture-range”, the “Lock[or hold-in]Range” is often specified as a
percentage of VCO’s “free-running-frequency [ ffR ] ” and is always wider then the “capture-
range” . -> [ Lock{or Hold-in} Range Capture-range ] .
Once the loop has acquired capture and phase-lock, if the fin then shifts to a frequency
outside the “lock-range”, then the loop immediately loses “Phase-lock” and the -> [fo = ffR(VCO)
].
[ ];
For the loop to again be “Phase-Locked”, the “new input signal ” then has to be with in the
loop’s capture-range to start the cycle all over again.
----------------------------------------
[13-2 ] THE “FREQUENCY-SYNTHESIZER” OR “FREQUENCY-MULTIPLIERS”:
A “Frequency-Synthesizer [or Multipliers]” is a frequency source whose output is an integer-
multiple of an input reference frequency. In its simplest form its nothing more than a
frequency multiplier and is now an important building block in many communication’s
system’s.
The basic-frequency synthesizer is formed by breaking the feed back path between the VCO
and “Phase-detector” of the basic PLL and inserting a “divide by Nth counter”.
Example:
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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In addition, the input-signal reference is Obtained from a very stable crystal-controlled
oscillator in [ 1M Hz –to --> 10M Hz ] range.
TTL-Based crystal controlled frequency reference from [ 1M Hz ---to- 10M Hz ].
The VCO output frequency [ fo = N.fREF(IN) ] is Nth times greater then input reference frequency [
fREF (IN) ] .
The output signal of VCO with [fo=N.[fREF[IN]] ], is then fed to divided by Nth-Counter, which
produces one output pulse for every Nth inputs pulses of clock to ÷ N counter.
The counter’s Modulus [N] may be either fixed or programmable through [via ] thumb-wheel
switches in BCD [binary coded decimal] formate.
The output frequency of counter fc is then [ fc=fo/N ];
÷ Nth counter output frequency fc = fc = [
].
÷ Nth-Counter Out put frequency[fc ] = fc = fREF(IN) .
When the loop is “Phase-locked” , the frequencies of two input of phase-detector are equal,
except for a possible phase-difference.
In communication’s systems , practical-synthesizer’s generally have their output frequency [ fo
] in { } range [ VHF & UHF ] , however, synthesizers are capable of
working with low-frequency signals in Audio-frequency range [ 20 Hz --- to 20 K hz ] .
Very often, a frequency-synthesizer will be used to increase the resolution of a frequency-
counter by a factor of 10 or 100 with out increasing the sampling or display up-date time.
Most counters use a sampling or display up-date time of 1’s . in order to obtain a resolution of
one more decimal place, the frequency-counter must then be set to have a sampling or
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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display up-datetime of 10-seconds, which will take 10time longer to display the input
frequency;
In this 10-seconds interval, the input signal might change frequency-slightly and give
erroneous-readings.
Instead of using a very stable fREF(IN) , the frequency that would otherwise be measured by
frequency-counter is now fed to input of the synthesizer. The frequency counter is connected
to output of VCO and reads either 10 or 100 times larger that the input signal [ fig # 7 ] ,
forexample : a frequency-counter measures a given signal and indicates a frequency of 974 Hz
because of typical ( ± 1 ) count error inherent to all digital-display, the actual input frequency
could be between [ 973 Hz & 975 Hz ] .
To achieve a greater resolution, a ( x 10 ) synthesizer is placed between the frequency source
and frequency-counter.suppose, the counter reads 9746 Hz the actual input frequency is then
[ 9746 Hz/10 = 974.6 Hz ] , {Actually the frequency will be b/w 974.5Hz and 974.7 Hz } , as
mentioned earlier, we could set the frequency-counter to have a sampling or display time of [
10 second ] in order to produce the extra decimal place, but it would take ten times longer to
display the fin .
Using the synthesizer method , the extra time lag is eliminated. All that is necessary is
mentally to divide the displayed frequency by 10 [ or 100, if need be ] to obtain the correct [
input frequency fin = fREF(IN) ].
-------------------------
ANALOG-PHASE-LOCKED-LOOP [ A-PLL ] { 560-SERIES ] :[NEW-TOPIC]:
There are 560-series of PLL in which [ Vo(VCO] = SQUARE-WAVE ] in all cases of 560-series [
560B, 561B, 562, 564, 565, 566 and 567 ) .
1. 560B-PHASE-LOCKED-LOOP [PLL] OR “FM-DEMODULATOR” :-
560-series [ Analog-PLL ] -> [ 560B, 561B, 562, 564, 565, 566 & 567 ).
The devices in 560-series are commonly referred to as “Analog-Phase-locked-loops” and
they are differ from “digital-phase-locked-loops”.
When locked onto an input signal , two useful output are provided, that is
1) 1st , an output voltage that is proportional to frequency of incoming signal
is available at [ pin # 9 ] as the de-modulated FM output.
2) 2nd, output is square-wave output signal of the VCO.
The value of external capacitor, connected between pins 2 & 3 , sets the VCO free-
running frequency According to [
].
The 560B is used primary as an FM-De-Modulator.
The VCO is adjusted by Co to the center-frequency of the FM-signal.
For most applications , the pair of loop-filter capacitors [ C2 and C1 ] can be calculated
as let, -> [
].
Where [ f3(dB) ] is the desired [ 3-dB ] band-width of the “De-modulated-information”.
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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FM-DEMODULATOR-USING-A-560B [ PLL-IC ] :-
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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----------FINISHED HERE -----------
561B PHASE-LOCKED-LOOP OR AM-RECIVER OR FM-DE-MODULATOR :-
The 561B-PLL is identical to 560B except that it includes an additional phase-detector, which
allows the device to be used as a synchronous AM-detector as well as an FM-demodulator.
The demodulated FM output at [Pin # 9 ] is an output voltage that is a function of the
frequency deviation of input signal.
For a [ ± 1 % ] deviation, the output is approximately [ 0.3 v ] peak-to-peak [ 0.11 VRMS ] .
As an example, a standard 10.7 M Hz IF [intermediate-frequency ] circuit has a deviation of
approximately [ ± 75k Hz ]. The percent[%] deviation is then
[
] consequently, the output voltage swing is
[formula for Vo->
],[ for Vo->
];
---------------------
AM-RECEIVER [OR AM-DETECTOR ] WITH “561B[A-PLL]”:-
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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--------
AM-RECEIVER [ WITH 561B [PLL-IC]:-
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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This AM-Receiver unlike other AM-Receivers requires no capacitor-Inductor tank circuit for
tuning, instead, the [ 365pF = CT ] “Tuning-capacitor[CT]” between pin-2 and pin-3 is Adjusted
to make the VCO oscillate at the carrier-frequency of station to be received.
To operate, the receiver circuit requires an out-side Antenna and a good ground, in addition
sufficient signal [ input] must be present at input of the phase-locked-loop[PLL], otherwise a
“Swishing” sound may result, which is due to the frequency difference between the incoming
carrier and the VCO when the “loop-lock” is un-stable.
Another draw-back to this simple circuit is the “hand-Capacitance” effect as a result of non-
grounded capacitive tuning of VCO, one remedy for this problem is to use a Vernier dial and
an insulated shaft on the tuning capacitor.
Furthermore, the circuits operation may be enhanced by using an un-tuned broad-band
Amplifier ahead of the receiver to increase sensitivity while limiting input[I/P]-signal levels to
less than [0.5 VRMS ] .
----------------------FINISHED-------
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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562 PHASE-LOCKED-LOOP[PLL] AS A “FREQUENCY-MULTIPLIER/OR FREQUENCY-
SYNTHESIZER”:-
The [562-PLL] is similar to 560B, except that the internal-connection between the VCO output
and the phase-detector is broken [or dis-connected ].
Thus, two external connection are provided which allow for insertion of TTL[Transistor-
Transistor-Logic]-counters to be placed in feed-back path for frequency-synthesis .
FREQUENCY-MULTIPLIER [OR SYNTHESIZER ] :-
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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÷ NTH MODULE-COUNTER :-
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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Note: for further detail about counter circuits please read the counter chapter from DLD-III [Digital-
Logic-design , part-1 and 2 ] section from my blog -> www.medical-image-processing.blogspot.com
-----------part-1 finished here--------
2/2/2013
XMUHAMMAD-SIKANDAR-KHAN-LODHI
OWNER OF MY PERSOLAL NOTES
[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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[{ANALOG} “PHASE-LOCKED-LOOP[A-PLL]” [ Part-1-of- ]]
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