Download - Ouroborus Doc Nm

Codex Ouroborus

By Karl Lautman

1/01 - 6/01

Copyright 2001 Karl Lautman

Ouroboros: emblematic serpent of ancient Egypt and Greece represented with its tail in its mouthcontinually devouring itself and being reborn from itself. A Gnostic and alchemical symbol, Ou-roboros expresses the unity of all things, material and spiritual, which never disappear but perpetu-ally change form in an eternal cycle of destruction and...

Description

A circle of 40 dominoes, approximately 13” in diameter, arranged atop a square base approximately 6” high. A single cordprovides wall power (110V AC). There is a single momentary pushbutton on the front of the base. Pressing the buttoncauses an activation mechanism to topple the first domino, triggering the familiar chain reaction. When half the dominoeshave fallen, the initial ones begin to right themselves, in order, creating a continuous wave of falling and rising dominoes.After five cycles all the dominoes are righted, ready to go again with the next press of the pushbutton.

Principle of Operation

Each domino has two holes drilled in its base. Into each hole are attached the ends of a loop of polyester thread. Eachloop is threaded through a corresponding hole in the surface on which the dominoes stand. The two loops are attachedto the plunger of a solenoid directly beneath each domino (one solenoid per domino). After waiting a few moments afterstarting the cascade, a circuit stored in an FPGA energizes the solenoid for the first domino, pulling on the loops, standingit up. A short time later the solenoid for the second domino is fired, and so on until the 40th solenoid.

A counter within the FPGA keeps track of each cycle. When it gets to five, the unit turns itself off by opening a normallyclosed relay, killing power to the rest of the machine; the pushbutton activates a normally open relay which powers theunit up, and is wired so as to bypass the pushbutton, latching itself on.

In the event all the dominoes are lying down at start-up (due to transportation, nudging, etc.), the unit will simply rightthem all on the first cycle, then hum as it completes the remaining four cycles, and turn itself off, reset and ready to go.

Development and Implementation

There were a number of questions at the start of the project:

1. What material should be used for the loops? It must be strong, flexible, and wear-resistant due to friction caused byrubbing against the holes it would pass through.

Fishing line was tested first as this is readily available in a wide variety of strengths. It was soon apparent, however,that line that was strong enough to not stretch was too stiff to allow a domino to fall naturally. Kevlar was found tobe sufficiently flexible and strong.

2. What adhesive should attach the loops to the dominoes? It, too, must be strong, but low viscosity, to flow into theholes.

Epoxy was adequate for one or two dominoes, for experimentation, but its viscosity led to lots of mess requiring toomuch cleanup to be practical for dozens of dominoes. UV-curable adhesive was considered but dismissed since theholes it would be injected into, at .0625” diameter by about .5” deep, would be too narrow and deep for the UV topenetrate sufficiently. Loctite 401 super glue was adopted after being recommended by Loctite. The glue is injectedinto a hole using a fine tip attached to the glue’s squeeze bottle, and then the ends of the loop are inserted and heldin place for a few seconds. A light tug tests the bond, which, while strong right away, reaches full strength in 24hours.

The photo above shows the jig used to hold a domino while drilling the two holes in its base.

3. How much force is required to right a domino? This would determine the solenoids to be used.

Two holes were drilled in a small board allowing one domino to be set up, with its loops threaded through, andtipped over to rest on an adjacent domino as would be the case in the ouroborus (considerably more force would berequired to right a domino lying flat). A small container was attached to the loops and washers added one by one tothe container. When the domino finally stood up, the container was weighed. The weight was the required force.

4. How would the dozens of holes through which the loops would pass be drilled with the requisite precision?

A jig using a lazy susan would be bolted to the stage of a drill press, with the board on which the dominoes wouldstand screwed to, and centered on, the lazy susan. A pencil would be placed in the chuck of the drill press and thestage raised until the board was in contact with the pencil. Then the board would be slowly spun through 360 de-grees, causing a circle to be drawn on it. A second, concentric circle, with .5” greater radius (the holes in the domi-noes in which the loops are glued are .5” apart, drilled with the aid of the jig, below) would be drawn in the sameway. Radials would be drawn with a straight edge out from the center to intersect the circles. The intersectionswould mark where to drill, after replacing the pencil with a .0625” bit.

Two limits arise from this approach. One is the size of the board, since the corners of a sufficiently large board wouldcontact the pillar supporting the drill press, preventing the board from turning (see figure on next page). The otheris the number of radials (which is the number of dominoes). This number must be a “simple” divisor of 360, sincedependence on a protractor for odd angles is unreliable over the distances and quantities of radials envisioned. E.g.,it’s easy to divide a circle into four parts with just a straight edge and square (and knowledge of the center). It’s notso easy to divide it into five parts.

7 x 16

1.625

5

1

7.5

Domino

boa

rd

19.6

25 x

19.

625

x (.7

5)

Drill presspillar

Drill pressstage

Base of jig attached tostage

Lazysusan

The above figure shows the relationship of the board, lazy susan drilling fixture, and drill press, from above.

The above photo shows the lazy susan tool attached to the drill press.

This photo shows drilling in progress, with the inner circle barely visible.

5. How many dominoes should be used, and how far apart should they be spaced? This would determine the final sizeof the machine.

Based on the considerations from 4., above, 32, 40, and 48 radials were tested on circles with diameters of 11.51”,14.057”, 17.265”, and 17.571”; these diameters result from the selection of domino spacings of .75” and 1”. The cir-cles were drawn concentrically on a large sheet of paper, along with the radials, and dominoes set up by hand on onecircle and radial set at a time. They were then knocked over and their falling timed and videotaped. The tape waslater watched to see if there might be any problems with the patterns the dominoes made as they came to rest.

Nothing came from these tests that definitively argued in favor of one layout over another. The design was fixed at 40dominoes as a compromise between size (the bigger the better) and cost (solenoids are about $10 each). A 14.057”circle was chosen as this would result in the largest board (after adding margin) that would fit under the drill press.This also results in the closest possible spacing between the dominoes (.75”) due to the width of the solenoids andtheir associated mounting brackets.

.87 x 1.125 14.888 dia., 46.772 circ.

15.888 dia., 49.914 circ.

8.5 x 8.5

19.625 x 19.625 x (.75)

Inner radius = 7 7/16 = 7.438

7.438

Dist. from one inner hole tothe next = 1.168 = 1 11/64

9 deg.

4.5 deg.

7.438

sin (opp./hyp.) 4.5 deg. = .0785, so a =7.438 x .0785 = .584 = 1/2 of distanceto next hole. Total distance = 2 x .584= 1.168.

a

PCB6 x 4.625

5VD

C

The above figure show the arrangement of the dominoes (small rectangles) on the board, with the two outermost ci r-cles indicating where the loop holes will go. Also shown are the solenoids (squares with solid circles at their center),

the solenoid mounting brackets (large rectangles), and starting solenoid in the upper left.

This photo shows a lone solenoid mounting bracket, as well as one installed in the jig used for precisely drilling holesin its long (solenoid mounting) and short (board attachment) legs. The jig is bolted to the drill press stage when in

use.

This photo shows a test fixture used to determine the effect of the weight of a solenoid plunger (washers) pulling on each dominoon the speed at which the dominoes fall, as well as their resting orientation.

6. How durable should the machine be? A minimum life expectancy of 10,000 up/down cycles/domino (correspondingto 2,000 button pushes) was arbitrarily selected. How would this limit be tested?

A test stand with one domino and two solenoids was built. One solenoid knocked the domino over (see 7., below)and the other stood it up again, as described earlier; a complete cycle took about 1.5 seconds. An optical sensor at-tached to the solenoid plunger detected when the domino fell. A Basic Stamp microcontroller was used to controlthe solenoids and monitor the sensor. Unfortunately, this piece of equipment was cannibalized for parts before be-ing photographed.

The first test ran for 22 cycles before one of the reed relays driving one of the solenoids fused due to being overpowered. Suitable MOSFET transistors were located to drive the solenoids and the test repeated. This time it ran for872 cycles when the Kevlar thread used for the loops wore out due to abrasion with the holes in the board. The Kev-lar was replaced with polyester thread and the test repeated. It ran for 9,687 cycles when a piece of the thread retain-ing the plunger in the starter solenoid gave out. Since this greatly exceed the life requirement for the starter, and theloops were holding up well, the test was deemed a success, leading to the selection of polyester thread for the loopsand MOSFET transistors for the drive electronics.

7. How should the cascade be started? A manual push by the user was deemed too unreliable. Also, provision shouldbe made for operation under a clear, Plexiglas cover to prevent dust accumulation. Some consideration was given toa rotating arm attached to a small pylon beside the domino that would be the first to fall. The arm would rotate in avertical plane, contacting the top 1/3 of the domino, knocking it over, then returning to its resting position above thedomino ring. After experimentation, this was deemed too complicated and unreliable.

The final mechanism, shown below, uses a horizontal thread anchored at one end and attached to a horizontal sole-noid at the other. A small, vertical wire rests on the bite of the thread. When the solenoid is activated, the threadgoes taught, shoving the wire up through a hole in the board. The hole is midway between the two loop holes, butnot in line with them, so the wire provides an off-center impetus to the base of the domino, knocking it over.

1

1.5 x 2.125 x (.25)

.5

1

1.2"

This figure shows the starting mechanism beneath the first domino.

8. How long should each solenoid be activated? While some minimum activation time would be required to right adomino, in practice the solenoid would have to be active somewhat longer since the rising domino’s momentumwould carry it past the upright position. If the solenoid were released prematurely, the domino would collide withits predecessor, possibly knocking it backward and starting a second wave in the opposite direction. On the otherhand, if the solenoid were active for too long, the “falling-down” wave would catch up to the domino and die, as thedomino would not fall over (being held in place by the solenoid). This effect would actually be used to stop the cas-cade the end of a run.

A test stand with two dominoes and two solenoids for righting them was built (see photo below). It was controlledagain by the Basic Stamp, which allowed quick and easy changes to the activation time of the solenoids, as well as thedelay between the first and second solenoids. The dominoes are knocked over manually.

This photo shows the two-domino test setup.

Solenoid power supply

Basic Stamp

Test stand

Solenoids

The above photo shows the Basic Stamp, rotated from its orientation in the previous photo.

(19.625) x (19.625) x .75

1.25

1.125

3

2 screws: M4 x .7, 6 mm long(must be zinc)2 lock washers, >.15" dia.

Rear viewTail on other

side

3

.87

1.72

.5

.437 (7/16)

11/64

(19.625) x (19.625) x .75

2 tapped holes:M4 x .7

2 tapped holes:M4 x .7, .75"centers

Sensor:Omron EE-SX670w/ EE-1006connector andcable attached (notshown).

20th solenoid

Total thread/loop:2(.5 + .75 + .91) = 4.32 = 45/16.For 80 loops, cut 5 lengths,69.125" long. Cut eachlength in half 4 times, for 16lengths of 4.32".

.75

.3

1.5

1

.15

3/16

.25

2 M4 x .7,10 mmscrews

2 M4 x .7, 9 mmscrews

2 untapped holes, locationand size as needed for

proper sensor opperation.

Tail from mountingbracket

.875

.5

.75

.91

Polyester thread, trade size138, .023" dia., McmAster-Carr part # 87635K78

MagneticSensor SystemsS-17-85-39QH

Cableconnector

Attach to solenoid with .75"of paper clip wire.

Single #8 x 5/8 self-tappingscrew into .125" hole inwood.

.156

MagneticSensor SystemsS-17-85-39Q

Magnetic Sensor Sysstems SP-10 return spring, cut to .25"height when compressed underplunger, solenoid inactive.

3/16

2 M4 x .7, 9 mmscrews

Domino

.5

This figure displays various details of the solenoid mounting bracket. The modifications for the optical sensor onthe right side were discarded when it was determined the sensor was unnecessary. It was to be used on the 20th

domino to trigger the cascade, but a time delay was deemed more reliable.

20.375"

19.75"

3.625

.75

.25.25

.5

.5

5.875"

25/32"

.5"

.5"9/32"

13/32"

23/32"

13/32"

Requires 80.25" of 3/4" x 5 7/8" stock19.625" x 19.625" of 1/4" masonite

Masonite

1.25"

1.23"

1.06" 1.25"

Power inlet hole (rear)

2 15/16"

10 3/16"

Pushbutton hole (front)

Exterior

Interior

.5"

.75"

3/16"

This figure shows details of the cabinet in which the ouroborus is mounted. The stack of boxes near the left edge of the bottom drawing illustratesthe vertical relationship of the various components of the piece to determine the minimum height of the cabinet.

Principal of Logic Implemented in FPGA (see following diagrams)

A 10 MHz clock is divided by 400,000 (by CLK_DIV) to yield a 40 ms internal clock; this is roughly the speed with whichdominos fall and, therefore, the speed with which they must be stood up for things to stay in sync. On power-up, theCNT25 counter begins counting clock ticks. While its output is less than 8, the LT_8 comparator outputs a 1, activatingthe start solenoid for 320 ms, knocking over the first domino. When CNT25 gets to 25, its terminal count output disablesits own clock, freezing the counter. The same output enables the L1 counter. While L1 is less than 10, comparator LT_10outputs a 1 which is fed into the LSB of the SHIFT_40 serial in/parallel out shift register. This causes a 1 to be shifted intoSHIFT_40 for 10 consecutive clock ticks commencing with the 25th tick. This block of 10 1s then circulates through, andout of, SHIFT_40 as L1 counts to 39, at which point L1 resets itself to 0 and starts over. Each output bit of SHIFT_40drives a solenoid, so the rotating block of 10 1s causes each solenoid to turn on for 10 x 40 ms = 400 ms. The LSB ofSHIFT_40’s output clocks the CNT6 counter. When it gets to 6, its terminal count clocks the FD flip-flop, outputting theoff signal.

Solenoid power is provided by a relay driven by the SOL output. This ensures that no power is provided to the solenoidsuntil configuration of the FPGA is complete. Otherwise, they all might turn on for 40 - 50 ms during configuration, apply-ing an extreme load to the power supply.

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

E E

F F

G G

H H

Zero Point Studios1052 N. Clark Ave.

Mountain View, CA 94040

Project: OURBORUSSheet: OURBORU4_1

Date: 3/14/01

Date Last Modified: 6/10/1

DIV_BY_400K

CLK_DIV

CLK_OUTCLOCK

SHIFT_40

SHIFT

LS_IN

Q_OUT[39:0]

CLOCK

AND2

LT_10

COMPARE

C

A[7:0]

A_LT_B

IBUF

OBUF

L1

COUNTER

Q_OUT[7:0]

CLOCK

CLK_EN

BUFG

CNT6

COUNTER

Q_OUT[3:0]

TERM_CNTCLOCK

CLK_EN

FD

C

D Q

LT_8

COMPARE

C

A[7:0]

A_LT_B

INV

OBUF

CNT25

COUNTER

Q_OUT[7:0]

TERM_CNTCLOCK

CLK_EN

INV

AND2

INV

VCC

Q_OUT[39:0]

CNT5_OUT[3:0]

CLK_OUT

Q_OUT0

OFF

CLK

START

Q_OUT8

Karl Lautman

This is the principal logic of the ouroborus, contained in the FPGA (Xylinx XC4005XL-3PC)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

A A

B B

C C

D D

E E

F F

G G

H H

Zero Point Studios1052 N. Clark Ave.

Mountain View, CA 94040

Project: OURBORUSSheet: OURBORU4_2

Date: 3/14/01

Date Last Modified: 6/10/1

This block keeps the 1st domino standing at the end of

the run to keep the last domino from knocking it over.

This block applies power to the last domino whenever the 1st one is raised,

to keep the last one from being knocked over by the recoil from the 1st one.

Turn on solenoi power as soon as logic is configured.

OBUF

OR2

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUF

OBUFOR2

OBUF

OBUF

GND

AND2

Q_OUT[39:0]

Q_OUT[39:0]

Q_OUT39

SOL_01

SOL_02

SOL_03

SOL_04

SOL_06

SOL_05

SOL_35

Q_OUT1

Q_OUT2

Q_OUT3

Q_OUT4

Q_OUT5

Q_OUT6

SOL_11

SOL_08

SOL_09

SOL_10

SOL_07Q_OUT7

Q_OUT8

Q_OUT9

Q_OUT10

Q_OUT11

Q_OUT32

Q_OUT33

Q_OUT34

Q_OUT35

Q_OUT36

Q_OUT37

Q_OUT38

Q_OUT12

Q_OUT13

Q_OUT14

Q_OUT15

Q_OUT16

Q_OUT17

Q_OUT18

Q_OUT19SOL_19

Q_OUT20

Q_OUT21

Q_OUT22

Q_OUT23

Q_OUT24

Q_OUT25

Q_OUT26

Q_OUT27

Q_OUT28

Q_OUT29

Q_OUT30

Q_OUT31

SOL_12

SOL_13

SOL_14

SOL_15

SOL_16

SOL_17

SOL_18

SOL_30

SOL_28

SOL_27

SOL_24

SOL_22

SOL_25

SOL_26

SOL_23

SOL_00

SOL_21

SOL_39

Q_OUT0

SOL_29

SOL_31

SOL_38

SOL_34

SOL_37

SOL_32

SOL_36

SOL_33

SOL_20

SOL

CNT5_OUT0

CNT5_OUT2

Karl Lautman

This is the remainder of the FPGA logic.

Logic Waveforms

0.0 1.02s 2.04s 3.06s 4.08s 5.1s 6.12s 7.14s 8.16s 9.18s

l CLK_OUT........

o START..........

o OFF............

o SOL_00.........

o SOL_01.........

o SOL_02.........

o SOL_03.........

o SOL_04.........

o SOL_05.........

o SOL_06.........

o SOL_07.........

o SOL_08.........

o SOL_09.........

o SOL_10.........

o SOL_11.........

Logic Waveforms

0.0 1.02s 2.04s 3.06s 4.08s 5.1s 6.12s 7.14s 8.16s 9.18s

o SOL_12.........

o SOL_13.........

o SOL_14.........

o SOL_15.........

o SOL_16.........

o SOL_17.........

o SOL_18.........

o SOL_19.........

o SOL_20.........

o SOL_21.........

o SOL_22.........

o SOL_23.........

o SOL_24.........

o SOL_25.........

o SOL_26.........

Logic Waveforms

0.0 1.02s 2.04s 3.06s 4.08s 5.1s 6.12s 7.14s 8.16s 9.18s

o SOL_27.........

o SOL_28.........

o SOL_29.........

o SOL_30.........

o SOL_31.........

o SOL_32.........

o SOL_33.........

o SOL_34.........

o SOL_35.........

o SOL_36.........

o SOL_37.........

o SOL_38.........

o SOL_39.........

PAR: Xilinx Place And Route C.16.Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.Sun Jun 10 16:04:48 2001

Xilinx PAD Specification File*****************************

Input file: map.ncdOutput file: ourborus.ncdPart type: xc4005xlSpeed grade: -3Package: pc84

Sun Jun 10 16:04:48 2001

Pinout by Pin Name:+------------------------------------------------+-----------+--------------+| Pin Name | Direction | Pin Number |+------------------------------------------------+-----------+--------------+| CLK | INPUT | P13 || OFF | OUTPUT | P56 || SOL | OUTPUT | P14 || SOL_00 | OUTPUT | P29 || SOL_01 | OUTPUT | P28 || SOL_02 | OUTPUT | P27 || SOL_03 | OUTPUT | P26 || SOL_04 | OUTPUT | P25 || SOL_05 | OUTPUT | P24 || SOL_06 | OUTPUT | P23 || SOL_07 | OUTPUT | P20 || SOL_08 | OUTPUT | P19 || SOL_09 | OUTPUT | P18 || SOL_10 | OUTPUT | P9 || SOL_11 | OUTPUT | P8 || SOL_12 | OUTPUT | P7 || SOL_13 | OUTPUT | P6 || SOL_14 | OUTPUT | P5 || SOL_15 | OUTPUT | P4 || SOL_16 | OUTPUT | P3 || SOL_17 | OUTPUT | P84 || SOL_18 | OUTPUT | P83 || SOL_19 | OUTPUT | P82 || SOL_20 | OUTPUT | P70 || SOL_21 | OUTPUT | P69 || SOL_22 | OUTPUT | P68 || SOL_23 | OUTPUT | P67 || SOL_24 | OUTPUT | P66 || SOL_25 | OUTPUT | P65 || SOL_26 | OUTPUT | P62 || SOL_27 | OUTPUT | P61 || SOL_28 | OUTPUT | P60 || SOL_29 | OUTPUT | P59 || SOL_30 | OUTPUT | P50 || SOL_31 | OUTPUT | P49 || SOL_32 | OUTPUT | P48 || SOL_33 | OUTPUT | P47 || SOL_34 | OUTPUT | P46 |

| SOL_35 | OUTPUT | P45 || SOL_36 | OUTPUT | P44 || SOL_37 | OUTPUT | P40 || SOL_38 | OUTPUT | P39 || SOL_39 | OUTPUT | P38 || START | OUTPUT | P37 |+------------------------------------------------+-----------+--------------+| Dedicated or Special Pin Name | Pin Number |+------------------------------------------------------------+--------------+| /PROG | P55 || CCLK | P73 || DONE | P53 || GND | P21 || GND | P43 || GND | P52 || GND | P64 || GND | P76 || GND | P31 || GND | P12 || GND | P1 || M0 | P32 || M1 | P30 || M2 | P34 || TDO | P75 || TDO | TDO || VCC | P2 || VCC | P63 || VCC | P11 || VCC | P22 || VCC | P54 || VCC | P42 || VCC | P33 || VCC | P74 |+------------------------------------------------------------+--------------+

Pinout by Pin Number:+--------------+-----------------------------------+-----------+------------+| Pin Number | Pin Name | Direction | Constraint |+--------------+-----------------------------------+-----------+------------+| P1 | (GND) | | || P2 | (VCC) | | || P3 | SOL_16 | OUTPUT | LOCATED || P4 | SOL_15 | OUTPUT | LOCATED || P5 | SOL_14 | OUTPUT | LOCATED || P6 | SOL_13 | OUTPUT | LOCATED || P7 | SOL_12 | OUTPUT | LOCATED || P8 | SOL_11 | OUTPUT | LOCATED || P9 | SOL_10 | OUTPUT | LOCATED || P10 | --- | UNUSED | || P11 | (VCC) | | || P12 | (GND) | | || P13 | CLK | INPUT | LOCATED || P14 | SOL | OUTPUT | LOCATED || P15 | --- | UNUSED | || P16 | --- | UNUSED | || P17 | --- | UNUSED | || P18 | SOL_09 | OUTPUT | LOCATED |

| P19 | SOL_08 | OUTPUT | LOCATED || P20 | SOL_07 | OUTPUT | LOCATED || P21 | (GND) | | || P22 | (VCC) | | || P23 | SOL_06 | OUTPUT | LOCATED || P24 | SOL_05 | OUTPUT | LOCATED || P25 | SOL_04 | OUTPUT | LOCATED || P26 | SOL_03 | OUTPUT | LOCATED || P27 | SOL_02 | OUTPUT | LOCATED || P28 | SOL_01 | OUTPUT | LOCATED || P29 | SOL_00 | OUTPUT | LOCATED || P30 | (M1) | | || P31 | (GND) | | || P32 | (M0) | | || P33 | (VCC) | | || P34 | (M2) | | || P35 | --- | UNUSED | || P36 | --- | UNUSED | || P37 | START | OUTPUT | LOCATED || P38 | SOL_39 | OUTPUT | LOCATED || P39 | SOL_38 | OUTPUT | LOCATED || P40 | SOL_37 | OUTPUT | LOCATED || P41 | --- | UNUSED | || P42 | (VCC) | | || P43 | (GND) | | || P44 | SOL_36 | OUTPUT | LOCATED || P45 | SOL_35 | OUTPUT | LOCATED || P46 | SOL_34 | OUTPUT | LOCATED || P47 | SOL_33 | OUTPUT | LOCATED || P48 | SOL_32 | OUTPUT | LOCATED || P49 | SOL_31 | OUTPUT | LOCATED || P50 | SOL_30 | OUTPUT | LOCATED || P51 | --- | UNUSED | || P52 | (GND) | | || P53 | (DONE) | | || P54 | (VCC) | | || P55 | (/PROG) | | || P56 | OFF | OUTPUT | LOCATED || P57 | --- | UNUSED | || P58 | --- | UNUSED | || P59 | SOL_29 | OUTPUT | LOCATED || P60 | SOL_28 | OUTPUT | LOCATED || P61 | SOL_27 | OUTPUT | LOCATED || P62 | SOL_26 | OUTPUT | LOCATED || P63 | (VCC) | | || P64 | (GND) | | || P65 | SOL_25 | OUTPUT | LOCATED || P66 | SOL_24 | OUTPUT | LOCATED || P67 | SOL_23 | OUTPUT | LOCATED || P68 | SOL_22 | OUTPUT | LOCATED || P69 | SOL_21 | OUTPUT | LOCATED || P70 | SOL_20 | OUTPUT | LOCATED || P71 | --- | UNUSED | || P72 | --- | UNUSED | || P73 | (CCLK) | | || P74 | (VCC) | | || P75 | (TDO) | | |

| P76 | (GND) | | || P77 | --- | UNUSED | || P78 | --- | UNUSED | || P79 | --- | UNUSED | || P80 | --- | UNUSED | || P81 | --- | UNUSED | || P82 | SOL_19 | OUTPUT | LOCATED || P83 | SOL_18 | OUTPUT | LOCATED || P84 | SOL_17 | OUTPUT | LOCATED || TDO | (TDO) | | |+--------------+-----------------------------------+-----------+------------+

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

3I/O

(A

8)

4I/O

(A

9)

5I/O

(A

10)

6I/O

(A

11)

7I/O

(A

12)

8I/O

(A

13)

9I/O

(A

14)

10I/O

, GC

K8

(A15

)

13I/O, GCK1 (A16)14I/O (A17)15I/O, TDI16I/O, TCK17I/O, TMS18I/O19I/O20I/O

23I/O24I/O25I/O26I/O27I/O28I/O29I/O, GCK230I (M1)

32I (M0)

34I (

M2)

35I/O

, GC

K3

36I/O

(HD

C)

37I/O

(LD

C)

38I/O

39I/O

40I/O

41I/O

(IN

IT)

44I/O

45I/O

46I/O

47I/O

48I/O

49I/O

50I/O

51I/O

, GC

K4

53D

ON

E

55PROGRAM

56I/O (D7)

57I/O, GCK5

58I/O (D6)

59I/O (D5)

60I/O (CSO)

61I/O (D4)

62I/O

65I/O (D3)

66I/O (RS)

67I/O (D2)

68I/O

69I/O (D1)

70I/O (RCLK, RDY/BUSY)

71I/O (D0, DIN)

72I/O, GCK6 (DOUT)

73CCLK

75O

, TD

O

77I/O

(A

0, W

S)

78I/O

, GC

K7

(A1)

79I/O

, CS

1 (A

2)

80I/O

(A

3)

81I/O

(A

4)

82I/O

(A

5)

83I/O

(A

6)

84I/O

(A

7)

1211

12

21

22

31

33 42 43 52

54

63

64

74

76

GNDVccVcc

GND

GND

Vcc

GND

Vcc VccGND GND

Vcc

Vcc

GND

Vcc

GND

U1

4005XL-PC84

GND

1Data2CLK3Reset/OE4CE

5GND

6CEO

7SER_EN

8Vcc

U2

AT17C256

Vcc5 Vcc5

8Vdd

1OE

4GND

5OUT

U3

10_MHz_Clock

Vcc5

116R1A

4_7K

215

R1B4_7K1

2

C1

SOL

OFF

DOWN

Vcc5

Power

power3.sch

BA[0..10]

BB[0..10]

Headers

headers3a.sch

BC[0..10]

BD[0..10]

Headers2

headers3b.sch

12

C2 12

C3 12

C4 12

C5 12

C6 12

C7 12

C8 12

C9

GND

314R1C

4_7K

413R1D

4_7K

Vcc

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

HOFF

SOL

DOWN

GND

160DC

Vcc

GND

1In

2G

ND 3

OUT

U43_3V_Reg

Vcc5

1

2

3

G1ZVN4424A

GND

12

C1047uf

12

C11.47uf

GND

Vcc5

18

7

52

4

6

3

K1

ON_RELAY

15

24

3

K2

OFF_RELAY

1

2

4

3

D1

Bridge3

123456789101112

J1

TERMINAL12

2

1

J2BNC2

15

24

3

K3SOL_RELAY

1

2

3

G2ZVN4424A

160DCVcc5

Vcc5 Vcc5

GND

12

C12470uf

12

J3

Jumper

160DC

12

D21N4004

512

R1E

4_7K

1

2

3

G3ZVN4424A

611

R1F 4_7K

1

2

3

G4ZVN4424A

710

R1G 4_7K

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

BA[0..9]

BB[0..10]

1110987654321

J4

Header

1110987654321

J5

Header

1

2

3

G5

1

2

3

G6

1

2

3

G7

1

2

3

G8

1

2

3

G9

1

2

3

G10

1

2

3

G11

1

2

3

G12

1

2

3

G13

1

2

3

G14

GND

1

2

3

G15

1

2

3

G16

1

2

3

G171

23

G18

1

2

3

G19

1

2

3

G20

1

2

3

G21

1

2

3

G22

1

2

3

G23

1

2

3

G24

1

2

3

G25

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

BC[0..10]

BD[0..10]

1110987654321

J6

Header

1110987654321

J7

Header

1

2

3

G26

1

2

3

G27

1

2

3

G28

1

2

3

G29

1

2

3

G30

1

2

3

G31

1

2

3

G32

1

2

3

G33

1

2

3

G34

1

2

3

G35

1

2

3

G36

GND

1

2

3

G37

1

2

3

G38

1

2

3

G391

23

G40

1

2

3

G41

1

2

3

G42

1

2

3

G43

1

2

3

G44

1

2

3

G45

1

2

3

G46

1

2

3

G47

Ouroborus Bill of Materials

Qty References Value Module Name Disti Disti Part # Price Ext. Mfg. Mfg. Part # Details82 Spade connector Action Electronics RC-03-105A 0.07 5.74 Female spade connectors, red, .187" (100 pack)41 Solenoid bracket Allan Steel NA 0.50 20.50 Cut from 3" x 2" x .125" aluminum angle stock1 K3 SOL_RELAY G6RN-SPDT Digieky Z987-ND 2.35 2.35 Omron G6RN-1-DC5 5VDC/8A SPDT relay2 8-pin solder tab sockets Digikey A9408-ND 0.28 0.56 AMP Div. Of TYCO 2-640463-41 16-pin solder tab socket Digikey A9416-ND 0.37 0.37 AMP Div. Of TYCO 2-640358-41 Power cord (IEC) Digikey AE1121-ND 3.43 3.43 Assmann Electronics AK 500/U-2-21 U2 AT17C256 8DIP300 Digikey AT17C256-10PC-ND 17.20 17.20 Atmel AT17C256-10PC Serial configuration EEPROM8 C2 - C9 .22uF CK05 Digikey 1204PHCT-ND 0.30 2.36 BC Components A224Z20Z5UFVVWT Axial lead ceramic cap1 C1 .22uF CK05 Digikey 1211PHCT-ND 0.30 0.30 BC Components A224M20Z5UFVVWT Axial lead ceramic cap1 R1 4_7K 16DIP300 Digikey 4116R-1-472-ND 0.60 0.60 Bourns 4116R-001-472 8 resistor DIP n/w1 J2 BNC2 BNC Digikey CP-102A-ND 0.38 0.38 CUI Stack PJ-102A CONN JACK POWER 2MM PCB1 5V DC power supply Digikey T920-P5P-ND 16.50 16.50 CUI Stack DPS050240-P5P2 D2,D3 1N4004 1N4004 Digikey 1N4004DICT-ND 0.26 0.52 Diodes Inc. 1N4004-T1 D1 Bridge3 Bridge Digikey RS403LDI-ND 1.60 1.60 Diodes Inc. RS403L 4A/200V bridge rectifier1 U3 10_MHz_Clock 8DIP300 Digikey SE1208-ND 3.00 3.00 Epson Elec. Amer. SG-531P 10 MHz1 SPST momentary pushbutton Digikey EG2005-ND 2.32 2.32 E-Switch PS1023AT-RED1 84-pin solder tab PLCC socket Digikey ED80006-ND 2.39 2.39 Mill-Max Manufacturing 540-99-084-24-4 J4 - J7 Header 11_HEADER_R Digikey WM4309-ND 1.34 5.36 Molex/GC/Waldom 22-05-3111 Mates w/ WM2009-ND44 Crimp terminals Digikey WM2200-ND 0.14 6.03 Molex/GC/Waldom 08-50-01144 Female connector Digikey WM2009-ND 0.77 3.08 Molex/GC/Waldom 22-01-3117 Receives WM2200 and WM43091 J3 Jumper 2HDR-100 Digikey WM4000-ND 0.25 0.25 Molex/GC/Waldom 22-03-20211 U4 3_3V_Reg TO-220 Digikey LM3940IT-3.3-ND 2.29 2.29 Natl. Semi. LM3940IT-3.3 3.3V1 K2 OFF_RELAY G6RN-SPDT Digikey Z987-ND 2.35 2.35 Omron G6RN-1-DC5 5VDC/8A SPDT relay1 K1 ON_RELAY G2R-DPDT Digikey Z846-ND 7.15 7.15 Omron G2R-24-AC120 120VAC/4A DPDT relay1 C11 .47uf 200WIDE Digikey P4671-ND 0.36 0.36 Panasonic ECQ-V1H474JL .47 uf1 C12 470uf TS-UP Digikey P6121-ND 4.78 4.78 Panasonic ECO-S2DP471DA 470 uf1 C10 47uf SOLID_TANT Digikey P2042-ND 2.85 2.85 Panasonic ECS-F1CE476 47 uf1 J1 TERMINAL12 12HDR-200 Digikey 277-1246-ND 4.24 4.24 Phoenix Contact 1729115 Terminal block1 Power inlet (IEC) w/ fuseholder Digikey Q202-ND 2.50 2.50 Qualtek/Fan-S Div. 719W-00/031 Fuse, 12VAC, 4A, 5x20 Digikey WK4716-ND 0.19 0.19 Wikmann USA 1911400000 10 pack45 G1-G45 ZVN4424A T0-92 Digikey ZVN4424A-ND 1.26 56.70 Zetex ZVN4424A T0-92 pkg.1 PCB ECD 140.00 140.00 ECD1 U1 4005XL-PC84 84QUAD Insight Electronics XC4005XL-3PC84C 27.00 27.00 Xilinx XC4005XL-PC84-3 FPGA40 Solenoid Magnetic Sensor Systems S-17-85-37Q 9.15 366.00 Magnetic Sensor Systems S-17-85-37Q Stand-up solenoids1 Solenoid Magnetic Sensor Systems S-17-85-37QH 14.97 14.97 Magnetic Sensor Systems S-17-85-37QH Start solenoid1 Solenoid return spring Magnetic Sensor Systems SP-10 1.00 1.00 Magnetic Sensor Systems SP-10 For start solenoid82 Screws, M4 x .7, 6 mm long, zinc Olander 0.00 Olander Solenoid attachment82 Split lockwashers for M4 x .7 Olander 0.00 Olander Solenoid attachment4 Screws, M4 x .7, 9 mm long, zinc Orchard Supply 0.00 For mounting optical sensor4 Screws, M4 x .7, 12 mm long, zinc Orchard Supply 0.00 For mounting optical sensor1 1" x 1.5" x .125" aluminum strip Orchard Supply 0.00 Orchard Supply For mounting optical sensor3 Square screw hooks, 1 13/16" Orchard Supply SKU = 9040882 0.20 0.60 Orchard Supply For mounting 5V DC power supply1 2' of 16/3 wire for power Orchard Supply SKU = 6037501 0.70 0.70 Orchard Supply Runs from power inlet to PCB1 Extension cord Orchard Supply 1.49 1.49 Orchard Supply For powering 5V DC power supply42 Screws, #8 x 5/8 self-tapping Orchard Supply 0.00 Orchard Supply Bracket attachment2 Dominoes Puremco PD6 9.95 19.90 Puremco PD6 Professional Double 6 Dominoes. 28/set, www.dominoes.com

Total 749.91

DS21315 Rev. D-3 1 of 2 RS401L-RS407L

Plastic Package has UL Flammability Classification94V-0

Surge Overload Rating of 200A Peak Ideal for Oriented Circuit Board High Reliability and Low Leakage Rating to 1000V PIV UL Recognized Under Component Index,

File Number E94661

Mechanical Data

Characteristic Symbol RS401L

RS402L

RS403L

RS404L

RS405L

RS406L

RS407L

Units

Maximum Recurrent Peak Reverse Voltage VRRM 50 100 200 400 600 800 1000 V

Maximum RMS Voltage VRSM 35 70 140 280 420 560 700 V

Maximum DC Blocking Voltage VDC 50 100 200 400 600 800 1000 V

Maximum Average Forward RectifiedOutput Current at TA = 50C I(AV) 4.0 A

Peak Forward Surge Current, 8.3 ms half sine-wavesuperimposed on rated load (JEDEC Method) IFSM 200 A

Maximum Forward Voltage at 3.0A VF 1.0 V

Maximum DC Reverse Current TA = 25Cat Rated DC Blocking Voltage TC = 100C IR

10.01.0

AmA

I2t Rating for fusing (t<8.3ms) I2t 166 A2 s

Operating Temperature Range TJ -55 to +150 C

Storage Temperature Range TSTG -55 to +150 C

Features

Case: RS-4L, Plastic Terminals: Plated Leads Solderable per

MIL-STD-202, Method 208 Mounting Position: Any Approx. Weight: 5.6 grams

RS-4L

Dim Min Max

A 18.5 19.5

B 15.4 16.0

C 19.0 -

D 6.2 6.5

E 4.6 5.6

G 1.5 2.0

H 1.3 Typical

All Dimensions in mm

RS401L - RS407L4.0A BRIDGE RECTIFIER

-+

A

B

C

E

G

H

D

EE

Maximum Ratings and Electrical Characteristics @ TA = 25°C unless otherwise specified

Single phase, 60Hz, resistive or inductive load.For capacitive load, derate current by 20%.

DS21315 Rev. D-3 2 of 2 RS401L-RS407L

0

1

2

3

4

5

20 40 60 80 100 120 140

I,

AV

ER

AG

EO

UT

PU

TC

UR

RE

NT

(A)

(AV

)

T , CASE TEMPERATURE (°C)

Fig. 1 Forward Current Derating CurveC

Single Phase Half Wave60 Hz Resistive or Inductive Load

0

50

100

150

200

250

1 10 100

8.3ms Single Half Sine-WaveJEDEC Method

I,

PE

AK

FO

RW

AR

DS

UR

GE

CU

RR

EN

T(A

)F

SM

NUMBER OF CYCLES AT 60 HzFig. 4 Max Non-Repetitive Peak Fwd Surge Current

0.01

0.1

1.0

10

0 20 40 60 80 100 120 140

I,

INS

TA

NTA

NE

OU

SR

EV

ER

SE

CU

RR

EN

T(m

A)

R

PERCENT OF RATED PEAK REVERSE VOLTAGE (%)Fig. 3 Typical Reverse Characteristics

0.01

0.1

1.0

10

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

I,

INS

TA

NTA

NE

OU

SF

WD

CU

RR

EN

T(A

)F

V , INSTANTANEOUS FORWARD VOLTAGE (V)

Fig. 2 Typical Forward CharacteristicsF

TJ = 25ºCPulse Width = 300 ms

2% Duty Cycle

33

Crystal oscillator

1 OE or ST4 GND5 OUT8 VDD

NO.1 OE7 GND8 OUT14 VDD

NO.

#14 #8

#1 #1 #4

#8 #5

#7

5.3

Max

.2.

54 M

in.

0.2

Min

.

0.2

Min

.

6.36

External dimensions

SG-51 series

Specifications (characteristics)

(Unit: mm)

SG51PH 6052AESG531PTJC

32.0000MHz C20.0000M

9353BE

5.3

Max

.2.

54 M

in.

15.24

0.51

7.62

0.510.25 0.25

90° to105°

90° to105°

7.62 7.62

19.8 Max. 13.7 Max.

6.6

SG-531 series

Pin terminalPin terminal

FULL-SIZE DIP HIGH-FREQUENCY CRYSTAL OSCILLATOR

SG-51 series

Item

Output frequency range

Power source voltage

Temperature range

Frequency stability

Current consumptionOutput disable current

Duty

Output voltage

Output loadcondition (fan out)

Output enable/disable input voltage

Output rise time

Output fall time

Oscillation start up time

Aging

Shock resistance

Symbol

f0

VDD-GNDVDD

TSTG

TOPR

∆f/f0

IopIOE

tw/t

VOH

VOL

CL

NVIH

VIL

tTLH

tTHL

tOSC

fa

S.R.

HALF-SIZE DIP HIGH-FREQUENCY CRYSTAL OSCILLATOR

SG-531 series

C-MOS levelTTL level

C-MOS levelTTL levelC-MOS levelTTL level

C-MOSTTL

SG-51P/531P SG-51PTJ/531PTJ SG-51PH/531PH

Specifications

26.0001 MHz to 66.6667 MHz

-0.3 V to +7.0 V -0.5 V to +7.0 V5.0 V±0.5 V

-55 °C to +125 °C-20 °C to +70 °C (-40 °C to +85 °C)

B: ± 50 x 10-6

C: ±100 x 10-6

23 mA Max. 35 mA Max.12 mA Max. 28 mA Max. 20 mA Max.

40 % to 60 % — 40 % to 60 %45 % to 55 % —

VDD-0.4 V Min. 2.4 V Min. VDD -0.4 V Min.0.4 V Max.

50 pF Max. — 50 pF Max.10 TTL Max. 5 TTL Max. —2.0 V Min. 3.5 V Min. 2.0 V Min.0.8 V Max. 1.5 V Max. 0.8 V Max.

8 ns Max.

8 ns Max.

4 ms Max. 10 ms Max.

±5 x 10-6/year Max.

±20 x 10-6 Max.

Remarks

Stored as bare product after unpacking

B type is possible up to 55.0 MHz

No load conditionOE=GND

1/2 VDD level1.4 V level

IOH = -400 µA (P,PTJ) /-4 mA (PH)IOL = 16 mA (P) / 8 mA (PTJ) / 4mA (PH)

CL≤15 pFIIH=1 µA Max. (OE=VDD)

IIL= -100 µA Min. (OE=GND), PTJ: -500 µAC-MOS load: 20 %→80 % VDD

TTL load: 0.4 V→2.4 VC-MOS load: 80 %→20 % VDD

TTL load: 2.4 V→0.4 V

More than for 1 ms until VDD =0 V→4.5 VTime at 4.5 V to be 0 s

Ta=+25 °C, VDD =5 V,first yearThree drops on a hard board from 750 mm orexcitation test with 29400 m/s2 x 0.3 ms x 1/2

sine wave in 3 directions

Note: • Unless otherwise stated, characteristics (specifications) shown in the above table are based on the rated operating temperature and voltage condition.• External by-pass capacitor is recommended.

Max. supply voltageOperating voltageStorage temperatureOperating temperature

1.0250 MHz to 26.0000 MHz

—5 ns Max.

—5 ns Max.

7 ns Max.—

7 ns Max.—

• Pin compatible with full-size metal can. (SG-51 series)• Pin compatible with half-size metal can. (SG-531 series)• Cylindrical AT-cut crystal unit builtin, thus assuring high reliability.• Use of C-MOS IC enables reduction of current consumption.

Please contact us on availability of -40 °C to +85 °C

Actual size

Products number Q3 2 5 1 0 x x xx x x x 00Q3 2 5 3 1 x x xx x x x 00

34

Crystal oscillator

Specifications (characteristics)

Operating condition and Frequency band

100 MHz50 MHz1 MHz 150 MHz

SG-51/531P SG-51/531PTJ/PH SG-531PTW/STW/PHW/SHWFrequency stability:B

( -20 to +70 °C)

SG-51/531P SG-51/531PTJ/PH SG-531PTW/STW/PHW/SHWFrequency stability:C

( -20 to +70 °C)

SG-531PCW/SCWFrequency stability:B

( -20 to +70 °C)

261.025 55

Frequency stability:C( -20 to +70 °C) SG-531PCW/SCW

Frequency stability:M( -40 to +85 °C)

Operating condition

135

26 135

26 135

SG-531PCW/SCW

26 135

261.025 66.6667 135

3.3 V±0.3 V

5 V±0.5 V

Output frequency range

Power source voltageTemperature range

Frequency stability

Current consumptionOutput disable currentStandby current

Duty

Output voltage

Output load condition (fan out)Output enabledisable input voltageOutput rise timeOutput fall time

Oscillation start up time

Aging

Shock resistance

f0

VDD-GNDVDD

TSTG

TOPR

∆f/f0

IopIoE

IST

tw/t

VOH

VOL

CL

VIH

VIL

tTLH

tTHL

tOSC

fa

S.R.

C-MOS levelTTL level

C-MOS levelTTL levelC-MOS levelTTL level

SG-531PTW/STW SG-531PHW/SHW SG-531PCW/SCWSpecifications

Remarks

55.0001 MHz to 135.0000 MHz

-0.5 V to +7.0 V5.0 V±0.5 V 3.3 V±0.3 V

-55 °C to +125 °C-20 °C to +70 °C -40 °C to +85 °C

B: ±50 x 10-6 C: ±100 x 10-6

M: ±100 x 10-6

45 mA Max. 28 mA Max.30 mA Max. 16 mA Max.

50 µA Max.— 40 % to 60 %

40 % to 60 % —VDD-0.4 V Min.

0.4 V Max.15 pF Max.

10 ms Max.

±5 x 10-6/year Max.

±20 x 10-6 Max.

Stored as bare product after unpacking

-20 °C to +70 °C-40 °C to +85 °CNo load conditionOE=GND(P*W)

ST=GND(S*W)C-MOS load: 1/2VDD

TTL load: 1.4 VIOH= -16 mA (*TW/HW)/-8 mA(*CW)IOL= -16 mA (*TW/HW)/8 mA(*CW)

OE,STOE,ST

C-MOS load: 20 %→80 % VDD

TTL load: 0.4 V→2.4 VC-MOS load: 80 %→20 % VDD

TTL load: 2.4 V→0.4 V

Time at minimum operating voltage to be 0 s

Ta=+25 °C, VDD =5 V

Three drops on a hard board from 750 mm orexcitation test with 29400 m/s2 x 0.3 ms x 1/2

sine wave in 3 directions

Max. supply voltageOperating voltageStorage temperatureOperating temperature

26.0001 MHz to 135.0000 MHz

Item Symbol

4 ns Max.—

4 ns Max.—

0.7 VDD Min.0.2 VDD Min.

—4 ns Max.

—4 ns Max.

4 ns Max.—

4 ns Max.—

2.0 V Min.0.8 V Max.

LM39401A Low Dropout Regulator for 5V to 3.3V ConversionGeneral DescriptionThe LM3940 is a 1A low dropout regulator designed to pro-vide 3.3V from a 5V supply.

The LM3940 is ideally suited for systems which contain both5V and 3.3V logic, with prime power provided from a 5V bus.

Because the LM3940 is a true low dropout regulator, it canhold its 3.3V output in regulation with input voltages as lowas 4.5V.

The T0-220 package of the LM3940 means that in most ap-plications the full 1A of load current can be delivered withoutusing an additional heatsink.

The surface mount TO-263 package uses minimum boardspace, and gives excellent power dissipation capability whensoldered to a copper plane on the PC board.

Featuresn Output voltage specified over temperaturen Excellent load regulationn Guaranteed 1A output currentn Requires only one external componentn Built-in protection against excess temperaturen Short circuit protected

Applicationsn Laptop/Desktop Computersn Logic Systems

Typical Application

DS012080-1

*Required if regulator is located more than 1" from the power supply filter capacitor or if battery power is used.**See Application Hints.

May 1999

LM3940

1ALow

DropoutR

egulatorfor

5Vto

3.3VC

onversion

© 1999 National Semiconductor Corporation DS012080 www.national.com

Connection Diagram/Ordering Information

DS012080-2

3-Lead TO-220 Package(Front View)

Order Part Number LM3940IT-3.3NSC Drawing Number TO3B

DS012080-3

3-Lead TO-263 Package(Front View)

Order Part Number LM3940IS-3.3NSC Drawing Number TS3B

DS012080-10

3-Lead SOT-223(Front View)

Order Part Number LM3940IMP-3.3Package Marked L52B

NSC Drawing Number MA04A

DS012080-27

16-Lead Ceramic Dual-in-Line Package(Top View)

Order Part Number LM3940J-3.3-QML5962-9688401QEA

NSC Drawing Number J16A

DS012080-28

16-Lead Ceramic Surface-Mount Package(Top View)

Order Part Number LM3940WG-3.3-QML5962-9688401QXA

NSC Drawing Number WG16A

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Storage Temperature Range −65˚C to +150˚C

Operating Junction Temperature Range −40˚C to +125˚CLead Temperature (Soldering, 5 seconds) 260˚CPower Dissipation (Note 2) Internally LimitedInput Supply Voltage 7.5VESD Rating (Note 3) 2 kV

Electrical CharacteristicsLimits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Un-less otherwise specified: VIN = 5V, IL = 1A, COUT = 33 µF.

Symbol Parameter Conditions Typical LM3940 (Note 4) Units

min max

VO Output Voltage 5 mA ≤ IL ≤ 1A 3.3 3.20 3.40 V

3.13 3.47

Line Regulation IL = 5 mA 20 40 mV

4.5V ≤ VO ≤ 5.5V

Load Regulation 50 mA ≤ IL ≤ 1A 35 50

80

ZO Output Impedance IL (DC) = 100 mA

IL (AC) = 20 mA (rms) 35 mΩf = 120 Hz

IQ Quiescent Current 4.5V ≤ VIN ≤ 5.5V 10 15 mA

IL = 5 mA 20

VIN = 5V 110 200

IL = 1A 250

en Output Noise Voltage BW = 10 Hz–100 kHz 150 µV (rms)

IL = 5 mA

VO − VIN Dropout Voltage IL = 1A 0.5 0.8 V

(Note 5) 1.0

IL = 100 mA 110 150 mV

200

IL(SC) Short Circuit Current RL = 0 1.7 1.2 A

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the de-vice outside of its rated operating conditions.

Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal resistance, θJ−A, and theambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.The value of θJ−A (for devices in still air with no heatsink) is 60˚C/W for the TO-220 package, 80˚C/W for the TO-263 package, and 174˚C/W for the SOT-223 package.The effective value of θJ−A can be reduced by using a heatsink (see Application Hints for specific information on heatsinking).

Note 3: ESD rating is based on the human body model: 100 pF discharged through 1.5 kΩ.

Note 4: All limits guaranteed for TJ = 25˚C are 100% tested and are used to calculate Outgoing Quality Levels. All limits at temperature extremes are guaranteedvia correlation using standard Statistical Quality Control (SQC) methods.

Note 5: Dropout voltage is defined as the input-output differential voltage where the regulator output drops to a value that is 100 mV below the value that is measuredat VIN = 5V.

www.national.com3

Typical Performance Characteristics

Dropout Voltage

DS012080-13

Dropout Voltagevs Temperature

DS012080-14

Output Voltagevs Temperature

DS012080-15

Quiescent Currentvs Temperature

DS012080-16

Quiescent Current vs V IN

DS012080-17

Quiescent Current vs Load

DS012080-18

Line Transient Response

DS012080-19

Load Transient Response

DS012080-20

Ripple Rejection

DS012080-21

Low Voltage Behavior

DS012080-22

Output Impedance

DS012080-23

Peak Output Current

DS012080-24

www.national.com 4

Application HintsEXTERNAL CAPACITORS

The output capacitor is critical to maintaining regulator stabil-ity, and must meet the required conditions for both ESR(Equivalent Series Resistance) and minimum amount of ca-pacitance.

MINIMUM CAPACITANCE:

The minimum output capacitance required to maintain stabil-ity is 33 µF (this value may be increased without limit).Larger values of output capacitance will give improved tran-sient response.

ESR LIMITS:

The ESR of the output capacitor will cause loop instability ifit is too high or too low. The acceptable range of ESR plottedversus load current is shown in the graph below. It is essen-tial that the output capacitor meet these requirements,or oscillations can result.

It is important to note that for most capacitors, ESR is speci-fied only at room temperature. However, the designer mustensure that the ESR will stay inside the limits shown over theentire operating temperature range for the design.

For aluminum electrolytic capacitors, ESR will increase byabout 30X as the temperature is reduced from 25˚C to−40˚C. This type of capacitor is not well-suited for low tem-perature operation.

Solid tantalum capacitors have a more stable ESR over tem-perature, but are more expensive than aluminum electrolyt-ics. A cost-effective approach sometimes used is to parallelan aluminum electrolytic with a solid Tantalum, with the totalcapacitance split about 75/25% with the Aluminum being thelarger value.

If two capacitors are paralleled, the effective ESR is the par-allel of the two individual values. The “flatter” ESR of the Tan-talum will keep the effective ESR from rising as quickly at lowtemperatures.

HEATSINKING

A heatsink may be required depending on the maximumpower dissipation and maximum ambient temperature of theapplication. Under all possible operating conditions, the junc-tion temperature must be within the range specified underAbsolute Maximum Ratings.

To determine if a heatsink is required, the power dissipatedby the regulator, PD, must be calculated.

The figure below shows the voltages and currents which arepresent in the circuit, as well as the formula for calculatingthe power dissipated in the regulator:

The next parameter which must be calculated is the maxi-mum allowable temperature rise, TR (max). This is calcu-lated by using the formula:

TR (max) = TJ (max) − TA (max)

Where: TJ (max) is the maximum allowable junction tem-perature, which is 125˚C for commercialgrade parts.

TA (max) is the maximum ambient temperaturewhich will be encountered in the applica-tion.

Using the calculated values for TR(max) and PD, the maxi-mum allowable value for the junction-to-ambient thermal re-sistance, θ(J−A), can now be found:

θ(J−A) = TR (max)/PD

IMPORTANT: If the maximum allowable value for θ(J−A) isfound to be ≥ 60˚C/W for the TO-220 package, ≥ 80˚C/W forthe TO-263 package, or ≥174˚C/W for the SOT-223 pack-age, no heatsink is needed since the package alone will dis-sipate enough heat to satisfy these requirements.

If the calculated value for θ(J−A)falls below these limits, aheatsink is required.

HEATSINKING TO-220 PACKAGE PARTS

The TO-220 can be attached to a typical heatsink, or se-cured to a copper plane on a PC board. If a copper plane isto be used, the values of θ(J−A) will be the same as shown inthe next section for the TO-263.

DS012080-5

FIGURE 1. ESR Limits

DS012080-6

IIN = IL + IGPD = (VIN − VOUT) IL + (VIN) IG

FIGURE 2. Power Dissipation Diagram

www.national.com5

Application Hints (Continued)

If a manufactured heatsink is to be selected, the value ofheatsink-to-ambient thermal resistance, θ(H−A), must first becalculated:

θ(H−A) = θ(J−A) − θ(C−H) − θ(J−C)

Where: θ(J−C) is defined as the thermal resistance fromthe junction to the surface of the case. Avalue of 4˚C/W can be assumed for θ(J−C)

for this calculation.

θ(C−H) is defined as the thermal resistance be-tween the case and the surface of the heat-sink. The value of θ(C−H) will vary fromabout 1.5˚C/W to about 2.5˚C/W (depend-ing on method of attachment, insulator,etc.). If the exact value is unknown, 2˚C/Wshould be assumed for θ(C−H).

When a value for θ(H−A) is found using the equation shown,a heatsink must be selected that has a value that is less thanor equal to this number.

θ(H−A) is specified numerically by the heatsink manufacturerin the catalog, or shown in a curve that plots temperature risevs power dissipation for the heatsink.

HEATSINKING TO-263 AND SOT-223 PACKAGE PARTS

Both the TO-263 (“S”) and SOT-223 (“MP”) packages use acopper plane on the PCB and the PCB itself as a heatsink.To optimize the heat sinking ability of the plane and PCB,solder the tab of the package to the plane.

Figure 3 shows for the TO-263 the measured values of θ(J−A)

for different copper area sizes using a typical PCB with 1ounce copper and no solder mask over the copper area usedfor heatsinking.

As shown in the figure, increasing the copper area beyond 1square inch produces very little improvement. It should alsobe observed that the minimum value of θ(J−A) for the TO-263package mounted to a PCB is 32˚C/W.

As a design aid, Figure 4 shows the maximum allowablepower dissipation compared to ambient temperature for theTO-263 device (assuming θ(J−A) is 35˚C/W and the maxi-mum junction temperature is 125˚C).

Figure 5 and Figure 6 show the information for the SOT-223package. Figure 6 assumes a θ(J−A) of 74˚C/W for 1 ouncecopper and 51˚C/W for 2 ounce copper and a maximumjunction temperature of 125˚C.

Please see AN1028 for power enhancement techniques tobe used with the SOT-223 package.

DS012080-7

FIGURE 3. θ(J−A) vs Copper (1 ounce) Area for theTO-263 Package

DS012080-8

FIGURE 4. Maximum Power Dissipation vs T AMB forthe TO-263 Package

DS012080-11

FIGURE 5. θ(J−A) vs Copper (2 ounce) Area for theSOT-223 Package

DS012080-12

FIGURE 6. Maximum Power Dissipation vs T AMB forthe SOT-223 Package

www.national.com 6

Physical Dimensions inches (millimeters) unless otherwise noted

3-Lead SOT-223 PackageOrder Part Number LM3940IMP-3.3

NSC Package Number MA04A

www.national.com7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

3-Lead TO-220 PackageOrder Part Number LM3940IT-3.3

NSC Package Number TO3B

www.national.com 8


3-Lead TO-263 PackageOrder Part Number LM3940IS-3.3

NSC Package Number TS3B

www.national.com9


16-Lead Ceramic Dual-in-Line PackageOrder Part Number LM3940J-3.3-QML

5962-9688401QEANSC Drawing Number J16A

www.national.com 10


LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National SemiconductorCorporationAmericasTel: 1-800-272-9959Fax: 1-800-737-7018Email: [email protected]

National SemiconductorEurope

Fax: +49 (0) 1 80-530 85 86Email: [email protected]

Deutsch Tel: +49 (0) 1 80-530 85 85English Tel: +49 (0) 1 80-532 78 32Français Tel: +49 (0) 1 80-532 93 58Italiano Tel: +49 (0) 1 80-534 16 80

National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: [email protected]

National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507

www.national.com

16-Lead Ceramic Surface-Mount PackageOrder Part Number LM3940WG-3.3-QML

5962-9688401QXANSC Package Number WG16A

LM3940

1ALow

DropoutR

egulatorfor

5Vto

3.3VC

onversion

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Ð EE250 Ð

Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.

Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.

I < 0.008 CV or 0.05 (µA) after 2 minutes application ofrated working voltage at +20 ûC ( )

Series:EFType: F (Resin Dipped Type)

Resin Dipped Type Tantalum SolidElectrolytic Capacitors

Japan

Operating Temp. Range

Rated W.V. Range

Nominal Cap. Range

Capacitance Tolerance

Ð55 to +85 ûC (W.V. > 10 V.DC ááááá Ð55 to +105 ûC)

4 to 50 V.DC

0.1 to 220 µF

±20 %, (120 Hz/+20 ûC)

DC Leakage Current Whichever, greater

< 1 µF ááááááááááááááááááá 0.04 max.1.5 to 68 µF ááááááááá 0.06 max. 4 W.V. ááááááááááá 0.1 max. (120 Hz/+20 ûC)> 100 µF ááááááááááááááá 0.08 max.

Specifications

Features Compact size and wide capacitance range Excellent frequency and temperature characteristics Available for direct mounting on thin circuit boards Washable in organic solvents after soldering IEC pub. 384-15 approved

Recommended Applications TV, Audio, Compact size electronic equipment

After 500 hours exposure at +40 ûC and 90 to 95 % R.H. without load, the capacitorshall meet the following limits.

Capacitance change ±10 % of initial measured valueD.F. < 150 % of initial specified valueDC leakage current 0.012 CV or 0.75 (µA) max. whichever, greater

After 2000 hours application of rated DC working voltage at +85 ûC or 1000 hours at+105 ûC with derated voltage for 10 to 50 W.V., the capacitor shall meet the following limits.

Capacitance change ±10 % of initial measured valueD.F. < Initial specified valueDC leakage current 0.01 CV or 0.625 (µA) max. whichever, greater

Endurance

Moisture Resistance

Tantalum Solid Electrolytic Capacitors/EF

Dissipation Factor

Ð EE251 Ð



Explanation of Part Numbers

Marking Dimensions in mm (not to scale)

(for 6.3 W.V.abbreviated to 6)

E

1

Product Code Style R.W. Voltage Code Series Code N.Capacitance Code Option

C

2

S

3

F

4

5

6

E

7

8

9

10

11

12

1A

10

1C

16

1E

25

1V

35

0G

4

0J

6.3

W.V. code

W.V.(V)

1H

50

Capacitance code

474

475

Capacitance

470000 pF=0.47 µF

4700000 pF=4.7 µF

Example:

Case sizeW.V.(V.DC)

4 (0G) 6.3 (0J) 10 (1A) 16 (1C) 25 (1E) 35 (1V) 50 (1H)Cap.(µF)0.10 (104) A0.22 (224) B0.47 (474) B D1.0 (105) C E1.5 (155) C F2.2 (225) C D G3.3 (335) C D E H4.7 (475) C D E F I6.8 (685) C D E F H

10 (106) C D E F H I15 (156) D E F G I J22 (226) E F G H J K33 (336) F G H I K47 (476) G H I J68 (686) H I J K

100 (107) I J K150 (157) J K220 (227) K

Note: 1. ( ) shows W.V. and capacitance code.2. Products designated by () have the voltage code on the body.3. When selecting W.V., see the page 230.

+

Ð

+

10

16

Cap. (µF)

W.V. (V)

Size code fD L F

A 3.3 5.0 2.5±0.5

B 3.3 5.5 2.5±0.5

C 3.5 5.5 2.5±0.5

D 3.7 6.5 2.5±0.5

E 4.0 7.0 2.5

F 4.5 7.0 2.5

G 4.7 8.0 2.5

H 5.2 8.5 2.5

I 5.5 9.5 2.5

J 6.0 11.0 2.5

K 7.5 12.5 5.0±0.5

+1.0Ð 0.5

+1.0Ð 0.5

+1.0Ð 0.5

+1.0Ð 0.5

+1.0Ð 0.5

+1.0Ð 0.5


f

0.50±0.05

f

D max.

F

2 m

in.

10 m

in.

L m

ax.

0.8 max

Straight-lead-products

1.5 max. for size

codes K


Ð EE252 Ð



L.C

( m m ) (pcs)

Body Size

(V) (µF)

D.F.

( m m ) (µA) (pcs)(mm)

B1 BB

(mm) (mm)

10 3.5 [4.5] 5.5 [9 ] C 0.1 0.4 2.5 2.5 5.0 ECSF0GE106( ) 200 2000

15 3.7 [5 ] 6.5 [9 ] D 0.1 0.5 2.5 2.5 5.0 ECSF0GE156( ) 200 2000

22 4 [5.5] 7 [9 ] E 0.1 0.8 2.5 2.5 5.0 ECSF0GE226( ) 200 2000

33 4.5 [5.5] 7 [10 ] F 0.1 1.1 2.5 2.5 5.0 ECSF0GE336( ) 200 2000

47 4.7 [6 ] 8 [11 ] G 0.1 1.6 2.5 2.5 5.0 ECSF0GE476( ) 200 2000

68 5.2 [6 ] 8.5 [11.5] H 0.1 2.2 2.5 2.5 5.0 ECSF0GE686( ) 200 2000

100 5.5 [6.5] 9.5 [12.5] I 0.1 3.2 2.5 2.5 5.0 ECSF0GE107( ) 200 2000

150 6 11 J 0.1 4.8 2.5 ECSF0GE157 200

220 7.5 12.5 K 0.1 7.1 5.0 ECSF0GE227 100

6.8 3.5 [4.5] 5.5 [9 ] C 0.06 0.4 2.5 2.5 5.0 ECSF0JE685( ) 200 2000

10 3.7 [5 ] 6.5 [9 ] D 0.06 0.6 2.5 2.5 5.0 ECSF0JE106( ) 200 2000

15 4 [5.5] 7 [9 ] E 0.06 0.8 2.5 2.5 5.0 ECSF0JE156( ) 200 2000

22 4.5 [5.5] 7 [10 ] F 0.06 1.2 2.5 2.5 5.0 ECSF0JE226( ) 200 2000

33 4.7 [6 ] 8 [11 ] G 0.06 1.7 2.5 2.5 5.0 ECSF0JE336( ) 200 2000

47 5.2 [6 ] 8.5 [11.5] H 0.06 2.4 2.5 2.5 5.0 ECSF0JE476( ) 200 2000

68 5.5 [6.5] 9.5 [12.5] I 0.06 3.5 2.5 2.5 5.0 ECSF0JE686( ) 200 2000

100 6 11 J 0.08 5.1 2.5 ECSF0JE107 200

150 7.5 12.5 K 0.08 7.6 5 ECSF0JE157 100

4.7 3.5 [4.5] 5.5 [9 ] C 0.06 0.4 2.5 2.5 5.0 ECSF1AE475( ) 200 2000

6.8 3.7 [5 ] 6.5 [9 ] D 0.06 0.6 2.5 2.5 5.0 ECSF1AE685( ) 200 2000

10 4 [5.5] 7 [9 ] E 0.06 0.8 2.5 2.5 5.0 ECSF1AE106( ) 200 2000

15 4.5 [5.5] 7 [10 ] F 0.06 1.2 2.5 2.5 5.0 ECSF1AE156( ) 200 2000

22 4.7 [6 ] 8 [11 ] G 0.06 1.8 2.5 2.5 5.0 ECSF1AE226( ) 200 2000

33 5.2 [6 ] 8.5 [11.5] H 0.06 2.7 2.5 2.5 5.0 ECSF1AE336( ) 200 2000

47 5.5 [6.5] 9.5 [12.5] I 0.06 3.8 2.5 2.5 5.0 ECSF1AE476( ) 200 2000

68 6 11 J 0.06 5.5 2.5 ECSF1AE686 200

100 7.5 12.5 K 0.08 8.0 5.0 ECSF1AE107 100

3.3 3.5 [4.5] 5.5 [9 ] C 0.06 0.5 2.5 2.5 5.0 ECSF1CE335( ) 200 2000

4.7 3.7 [5 ] 6.5 [9 ] D 0.06 0.7 2.5 2.5 5.0 ECSF1CE475( ) 200 2000

6.8 4 [5.5] 7 [9 ] E 0.06 0.9 2.5 2.5 5.0 ECSF1CE685( ) 200 2000

10 4.5 [5.5] 7 [10 ] F 0.06 1.3 2.5 2.5 5.0 ECSF1CE106( ) 200 2000

15 4.7 [6 ] 8 [11 ] G 0.06 2.0 2.5 2.5 5.0 ECSF1CE156( ) 200 2000

22 5.2 [6 ] 8.5[11.5] H 0.06 2.9 2.5 2.5 5.0 ECSF1CE226( ) 200 2000

33 5.5 [6.5] 9.5[12.5] I 0.06 4.3 2.5 2.5 5.0 ECSF1CE336( ) 200 2000

47 6 11 J 0.06 6.1 2.5 ECSF1CE476 200

68 7.5 12.5 K 0.06 8.8 5.0 ECSF1CE686 100

2.2 3.5 [4.5] 5.5 [9 ] C 0.06 0.5 2.5 2.5 5.0 ECSF1EE225( ) 200 2000

3.3 3.7 [5 ] 6.5 [9 ] D 0.06 0.7 2.5 2.5 5.0 ECSF1EE335( ) 200 2000

4.7 4 [5.5] 7 [9 ] E 0.06 1.0 2.5 2.5 5.0 ECSF1EE475( ) 200 2000

6.8 4.5 [5.5] 7 [10 ] F 0.06 1.4 2.5 2.5 5.0 ECSF1EE685( ) 200 2000

10 5.2 [6 ] 8.5 [11.5] H 0.06 2.0 2.5 2.5 5.0 ECSF1EE106( ) 200 2000

15 5.5 [6.5] 9.5 [12.5] I 0.06 3.0 2.5 2.5 5.0 ECSF1EE156( ) 200 2000

6.3

4

SpecificationCap.

(±20%)W.V.

Standard ProductsPart No.

Taping

Min. Packaging Q'ty

StraightLeads

Taping

Lead Space

Dia. Length Straight TapingS i zeCode

When requesting taped product, please put the letter "B1" or "BB" between the "( )".diameter, length in brackets [ ] represent taping dimentions for suffix (BB).

16

25

10


Ð EE253 Ð



22 6 11 J 0.06 4.4 2.5 ECSF1EE226 200

33 7.5 12.5 K 0.06 6.6 5.0 ECSF1EE336 100

0.47 3.3 [4.5] 5.5 [9 ] B 0.04 0.2 2.5 2.5 5.0 ECSF1VE474( ) 200 2000

1 3.5 [4.5] 5.5 [9 ] C 0.04 0.3 2.5 2.5 5.0 ECSF1VE105( ) 200 2000

1.5 3.5 [4.5] 5.5 [9 ] C 0.06 0.5 2.5 2.5 5.0 ECSF1VE155( ) 200 2000

2.2 3.7 [5 ] 6.5 [9 ] D 0.06 0.7 2.5 2.5 5.0 ECSF1VE225( ) 200 2000

3.3 4 [5.5] 7 [9 ] E 0.06 1.0 2.5 2.5 5.0 ECSF1VE335( ) 200 2000

4.7 4.5 [5.5] 7 [10 ] F 0.06 1.4 2.5 2.5 5.0 ECSF1VE475( ) 200 2000

6.8 5.2 [6 ] 8.5 [11.5] H 0.06 2.0 2.5 2.5 5.0 ECSF1VE685( ) 200 2000

10 5.5 [6.5] 9.5 [12.5] I 0.06 2.8 2.5 2.5 5.0 ECSF1VE106( ) 200 2000

15 6 11 J 0.06 4.2 2.5 ECSF1VE156 200

22 7.5 12.5 K 0.06 6.2 5.0 ECSF1VE226 100

0.1 3.3 [4.5] 5 [9 ] A 0.04 0.05 2.5 2.5 5.0 ECSF1HE104( ) 200 2000

0.22 3.3 [4.5] 5.5 [9 ] B 0.04 0.09 2.5 2.5 5.0 ECSF1HE224( ) 200 2000

0.47 3.7 [5 ] 6.5 [9 ] D 0.04 0.2 2.5 2.5 5.0 ECSF1HE474( ) 200 2000

1 4 [5.5] 7 [9 ] E 0.04 0.4 2.5 2.5 5.0 ECSF1HE105( ) 200 2000

1.5 4.5 [5.5] 7 [10 ] F 0.06 0.6 2.5 2.5 5.0 ECSF1HE155( ) 200 2000

2.2 4.7 [6 ] 8 [11 ] G 0.06 0.9 2.5 2.5 5.0 ECSF1HE225( ) 200 2000

3.3 5.2 [6 ] 8.5 [11.5] H 0.06 1.4 2.5 2.5 5.0 ECSF1HE335( ) 200 2000

4.7 5.5 [6.5] 9.5 [12.5] I 0.06 1.9 2.5 2.5 5.0 ECSF1HE475( ) 200 2000

( m m ) (pcs)(V) (µF)

D.F.

( m m ) (µA) (pcs)(mm)

B1 BB

(mm) (mm)

L.C

Body Size SpecificationCap.

(±20%)W.V.

Standard Products

Taping StraightLeads

Taping

Lead Space

Dia. Length Straight TapingS i zeCode

Part No. Min. Packaging Q'ty

When requesting taped product, please put the letter "B1" or "BB" between the "( )".diameter, length in brackets [ ] represent taping dimentions for suffix (BB).

25

35

50

Mill-Max-Mfg.Corp.,P.O.Box 300,190 Pine Hollow Road,Oyster Bay,NY 11771-0300.Tel:516-922-6000 Fax:516-922-9253 94

COMPACT PLCC SOCKETSFor Through Board Mount

Series 540

• Note: End stackable.• Series 540 PLCC sockets

are designed to acceptJEDEC type MO-047 leadedplastic substrates.

• Body has polarizing featuresfor both substrate and socketinsertion.

• Contacts of highly reliabledesign safely hold the substratein place by positive spring action.

• PLCC chip extraction toolavailable. See page 96.

ALL SERIES 540 CONTACTS ARE PLATED TIN/LEAD. SEE PAGE 96 FOR TECHNICAL SPECIFICATIONS.

No. ofPins

ORDERING INFORMATION - A - - B - - C - - D -

202832*44526884

540-99-020-24-000540-99-028-24-000540-99-032-24-000540-99-044-24-000540-99-052-24-000540-99-068-24-000540-99-084-24-000

*RECTANGULAR

.590

.690.783 / .683

.890

.9901.1901.390

.360

.460.564 / .464

.660

.760

.9601.160

.200

.300.400 / .300

.500

.600

.8001.000

.400

.500.600 / .500

.700

.8001.0001.200

Quantityper

Tube

41352427242017

SUFFIX C

N-CHANNEL ENHANCEMENT

MODE VERTICAL DMOS FETISSUE 3 – August 1994

FEATURES* Compact E-LINE (TO92 style) package* 240 Volt BVDS* RDS(on)=4.3Ω Typical at VGS=2.5V* Low threshold* Fast switching

APPLICATIONS* Earth recall and dialling switches* Electronic hook switches* Battery powered equipment* Telecoms and high voltage dc-dc converters

ABSOLUTE MAXIMUM RATINGS.

PARAMETER SYMBOL VALUE UNIT

Drain-Source Voltage VDS 240 V

Continuous Drain Current at Tamb=25°C ID 260 mA

Pulsed Drain Current IDM 1.5 A

Gate Source Voltage VGS ± 40 V

Power Dissipation at Tamb=25°C Ptot 750 mW

Operating and Storage Temperature Range Tj:Tstg -55 to +150 °C

G D S

ZVN4424A/C

D G S

E-Line

TO92 Compatible

SUFFIX A

SPICE PARAMETERS*ZVN4424 MODEL LAST REVISION 1/94

*

.SUBCKT ZVN4424 30 40 50

* NODES: DRAIN GATE SOURCE

M1 30 20 50 50 MOD1 L=1 W=1

RG 40 20 200

RL 30 50 240E6

D1 50 30 DIODE1

.MODEL MOD1 NMOS VT0=1.25 RS=2.34 RD=1.634 IS=1E-15 KP=5.319

+CGS0=101P CGD0=4P CBD=66.2P PB=1

.MODEL DIODE1 D IS=5.516E-13 RS=0.2084 N=1.0078

.ENDS ZVN4424

For clarification of the above or for technical enquires generally please contact the Applications Dept.at Zetex plc.

©1992 ZETEX plcThe copyright in this model and the design embodied belonging to Zetex plc (“Zetex”). It is supplied free of charge by Zetex for thepurpose of research and design and may be used or copied intact (including this notice) for that purpose only. All other rights arereserved. The model is believed accurate but no condition or warranty as to its merchantability or fitness for the purpose is given and noliability in respect of any use is accepted by Zetex plc, its distributors or agents.

ZVN4424A/C

Zetex plc. Fields New Road, Chadderton, Oldham, OL9-8NP, United Kingdom. Telephone: (44)161-627 5105 (Sales), (44)161-627 4963 (General Enquiries) Fax: (44)161-627 5467

Zetex GmbH Zetex Inc. Zetex (Asia) Ltd. These are supported byStreitfeldstraße 19 47 Mall Drive, Unit 4 3510 Metroplaza, Tower 2 agents and distributors inD-81673 München Commack NY 11725 Hing Fong Road, major countries world-wideGermany USA Kwai Fong, Hong Kong Zetex plc 1997Telefon: (49) 89 45 49 49 0 Telephone: (516) 543-7100 Telephone:(852) 26100 611 Internet:Fax: (49) 89 45 49 49 49 Fax: (516) 864-7630 Fax: (852) 24250 494 http://www.zetex.com

This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, appliedor reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products orservices concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of anyproduct or service.

ZVN4424A/CZVN4424A/C

ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).

PARAMETER SYMBOL MIN. TYP MAX. UNIT CONDITIONS.

Drain-SourceBreakdown Voltage

BVDSS 240 V ID=1mA, VGS=0V

Gate-Source ThresholdVoltage

VGS(th) 0.8 1.3 1.8 V ID=1mA, VDS= VGS

Gate-Body Leakage IGSS 100 nA VGS=± 40V, VDS=0V

Zero Gate Voltage DrainCurrent

IDSS 10100

µAµA

VDS=240 V, VGS=0VDS=190 V,VGS=0V, T=125°C

On-State Drain Current ID(on) 0.8 1.4 A VDS=10 V, VGS=10V

Static Drain-SourceOn-State Resistance

RDS(on) 44.3

5.56

ΩΩ

VGS=10V,ID=500mAVGS=2.5V,ID=100mA

ForwardTransconductance (1) (2)

gfs 0.4 0.75 S VDS=10V,ID=0.5A

Input Capacitance (2) Ciss 110 200 pF

VDS=25V, VGS=0V, f=1MHzCommon Source OutputCapacitance (2)

Coss 15 25 pF

Reverse Transfer Capacitance (2)

Crss 3.5 15 pF

Turn-On Delay Time(2)(3)

td(on) 2.5 5 ns

VDD ≈50V, ID =0.25A,VGEN=10VRise Time (2)(3) tr 5 8 ns

Turn-Off Delay Time(2)(3)

td(off) 40 60 ns

Fall Time (2)(3) tf 16 25 ns

(1)*Measured under pulsed conditions. Pulse width=300µs. Duty cycle ≤2% (2)Sample Test

(3) Switching times measured with 50Ω source impedance and >5ns rise time on pulse generator

SUFFIX C

N-CHANNEL ENHANCEMENT

MODE VERTICAL DMOS FETISSUE 3 – August 1994

FEATURES* Compact E-LINE (TO92 style) package* 240 Volt BVDS* RDS(on)=4.3Ω Typical at VGS=2.5V* Low threshold* Fast switching

APPLICATIONS* Earth recall and dialling switches* Electronic hook switches* Battery powered equipment* Telecoms and high voltage dc-dc converters

ABSOLUTE MAXIMUM RATINGS.

PARAMETER SYMBOL VALUE UNIT

Drain-Source Voltage VDS 240 V

Continuous Drain Current at Tamb=25°C ID 260 mA

Pulsed Drain Current IDM 1.5 A

Gate Source Voltage VGS ± 40 V

Power Dissipation at Tamb=25°C Ptot 750 mW

Operating and Storage Temperature Range Tj:Tstg -55 to +150 °C

G D S

ZVN4424A/C

D G S

E-Line

TO92 Compatible

SUFFIX A

SPICE PARAMETERS*ZVN4424 MODEL LAST REVISION 1/94

*

.SUBCKT ZVN4424 30 40 50

* NODES: DRAIN GATE SOURCE

M1 30 20 50 50 MOD1 L=1 W=1

RG 40 20 200

RL 30 50 240E6

D1 50 30 DIODE1

.MODEL MOD1 NMOS VT0=1.25 RS=2.34 RD=1.634 IS=1E-15 KP=5.319

+CGS0=101P CGD0=4P CBD=66.2P PB=1

.MODEL DIODE1 D IS=5.516E-13 RS=0.2084 N=1.0078

.ENDS ZVN4424

For clarification of the above or for technical enquires generally please contact the Applications Dept.at Zetex plc.

©1992 ZETEX plcThe copyright in this model and the design embodied belonging to Zetex plc (“Zetex”). It is supplied free of charge by Zetex for thepurpose of research and design and may be used or copied intact (including this notice) for that purpose only. All other rights arereserved. The model is believed accurate but no condition or warranty as to its merchantability or fitness for the purpose is given and noliability in respect of any use is accepted by Zetex plc, its distributors or agents.

ZVN4424A/C

Zetex plc. Fields New Road, Chadderton, Oldham, OL9-8NP, United Kingdom. Telephone: (44)161-627 5105 (Sales), (44)161-627 4963 (General Enquiries) Fax: (44)161-627 5467

Zetex GmbH Zetex Inc. Zetex (Asia) Ltd. These are supported byStreitfeldstraße 19 47 Mall Drive, Unit 4 3510 Metroplaza, Tower 2 agents and distributors inD-81673 München Commack NY 11725 Hing Fong Road, major countries world-wideGermany USA Kwai Fong, Hong Kong Zetex plc 1997Telefon: (49) 89 45 49 49 0 Telephone: (516) 543-7100 Telephone:(852) 26100 611 Internet:Fax: (49) 89 45 49 49 49 Fax: (516) 864-7630 Fax: (852) 24250 494 http://www.zetex.com

This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, appliedor reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products orservices concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of anyproduct or service.

FPGA Configuration EEPROM Memory64K, 128K and 256K

AT17C65AT17LV65 AT17C128AT17LV128 AT17C256 AT17LV256

Features• EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories

Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)

• In-System Programmable via 2-wire Bus• Simple Interface to SRAM FPGAs• Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX® Devices, Lucent ORCA®

FPGAs, Xilinx XC3000, XC4000, XC5200, SPARTAN® FPGAs, Motorola MPA1000 FPGAs• Cascadable Read Back to Support Additional Configurations or Future Higher-density

Arrays (128K and 256K only)• Low-power CMOS EEPROM Process• Programmable Reset Polarity• Available in the Space-efficient Plastic DIP or SOIC Packages; PLCC Package is

Pin-compatible Across Product Family• Emulation of Atmel’s AT24CXXX Serial EEPROMs• Available in 3.3V ± 10% LV and 5V ± 5% C Versions• Low-power Standby Mode

DescriptionThe AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGAConfiguration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-figuration memory for Field Programmable Gate Arrays. The low-density AT17 Seriesis packaged in the 8-pin PDIP, 8-lead SOIC, and the popular 20-lead PLCC andSOIC. The AT17 Series family uses a simple serial-access procedure to configure oneor more FPGA devices. The AT17 Series organization supplies enough memory toconfigure one or multiple smaller FPGAs. Using a feature of the AT17 Series, the usercan select the polarity of the reset function by programming a special EEPROM byte.These devices also support a write-protection mechanism within its programmingmode.

The AT17 Series Configurators can be programmed with industry-standard program-mers, or Atmel’s ATDH2200E Programming Kit.

1

Pin Configurations20-lead PLCC

8-pin PDIP

20-lead SOIC

8-lead SOIC

45678

1817161514

CLKNC

(WP) RESET/OENCCE

NCSER_ENNCNCCEO (A2)

3 2 12

01

9

9 10

11

12

13

NC

GN

DN

CN

CN

C

NC

D

AT

AN

CV

CC

NC

1234

8765

DATACLK

(WP) RESET/OECE

VCCSER_ENCEO (A2)GND

12345678910

20191817161514131211

NCDATA

NCCLKNC

(WP) RESET/OENCCENC

GND

VCCNCNCSER_ENNCNCCEO (A2)NCNCNC

1234

8765

DATACLK

(WP) RESET/OECE

VCCSER_ENCEO (A2)GND

Rev. 1636B–05/00

Block Diagram

FPGA Master Serial Mode SummaryThe I/O and logic functions of the FPGA and their associ-ated interconnections are established by a configurationprogram. The program is loaded either automatically uponpower-up, or on command, depending on the state of theFPGA mode pins. In Master Mode, the FPGA automaticallyloads the configuration program from an external memory.The AT17 Serial Configuration EEPROM has beendesigned for compatibility with the Master Serial Mode.

This document discusses the AT6000 FPGA interface. Formore details or AT40K FPGA applications, please refer-ence “AT6000 Series Configuration” or “AT40K SeriesConfiguration” application notes.

Controlling the Low-density AT17 Series Serial EEPROMs During ConfigurationMost connections between the FPGA device and the AT17Serial EEPROM are simple and self-explanatory.• The DATA output of the AT17 Series Configurator drives

DIN of the FPGA devices.

• The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator.

• The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of EEPROMs. An AT17C/LV65 can only be used at the end of a cascade chain or as a standalone device.

• SER_EN must be connected to VCC (except during ISP).

There are two different ways to use the inputs CE and OE.

Condition 1The simplest connection is to have the FPGA CON pindrive both CE and RESET/OE(1) in parallel (Figure 1). Dueto its simplicity, however, this method will fail if the FPGAreceives an external reset condition during the configura-tion cycle. If a system reset is applied to the FPGA, it willabort the original configuration and then reset itself for anew configuration, as intended. Of course, the AT17 SeriesConfigurator does not see the external reset signal and willnot reset its internal address counters and, consequently,will remain out of sync with the FPGA for the remainder ofthe configuration cycle.

Note: 1. For this condition, the reset polarity of the EEPROM must be set active High.

POWER ONRESET

AT17C/LV65/128/2562

AT17C/LV65/128/256

Figure 1. Condition 1 Connection

Notes: 1. 4.7 kΩ resistors used unless otherwise specified.

2. Reset polarity of EEPROM must be set active High.

Condition 2The FPGA CON pin drives only the CE input of the AT17Series Configurator, while the RESET/OE input is driven byan input to the FPGA RESET input pin. This connectionworks under all normal circumstances, even when the useraborts a configuration before CON has gone High. A Lowlevel on the RESET/OE(1) input – during FPGA reset –clears the Configurator’s internal address pointer, so thatthe reconfiguration starts at the beginning.

Note: 1. For this condition, the reset polarity of the EEPROM must be set active Low.

The AT17 Series Configurator does not require aninverter for either condition since the RESET polarity isprogrammable.

Cascading Serial Configuration EEPROMs(AT17C/LV128 and AT17C/LV256 only)(1)

For multiple FPGAs configured as a daisy-chain, or forfuture FPGAs requiring larger configuration memories,cascaded Configurators provide additional memory.

After the last bit from the first Configurator is read, the nextclock signal to the Configurator asserts its CEO output lowand disables its DATA line driver. The second Configuratorrecognizes the Low level on its CE input and enables itsDATA output.

After configuration is complete, the address counters of allcascaded Configurators are reset if the RESET/OE oneach Configurator is driven to its active (default High) level.

If the address counters are not to be reset upon comple-tion, then the RESET/OE input can be tied to its inactive(default Low) level. Note: 1. A single AT17C/LV65 may be used at the end of a

cascade chain.

AT17 Series Reset PolarityThe AT17 Series Configurator allows the user to programthe reset polarity as either RESET/OE or RESET/OE. Thisfeature is supported by industry-standard programmeralgori thms. For more detai ls on programming theEEPROM’s reset polarity, please reference the “Program-ming Specification for Atmel ’s FPGA ConfigurationEEPROMs” application note.

Programming Mode The programming mode is entered by bringing SER_ENLow. In this mode the chip can be programmed by the2-wire serial bus. The programming is done at VCC supplyonly. Programming super voltages are generated inside thechip. See the “Programming Specification for Atmel’sFPGA Configuration EEPROMs” application note forfurther information. The AT17C parts are read/write at 5Vnominal. The AT17LV parts are read/write at 3.3V nominal.

Standby ModeThe AT17C/LV65/128/256 enters a low-power standbymode whenever CE is asserted High. In this mode, theConfigurator consumes less than 75 µA of current at 5.0V.The output remains in a high impedance state regardless ofthe state of the OE input.

M0

M1

CON

CCLK

D0REBOOT

AT60xxAT17C65/128/256

AT17LV65/128/256

GND

VCC

RESET/OE

SER_EN

CE

CLK

DATAM2

CS

VCC

3

Pin Configurations20

PLCC/ SOIC Pin

8DIP/SOICPin Name I/O Description

2 1 DATA I/O Three-state DATA output for configuration. Open-collector bi-directional pin for programming.

4 2 CLK I Clock input. Used to increment the internal address and bit counter for reading and programming.

6 3 RESET/OE I RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.

WP I Write protect (WP) input (when CE is Low). When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be written. This feature is only active in the 2-wire serial Programming Mode (i.e., when SER_EN is Low; see “Programming Specification” application note for more details).

8 4 CE I Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).

10 5 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.

14 6 CEO O Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.

A2 I Device selection input, A2. This is used to enable (or select) the device during programming (i.e. when SER_EN is Low; see the “Programming Specification” application note for more details.

17 7 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode.

20 8 VCC +3.3V/+5V Power Supply Pin.

Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper-ating conditions is not implied. Exposure to Abso-lute Maximum Rating conditions for extended periods of time may affect device reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pinwith Respect to Ground ..............................-0.1V to VCC +0.5V

Supply Voltage (VCC) .........................................-0.5V to +7.0V

Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C

ESD (RZAP = 1.5K, CZAP = 100pF).................................. 2000V

AT17C/LV65/128/2564

AT17C/LV65/128/256

Operating Conditions

Symbol Description

AT17CXXX AT17LVXXX

UnitsMin/Max Min/Max

VCC

CommercialSupply voltage relative to GND-0°C to +70°C 4.75/5.25 3.0/3.6 V

IndustrialSupply voltage relative to GND-40°C to +85°C 4.5/5.5 3.0/3.6 V

MilitarySupply voltage relative to GND-55°C to +125°C 4.5/5.5 3.0/3.6 V

5

DC CharacteristicsVCC = 5V ± 5% Commercial/5V ± 10% Ind./Mil.

Symbol Description Min Max Units

VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = -4 mA)Commercial

3.7 V

VOL Low-level output voltage (IOL = +4 mA) 0.32 V

VOH High-level output voltage (IOH = -4 mA)Industrial

3.6 V


VOH High-level output voltage (IOH = -4 mA)Military

3.5 V


ICCA Supply current, active mode 10 mA

IL Input or output leakage current (VIN = VCC or GND) -10 10 µA

ICCS Supply current, standby modeCommercial 75 µA

Industrial/Military 150 µA

DC CharacteristicsVCC = 3.3V ± 10%


VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = -2.5 mA)Commercial

2.4 V


VOH High-level output voltage (IOH = -2 mA)Industrial

2.4 V


VOH High-level output voltage (IOH = -2 mA)Military

2.4 V

VOL Low-level output voltage (IOL = +2.5 mA) 0.4 V

ICCA Supply current, active mode 5 mA

IL Input or output leakage current (VIN = VCC or GND) -10 10 µA

ICCS Supply current, standby modeCommercial 50 µA

Industrial/Military 100 µA

AT17C/LV65/128/2566

AT17C/LV65/128/256

AC Characteristics

AC Characteristics When Cascading

TSCE

TOE

TCE

TLC THC

TCAC TOH

THOE

TDF

TOH

TSCE

THCE

CE

RESET/OE

CLK

DATA

TCDF

TOCK TOCE

TOCE

TOOE

FIRST BITLAST BIT

CE

RESET/OE

CLK

DATA

CEO

7

Notes: 1. Preliminary specifications for military operating range only.2. AC test load = 50 pF.3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

AC Characteristics for AT17C65/128VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Ind./Mil.

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TOE(2) OE to Data Delay 30 35 ns

TCE(2) CE to Data Delay 50 50 ns

TCAC(2) CLK to Data Delay 50 55 ns

TOH Data Hold from CE, OE, or CLK 0 0 ns

TDF(3) CE or OE to Data Float Delay 50 50 ns

TLC CLK Low Time 30 35 ns

THC CLK High Time 30 35 ns

TSCE CE Setup Time to CLK (to guarantee proper counting) 45 50 ns

THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns

THOE OE High Time (guarantees counter is reset) 25 25 ns

FMAX MAX Input Clock Frequency 12.5 12.5 MHz

AC Characteristics for AT17C128 When CascadingVCC = 5V± 5% Commercial/VCC = 5V ± 10% Ind./Mil.

Symbol Description



TCDF(3) CLK to Data Float Delay 50 50 ns

TOCK(2) CLK to CEO Delay 55 60 ns

TOCE(2) CE to CEO Delay 55 60 ns

TOOE(2) RESET/OE to CEO Delay 40 45 ns

FMAX MAX Input Clock Frequency 8 8 MHz

AT17C/LV65/128/2568

AT17C/LV65/128/256

Notes: 1. Preliminary specifications for military operating range only.2. AC test load = 50 pF.3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

AC Characteristics for AT17C256VCC = 5V ±5% Commercial/VCC = 5V ± 10% Ind./Mil.

Symbol Description













FMAX MAX Input Clock Frequency 12.5 12.5 MHz

AC Characteristics for AT17C256 When CascadingVCC = 5V±5% Commercial/VCC = 5V ± 10% Ind./Mil.

Symbol Description








9

Notes: 1. Preliminary specifications for military operating range only.2. AC test lead = 50 pF.3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

AC Characteristics for AT17LV65/128/256VCC = 3.3V ± 10%

Symbol Description














AC Characteristics for AT17LV128/256 When CascadingVCC = 3.3V ± 10%

Symbol Description








AT17C/LV65/128/25610

AT17C/LV65/128/256

Ordering Information – 5V DevicesMemory Size Ordering Code Package Operation Range

64K AT17C65-10PCAT17C65-10NC

AT17C65-10JCAT17C65-10SC

8P38S1

20J20S

Commercial(0°C to 70°C)

AT17C65-10PIAT17C65-10NI

AT17C65-10JIAT17C65-10SI

8P38S1

20J20S

Industrial(-40°C to 85°C)

128K AT17C128-10PCAT17C128-10NC

AT17C128-10JCAT17C128-10SC

8P38S1

20J20S


AT17C128-10PIAT17C128-10NI

AT17C128-10JIAT17C128-10SI

8P38S1

20J20S


256K AT17C256-10PCAT17C256-10NC

AT17C256-10JCAT17C256-10SC

8P38S1

20J20S


AT17C256-10PIAT17C256-10NI

AT17C256-10JIAT17C256-10SI

8P38S1

20J20S


Package Type

8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

11

Ordering Information – 3.3V DevicesMemory Size Ordering Code Package Operation Range

64K AT17LV65-10PC

AT17LV65-10NCAT17LV65-10JCAT17LV65-10SC

8P3

8S120J20S

Commercial

(0°C to 70°C)

AT17LV65-10PI

AT17LV65-10NIAT17LV65-10JIAT17LV65-10SI

8P3

8S120J20S

Industrial

(-40°C to 85°C)

128K AT17LV128-10PC

AT17LV128-10NCAT17LV128-10JCAT17LV128-10SC

8P3

8S120J20S

Commercial

(0°C to 70°C)

AT17LV128-10PI

AT17LV128-10NIAT17LV128-10JI

AT17LV128-10SI

8P3

8S120J

20S

Industrial

(-40°C to 85°C)

256K AT17LV256-10PCAT17LV256-10NCAT17LV256-10JC

AT17LV256-10SC

8P38S120J

20S


AT17LV256-10PIAT17LV256-10NIAT17LV256-10JI

AT17LV256-10SI

8P38S120J

20S


Package Type

8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

AT17C/LV65/1212

AT17C/LV65/128/

Packaging Information

.400 (10.16)

.355 (9.02)

PIN1

.280 (7.11)

.240 (6.10)

.037 (.940)

.027 (.690).300 (7.62) REF

.210 (5.33) MAX

SEATINGPLANE

.100 (2.54) BSC

.015 (.380) MIN

.022 (.559)

.014 (.356)

.150 (3.81)

.115 (2.92).070 (1.78).045 (1.14)

.325 (8.26)

.300 (7.62)

015

REF

.430 (10.9) MAX

.012 (.305)

.008 (.203)

JEDEC STANDARD MS-001 BA

.020 (.508)

.013 (.330)

PIN 1

.157 (3.99)

.150 (3.81).244 (6.20).228 (5.79)

.050 (1.27) BSC

.196 (4.98)

.189 (4.80).068 (1.73).053 (1.35)

.010 (.254)

.004 (.102)

08

REF .010 (.254).007 (.203)

.050 (1.27)

.016 (.406)

0.299 (7.60)0.291 (7.39)

0.020 (0.508)0.013 (0.330)

0.420 (10.7)0.393 (9.98)

PIN 1

.050 (1.27) BSC

0.513 (13.0)0.497 (12.6)

0.012 (0.305)0.003 (0.076)

0.105 (2.67)0.092 (2.34)

08

REF

0.035 (0.889)0.015 (0.381)

0.013 (0.330)0.009 (0.229)

8P3, 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)Dimensions in Inches and (Millimeters)

8S1, 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)Dimensions in Inches and (Millimeters)

20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-018 AA

20S, 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)Dimensions in Inches and (Millimeters)

13

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility forany errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time withoutnotice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products arenot authorized for use as critical components in life support devices or systems.

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Printed on recycled paper.

1636B–05/00/xM

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

6

XC4000XL Electrical SpecificationsDefinition of TermsIn the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined asfollows:

Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, ordevicefamilies. Values are subject to change. Use as estimates, not for production.

Preliminary: Based on preliminary characterization. Further changes are not expected.

Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.

Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document arederived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junctiontemperature conditions.

All specifications subject to change without notice.

XC4000XL D.C. Characteristics

Absolute Maximum Ratings

Recommended Operating Conditions

Description Units

VCC Supply voltage relative to Ground -0.5 to 4.0 V

VIN Input voltage relative to Ground (Note 1) -0.5 to 5.5 V

VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V

VCCt Longest Supply Voltage Rise Time from 1 V to 3V 50 ms

TSTG Storage temperature (ambient) -65 to +150 °CTSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C

TJ Junction TemperatureCeramic packages +150 °CPlastic packages +125 °C

Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier toachieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC +2.0 V, provided this over orundershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those listed underRecommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extendedperiods of time may affect device reliability.


VCCSupply voltage relative to Gnd, TJ = 0 °C to +85°C Commercial 3.0 3.6 V

Supply voltage relative to Gnd, TJ = -40°C to +100°C Industrial 3.0 3.6 V

VIH High-level input voltage 50% of VCC 5.5 V

VIL Low-level input voltage 0 30% of VCC V

TIN Input signal transition time 250 ns

Notes: At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.Input and output measurement threshold is ~50% of VCC.

DS005 (v. 1.8 October 18, 1999 - Product Specification 6-73

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D.C. Characteristics Over Recommended Operating Conditions

Power-0n Power Supply RequirementsXilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supplyramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. Theslowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2ms. The current capacityvaries linealy with ramp-up time, e.g., an XC4036XL with a ramp-up time of 25 ms would require a capacity predicted by thepoint on the straight line drawn from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately750 mA .


VOHHigh-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) 2.4 V

High-level output voltage @ IOH = -500 µA, (LVCMOS) 90% VCC V

VOLLow-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) 0.4 V

Low-level output voltage @ IOL = 1500 µA, (LVCMOS) 10% VCC V

VDR Data Retention Supply Voltage (below which configuration data may be lost) 2.5 V

ICCO Quiescent FPGA supply current (Note 2) 5 mA

IL Input or output leakage current -10 +10 µA

CIN

Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQpackages

10 pF

PGA packages 16 pF

IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA

IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA

IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA

Note 1: With up to 64 pins simultaneously sinking 12 mA.Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.

Product DescriptionRamp-up Time

Fast (120 µs) Slow (50 ms)

XC4005 - 36XL Minimum required current supply 1 A 500 mA

XC4044- 62XL Minimum required current supply 2 A 500 mA

XC4085XL1 Minimum required current supply 2 A1 500 mA

Notes: 1. The XC4085XL fast ramp-up time is 5 ms.Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may

result in a larger initialization current.This specification applies to Commercial and Industrial grade products only.Ramp-up Time is measured from 0 VDC to 3.6 VDC. Peak current required lasts less than 3 ms, and occurs near the

internal power on reset threshold voltage. After initialization and before configuration, ICCmax is less than 10 mA.

6-74 DS005 (v. 1.8 October 18, 1999 - Product Specification

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6

XC4000XL A.C. CharacteristicsTesting of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values where one global clock input drives one vertical clock line in each accessible column, and where allaccessible IOB and CLB flip-flops are clocked by the global clock net.

When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are drivenfrom the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflectingthe actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the statictiming analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junctiontemperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.

Global Low Skew Buffer to Clock K

Speed Grade All -3 -2 -1 -09 -08Units

Description Symbol Device Min Max Max Max Max Max

Delay from pad through GLS buffer toany clock input, K

TGLS XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

0.30.40.50.60.70.91.11.21.31.41.6

2.12.73.23.64.04.44.85.35.76.37.2

1.82.32.83.13.53.84.24.65.05.46.2

1.62.02.42.73.03.33.64.04.54.75.7

1.51.92.32.62.93.23.53.94.44.65.5

2.3

3.1

4.0

nsnsnsnsnsnsnsnsnsnsns


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Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock

Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock



Delay from pad through GE buffer to anyIOB clock input.

TGE XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

0.10.30.30.40.40.30.30.20.30.30.4

1.61.92.22.42.62.83.13.54.04.95.8

1.41.81.92.12.22.42.73.03.54.35.1

1.31.71.71.82.12.12.32.63.03.74.7

1.21.61.71.72.02.02.22.43.03.44.3

1.5

1.9

3.0




Delay from pad through GE buffer to anyIOB clock input.

TGE XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

0.50.70.70.70.80.90.91.01.11.21.3

2.83.13.53.84.14.44.75.15.55.96.8

2.52.83.13.33.63.94.24.54.85.26.0

2.12.72.82.93.43.43.74.04.34.85.5

1.72.52.72.83.23.33.63.74.34.55.2

2.4

3.1

4.0



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6

XC4000XL CLB CharacteristicsTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by thestatic timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timingparameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to allXC4000XL devices and are expressed in nanoseconds unless otherwise noted.

CLB Switching Characteristic Guidelines

Speed Grade -3 -2 -1 -09 -08

Description Symbol Min Max Min Max Min Max Min Max Min Max

Combinatorial Delays

F/G inputs to X/Y outputsF/G inputs via H’ to X/Y outputsF/G inputs via transparent latch to Q outputsC inputs via SR/H0 via H to X/Y outputsC inputs via H1 via H to X/Y outputsC inputs via DIN/H2 via H to X/Y outputsC inputs via EC, DIN/H2 to YQ, XQ output (bypass)

TILOTIHOTITOTHH0OTHH1OTHH2OTCBYP

1.62.72.92.52.42.51.5

1.52.42.62.22.12.21.3

1.32.22.22.01.92.01.1

1.22.02.01.81.61.81.0

1.11.91.81.81.51.80.9

CLB Fast Carry Logic

Operand inputs (F1, F2, G1, G4) to COUTAdd/Subtract input (F3) to COUTInitialization inputs (F1, F3) to COUTCIN through function generators to X/Y outputsCIN to COUT, bypass function generatorsCarry Net Delay, COUT to CIN

TOPCYTASCYTINCYTSUMTBYPTNET

2.73.32.02.8

0.260.32

2.32.91.82.6

0.230.28

2.02.51.52.40.200.25

1.61.81.01.70.140.24

1.61.80.91.5

0.140.24

Sequential Delays

Clock K to Flip-Flop outputs QClock K to Latch outputs Q

TCKOTCKLO

2.12.1

1.91.9

1.61.6

1.51.5

1.41.4

Setup Time before Clock K

F/G inputsF/G inputs via HC inputs via H0 through HC inputs via H1 through HC inputs via H2 through HC inputs via DINC inputs via ECC inputs via S/R, going Low (inactive)CIN input via F/GCIN input via F/G and H

TICKTIHCKTHH0CKTHH1CKTHH2CKTDICKTECCKTRCKTCCKTCHCK

1.12.22.01.92.00.91.00.62.33.4

1.01.91.71.61.70.80.90.52.13.0

0.91.71.61.41.60.70.80.51.92.7

0.81.61.41.21.40.60.70.41.32.1

0.81.51.41.11.40.60.70.41.22.0

Hold Time after Clock K

F/G inputsF/G inputs via HC inputs via SR/H0 through HC inputs via H1 through HC inputs via DIN/H2 through HC inputs via DIN/H2C inputs via ECC inputs via SR, going Low (inactive)

TCKITCKIHTCKHH0TCKHH1TCKHH2TCKDITCKECTCKR

00000000

00000000

00000000

00000000

00000000

Clock

Clock High timeClock Low time

TCHTCL

3.03.0

2.82.8

2.52.5

2.32.3

2.12.1

Set/Reset Direct

Width (High)Delay from C inputs via S/R, going High to Q

TRPWTRIO

3.03.7

2.83.2

2.52.8

2.32.7

2.32.6

Global Set/Reset

Minimum GSR Pulse Width TMRW 19.8 17.3 15.0 14.0 14.0

Delay from GSR input to any Q TMRQ See Table on page 85 for TRRI values per device.

Toggle Frequency (MHz) (for export control) FTOG (MHz) 166 179 200 217 238


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CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by thestatic timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timingparameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to allXC4000XL devices and are expressed in nanoseconds unless otherwise noted.

Single Port RAM Speed Grade -3 -2 -1 -09 -08

Size Symbol Min Max Min Max Min Max Min Max Min Max

Write Operation

Address write cycle time (clock K period) 16x232x1

TWCSTWCTS

9.09.0

8.48.4

7.77.7

7.47.4

7.47.4

Clock K pulse width (active edge) 16x232x1

TWPSTWPTS

4.54.5

4.24.2

3.93.9

3.73.7

3.73.7

Address setup time before clock K 16x232x1

TASSTASTS

2.22.2

2.02.0

1.71.7

1.71.7

1.61.7

Address hold time after clock K 16x232x1

TAHSTAHTS

00

00

00

00

00

DIN setup time before clock K 16x232x1

TDSSTDSTS

2.02.5

1.92.3

1.72.1

1.72.1

1.72.1

DIN hold time after clock K 16x232x1

TDHSTDHTS

00

00

00

00

00

WE setup time before clock K 16x232x1

TWSSTWSTS

2.01.8

1.81.7

1.61.5

1.61.5

1.61.5

WE hold time after clock K 16x232x1

TWHSTWHTS

00

00

00

00

00

Data valid after clock K 16x232x1

TWOSTWOTS

6.88.1

6.37.5

5.86.9

5.86.7

5.76.7

Read Operation

Address read cycle time 16x232x1

TRCTRCT

4.56.5

3.15.5

2.63.8

2.63.8

2.63.8

Data Valid after address change (noWrite Enable)

16x232x1

TILOTIHO

1.62.7

1.52.4

1.32.2

1.22.0

1.11.9

Address setup time before clock K 16x232x1

TICKTIHCK

1.12.2

1.01.9

0.91.7

0.81.6

0.81.5


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6

CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by thestatic timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timingparameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to allXC4000XL devices and are expressed in nanoseconds unless otherwise noted.

CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms

Dual Port RAM Speed Grade -3 -2 --1 -09 -08

Size Symbol Min Max Min Max Min Max Min Max Min Max

Address write cycle time (clock K period)Clock K pulse width (active edge)Address setup time before clock KAddress hold time after clock KDIN setup time before clock KDIN hold time after clock KWE setup time before clock KWE hold time after clock KData valid after clock K

16x116x116x116x116x116x116x116x116x1

TWCDSTWPDSTASDSTAHDSTDSDSTDHDSTWSDSTWHDSTWODS

9.04.52.50

2.50

1.80

7.8

8.44.22.00

2.30

1.70

7.3

7.73.91.70

2.00

1.60

6.7

7.43.71.70

2.00

1.60

6.7

7.43.71.60

2.00

1.60

6.6

X6461

WCLK (K)

WE

ADDRESS

DATA IN

DATA OUT OLD NEW

TDSSTDHS

TASS TAHS

TWSS

TWPS

TWHS

TWOS

TILOTILO

WCLK (K)

WE

ADDRESS

DATA IN

TDSDSTDHDS

TASDS TAHDS

TWSDS

TWPDS

TWHDS

X6474

DATA OUT OLD NEW

TWODS

TILOTILO

Single-Port RAM Dual-Port RAM


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XC4000XL Pin-to-Pin Output Parameter GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and areguaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representativevalues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx DevelopmentSystem) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted fromthe static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.

Output Flip-Flop, Clock to Out

Capacitive Load FactorFigure 60 shows the relationship between I/O output delayand load capacitance. It allows a user to adjust the speci-fied output delay if the load capacitance is different than50 pF. For example, if the actual load capacitance is120 pF, add 2.5 ns to the specified delay. If the load capac-itance is 20 pF, subtract 0.8 ns from the specified outputdelay.

Figure 60 is usable over the specified operating conditionsof voltage and temperature and is independent of the out-put slew rate control.

Figure 60: Delay Factor at Various Capacitive Loads



Global Low Skew Clock to Output us-ing Output Flip Flop

TICKOF XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

1.21.31.41.51.61.82.02.12.22.32.5

7.17.78.28.69.09.49.8

10.310.711.312.2

6.16.67.17.47.88.18.58.99.39.7

10.5

5.45.86.26.56.87.17.47.88.38.59.5

5.15.45.86.16.46.77.07.47.98.19.0

5.6

6.4

7.3


For output SLOW option add TSLOW All Devices 0.5 3.0 2.5 2.0 1.7 1.6 ns

Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay ismeasured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving allaccessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determinedby the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pinclock-to-out delay for clocked outputs for FAST mode configurations.

Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.

X8257

-20 20 40 60 80

Capacitance (pF)

Del

ta D

elay

(ns

)

100 120 140

-1

0

1

2

3


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6

Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6

Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8



Global Early Clock to Output usingOutput Flip Flop. Values are for BUF-GE #s 1, 2, 5, and 6.

TICKEOF XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

1.01.21.21.31.31.21.21.11.21.21.3

6.66.97.27.47.67.88.18.59.09.9

10.8

5.76.16.26.46.56.77.07.37.88.69.4

5.15.55.55.65.95.96.16.46.87.58.5

4.85.25.35.35.65.65.86.06.67.07.9

4.8

5.2

6.3






Global Early Clock to Output usingOutput Flip Flop. Values are for BUF-GE #s 3, 4, 7, and 8.

TICKEOF XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

1.31.51.61.61.71.71.81.92.02.02.2

7.88.18.58.89.19.49.7

10.110.510.911.8

6.87.17.47.67.98.28.58.89.19.5

10.3

5.96.56.66.77.27.27.57.88.18.69.3

5.36.16.36.46.86.97.27.37.98.18.8

5.7

6.4

7.3





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XC4000XL Pin-to-Pin Input Parameter GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and areguaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representativevalues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx DevelopmentSystem) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted fromthe static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted

Global Low Skew Clock, Set-Up and Hold

Speed Grade -3 -2 -1 -09 -08Units

Description Symbol Device Min Min Min Min MinInput Setup and Hold TimesNo DelayGlobal Low Skew Clock and IFFGlobal Low Skew Clock and FCL

TPSN/TPHN XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

2.5 / 1.51.2 / 2.61.2 / 3.01.2 / 3.21.2 / 3.71.2 / 4.41.2 / 5.51.2 / 5.81.2 / 7.11.2 / 7.01.2 / 9.4

2.2 / 1.31.1 / 2.21.1 / 2.61.1 / 2.81.1 / 3.21.1 / 3.81.1 / 4.81.1 / 5.01.1 / 6.21.1 / 6.11.1 / 8.2

1.9 / 1.20.9 / 2.00.9 / 2.30.9 / 2.40.9 / 2.80.9 / 3.30.9 / 4.10.9 / 4.40.9 / 5.40.9 / 5.30.9 / 7.1

1.7 / 1.00.8 / 1.70.8 / 2.00.8 / 2.10.8 / 2.40.8 / 2.90.8 / 3.60.8 / 3.80.8 / 4.70.8 / 4.60.8 / 6.2

0.8 / 2.1

0.8 / 3.6

0.8 / 4.6


Partial DelayGlobal Low Skew Clock and IFFGlobal Low Skew Clock and FCL

TPSP/TPHP XC4002XLXC4005XLXC4010XLXC4013XL*XC4020XLXC4028XLXC4036XL*XC4044XLXC4052XLXC4062XL*XC4085XL

8.4 / 0.010. 5 / 0.011.1 / 0.0

6.1 / 1.011.9 / 1.012.3 / 1.0

6.4 / 1.013.1 / 1.011.9 / 1.0

6.7 / 1.212.9 / 1.2

7.3 / 0.09.1 / 0.09.7 / 0.05.3 / 1.0

10.3 / 1.010.7 / 1.05.6 / 1.0

11.4 / 1.010.3 / 1.05.8 / 1.2

11.2 / 1.2

6.3 / 0.07.9 / 0.08.4 / 0.04.6 / 1.09.0 / 1.09.3 / 1.04.8 / 1.09.9 / 1.09.0 / 1.05.1 / 1.29.8 / 1.2

5.5 / 0.06.9 / 0.07.3 / 0.04.0 / 1.07.8 / 1.08.1 / 1.04.2 / 1.08.6 / 1.07.8 / 1.04.4 / 1.28.5 / 1.2

3.7 / 0.5

4.0/ 0.8

4.2/ 1.0


Full DelayGlobal Low Skew Clock and IFF

TPSD/TPHD XC4002XLXC4005XLXC4010XLXC4013XL*XC4020XLXC4028XLXC4036XL*XC4044XLXC4052XLXC4062XL*XC4085XL

6.8 / 0.08.8 / 0.09.0 / 0.06.4 / 0.08.8 / 0.09.3 / 0.06.6 / 0.0

10.6 / 0.011.2 / 0.0

6.8 / 0.012.7 / 0.0

6.0 / 0.07.6 / 0.07.8 / 0.06.0 / 0.07.6 / 0.08.1 / 0.06.2 / 0.09.2 / 0.09.7 / 0.06.4 / 0.0

11.0 / 0.0

5.2 / 0.06.6 / 0.06.8 / 0.05.6 / 0.06.6 / 0.07.0 / 0.05.8 / 0.08.0 / 0.08.4 / 0.06.0 / 0.09.6 / 0.0

4.5 / 0.05.6 / 0.05.8 / 0.04.8 / 0.06.2 / 0.06.4 / 0.05.3 / 0.06.8 / 0.07.0 / 0.05.5 / 0.08.4 / 0.0

4.8 / 0.0

5.3 / 0.0

5.5 / 0.0


IFF = Input Flip-Flop or Latch* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.Notes: Input setup time is measured with the fastest route and the lightest load.

Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving allaccessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determinedby the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.


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6

Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL


Description Symbol Device Min Min Min Min MinInput Setup and HoldTimesNo DelayGlobal Early Clock and IFFGlobal Early Clock and

FCL

TPSEN/TPHENTPFSEN/TPFHEN

XC4002XLXC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

2.8 / 1.51.2 / 4.11.2 / 4.41.2 / 4.71.2 / 4.61.2 / 5.31.2 / 6.71.2 / 6.51.2 / 6.71.2 / 8.41.2 / 8.7

2.5 / 1.31.1 / 3.61.1 / 3.81.1 / 4.11.1 / 4.01.1 / 4.61.1 / 5.81.1 / 5.71.1 / 5.81.1 / 7.31.1 / 7.5

2.2 / 1.20.9 / 3.10.9 / 3.30.9 / 3.60.9 / 3.50.9 / 4.00.9 / 5.10.9 / 4.90.9 / 5.10.9 / 6.30.9 / 6.6

1.9 / 1.00.8 / 2.70.8 / 2.90.8 / 3.10.8 / 3.00.8 / 3.50.8 / 4.40.8 / 4.30.8 / 4.40.8 / 5.50.8 / 5.7

0.5 / 2.7

0.5 / 3.7

0.5 / 4.7


Partial DelayGlobal Early Clock and IFFGlobal Early Clock and

FCL

TPSEP/TPHEPTPFSEP/TPFHEP

XC4002XLXC4005XLXC4010XLXC4013XL*XC4020XLXC4028XLXC4036XL*XC4044XLXC4052XLXC4062XL*XC4085XL

8.1 / 0.99.0 / 0.0

11.9 / 0.06.4 / 0.0

10.8 / 0.014.0 / 0.07.0 / 0.0

14.6 / 0.016.4 / 0.09.0 / 0.8

16.7 / 0.0

7.0 / 0.88.5 / 0.0

10.4 / 0.05.9 / 0.0

10.3 / 0.012.2 / 0.06.6 / 0.0

12.7 / 0.014.3 / 0.08.6 / 0.8

14.5 / 0.0

6.1 / 0.78.0 / 0.09.0 / 0.05.4 / 0.09.8 / 0.0

10.6 / 0.06.2 / 0.0

11.0 / 0.012.4 / 0.08.2 / 0.8

12.6 / 0.0

5.3 / 0.67.5 / 0.08.0 / 0.04.9 / 0.09.0 / 0.09.8 / 0.05.2 / 0.0

10.8 / 0.011.4 / 0.07.0 / 0.8

11.6 / 0.0

4.4 / 0.0

4.7 / 0.0

6.3 / 0.5


Full DelayGlobal Early Clock and IFF TPSED/TPHED


6.7 / 0.010.8 / 0.010.3 / 0.010.0 / 0.012.0 / 0.012.6 / 0.012.2 / 0.013.8 / 0.014.1 / 0.013.1 / 0.017.9 / 0.0

5.8 / 0.09.4 / 0.09.0 / 0.08.7 / 0.0

10.4 / 0.011.0 / 0.010.6 / 0.012.0 / 0.012.3 / 0.011.4 / 0.015.6 / 0.0

5.1 / 0.08.2 / 0.07.8 / 0.07.6 / 0.09.1 / 0.09.5 / 0.09.2 / 0.0

10.5 / 0.010.7 / 0.09.9 / 0.0

13.6 / 0.0

4.4 / 0.07.1 / 0.06.8 / 0.06.6 / 0.07.9 / 0.08.3 / 0.08.0 / 0.09.1 / 0.09.3 / 0.08.6 / 0.0

11.8 / 0.0

6.0 / 0.0

7.2 / 0.0

7.8 / 0.0


IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.Notes: Input setup time is measured with the fastest route and the lightest load.



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Global Early Clock BUFGEs 3, 4, 7, and 8 Set-up and Hold for IFF and FCL


Description Symbol Device Min Min Min Min MinInput Setup & Hold TimesNo DelayGlobal Early Clock and

IFFGlobal Early Clock and

FCL

TPSEN/TPHENTPFSEN/TPFHEN


3.0 / 2.01.2 / 4.11.2 / 4.41.2 / 4.71.2 / 4.61.2 / 5.31.2 / 6.71.2 / 6.51.2 / 6.71.2 / 8.41.2 / 8.7

2.6 / 1.71.1 / 3.61.1 / 3.81.1 / 4.11.1 / 4.01.1 / 4.61.1 / 5.81.1 / 5.71.1 / 5.81.1 / 7.31.1 / 7.5

2.3 / 1.50.9 / 3.10.9 / 3.30.9 / 3.60.9 / 3.50.9 / 4.00.9 / 5.10.9 / 4.90.9 / 5.10.9 / 6.30.9 / 6.6

2.0 / 1.30.8 / 2.70.8 / 2.90.8 / 3.10.8 / 3.00.8 / 3.50.8 / 4.40.8 / 4.30.8 / 4.40.8 / 5.50.8 / 5.7

0.5 / 2.7

0.5 / 3.7

0.5 / 4.7


Partial DelayGlobal Early Clock and

IFFGlobal Early Clock and

FCL

TPSEP/TPHEPTPFSEP/TPFHEP


7.3 / 1.58.4 / 0.0

10.3 / 0.05.4 / 0.09.8 / 0.0

12.7 / 0.06.4 / 0.8

13.8 / 0.014.5 / 0.08.4 / 1.5

14.5 / 0.0

6.4 / 1.37.9 / 0.09.0 / 0.04.9 / 0.09.3 / 0.0

11.0 / 0.05.9 / 0.8

12.0 / 0.012.7 / 0.0

7.9 / 1.512.7 / 0.0

5.5 / 1.27.4 / 0.07.8 / 0.04.4 / 0.08.8 / 0.09.6 / 0.05.4 / 0.8

10.4 / 0.011.0 / 0.07.4 / 1.5

11.0 / 0.0

4.8 / 1.07.2 / 0.07.4 / 0.04.3 / 0.08.5 / 0.09.3 / 0.05.0 / 0.8

10.2 / 0.010.7 / 0.06.8 / 1.5

10.8 / 0.0

4.0 / 0.0

4.6 / 0.2

6.2 / 0.0


Full DelayGlobal Early Clock and

IFFTPSED/TPHED


5.9 / 0.010.8 / 0.010.3 / 0.010.0 / 0.012.0 / 0.012.6 / 0.012.2 / 0.013.8 / 0.014.1 / 0.013.1 / 0.017.9 / 0.0

5.2 / 0.09.4 / 0.09.0 / 0.08.7 / 0.0

10.4 / 0.011.0 / 0.010.6 / 0.012.0 / 0.012.3 / 0.011.4 / 0.015.6 / 0.0

4.5 / 0.08.2 / 0.07.8 / 0.07.6 / 0.09.1 / 0.09.5 / 0.09.2 / 0.0

10.5 / 0.010.7 / 0.09.9 / 0.0

13.6 / 0.0

3.9 / 0.07.1 / 0.06.8 / 0.06.6 / 0.07.9 / 0.08.3 / 0.08.0 / 0.09.1 / 0.09.3 / 0.08.6 / 0.0

11.8 / 0.0

6.0 / 0.0

7.2 / 0.0

7.8 / 0.0


* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.IFF = Input Flip Flop or Latch. FCL = Fast Capture LatchNotes: Input setup time is measured with the fastest route and the lightest load.



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6

XC4000XL IOB Input Switching Characteristic GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by thestatic timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These pathdelays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assumeworst-case operating conditions (supply voltage and junction temperature).


Description Symbol Device Min Min Min Min MinClocksClock Enable (EC) to Clock (IK) TECIK All devices 0.1 0.1 0.1 0.1 0.1 nsDelay from FCL enable (OK) active edge toIFF clock (IK) active edge

TOKIK XC4002XLXC4013, 36, 62XLBalance of Family

3.02.22.2

2.71.91.9

2.31.61.6

2.31.61.6

1.6nsnsns

Setup TimesPad to Clock (IK), no delay TPICK XC4002XL

XC4013, 36, 62XLBalance of Family

2.61.71.7

2.31.51.5

2.01.31.3

2.01.31.3

1.2nsnsns

Pad to Clock (IK), via transparent Fast Cap-ture Latch, no delay

TPICKF XC4002XLXC4013, 36, 62XLBalance of Family

3.22.32.3

2.92.02.0

2.51.81.8

2.41.71.7

1.6nsnsns

Pad to Fast Capture Latch Enable (OK), nodelay

TPOCK XC4013, 36, 62XLBalance of Family

1.21.2

1.01.0

0.90.9

0.90.9

0.9 nsns

Hold TimesAll Hold Times All Devices 0 0 0 0 0Global Set/ResetMinimum GSR Pulse Width TMRW All devices 19.8 17.3 15.0 14.0 14.0 nsGlobal Set/Reset Max Max Max Max MaxDelay from GSR input to any Q TRRI* XC4002XL

XC4005XLXC4010XLXC4013XLXC4020XLXC4028XLXC4036XLXC4044XLXC4052XLXC4062XLXC4085XL

9.811.313.915.918.620.522.525.127.229.134.4

8.59.8

12.113.816.117.919.621.923.625.329.9

7.48.5

10.512.014.015.517.019.020.522.026.0

7.08.110.011.413.314.316.218.119.520.924.7

10.9

16.2

20.4


Propagation DelaysPad to I1, I2 TPID All devices 1.6 1.4 1.2 1.1 1.0 nsPad to I1, I2 via transparent input latch,no delay

TPLI XC4002XLXC4013, 36, 62XLBalance of Family

4.73.13.1

4.22.72.7

3.62.42.4

3.52.22.2

2.1nsnsns

Pad to I1, I2 via transparent FCL and in-put latch, no delay

TPFLI X4002XLXC4013, 36, 62XLBalance of Family

5.43.73.7

4.73.33.3

4.12.82.8

3.92.72.7

2.5nsnsns

Clock (IK) to I1, I2 (flip-flop)Clock (IK) to I1, I2 (latch enable, activeLow)FCL Enable (OK) active edge to I1, I2

(via transparent standard input latch)

TIKRITIKLITOKLI

All devicesAll devicesXC4002XL

XC4013, 36, 62XLBalance of Family

1.71.85.23.63.6

1.51.64.63.13.1

1.31.44.02.72.7

1.21.33.82.62.6

1.21.3

2.5

nsnsnsnsns

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch* Indicates Minimum Amount of Time to Assure Valid Data.


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XC4000XL IOB Output Switching Characteristic GuidelinesTesting of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below arerepresentative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by thestatic timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These pathdelays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assumeworst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unlessotherwise noted. Values are expressed in nanoseconds unless otherwise noted.

-3 -2 -1 -09 -08

Description Symbol Min Max Min Max Min Max Min Max Min Max

Clocks

Clock HighClock Low

TCHTCL

3.03.0

2.82.8

2.52.5

2.32.3

2.12.1

Propagation Delays

Clock (OK) to PadOutput (O) to Pad3-state to Pad hi-Z (slew-rate independent)3-state to Pad active and validOutput (O) to Pad via Fast Output MUXSelect (OK) to Pad via Fast MUX

TOKPOFTOPFTTSHZTTSONFTOFPFTOKFPF

5.04.14.04.45.55.1

4.33.63.53.84.84.5

3.83.13.03.34.23.9

3.53.02.93.34.03.7

3.32.82.93.33.73.4

Setup and Hold Times

Output (O) to clock (OK) setup timeOutput (O) to clock (OK) hold timeClock Enable (EC) to clock (OK) setup timeClock Enable (EC) to clock (OK) hold time

TOOKTOKOTECOKTOKEC

0.50.00.00.3

0.40.00.00.2

0.30.00.00.1

0.30.00.00.0

0.30.00.00.0

Global Set/Reset

Minimum GSR pulse widthDelay from GSR input to any Pad


TMRWTRPO*

19.8

14.315.918.520.523.225.127.129.731.733.739.0

17.3

12.513.816.117.820.121.923.625.927.629.333.9

15.0

10.912.014.015.517.519.020.522.524.025.529.5

14.0

10.311.413.314.716.617.619.421.422.824.228.0

14.0

14.0

19.3

23.5

Slew Rate Adjustment

For output SLOW option add TSLOW 3.0 2.5 2.0 1.7 1.6

Note: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.* Indicates Minimum Amount of Time to Assure Valid Data.


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6

Revision ControlVersion Nature of Changes

2/1/99 (1.5) Release included in the 1999 data book, section 65/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and

added URL link on placeholder page for electrical specifications/pinouts for WebLINX users9/30/99 (1.7) Added Power-on specification.

10/18/99 (1.8) Corrected posted file to include missing page (IOB Output Parameters).


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84-Pin PLCCXC4000/XC5200 Common Footprint

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CONFIGURATION MODE

Master Parallel High A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Master Parallel Low (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O) (O)

Sync. Periph. Mode TDO

Async. Periph. Mode CS1(I) WS(I)(O)

Master Serial ModeSerial Slave Mode

Normal OperationV

CC

üü I/O

VC

C

GN

D

I/O

GC

K4

GN

D

üü

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

GND 12 74 VCCA16(O) GCK1 13 Top View 73 CCLK(I) CCLK(I) CCLK(O) CCLK(I) CCLK(O)

A17(O) 14 72 üü DOUT(O)

TDI(I) üü 15 71 DIN(I) D0(I)

TCK(I) üü 16 70 RDY/BSY(O) RCLK(O)

TMS(I) 17 69 I/O D1(I)

I/O 18 68

19 67 D2(I)

20 66 RS(I)

GND 21 65 D3(I)

VCC 22 64 GND23 63 VCC24 62

25 61 D4(I)

I/O 26 60 CS0(I)

27 59 I/O D5(I)

28 58 D6(I)

üü 29 57 GCK3

M1 HI LO HI LO LO HI üü 30 56 D7(I)

GND 31 55 PROG(I)

M0 LO LO HI HI LO HI üü 32 54 VCC33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

VC

C

üü

GC

K2

I/O

VC

C

GN

D

I/O üü

GN

DD

ON

E(O

)

Normal Operation

HI Serial Slave ModeLO HDC LDC INIT Master Serial ModeHI

(O) (O) (O) Async. Periph. ModeLO Sync. Periph. ModeHI Master Parallel LowHI Master Parallel High

M2 CONFIGURATION MODEIndicates a pin that is not active during configuration.

Pin Type Number As User I/O

General user I/O (no special symbols required) 59 Pin Special Pin Functions XC4000 XC5200JTAG as I/O (using TDO, TDI, TCK special symbols) 3 ü P10 XC4000 secondary buffer (SGCK1), not in XC5200 I/O I/OM2, M1, M0 as I/O (using M2, M1, M0 special symbols) 3 P13 Global buffer input I/O I/OTOTAL POSSIBLE I/O PINS 65 ü P15 Optional JTAG Test Data Input (TDI symbol) I I/OVCC pins 8 ü P16 Optional JTAG Test Clock input (TCK symbol) I I/OGround (GND) pins 8 P17 Optional JTAG Test Mode Select input (TMS) I/O I/ODedicated control pins 3 ü P29 XC4000 secondary buffer (SGCK2), not in XC5200 I/O I/OTOTAL DEVICE PINS 84 ü P30 M1 mode pin (M1 symbol), RTRIG read trigger O I/O

ü P32 M0 mode pin (M0 symbol), RDATA readback data I I/Oü P34 M2 mode pin (M2 symbol) I I/O

P35 Global buffer input I/O I/Oü P51 XC4000 secondary buffer (SGCK3), not in XC5200 I/O I/O

P57 Global buffer input I/O I/Oü P72 XC4000 secondary buffer (SGCK4), not in XC5200 I/O I/Oü P75 Optional JTAG Test Data Output (TDO symbol) O I/O

P78 Global buffer input I/O I/Oü XC4000/XC5200 functional difference. Please check. Optional JTAG function.

Global clock buffer input.

XC4002AXC4003AXC4004AXC4005A

XC4003/EXC4005/E/XLXC4006/EXC4008/EXC4010/E/XL

XC5202XC5204XC5206XC5210

© 1995 Xilinx, Inc. All Rights Reserved. 2/8/97

6

XC4000E and XC4000X SeriesFeaturesNote: Information in this data sheet covers the XC4000E,XC4000EX, and XC4000XL families. A separate data sheetcovers the XC4000XLA and XC4000XV families. ElectricalSpecifications and package/pin information are covered inseparate sections for each family to make the informationeasier to access, review, and print. For access to these sec-tions, see the Xilinx WEBLINX web site at

http://www.xilinx.com/partinfo/databook.htm#xc4000.

• System featured Field-Programmable Gate Arrays- Select-RAMTM memory: on-chip ultra-fast RAM with

- synchronous write option- dual-port RAM option

- Fully PCI compliant (speed grades -2 and faster)- Abundant flip-flops- Flexible function generators- Dedicated high-speed carry logic- Wide edge decoders on each edge- Hierarchy of interconnect lines- Internal 3-state bus capability- Eight global low-skew clock or signal distribution

networks• System Performance beyond 80 MHz• Flexible Array Architecture• Low Power Segmented Routing Architecture• Systems-Oriented Features

- IEEE 1149.1-compatible boundary scan logicsupport

- Individually programmable output slew rate- Programmable input pull-up or pull-down resistors- 12 mA sink current per XC4000E output

• Configured by Loading Binary File- Unlimited re-programmability

• Read Back Capability- Program verification- Internal node observability

• Backward Compatible with XC4000 Devices• Development System runs on most common computer

platforms- Interfaces to popular design environments- Fully automatic mapping, placement and routing- Interactive design editor for design optimization

Low-Voltage Versions Available• Low-Voltage Devices Function at 3.0 - 3.6 Volts• XC4000XL: High Performance Low-Voltage Versions of

XC4000EX devices

Additional XC4000X Series Features• Highest Performance — 3.3 V XC4000XL• Highest Capacity — Over 180,000 Usable Gates• 5 V tolerant I/Os on XC4000XL• 0.35 µm SRAM process for XC4000XL• Additional Routing Over XC4000E

- almost twice the routing capacity for high-densitydesigns

• Buffered Interconnect for Maximum Speed Blocks• Improved VersaRingTM I/O Interconnect for Better Fixed

Pinout Flexibility• 12 mA Sink Current Per XC4000X Output• Flexible New High-Speed Clock Network

- Eight additional Early Buffers for shorter clock delays- Virtually unlimited number of clock signals

• Optional Multiplexer or 2-input Function Generator onDevice Outputs

• Four Additional Address Bits in Master ParallelConfiguration Mode

• XC4000XV Family offers the highest density with0.25 µm 2.5 V technology

IntroductionXC4000 Series high-performance, high-capacity Field Pro-grammable Gate Arrays (FPGAs) provide the benefits ofcustom CMOS VLSI, while avoiding the initial cost, longdevelopment cycle, and inherent risk of a conventionalmasked gate array.

The result of thirteen years of FPGA design experience andfeedback from thousands of customers, these FPGAs com-bine architectural versatility, on-chip Select-RAM memorywith edge-triggered and dual-port modes, increasedspeed, abundant routing resources, and new, sophisticatedsoftware to achieve fully automated implementation ofcomplex, high-density, high-performance designs.

The XC4000E and XC4000X Series currently have 20members, as shown in Table 1.

0

XC4000E and XC4000X Series FieldProgrammable Gate Arrays

May 14, 1999 (Version 1.6) 0 0* Product Specification

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May 14, 1999 (Version 1.6) 6-5

http://www.xilinx.com/partinfo/databook.htm#xc4000

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* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Note: All functionality in low-voltage families is the same asin the corresponding 5-Volt family, except where numericalreferences are made to timing or power.

DescriptionXC4000 Series devices are implemented with a regular,flexible, programmable architecture of Configurable LogicBlocks (CLBs), interconnected by a powerful hierarchy ofversatile routing resources, and surrounded by a perimeterof programmable Input/Output Blocks (IOBs). They havegenerous routing resources to accommodate the mostcomplex interconnect patterns.

The devices are customized by loading configuration datainto internal memory cells. The FPGA can either activelyread its configuration data from an external serial orbyte-parallel PROM (master modes), or the configurationdata can be written into the FPGA from an external device(slave and peripheral modes).

XC4000 Series FPGAs are supported by powerful andsophisticated software, covering every aspect of designfrom schematic or behavioral entry, floor planning, simula-tion, automatic block placement and routing of intercon-nects, to the creation, downloading, and readback of theconfiguration bit stream.

Because Xilinx FPGAs can be reprogrammed an unlimitednumber of times, they can be used in innovative designs

where hardware is changed dynamically, or where hard-ware must be adapted to different user applications.FPGAs are ideal for shortening design and developmentcycles, and also offer a cost-effective solution for produc-tion rates well beyond 5,000 systems per month. For lowesthigh-volume unit cost, a design can first be implemented inthe XC4000E or XC4000X, then migrated to one of Xilinx’compatible HardWire mask-programmed devices.

Taking Advantage of Re-configurationFPGA devices can be re-configured to change logic func-tion while resident in the system. This capability gives thesystem designer a new degree of freedom not availablewith any other type of logic.

Hardware can be changed as easily as software. Designupdates or modifications are easy, and can be made toproducts already in the field. An FPGA can even be re-con-figured dynamically to perform different functions at differ-ent times.

Re-configurable logic can be used to implement systemself-diagnostics, create systems capable of being re-con-figured for different environments or operations, or imple-ment multi-purpose hardware for a given application. As anadded benefit, using re-configurable FPGA devices simpli-fies hardware design and debugging and shortens producttime-to-market.

Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays

DeviceLogicCells

Max LogicGates

(No RAM)

Max. RAMBits

(No Logic)

TypicalGate Range

(Logic and RAM)*CLB

MatrixTotalCLBs

Numberof

Flip-FlopsMax.

User I/OXC4002XL 152 1,600 2,048 1,000 - 3,000 8 x 8 64 256 64XC4003E 238 3,000 3,200 2,000 - 5,000 10 x 10 100 360 80XC4005E/XL 466 5,000 6,272 3,000 - 9,000 14 x 14 196 616 112XC4006E 608 6,000 8,192 4,000 - 12,000 16 x 16 256 768 128XC4008E 770 8,000 10,368 6,000 - 15,000 18 x 18 324 936 144XC4010E/XL 950 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 160XC4013E/XL 1368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192XC4020E/XL 1862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224XC4025E 2432 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 256XC4028EX/XL 2432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256XC4036EX/XL 3078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288XC4044XL 3800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320XC4052XL 4598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352XC4062XL 5472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384XC4085XL 7448 85,000 100,352 55,000 - 180,000 56 x 56 3,136 7,168 448

6-6 May 14, 1999 (Version 1.6)

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6

XC4000E and XC4000X SeriesCompared to the XC4000For readers already familiar with the XC4000 family of Xil-inx Field Programmable Gate Arrays, the major new fea-tures in the XC4000 Series devices are listed in thissection. The biggest advantages of XC4000E andXC4000X devices are significantly increased systemspeed, greater capacity, and new architectural features,particularly Select-RAM memory. The XC4000X devicesalso offer many new routing features, including specialhigh-speed clock buffers that can be used to capture inputdata with minimal delay.

Any XC4000E device is pinout- and bitstream-compatiblewith the corresponding XC4000 device. An existingXC4000 bitstream can be used to program an XC4000Edevice. However, since the XC4000E includes many newfeatures, an XC4000E bitstream cannot be loaded into anXC4000 device.

XC4000X Series devices are not bitstream-compatible withequivalent array size devices in the XC4000 or XC4000Efamilies. However, equivalent array size devices, such asthe XC4025, XC4025E, XC4028EX, and XC4028XL, arepinout-compatible.

Improvements in XC4000E and XC4000X

Increased System Speed

XC4000E and XC4000X devices can run at synchronoussystem clock rates of up to 80 MHz, and internal perfor-mance can exceed 150 MHz. This increase in performanceover the previous families stems from improvements in bothdevice processing and system architecture. XC4000Series devices use a sub-micron multi-layer metal process.In addition, many architectural improvements have beenmade, as described below.

The XC4000XL family is a high performance 3.3V familybased on 0.35µ SRAM technology and supports systemspeeds to 80 MHz.

PCI Compliance

XC4000 Series -2 and faster speed grades are fully PCIcompliant. XC4000E and XC4000X devices can be used toimplement a one-chip PCI solution.

Carry Logic

The speed of the carry logic chain has increased dramati-cally. Some parameters, such as the delay on the carrychain through a single CLB (TBYP), have improved by as

much as 50% from XC4000 values. See “Fast Carry Logic”on page 18 for more information.

Select-RAM Memory: Edge-Triggered, Synchro-nous RAM Modes

The RAM in any CLB can be configured for synchronous,edge-triggered, write operation. The read operation is notaffected by this change to an edge-triggered write.

Dual-Port RAM

A separate option converts the 16x2 RAM in any CLB into a16x1 dual-port RAM with simultaneous Read/Write.

The function generators in each CLB can be configured aseither level-sensitive (asynchronous) single-port RAM,edge-triggered (synchronous) single-port RAM, edge-trig-gered (synchronous) dual-port RAM, or as combinatoriallogic.

Configurable RAM Content

The RAM content can now be loaded at configuration time,so that the RAM starts up with user-defined data.

H Function Generator

In current XC4000 Series devices, the H function generatoris more versatile than in the original XC4000. Its inputs cancome not only from the F and G function generators butalso from up to three of the four control input lines. The Hfunction generator can thus be totally or partially indepen-dent of the other two function generators, increasing themaximum capacity of the device.

IOB Clock Enable

The two flip-flops in each IOB have a common clock enableinput, which through configuration can be activated individ-ually for the input or output flip-flop or both. This clockenable operates exactly like the EC pin on the XC4000CLB. This new feature makes the IOBs more versatile, andavoids the need for clock gating.

Output Drivers

The output pull-up structure defaults to a TTL-liketotem-pole. This driver is an n-channel pull-up transistor,pulling to a voltage one transistor threshold below Vcc, justlike the XC4000 family outputs. Alternatively, XC4000Series devices can be globally configured with CMOS out-puts, with p-channel pull-up transistors pulling to Vcc. Also,the configurable pull-up resistor in the XC4000 Series is ap-channel transistor that pulls to Vcc, whereas in the origi-nal XC4000 family it is an n-channel transistor that pulls toa voltage one transistor threshold below Vcc.

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Input Thresholds

The input thresholds of 5V devices can be globally config-ured for either TTL (1.2 V threshold) or CMOS (2.5 Vthreshold), just like XC2000 and XC3000 inputs. The twoglobal adjustments of input threshold and output level areindependent of each other. The XC4000XL family has aninput threshold of 1.6V, compatible with both 3.3V CMOSand TTL levels.

Global Signal Access to Logic

There is additional access from global clocks to the F andG function generator inputs.

Configuration Pin Pull-Up Resistors

During configuration, these pins have weak pull-up resis-tors. For the most popular configuration mode, SlaveSerial, the mode pins can thus be left unconnected. Thethree mode inputs can be individually configured with orwithout weak pull-up or pull-down resistors. A pull-downresistor value of 4.7 kΩ is recommended.

The three mode inputs can be individually configured withor without weak pull-up or pull-down resistors after configu-ration.

The PROGRAM input pin has a permanent weak pull-up.

Soft Start-up

Like the XC3000A, XC4000 Series devices have “SoftStart-up.” When the configuration process is finished andthe device starts up, the first activation of the outputs isautomatically slew-rate limited. This feature avoids poten-tial ground bounce when all outputs are turned on simulta-neously. Immediately after start-up, the slew rate of theindividual outputs is, as in the XC4000 family, determinedby the individual configuration option.

XC4000 and XC4000A Compatibility

Existing XC4000 bitstreams can be used to configure anXC4000E device. XC4000A bitstreams must be recompiledfor use with the XC4000E due to improved routingresources, although the devices are pin-for-pin compatible.

Additional Improvements in XC4000X Only

Increased Routing

New interconnect in the XC4000X includes twenty-twoadditional vertical lines in each column of CLBs and twelvenew horizontal lines in each row of CLBs. The twelve “QuadLines” in each CLB row and column include optional repow-ering buffers for maximum speed. Additional high-perfor-mance routing near the IOBs enhances pin flexibility.

Faster Input and Output

A fast, dedicated early clock sourced by global clock buffersis available for the IOBs. To ensure synchronization with theregular global clocks, a Fast Capture latch driven by theearly clock is available. The input data can be initiallyloaded into the Fast Capture latch with the early clock, thentransferred to the input flip-flop or latch with the low-skewglobal clock. A programmable delay on the input can beused to avoid hold-time requirements. See “IOB Input Sig-nals” on page 20 for more information.

Latch Capability in CLBs

Storage elements in the XC4000X CLB can be configuredas either flip-flops or latches. This capability makes theFPGA highly synthesis-compatible.

IOB Output MUX From Output Clock

A multiplexer in the IOB allows the output clock to selecteither the output data or the IOB clock enable as the outputto the pad. Thus, two different data signals can share a sin-gle output pad, effectively doubling the number of deviceoutputs without requiring a larger, more expensive pack-age. This multiplexer can also be configured as anAND-gate to implement a very fast pin-to-pin path. See“IOB Output Signals” on page 23 for more information.

Additional Address Bits

Larger devices require more bits of configuration data. Adaisy chain of several large XC4000X devices may requirea PROM that cannot be addressed by the eighteen addressbits supported in the XC4000E. The XC4000X Seriestherefore extends the addressing in Master Parallel config-uration mode to 22 bits.

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Detailed Functional DescriptionXC4000 Series devices achieve high speed throughadvanced semiconductor technology and improved archi-tecture. The XC4000E and XC4000X support system clockrates of up to 80 MHz and internal performance in excessof 150 MHz. Compared to older Xilinx FPGA families,XC4000 Series devices are more powerful. They offeron-chip edge-triggered and dual-port RAM, clock enableson I/O flip-flops, and wide-input decoders. They are moreversatile in many applications, especially those involvingRAM. Design cycles are faster due to a combination ofincreased routing resources and more sophisticated soft-ware.

Basic Building BlocksXilinx user-programmable gate arrays include two majorconfigurable elements: configurable logic blocks (CLBs)and input/output blocks (IOBs).

• CLBs provide the functional elements for constructingthe user’s logic.

• IOBs provide the interface between the package pinsand internal signal lines.

Three other types of circuits are also available:

• 3-State buffers (TBUFs) driving horizontal longlines areassociated with each CLB.

• Wide edge decoders are available around the peripheryof each device.

• An on-chip oscillator is provided.

Programmable interconnect resources provide routingpaths to connect the inputs and outputs of these config-urable elements to the appropriate networks.

The functionality of each circuit block is customized duringconfiguration by programming internal static memory cells.The values stored in these memory cells determine thelogic functions and interconnections implemented in theFPGA. Each of these available circuits is described in thissection.

Configurable Logic Blocks (CLBs)Configurable Logic Blocks implement most of the logic inan FPGA. The principal CLB elements are shown inFigure 1. Two 4-input function generators (F and G) offerunrestricted versatility. Most combinatorial logic functionsneed four or fewer inputs. However, a third function gener-ator (H) is provided. The H function generator has threeinputs. Either zero, one, or two of these inputs can be theoutputs of F and G; the other input(s) are from outside theCLB. The CLB can, therefore, implement certain functionsof up to nine variables, like parity check or expand-able-identity comparison of two sets of four inputs.

Each CLB contains two storage elements that can be usedto store the function generator outputs. However, the stor-age elements and function generators can also be usedindependently. These storage elements can be configuredas flip-flops in both XC4000E and XC4000X devices; in theXC4000X they can optionally be configured as latches. DINcan be used as a direct input to either of the two storageelements. H1 can drive the other through the H functiongenerator. Function generator outputs can also drive twooutputs independent of the storage element outputs. Thisversatility increases logic capacity and simplifies routing.

Thirteen CLB inputs and four CLB outputs provide accessto the function generators and storage elements. Theseinputs and outputs connect to the programmable intercon-nect resources outside the block.

Function Generators

Four independent inputs are provided to each of two func-tion generators (F1 - F4 and G1 - G4). These function gen-erators, with outputs labeled F’ and G’, are each capable ofimplementing any arbitrarily defined Boolean function offour inputs. The function generators are implemented asmemory look-up tables. The propagation delay is thereforeindependent of the function implemented.

A third function generator, labeled H’, can implement anyBoolean function of its three inputs. Two of these inputs canoptionally be the F’ and G’ functional generator outputs.Alternatively, one or both of these inputs can come fromoutside the CLB (H2, H0). The third input must come fromoutside the block (H1).

Signals from the function generators can exit the CLB ontwo outputs. F’ or H’ can be connected to the X output. G’ orH’ can be connected to the Y output.

A CLB can be used to implement any of the following func-tions:

• any function of up to four variables, plus any secondfunction of up to four unrelated variables, plus any third

function of up to three unrelated variables1

• any single function of five variables• any function of four variables together with some

functions of six variables• some functions of up to nine variables.

Implementing wide functions in a single block reduces boththe number of blocks required and the delay in the signalpath, achieving both increased capacity and speed.

The versatility of the CLB function generators significantlyimproves system speed. In addition, the design-softwaretools can deal with each function generator independently.This flexibility improves cell usage.

1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only twounregistered function generator outputs are available from the CLB.

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Flip-Flops

The CLB can pass the combinatorial output(s) to the inter-connect network, but can also store the combinatorialresults or other incoming data in one or two flip-flops, andconnect their outputs to the interconnect network as well.

The two edge-triggered D-type flip-flops have commonclock (K) and clock enable (EC) inputs. Either or both clockinputs can also be permanently enabled. Storage elementfunctionality is described in Table 2.

Latches (XC4000X only)

The CLB storage elements can also be configured aslatches. The two latches have common clock (K) and clockenable (EC) inputs. Storage element functionality isdescribed in Table 2.

Clock Input

Each flip-flop can be triggered on either the rising or fallingclock edge. The clock pin is shared by both storage ele-ments. However, the clock is individually invertible for eachstorage element. Any inverter placed on the clock input isautomatically absorbed into the CLB.

Clock Enable

The clock enable signal (EC) is active High. The EC pin isshared by both storage elements. If left unconnected foreither, the clock enable for that storage element defaults tothe active state. EC is not invertible within the CLB.

LOGIC FUNCTION

OF G1-G4

G4

G3

G2

G1

G'

LOGIC FUNCTION

OF F1-F4

F4

F3

F2

F1

F'

LOGIC FUNCTION

OF F', G', AND H1

H'

DIN F' G' H'

DIN F' G' H'

G' H'

H' F'

S/R CONTROL

D

ECRD

Bypass

Bypass

SDYQ

XQ

Q

S/R CONTROL

D

ECRD

SDQ

1

1

K (CLOCK)

Multiplexer Controlled by Configuration Program

Y

X

DIN/H2H1 SR/H0 EC

X6692

C1 • • • C4 4

Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Table 2: CLB Storage Element Functionality(active rising edge is shown)

Mode K EC SR D QPower-Up or

GSRX X X X SR

Flip-FlopX X 1 X SR

__/ 1* 0* D D0 X 0* X Q

Latch1 1* 0* X Q0 1* 0* D D

Both X 0 0* X QLegend:

X__/SR0*1*

Don’t careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)

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Set/Reset

An asynchronous storage element input (SR) can be con-figured as either set or reset. This configuration optiondetermines the state in which each flip-flop becomes oper-ational after configuration. It also determines the effect of aGlobal Set/Reset pulse during normal operation, and theeffect of a pulse on the SR pin of the CLB. All threeset/reset functions for any single flip-flop are controlled bythe same configuration data bit.

The set/reset state can be independently specified for eachflip-flop. This input can also be independently disabled foreither flip-flop.

The set/reset state is specified by using the INIT attribute,or by placing the appropriate set or reset flip-flop librarysymbol.

SR is active High. It is not invertible within the CLB.

Global Set/Reset

A separate Global Set/Reset line (not shown in Figure 1)sets or clears each storage element during power-up,re-configuration, or when a dedicated Reset net is drivenactive. This global net (GSR) does not compete with otherrouting resources; it uses a dedicated distribution network.

Each flip-flop is configured as either globally set or reset inthe same way that the local set/reset (SR) is specified.Therefore, if a flip-flop is set by SR, it is also set by GSR.Similarly, a reset flip-flop is reset by both SR and GSR.

GSR can be driven from any user-programmable pin as aglobal reset input. To use this global net, place an input padand input buffer in the schematic or HDL code, driving theGSR pin of the STARTUP symbol. (See Figure 2.) A spe-cific pin location can be assigned to this input using a LOCattribute or property, just as with any other user-program-mable pad. An inverter can optionally be inserted after theinput buffer to invert the sense of the Global Set/Reset sig-nal.

Alternatively, GSR can be driven from any internal node.

Data Inputs and Outputs

The source of a storage element data input is programma-ble. It is driven by any of the functions F’, G’, and H’, or bythe Direct In (DIN) block input. The flip-flops or latches drivethe XQ and YQ CLB outputs.

Two fast feed-through paths are available, as shown inFigure 1. A two-to-one multiplexer on each of the XQ andYQ outputs selects between a storage element output andany of the control inputs. This bypass is sometimes used bythe automated router to repower internal signals.

Control Signals

Multiplexers in the CLB map the four control inputs (C1 - C4in Figure 1) into the four internal control signals (H1,DIN/H2, SR/H0, and EC). Any of these inputs can drive anyof the four internal control signals.

When the logic function is enabled, the four inputs are:

• EC — Enable Clock• SR/H0 — Asynchronous Set/Reset or H function

generator Input 0• DIN/H2 — Direct In or H function generator Input 2• H1 — H function generator Input 1.

When the memory function is enabled, the four inputs are:

• EC — Enable Clock• WE — Write Enable• D0 — Data Input to F and/or G function generator• D1 — Data input to G function generator (16x1 and

16x2 modes) or 5th Address bit (32x1 mode).

Using FPGA Flip-Flops and Latches

The abundance of flip-flops in the XC4000 Series invitespipelined designs. This is a powerful way of increasing per-formance by breaking the function into smaller subfunc-tions and executing them in parallel, passing on the resultsthrough pipeline flip-flops. This method should be seriouslyconsidered wherever throughput is more important thanlatency.

To include a CLB flip-flop, place the appropriate librarysymbol. For example, FDCE is a D-type flip-flop with clockenable and asynchronous clear. The corresponding latchsymbol (for the XC4000X only) is called LDCE.

In XC4000 Series devices, the flip flops can be used as reg-isters or shift registers without blocking the function gener-ators from performing a different, perhaps unrelated task.This ability increases the functional capacity of the devices.

The CLB setup time is specified between the function gen-erator inputs and the clock input K. Therefore, the specifiedCLB flip-flop setup time includes the delay through thefunction generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-uptables in the F’ and G’ function generators usable as anarray of Read/Write memory cells. Available modes arelevel-sensitive (similar to the XC4000/A/H families),edge-triggered, and dual-port edge-triggered. Dependingon the selected mode, a single CLB can be configured aseither a 16x2, 32x1, or 16x1 bit array.

PAD

IBUF

GSRGTS

CLK DONEINQ1Q4

Q2Q3

STARTUP

X5260

Figure 2: Schematic Symbols for Global Set/Reset

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Supported CLB memory configurations and timing modesfor single- and dual-port modes are shown in Table 3.

XC4000 Series devices are the first programmable logicdevices with edge-triggered (synchronous) and dual-portRAM accessible to the user. Edge-triggered RAM simpli-fies system timing. Dual-port RAM doubles the effectivethroughput of FIFO applications. These features can beindividually programmed in any XC4000 Series CLB.

Advantages of On-Chip and Edge-Triggered RAM

The on-chip RAM is extremely fast. The read access time isthe same as the logic delay. The write access time isslightly slower. Both access times are much faster thanany off-chip solution, because they avoid I/O delays.

Edge-triggered RAM, also called synchronous RAM, is afeature never before available in a Field ProgrammableGate Array. The simplicity of designing with edge-triggeredRAM, and the markedly higher achievable performance,add up to a significant improvement over existing deviceswith on-chip RAM.

Three application notes are available from Xilinx that dis-cuss edge-triggered RAM: “XC4000E Edge-Triggered andDual-Port RAM Capability,” “Implementing FIFOs inXC4000E RAM,” and “Synchronous and AsynchronousFIFO Designs.” All three application notes apply to bothXC4000E and XC4000X RAM.

RAM Configuration Options

The function generators in any CLB can be configured asRAM arrays in the following sizes:

• Two 16x1 RAMs: two data inputs and two data outputswith identical or, if preferred, different addressing foreach RAM

• One 32x1 RAM: one data input and one data output.

One F or G function generator can be configured as a 16x1RAM while the other function generators are used to imple-ment any function of up to 5 inputs.

Additionally, the XC4000 Series RAM may have either oftwo timing modes:

• Edge-Triggered (Synchronous): data written by thedesignated edge of the CLB clock. WE acts as a trueclock enable.

• Level-Sensitive (Asynchronous): an external WE signalacts as the write strobe.

The selected timing mode applies to both function genera-tors within a CLB when both are configured as RAM.

The number of read ports is also programmable:

• Single Port: each function generator has a commonread and write port

• Dual Port: both function generators are configuredtogether as a single 16x1 dual-port RAM with one writeport and two read ports. Simultaneous read and writeoperations to the same or different addresses aresupported.

RAM configuration options are selected by placing theappropriate library symbol.

Choosing a RAM Configuration Mode

The appropriate choice of RAM mode for a given designshould be based on timing and resource requirements,desired functionality, and the simplicity of the design pro-cess. Recommended usage is shown in Table 4.

The difference between level-sensitive, edge-triggered,and dual-port RAM is only in the write operation. Readoperation and timing is identical for all modes of operation.

RAM Inputs and Outputs

The F1-F4 and G1-G4 inputs to the function generators actas address lines, selecting a particular memory cell in eachlook-up table.

The functionality of the CLB control signals changes whenthe function generators are configured as RAM. TheDIN/H2, H1, and SR/H0 lines become the two data inputs(D0, D1) and the Write Enable (WE) input for the 16x2memory. When the 32x1 configuration is selected, D1 actsas the fifth address bit and D0 is the data input.

The contents of the memory cell(s) being addressed areavailable at the F’ and G’ function-generator outputs. Theycan exit the CLB through its X and Y outputs, or can be cap-tured in the CLB flip-flop(s).

Configuring the CLB function generators as Read/Writememory does not affect the functionality of the other por-

Table 3: Supported RAM Modes

16x1

16x2

32x1

Edge-Triggered

Timing

Level-Sensitive

TimingSingle-Port √ √ √ √ √Dual-Port √ √

Table 4: RAM Mode Selection

Level-Sensitive

Edge-Triggered

Dual-PortEdge-Trigg

eredUse for NewDesigns?

No Yes Yes

Size (16x1,Registered)

1/2 CLB 1/2 CLB 1 CLB

SimultaneousRead/Write

No No Yes

RelativePerformance

X 2X2X (4X

effective)

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6

tions of the CLB, with the exception of the redefinition of thecontrol signals. In 16x2 and 16x1 modes, the H’ functiongenerator can be used to implement Boolean functions ofF’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, orD0 signals.

Single-Port Edge-Triggered Mode

Edge-triggered (synchronous) RAM simplifies timingrequirements. XC4000 Series edge-triggered RAM timingoperates like writing to a data register. Data and addressare presented. The register is enabled for writing by a logicHigh on the write enable input, WE. Then a rising or fallingclock edge loads the data into the register, as shown inFigure 3.

Complex timing relationships between address, data, andwrite enable signals are not required, and the external writeenable pulse becomes a simple clock enable. The activeedge of WCLK latches the address, input data, and WE sig-

nals. An internal write pulse is generated that performs thewrite. See Figure 4 and Figure 5 for block diagrams of aCLB configured as 16x2 and 32x1 edge-triggered, sin-gle-port RAM.

The relationships between CLB pins and RAM inputs andoutputs for single-port, edge-triggered mode are shown inTable 5.

The Write Clock input (WCLK) can be configured as activeon either the rising edge (default) or the falling edge. It usesthe same CLB pin (K) used to clock the CLB flip-flops, but itcan be independently inverted. Consequently, the RAMoutput can optionally be registered within the same CLBeither by the same clock edge as the RAM, or by the oppo-site edge of this clock. The sense of WCLK applies to bothfunction generators in the CLB when both are configuredas RAM.

The WE pin is active-High and is not invertible within theCLB.

Note: The pulse following the active edge of WCLK (TWPSin Figure 3) must be less than one millisecond wide. Formost applications, this requirement is not overly restrictive;however, it must not be forgotten. Stopping WCLK at thispoint in the write cycle could result in excessive current andeven damage to the larger devices if many CLBs are con-figured as edge-triggered RAM.

X6461

WCLK (K)

WE

ADDRESS

DATA IN

DATA OUT OLD NEW

TDSSTDHS

TASS TAHS

TWSS

TWPS

TWHS

TWOS

TILOTILO

Figure 3: Edge-Triggered RAM Write Timing

Table 5: Single-Port Edge-Triggered RAM Signals

RAM Signal CLB Pin FunctionD D0 or D1 (16x2,

16x1), D0 (32x1)Data In

A[3:0] F1-F4 or G1-G4 AddressA[4] D1 (32x1) AddressWE WE Write EnableWCLK K ClockSPO(Data Out)

F’ or G’ Single Port Out(Data Out)

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G'4 G1 • • • G4

F1 • • • F4

C1 • • • C4

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

X6752

4

4

MUX

F'WRITE

DECODER

1 of 16

DIN

16-LATCH ARRAY

READ ADDRESS

READ ADDRESS

WRITE PULSE

LATCH ENABLE

LATCH ENABLE

K (CLOCK)

WE D1 D0EC

WRITE PULSE

MUX4

4

Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM

G'4

G1 • • • G4 F1 • • • F4

C1 • • • C4

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

X6754

4

4

MUX

F'WRITE

DECODER

1 of 16

DIN

16-LATCH ARRAY

READ ADDRESS

READ ADDRESS

WRITE PULSE

LATCH ENABLE

LATCH ENABLE

K (CLOCK)

WE D1/A4 D0

EC

EC

WRITE PULSE

MUX4

4

H'

Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

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Dual-Port Edge-Triggered Mode

In dual-port mode, both the F and G function generatorsare used to create a single 16x1 RAM array with one writeport and two read ports. The resulting RAM array can beread and written simultaneously at two independentaddresses. Simultaneous read and write operations at thesame address are also supported.

Dual-port mode always has edge-triggered write timing, asshown in Figure 3.

Figure 6 shows a simple model of an XC4000 Series CLBconfigured as dual-port RAM. One address port, labeledA[3:0], supplies both the read and write address for the Ffunction generator. This function generator behaves thesame as a 16x1 single-port edge-triggered RAM array. TheRAM output, Single Port Out (SPO), appears at the F func-tion generator output. SPO, therefore, reflects the data ataddress A[3:0].

The other address port, labeled DPRA[3:0] for Dual PortRead Address, supplies the read address for the G functiongenerator. The write address for the G function generator,however, comes from the address A[3:0]. The output fromthis 16x1 RAM array, Dual Port Out (DPO), appears at theG function generator output. DPO, therefore, reflects thedata at address DPRA[3:0].

Therefore, by using A[3:0] for the write address andDPRA[3:0] for the read address, and reading only the DPOoutput, a FIFO that can read and write simultaneously iseasily generated. Simultaneous access doubles the effec-tive throughput of the FIFO.

The relationships between CLB pins and RAM inputs andoutputs for dual-port, edge-triggered mode are shown inTable 6. See Figure 7 on page 16 for a block diagram of aCLB configured in this mode.

Table 6: Dual-Port Edge-Triggered RAM Signals

Note: The pulse following the active edge of WCLK (TWPSin Figure 3) must be less than one millisecond wide. Formost applications, this requirement is not overly restrictive;however, it must not be forgotten. Stopping WCLK at thispoint in the write cycle could result in excessive current andeven damage to the larger devices if many CLBs are con-figured as edge-triggered RAM.

Single-Port Level-Sensitive Timing Mode

Note: Edge-triggered mode is recommended for all newdesigns. Level-sensitive mode, also called asynchronousmode, is still supported for XC4000 Series backward-com-patibility with the XC4000 family.

Level-sensitive RAM timing is simple in concept but can becomplicated in execution. Data and address signals arepresented, then a positive pulse on the write enable pin(WE) performs a write into the RAM at the designatedaddress. As indicated by the “level-sensitive” label, thisRAM acts like a latch. During the WE High pulse, changingthe data lines results in new data written to the old address.Changing the address lines while WE is High results in spu-rious data written to the new address—and possibly atother addresses as well, as the address lines inevitably donot all change simultaneously.

The user must generate a carefully timed WE signal. Thedelay on the WE signal and the address lines must be care-fully verified to ensure that WE does not become activeuntil after the address lines have settled, and that WE goesinactive before the address lines change again. The datamust be stable before and after the falling edge of WE.

In practical terms, WE is usually generated by a 2X clock. Ifa 2X clock is not available, the falling edge of the systemclock can be used. However, there are inherent risks in thisapproach, since the WE pulse must be guaranteed inactivebefore the next rising edge of the system clock. Severalolder application notes are available from Xilinx that dis-cuss the design of level-sensitive RAMs. These applicationnotes include XAPP031, “Using the XC4000 RAM Capabil-ity,” and XAPP042, “High-Speed RAM Design in XC4000.”However, the edge-triggered RAM available in the XC4000Series is superior to level-sensitive RAM for almost everyapplication.

WE WE

D D Q

D Q

D

DPRA[3:0]

A[3:0]

AR[3:0]

AW[3:0]

WE

D

AR[3:0]

AW[3:0]

RAM16X1D Primitive

F Function Generator

G Function Generator

DPO (Dual Port Out)

Registered DPO

SPO (Single Port Out)

Registered SPO

WCLK

X6755

Figure 6: XC4000 Series Dual-Port RAM, SimpleModel

RAM Signal CLB Pin FunctionD D0 Data InA[3:0] F1-F4 Read Address for F,

Write Address for F and GDPRA[3:0] G1-G4 Read Address for GWE WE Write EnableWCLK K ClockSPO F’ Single Port Out

(addressed by A[3:0])DPO G’ Dual Port Out

(addressed by DPRA[3:0])

May 14, 1999 (Version 1.6) 6-15

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Figure 8 shows the write timing for level-sensitive, sin-gle-port RAM.

The relationships between CLB pins and RAM inputs andoutputs for single-port level-sensitive mode are shown inTable 7.

Figure 9 and Figure 10 show block diagrams of a CLB con-figured as 16x2 and 32x1 level-sensitive, single-port RAM.

Initializing RAM at Configuration

Both RAM and ROM implementations of the XC4000Series devices are initialized during configuration. The ini-tial contents are defined via an INIT attribute or property

attached to the RAM or ROM symbol, as described in theschematic library guide. If not defined, all RAM contentsare initialized to all zeros, by default.

RAM initialization occurs only during configuration. TheRAM content is not affected by Global Set/Reset.

Table 7: Single-Port Level-Sensitive RAM Signals

G'

G1 • • • G4

F1 • • • F4

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

X6748

4

4

MUX

F'WRITE

DECODER

1 of 16

DIN

16-LATCH ARRAY

READ ADDRESS

READ ADDRESS

WRITE PULSE

LATCH ENABLE

LATCH ENABLE

K (CLOCK) WRITE PULSE

MUX4

4

C1 • • • C4 4

WE D1 D0 EC

Figure 7: 16x1 Edge-Triggered Dual-Port RAM

RAM Signal CLB Pin FunctionD D0 or D1 Data InA[3:0] F1-F4 or G1-G4 AddressWE WE Write EnableO F’ or G’ Data Out

WCT

ADDRESS

WRITE ENABLE

DATA IN

AST WPT

DST DHT

REQUIRED

AHT

X6462

Figure 8: Level-Sensitive RAM Write Timing

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6

Enable

G'4 G1 • • • G4

F1 • • • F4

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

X6746

4 READ ADDRESS

MUX

Enable

F'WRITE

DECODER

1 of 16

DIN

16-LATCH ARRAY

4 READ ADDRESS

MUX4

C1 • • • C4 4

WE D1 D0 EC

Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

Enable

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

X6749

4

READ ADDRESS

MUX

Enable

WRITE DECODER

1 of 16

DIN

16-LATCH ARRAY

4

READ ADDRESS

MUX

G'4

G1 • • • G4 F1 • • • F4

C1 • • • C4 4

F'

WE D1/A4 D0 EC

4

H'

Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

May 14, 1999 (Version 1.6) 6-17

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Fast Carry Logic

Each CLB F and G function generator contains dedicatedarithmetic logic for the fast generation of carry and borrowsignals. This extra output is passed on to the function gen-erator in the adjacent CLB. The carry chain is independentof normal routing resources.

Dedicated fast carry logic greatly increases the efficiencyand performance of adders, subtractors, accumulators,comparators and counters. It also opens the door to manynew applications involving arithmetic operation, where theprevious generations of FPGAs were not fast enough or tooinefficient. High-speed address offset calculations in micro-processor or graphics systems, and high-speed addition indigital signal processing are two typical applications.

The two 4-input function generators can be configured as a2-bit adder with built-in hidden carry that can be expandedto any length. This dedicated carry circuitry is so fast andefficient that conventional speed-up methods like carrygenerate/propagate are meaningless even at the 16-bitlevel, and of marginal benefit at the 32-bit level.

This fast carry logic is one of the more significant featuresof the XC4000 Series, speeding up arithmetic and countinginto the 70 MHz range.

The carry chain in XC4000E devices can run either up ordown. At the top and bottom of the columns where thereare no CLBs above or below, the carry is propagated to theright. (See Figure 11.) In order to improve speed in thehigh-capacity XC4000X devices, which can potentiallyhave very long carry chains, the carry chain travels upwardonly, as shown in Figure 12. Additionally, standard intercon-nect can be used to route a carry signal in the downwarddirection.

Figure 13 on page 19 shows an XC4000E CLB with dedi-cated fast carry logic. The carry logic in the XC4000X issimilar, except that COUT exits at the top only, and the sig-nal CINDOWN does not exist. As shown in Figure 13, thecarry logic shares operand and control inputs with the func-tion generators. The carry outputs connect to the functiongenerators, where they are combined with the operands toform the sums.

Figure 14 on page 20 shows the details of the carry logicfor the XC4000E. This diagram shows the contents of thebox labeled “CARRY LOGIC” in Figure 13. The XC4000Xcarry logic is very similar, but a multiplexer on thepass-through carry chain has been eliminated to reducedelay. Additionally, in the XC4000X the multiplexer on theG4 path has a memory-programmable 0 input, which per-mits G4 to directly connect to COUT. G4 thus becomes anadditional high-speed initialization path for carry-in.

The dedicated carry logic is discussed in detail in Xilinxdocument XAPP 013: “Using the Dedicated Carry Logic in

XC4000.” This discussion also applies to XC4000Edevices, and to XC4000X devices when the minor logicchanges are taken into account.

The fast carry logic can be accessed by placing speciallibrary symbols, or by using Xilinx Relationally Placed Mac-ros (RPMs) that already include these symbols.

X6687

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

Figure 11: Available XC4000E Carry PropagationPaths

X6610

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

Figure 12: Available XC4000X Carry PropagationPaths (dotted lines use general interconnect)

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6

D QS/R

EC

YQ

Y

DIN

H

G

F

G

H

D QS/R

EC

XQ

DIN

H

G

F

H

X

H

F

G

G4

G3

G2

G1

FF3

F2

F1

F4

F CARRY

G CARRY

C C DOWNCARRY LOGIC

D

CC UP K S/R EC

H1

X6699

OUT

INOUT IN

IN

COUT0

Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)

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Input/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide theinterface between external package pins and the internallogic. Each IOB controls one package pin and can be con-figured for input, output, or bidirectional signals.

Figure 15 shows a simplified block diagram of theXC4000E IOB. A more complete diagram which includesthe boundary scan logic of the XC4000E IOB can be foundin Figure 40 on page 43, in the “Boundary Scan” section.

The XC4000X IOB contains some special features notincluded in the XC4000E IOB. These features are high-lighted in a simplified block diagram found in Figure 16, anddiscussed throughout this section. When XC4000X specialfeatures are discussed, they are clearly identified in thetext. Any feature not so identified is present in bothXC4000E and XC4000X devices.

IOB Input Signals

Two paths, labeled I1 and I2 in Figure 15 and Figure 16,bring input signals into the array. Inputs also connect to aninput register that can be programmed as either anedge-triggered flip-flop or a level-sensitive latch.

The choice is made by placing the appropriate library sym-bol. For example, IFD is the basic input flip-flop (rising edgetriggered), and ILD is the basic input latch (transpar-ent-High). Variations with inverted clocks are available, andsome combinations of latches and flip-flops can be imple-mented in a single IOB, as described in the XACT LibrariesGuide.

The XC4000E inputs can be globally configured for eitherTTL (1.2V) or 5.0 volt CMOS thresholds, using an option inthe bitstream generation software. There is a slight inputhysteresis of about 300mV. The XC4000E output levels arealso configurable; the two global adjustments of inputthreshold and output level are independent.

Inputs on the XC4000XL are TTL compatible and 3.3VCMOS compatible. Outputs on the XC4000XL are pulled tothe 3.3V positive supply.

The inputs of XC4000 Series 5-Volt devices can be drivenby the outputs of any 3.3-Volt device, if the 5-Volt inputs arein TTL mode.

Supported sources for XC4000 Series device inputs areshown in Table 8.

0 1

0 1

M

M

0

1

0 1

M

0

1

M

1 0M

M 0

3

M

1

M

I

G1

G4

F2

F1

F3

COUT

G2

G3

F4

C INUP

C IN DOWN

X2000

TOFUNCTIONGENERATORS

M

M

M

COUT0

Figure 14: Detail of XC4000E Dedicated Carry Logic

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6

Q

Flip- Flop/ Latch

D

D

CE

CE

QOut

T

Output Clock

I

Input Clock

Clock Enable

Delay

Pad

Flip-Flop

Slew Rate Control

Output Buffer

Input Buffer

Passive Pull-Up/

Pull-Down

2

I1

X6704

Figure 15: Simplified Block Diagram of XC4000E IOB

Q

Flip-Flop/ Latch

Fast Capture Latch

D

Q Latch

D

G

D

0

1

CE

CE

QOut

T

Output Clock

I

Input Clock

Clock Enable

Pad

Flip-Flop

Slew Rate Control

Output Buffer

Output MUX

Input Buffer

Passive Pull-Up/

Pull-Down

2

I1

X5984

Delay Delay

Figure 16: Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

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XC4000XL 5-Volt Tolerant I/Os

The I/Os on the XC4000XL are fully 5-volt tolerant eventhough the VCC is 3.3 volts. This allows 5 V signals todirectly connect to the XC4000XL inputs without damage,as shown in Table 8. In addition, the 3.3 volt VCC can beapplied before or after 5 volt signals are applied to the I/Os.This makes the XC4000XL immune to power supplysequencing problems.

Registered Inputs

The I1 and I2 signals that exit the block can each carryeither the direct or registered input signal.

The input and output storage elements in each IOB have acommon clock enable input, which, through configuration,can be activated individually for the input or output flip-flop,or both. This clock enable operates exactly like the EC pinon the XC4000 Series CLB. It cannot be inverted within theIOB.

The storage element behavior is shown in Table 9.

Table 9: Input Register Functionality(active rising edge is shown)

Optional Delay Guarantees Zero Hold Time

The data input to the register can optionally be delayed byseveral nanoseconds. With the delay enabled, the setuptime of the input flip-flop is increased so that normal clockrouting does not result in a positive hold-time requirement.A positive hold time requirement can lead to unreliable,temperature- or processing-dependent operation.

The input flip-flop setup time is defined between the datameasured at the device I/O pin and the clock input at theIOB (not at the clock pin). Any routing delay from the deviceclock pin to the clock input of the IOB must, therefore, besubtracted from this setup time to arrive at the real setuptime requirement relative to the device pins. A short speci-fied setup time might, therefore, result in a negative setuptime at the device pins, i.e., a positive hold-time require-ment.

When a delay is inserted on the data line, more clock delaycan be tolerated without causing a positive hold-timerequirement. Sufficient delay eliminates the possibility of adata hold-time requirement at the external pin. The maxi-mum delay is therefore inserted as the default.

The XC4000E IOB has a one-tap delay element: either thedelay is inserted (default), or it is not. The delay guaranteesa zero hold time with respect to clocks routed through anyof the XC4000E global clock buffers. (See “Global Nets andBuffers (XC4000E only)” on page 35 for a description of theglobal clock buffers in the XC4000E.) For a shorter inputregister setup time, with non-zero hold, attach a NODELAYattribute or property to the flip-flop.

The XC4000X IOB has a two-tap delay element, withchoices of a full delay, a partial delay, or no delay. Theattributes or properties used to select the desired delay areshown in Table 10. The choices are no added attribute,MEDDELAY, and NODELAY. The default setting, with noadded attribute, ensures no hold time with respect to any ofthe XC4000X clock buffers, including the Global Low-Skewbuffers. MEDDELAY ensures no hold time with respect tothe Global Early buffers. Inputs with NODELAY may have apositive hold time with respect to all clock buffers. For adescription of each of these buffers, see “Global Nets andBuffers (XC4000X only)” on page 37.

Table 10: XC4000X IOB Input Delay Element

Table 8: Supported Sources for XC4000 Series DeviceInputs

Source

XC4000E/EXSeries Inputs

XC4000XLSeries Inputs

5 V,TTL

5 V,CMOS

3.3 VCMOS

Any device, Vcc = 3.3 V,CMOS outputs

√Unreli-ableData

√

XC4000 Series, Vcc = 5 V,TTL outputs

√ √

Any device, Vcc = 5 V,TTL outputs (Voh ≤ 3.7 V)

√ √

Any device, Vcc = 5 V,CMOS outputs

√ √ √

Mode ClockClock

EnableD Q

Power-Up orGSR

X X X SR

Flip-Flop __/ 1* D D0 X X Q

Latch 1 1* X Q 0 1* D D

Both X 0 X QLegend:

X__/SR0*1*

Don’t careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)

Value When to Usefull delay(default, noattribute added)

Zero Hold with respect to GlobalLow-Skew Buffer, Global Early Buffer

MEDDELAY Zero Hold with respect to Global EarlyBuffer

NODELAY Short Setup, positive Hold time

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6

Additional Input Latch for Fast Capture (XC4000X only)

The XC4000X IOB has an additional optional latch on theinput. This latch, as shown in Figure 16, is clocked by theoutput clock — the clock used for the output flip-flop —rather than the input clock. Therefore, two different clockscan be used to clock the two input storage elements. Thisadditional latch allows the very fast capture of input data,which is then synchronized to the internal clock by the IOBflip-flop or latch.

To use this Fast Capture technique, drive the output clockpin (the Fast Capture latching signal) from the output of oneof the Global Early buffers supplied in the XC4000X. Thesecond storage element should be clocked by a GlobalLow-Skew buffer, to synchronize the incoming data to theinternal logic. (See Figure 17.) These special buffers aredescribed in “Global Nets and Buffers (XC4000X only)” onpage 37.

The Fast Capture latch (FCL) is designed primarily for usewith a Global Early buffer. For Fast Capture, a single clocksignal is routed through both a Global Early buffer and aGlobal Low-Skew buffer. (The two buffers share an inputpad.) The Fast Capture latch is clocked by the Global Earlybuffer, and the standard IOB flip-flop or latch is clocked bythe Global Low-Skew buffer. This mode is the safest way touse the Fast Capture latch, because the clock buffers onboth storage elements are driven by the same pad. There isno external skew between clock pads to create potentialproblems.

To place the Fast Capture latch in a design, use one of thespecial library symbols, ILFFX or ILFLX. ILFFX is a trans-parent-Low Fast Capture latch followed by an active-Highinput flip-flop. ILFLX is a transparent-Low Fast Capturelatch followed by a transparent-High input latch. Any of theclock inputs can be inverted before driving the library ele-ment, and the inverter is absorbed into the IOB. If a singleBUFG output is used to drive both clock inputs, the soft-ware automatically runs the clock through both a GlobalLow-Skew buffer and a Global Early buffer, and clocks theFast Capture latch appropriately.

Figure 16 on page 21 also shows a two-tap delay on theinput. By default, if the Fast Capture latch is used, the Xilinxsoftware assumes a Global Early buffer is driving the clock,and selects MEDDELAY to ensure a zero hold time. Select

the desired delay based on the discussion in the previoussubsection.

IOB Output Signals

Output signals can be optionally inverted within the IOB,and can pass directly to the pad or be stored in anedge-triggered flip-flop. The functionality of this flip-flop isshown in Table 11.

An active-High 3-state signal can be used to place the out-put buffer in a high-impedance state, implementing 3-stateoutputs or bidirectional I/O. Under configuration control, theoutput (OUT) and output 3-state (T) signals can beinverted. The polarity of these signals is independently con-figured for each IOB.

The 4-mA maximum output current specification of manyFPGAs often forces the user to add external buffers, whichare especially cumbersome on bidirectional I/O lines. TheXC4000E and XC4000EX/XL devices solve many of theseproblems by providing a guaranteed output sink current of12 mA. Two adjacent outputs can be interconnected exter-nally to sink up to 24 mA. The XC4000E and XC4000EX/XLFPGAs can thus directly drive buses on a printed circuitboard.

By default, the output pull-up structure is configured as aTTL-like totem-pole. The High driver is an n-channel pull-uptransistor, pulling to a voltage one transistor thresholdbelow Vcc. Alternatively, the outputs can be globally config-ured as CMOS drivers, with p-channel pull-up transistorspulling to Vcc. This option, applied using the bitstream gen-eration software, applies to all outputs on the device. It isnot individually programmable. In the XC4000XL, all out-puts are pulled to the positive supply rail.

IPAD

IPAD

BUFGE

BUFGLS

C

CE

D Q

GF

to internal logic

ILFFX

X9013

Figure 17: Examples Using XC4000X FCL

Table 11: Output Flip-Flop Functionality (active risingedge is shown)

Mode ClockClock

Enable T D QPower-Upor GSR

X X 0* X SR

Flip-Flop

X 0 0* X Q__/ 1* 0* D DX X 1 X Z0 X 0* X Q

Legend:X

__/SR0*1*Z

Don’t careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)3-state

May 14, 1999 (Version 1.6) 6-23

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Any XC4000 Series 5-Volt device with its outputs config-ured in TTL mode can drive the inputs of any typical3.3-Volt device. (For a detailed discussion of how to inter-face between 5 V and 3.3 V devices, see the 3V Productssection of The Programmable Logic Data Book.)

Supported destinations for XC4000 Series device outputsare shown in Table 12.

An output can be configured as open-drain (open-collector)by placing an OBUFT symbol in a schematic or HDL code,then tying the 3-state pin (T) to the output signal, and theinput pin (I) to Ground. (See Figure 18.)

Table 12: Supported Destinations for XC4000 SeriesOutputs

Output Slew Rate

The slew rate of each output buffer is, by default, reduced,to minimize power bus transients when switching non-criti-cal signals. For critical signals, attach a FAST attribute orproperty to the output buffer or flip-flop.

For XC4000E devices, maximum total capacitive load forsimultaneous fast mode switching in the same direction is200 pF for all package pins between each Power/Groundpin pair. For XC4000X devices, additional internal

Power/Ground pin pairs are connected to special Powerand Ground planes within the packages, to reduce groundbounce. Therefore, the maximum total capacitive load is300 pF between each external Power/Ground pin pair.Maximum loading may vary for the low-voltage devices.

For slew-rate limited outputs this total is two times larger foreach device type: 400 pF for XC4000E devices and 600 pFfor XC4000X devices. This maximum capacitive loadshould not be exceeded, as it can result in ground bounceof greater than 1.5 V amplitude and more than 5 ns dura-tion. This level of ground bounce may cause undesiredtransient behavior on an output, or in the internal logic. Thisrestriction is common to all high-speed digital ICs, and isnot particular to Xilinx or the XC4000 Series.

XC4000 Series devices have a feature called “SoftStart-up,” designed to reduce ground bounce when all out-puts are turned on simultaneously at the end of configura-tion. When the configuration process is finished and thedevice starts up, the first activation of the outputs is auto-matically slew-rate limited. Immediately following the initialactivation of the I/O, the slew rate of the individual outputsis determined by the individual configuration option for eachIOB.

Global Three-State

A separate Global 3-State line (not shown in Figure 15 orFigure 16) forces all FPGA outputs to the high-impedancestate, unless boundary scan is enabled and is executing anEXTEST instruction. This global net (GTS) does not com-pete with other routing resources; it uses a dedicated distri-bution network.

GTS can be driven from any user-programmable pin as aglobal 3-state input. To use this global net, place an inputpad and input buffer in the schematic or HDL code, drivingthe GTS pin of the STARTUP symbol. A specific pin loca-tion can be assigned to this input using a LOC attribute orproperty, just as with any other user-programmable pad. Aninverter can optionally be inserted after the input buffer toinvert the sense of the Global 3-State signal. Using GTS issimilar to GSR. See Figure 2 on page 11 for details.

Alternatively, GTS can be driven from any internal node.

Destination

XC4000 SeriesOutputs

3.3 V,CMOS

5 V,TTL

5 V,CMOS

Any typical device, Vcc = 3.3 V,CMOS-threshold inputs

√ √ some1

1. Only if destination device has 5-V tolerant inputs

Any device, Vcc = 5 V,TTL-threshold inputs

√ √ √

Any device, Vcc = 5 V,CMOS-threshold inputs

UnreliableData

√

X6702

OPADOBUFT

Figure 18: Open-Drain Output

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6

Output Multiplexer/2-Input Function Generator(XC4000X only)

As shown in Figure 16 on page 21, the output path in theXC4000X IOB contains an additional multiplexer not avail-able in the XC4000E IOB. The multiplexer can also be con-figured as a 2-input function generator, implementing apass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2inverted inputs. The logic used to implement these func-tions is shown in the upper gray area of Figure 16.

When configured as a multiplexer, this feature allows twooutput signals to time-share the same output pad; effec-tively doubling the number of device outputs without requir-ing a larger, more expensive package.

When the MUX is configured as a 2-input function genera-tor, logic can be implemented within the IOB itself. Com-bined with a Global Early buffer, this arrangement allowsvery high-speed gating of a single signal. For example, awide decoder can be implemented in CLBs, and its outputgated with a Read or Write Strobe Driven by a BUFGEbuffer, as shown in Figure 19. The critical-path pin-to-pindelay of this circuit is less than 6 nanoseconds.

As shown in Figure 16, the IOB input pins Out, OutputClock, and Clock Enable have different delays and differentflexibilities regarding polarity. Additionally, Output Clocksources are more limited than the other inputs. Therefore,the Xilinx software does not move logic into the IOB func-tion generators unless explicitly directed to do so.

The user can specify that the IOB function generator beused, by placing special library symbols beginning with theletter “O.” For example, a 2-input AND-gate in the IOB func-tion generator is called OAND2. Use the symbol input pinlabelled “F” for the signal on the critical path. This signal isplaced on the OK pin — the IOB input with the shortestdelay to the function generator. Two examples are shown inFigure 20.

Other IOB Options

There are a number of other programmable options in theXC4000 Series IOB.

Pull-up and Pull-down Resistors

Programmable pull-up and pull-down resistors are usefulfor tying unused pins to Vcc or Ground to minimize powerconsumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to Vcc.The configurable pull-down resistor is an n-channel transis-tor that pulls to Ground.

The value of these resistors is 50 kΩ − 100 kΩ. This highvalue makes them unsuitable as wired-AND pull-up resis-tors.

The pull-up resistors for most user-programmable IOBs areactive during the configuration process. See Table 22 onpage 58 for a list of pins with pull-ups active before and dur-ing configuration.

After configuration, voltage levels of unused pads, bondedor un-bonded, must be valid logic levels, to reduce noisesensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resis-tor active. Alternatively, they can be individually configuredwith the pull-down resistor, or as a driven output, or to bedriven by an external source. To activate the internalpull-up, attach the PULLUP library component to the netattached to the pad. To activate the internal pull-down,attach the PULLDOWN library component to the netattached to the pad.

Independent Clocks

Separate clock signals are provided for the input and outputflip-flops. The clock can be independently inverted for eachflip-flop within the IOB, generating either falling-edge or ris-ing-edge triggered flip-flops. The clock inputs for each IOBare independent, except that in the XC4000X, the FastCapture latch shares an IOB input with the output clock pin.

Early Clock for IOBs (XC4000X only)

Special early clocks are available for IOBs. These clocksare sourced by the same sources as the Global Low-Skewbuffers, but are separately buffered. They have fewer loadsand therefore less delay. The early clock can drive eitherthe IOB output clock or the IOB input clock, or both. Theearly clock allows fast capture of input data, and fastclock-to-output on output data. The Global Early buffersthat drive these clocks are described in “Global Nets andBuffers (XC4000X only)” on page 37.

Global Set/Reset

As with the CLB registers, the Global Set/Reset signal(GSR) can be used to set or clear the input and output reg-isters, depending on the value of the INIT attribute or prop-erty. The two flip-flops can be individually configured to set

IPAD

F OPADFAST

BUFGE

OAND2from internal logic

X9019

Figure 19: Fast Pin-to-Pin Path in XC4000X

OAND2

F

X6598

D0

S0

D1O

OMUX2

X6599

Figure 20: AND & MUX Symbols in XC4000X IOB

May 14, 1999 (Version 1.6) 6-25

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or clear on reset and after configuration. Other than the glo-bal GSR net, no user-controlled set/reset signal is availableto the I/O flip-flops. The choice of set or clear applies toboth the initial state of the flip-flop and the response to theGlobal Set/Reset pulse. See “Global Set/Reset” onpage 11 for a description of how to use GSR.

JTAG Support

Embedded logic attached to the IOBs contains test struc-tures compatible with IEEE Standard 1149.1 for boundaryscan testing, permitting easy chip and board-level testing.More information is provided in “Boundary Scan” onpage 42.

Three-State BuffersA pair of 3-state buffers is associated with each CLB in thearray. (See Figure 27 on page 30.) These 3-state bufferscan be used to drive signals onto the nearest horizontallonglines above and below the CLB. They can therefore beused to implement multiplexed or bidirectional buses on thehorizontal longlines, saving logic resources. Programmablepull-up resistors attached to these longlines help to imple-ment a wide wired-AND function.

The buffer enable is an active-High 3-state (i.e. anactive-Low enable), as shown in Table 13.

Another 3-state buffer with similar access is located neareach I/O block along the right and left edges of the array.(See Figure 33 on page 34.)

The horizontal longlines driven by the 3-state buffers havea weak keeper at each end. This circuit prevents undefinedfloating levels. However, it is overridden by any driver, evena pull-up resistor.

Special longlines running along the perimeter of the arraycan be used to wire-AND signals coming from nearby IOBsor from internal longlines. These longlines form the wideedge decoders discussed in “Wide Edge Decoders” onpage 27.

Three-State Buffer Modes

The 3-state buffers can be configured in three modes:

• Standard 3-state buffer• Wired-AND with input on the I pin• Wired OR-AND

Standard 3-State Buffer

All three pins are used. Place the library element BUFT.Connect the input to the I pin and the output to the O pin.The T pin is an active-High 3-state (i.e. an active-Lowenable). Tie the T pin to Ground to implement a standardbuffer.

Wired-AND with Input on the I Pin

The buffer can be used as a Wired-AND. Use the WAND1library symbol, which is essentially an open-drain buffer.WAND4, WAND8, and WAND16 are also available. See theXACT Libraries Guide for further information.

The T pin is internally tied to the I pin. Connect the input tothe I pin and the output to the O pin. Connect the outputs ofall the WAND1s together and attach a PULLUP symbol.

Wired OR-AND

The buffer can be configured as a Wired OR-AND. A Highlevel on either input turns off the output. Use theWOR2AND library symbol, which is essentially anopen-drain 2-input OR gate. The two input pins are func-tionally equivalent. Attach the two inputs to the I0 and I1pins and tie the output to the O pin. Tie the outputs of all theWOR2ANDs together and attach a PULLUP symbol.

Three-State Buffer Examples

Figure 21 shows how to use the 3-state buffers to imple-ment a wired-AND function. When all the buffer inputs areHigh, the pull-up resistor(s) provide the High output.

Figure 22 shows how to use the 3-state buffers to imple-ment a multiplexer. The selection is accomplished by thebuffer 3-state signal.

Pay particular attention to the polarity of the T pin whenusing these buffers in a design. Active-High 3-state (T) isidentical to an active-Low output enable, as shown inTable 13.

Table 13: Three-State Buffer Functionality

IN T OUTX 1 ZIN 0 IN

P U L L

U P

Z = DA

DB

(DC

+DD

) (DE

+DF)

DE

DF

DC

DD

DB

DA

WAND1 WAND1WOR2AND WOR2AND

X6465

Figure 21: Open-Drain Buffers Implement a Wired-AND Function

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Wide Edge DecodersDedicated decoder circuitry boosts the performance ofwide decoding functions. When the address or data field iswider than the function generator inputs, FPGAs needmulti-level decoding and are thus slower than PALs.XC4000 Series CLBs have nine inputs. Any decoder of upto nine inputs is, therefore, compact and fast. However,there is also a need for much wider decoders, especially foraddress decoding in large microprocessor systems.

An XC4000 Series FPGA has four programmable decoderslocated on each edge of the device. The inputs to eachdecoder are any of the IOB I1 signals on that edge plus onelocal interconnect per CLB row or column. Each row or col-umn of CLBs provides up to three variables or their compli-ments., as shown in Figure 23. Each decoder generates aHigh output (resistor pull-up) when the AND condition ofthe selected inputs, or their complements, is true. This isanalogous to a product term in typical PAL devices.

Each of these wired-AND gates is capable of accepting upto 42 inputs on the XC4005E and 72 on the XC4013E.There are up to 96 inputs for each decoder on theXC4028X and 132 on the XC4052X. The decoders mayalso be split in two when a larger number of narrowerdecoders are required, for a maximum of 32 decoders perdevice.

The decoder outputs can drive CLB inputs, so they can becombined with other logic to form a PAL-like AND/OR struc-ture. The decoder outputs can also be routed directly to thechip outputs. For fastest speed, the output should be on thesame chip edge as the decoder. Very large PALs can beemulated by ORing the decoder outputs in a CLB. Thisdecoding feature covers what has long been considered aweakness of older FPGAs. Users often resorted to externalPALs for simple but fast decoding functions. Now, the dedi-cated decoders in the XC4000 Series device can imple-ment these functions fast and efficiently.

To use the wide edge decoders, place one or more of theWAND library symbols (WAND1, WAND4, WAND8,WAND16). Attach a DECODE attribute or property to eachWAND symbol. Tie the outputs together and attach a PUL-

LUP symbol. Location attributes or properties such as L(left edge) or TR (right half of top edge) should also be usedto ensure the correct placement of the decoder inputs.

On-Chip OscillatorXC4000 Series devices include an internal oscillator. Thisoscillator is used to clock the power-on time-out, for config-uration memory clearing, and as the source of CCLK inMaster configuration modes. The oscillator runs at a nomi-nal 8 MHz frequency that varies with process, Vcc, andtemperature. The output frequency falls between 4 and 10MHz.

DNDCDBDA

A B C N

Z = DA • A + DB • B + DC • C + DN • N~100 kΩ

"Weak Keeper"

X6466

BUFT BUFT BUFT BUFT

Figure 22: 3-State Buffers Implement a Multiplexer

IOBIOB

BA

INTERCONNECT

( C) .....

(A • B • C) .....

(A • B • C) .....

(A • B • C) .....

.I1.I1

X2627

C

Figure 23: XC4000 Series Edge Decoding Example

F16K

F500K

F8M

F490

F15

X6703

OSC4

Figure 24: XC4000 Series Oscillator Symbol

May 14, 1999 (Version 1.6) 6-27

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The oscillator output is optionally available after configura-tion. Any two of four resynchronized taps of a built-in dividerare also available. These taps are at the fourth, ninth, four-teenth and nineteenth bits of the divider. Therefore, if theprimary oscillator output is running at the nominal 8 MHz,the user has access to an 8 MHz clock, plus any two of 500kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt-age devices). These frequencies can vary by as much as-50% or +25%.

These signals can be accessed by placing the OSC4library element in a schematic or in HDL code (seeFigure 24).

The oscillator is automatically disabled after configuration ifthe OSC4 symbol is not used in the design.

Programmable InterconnectAll internal connections are composed of metal segmentswith programmable switching points and switching matricesto implement the desired routing. A structured, hierarchicalmatrix of routing resources is provided to achieve efficientautomated routing.

The XC4000E and XC4000X share a basic interconnectstructure. XC4000X devices, however, have additional rout-ing not available in the XC4000E. The extra routingresources allow high utilization in high-capacity devices. AllXC4000X-specific routing resources are clearly identifiedthroughout this section. Any resources not identified asXC4000X-specific are present in all XC4000 Seriesdevices.

This section describes the varied routing resources avail-able in XC4000 Series devices. The implementation soft-ware automatically assigns the appropriate resourcesbased on the density and timing requirements of thedesign.

Interconnect OverviewThere are several types of interconnect.

• CLB routing is associated with each row and column ofthe CLB array.

• IOB routing forms a ring (called a VersaRing) aroundthe outside of the CLB array. It connects the I/O with theinternal logic blocks.

• Global routing consists of dedicated networks primarilydesigned to distribute clocks throughout the device withminimum delay and skew. Global routing can also beused for other high-fanout signals.

Five interconnect types are distinguished by the relativelength of their segments: single-length lines, double-lengthlines, quad and octal lines (XC4000X only), and longlines.In the XC4000X, direct connects allow fast data flowbetween adjacent CLBs, and between IOBs and CLBs.

Extra routing is included in the IOB pad ring. The XC4000Xalso includes a ring of octal interconnect lines near theIOBs to improve pin-swapping and routing to locked pins.

XC4000E/X devices include two types of global buffers.These global buffers have different properties, and areintended for different purposes. They are discussed indetail later in this section.

CLB Routing ConnectionsA high-level diagram of the routing resources associatedwith one CLB is shown in Figure 25. The shaded arrowsrepresent routing present only in XC4000X devices.

Table 14 shows how much routing of each type is availablein XC4000E and XC4000X CLB arrays. Clearly, very largedesigns, or designs with a great deal of interconnect, willroute more easily in the XC4000X. Smaller XC4000Edesigns, typically requiring significantly less interconnect,do not require the additional routing.

Figure 27 on page 30 is a detailed diagram of both theXC4000E and the XC4000X CLB, with associated routing.The shaded square is the programmable switch matrix,present in both the XC4000E and the XC4000X. TheL-shaped shaded area is present only in XC4000X devices.As shown in the figure, the XC4000X block is essentially anXC4000E block with additional routing.

CLB inputs and outputs are distributed on all four sides,providing maximum routing flexibility. In general, the entirearchitecture is symmetrical and regular. It is well suited toestablished placement and routing algorithms. Inputs, out-puts, and function generators can freely swap positionswithin a CLB to avoid routing congestion during the place-ment and routing operation.

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6
Table 14: Routing per CLB in XC4000 Series Devices
Programmable Switch Matrices

The horizontal and vertical single- and double-length linesintersect at a box called a programmable switch matrix(PSM). Each switch matrix consists of programmable passtransistors used to establish connections between the lines(see Figure 26).

For example, a single-length signal entering on the rightside of the switch matrix can be routed to a single-lengthline on the top, left, or bottom sides, or any combinationthereof, if multiple branches are required. Similarly, a dou-ble-length signal can be routed to a double-length line onany or all of the other three edges of the programmableswitch matrix.

Single-Length Lines

Single-length lines provide the greatest interconnect flexi-bility and offer fast routing between adjacent blocks. Thereare eight vertical and eight horizontal single-length linesassociated with each CLB. These lines connect the switch-ing matrices that are located in every row and a column ofCLBs.

Single-length lines are connected by way of the program-mable switch matrices, as shown in Figure 28. Routingconnectivity is shown in Figure 27.

Single-length lines incur a delay whenever they go througha switching matrix. Therefore, they are not suitable for rout-ing signals for long distances. They are normally used toconduct signals within a localized area and to provide thebranching for nets with fanout greater than one.

x5994

Quad

Quad

Single

Double

Long

Direct Connect

Long

CLB

Long Global Clock

Long Double Single Global Clock

Carry Chain

Direct Connect

Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)

XC4000E XC4000XVertical Horizontal Vertical Horizontal

Singles 8 8 8 8Doubles 4 4 4 4Quads 0 0 12 12Longlines 6 6 10 6DirectConnects

0 0 2 2

Globals 4 0 8 0Carry Logic 2 0 1 0Total 24 18 45 32

Six Pass Transistors Per Switch Matrix Interconnect Point

Singles

Double

Double

Single

s

Double

Double

X6600

Figure 26: Programmable Switch Matrix (PSM)

May 14, 1999 (Version 1.6) 6-29

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F1

C1

G1

F2 C2 G2

F3

C3

G3

F4 C4 G4

K

X

Y

XQ

YQ

LONGSINGLE

DOUBLE

LONG

GLOBAL

QUAD

LONG

SINGLE

DOUBLE

LONG

LONG

DOUBLE

DOUBLEQUAD

GLOBAL

Common to XC4000E and XC4000X

XC4000X only

Programmable Switch Matrix

CLB

DIRECTFEEDBACK

DIRECT

FEEDBACK

Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB

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Double-Length Lines

The double-length lines consist of a grid of metal segments,each twice as long as the single-length lines: they run pasttwo CLBs before entering a switch matrix. Double-lengthlines are grouped in pairs with the switch matrices stag-gered, so that each line goes through a switch matrix atevery other row or column of CLBs (see Figure 28).

There are four vertical and four horizontal double-lengthlines associated with each CLB. These lines provide fastersignal routing over intermediate distances, while retainingrouting flexibility. Double-length lines are connected by wayof the programmable switch matrices. Routing connectivityis shown in Figure 27.

Quad Lines (XC4000X only)

XC4000X devices also include twelve vertical and twelvehorizontal quad lines per CLB row and column. Quad linesare four times as long as the single-length lines. They areinterconnected via buffered switch matrices (shown as dia-monds in Figure 27 on page 30). Quad lines run past fourCLBs before entering a buffered switch matrix. They aregrouped in fours, with the buffered switch matrices stag-gered, so that each line goes through a buffered switchmatrix at every fourth CLB location in that row or column.(See Figure 29.)

The buffered switch matrixes have four pins, one on eachedge. All of the pins are bidirectional. Any pin can drive anyor all of the other pins.

Each buffered switch matrix contains one buffer and sixpass transistors. It resembles the programmable switchmatrix shown in Figure 26, with the addition of a program-mable buffer. There can be up to two independent inputs

and up to two independent outputs. Only one of the inde-pendent inputs can be buffered.

The place and route software automatically uses the timingrequirements of the design to determine whether or not aquad line signal should be buffered. A heavily loaded signalis typically buffered, while a lightly loaded one is not. Onescenario is to alternate buffers and pass transistors. Thisallows both vertical and horizontal quad lines to be bufferedat alternating buffered switch matrices.

Due to the buffered switch matrices, quad lines are veryfast. They provide the fastest available method of routingheavily loaded signals for long distances across the device.

Longlines

Longlines form a grid of metal interconnect segments thatrun the entire length or width of the array. Longlines areintended for high fan-out, time-critical signal nets, or netsthat are distributed over long distances. In XC4000Xdevices, quad lines are preferred for critical nets, becausethe buffered switch matrices make them faster for highfan-out nets.

Two horizontal longlines per CLB can be driven by 3-stateor open-drain drivers (TBUFs). They can therefore imple-ment unidirectional or bidirectional buses, wide multiplex-ers, or wired-AND functions. (See “Three-State Buffers” onpage 26 for more details.)

Each horizontal longline driven by TBUFs has either two(XC4000E) or eight (XC4000X) pull-up resistors. To acti-vate these resistors, attach a PULLUP symbol to thelong-line net. The software automatically activates theappropriate number of pull-ups. There is also a weakkeeper at each end of these two horizontal longlines. This

CLB

PSM PSM

PSMPSM

CLB CLB

CLB CLB CLB

CLB CLB CLB

Doubles

Singles

Doubles

X6601

Figure 28: Single- and Double-Length Lines, withProgrammable Switch Matrices (PSMs)

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

X9014

Figure 29: Quad Lines (XC4000X only)

May 14, 1999 (Version 1.6) 6-31

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circuit prevents undefined floating levels. However, it isoverridden by any driver, even a pull-up resistor.

Each XC4000E longline has a programmable splitter switchat its center, as does each XC4000X longline driven byTBUFs. This switch can separate the line into two indepen-dent routing channels, each running half the width or heightof the array.

Each XC4000X longline not driven by TBUFs has a buff-ered programmable splitter switch at the 1/4, 1/2, and 3/4points of the array. Due to the buffering, XC4000X longlineperformance does not deteriorate with the larger arraysizes. If the longline is split, the resulting partial longlinesare independent.

Routing connectivity of the longlines is shown in Figure 27on page 30.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efficient and fast connec-tions between adjacent CLBs. These nets facilitate a dataflow from the left to the right side of the device, or from thetop to the bottom, as shown in Figure 30. Signals routed onthe direct interconnect exhibit minimum interconnect prop-agation delay and use no general routing resources.

The direct interconnect is also present between CLBs andadjacent IOBs. Each IOB on the left and top device edgeshas a direct path to the nearest CLB. Each CLB on the rightand bottom edges of the array has a direct path to the near-est two IOBs, since there are two IOBs for each row or col-umn of CLBs.

The place and route software uses direct interconnectwhenever possible, to maximize routing resources and min-imize interconnect delays.

I/O RoutingXC4000 Series devices have additional routing around theIOB ring. This routing is called a VersaRing. The VersaRingfacilitates pin-swapping and redesign without affectingboard layout. Included are eight double-length lines span-ning two CLBs (four IOBs), and four longlines. Global linesand Wide Edge Decoder lines are provided. XC4000Xdevices also include eight octal lines.

A high-level diagram of the VersaRing is shown inFigure 31. The shaded arrows represent routing presentonly in XC4000X devices.

Figure 33 on page 34 is a detailed diagram of the XC4000Eand XC4000X VersaRing. The area shown includes twoIOBs. There are two IOBs per CLB row or column, there-fore this diagram corresponds to the CLB routing diagramshown in Figure 27 on page 30. The shaded areas repre-sent routing and routing connections present only inXC4000X devices.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eightinterconnect tracks provide for versatility in pin assignmentand fixed pinout flexibility. (See Figure 32 on page 33.)

These routing tracks are called octals, because they can bebroken every eight CLBs (sixteen IOBs) by a programma-ble buffer that also functions as a splitter switch. The buffersare staggered, so each line goes through a buffer at everyeighth CLB location around the device edge.

The octal lines bend around the corners of the device. Thelines cross at the corners in such a way that the segmentmost recently buffered before the turn has the farthest dis-tance to travel before the next buffer, as shown inFigure 32.

CLBIOB

X6603

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOBCLB

CLB

CLB

CLB

CLB

~~~~

~~~~

~~~~ ~~~~ ~~~~

Figure 30: XC4000X Direct Interconnect

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6

X5995

Direct Connect

Edge Decode

Double Long Global Clock

Octal

Quad

Single

Double

Long

Direct Connect

Long

INTERCONNECT

IOBWED

WED

WEDIOB

Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge)WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)

Segment with nearest buffer connects to segment with furthest buffer

IOB

IOBIOB

IOB

X9015

Figure 32: XC4000X Octal I/O Routing

May 14, 1999 (Version 1.6) 6-33

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TO

CLB

ARRAY

IK

OK

I1

CE

I2

DE

CO

DE

R

T O

OCTAL

EDGEDECODE

QUAD

LONG

SINGLE

DOUBLE

LONG

LONG

DOUBLE

DOUBLE

GLOBAL

IK

OK

I1

CE

I2

T O

DE

CO

DE

RD

EC

OD

ER

Common to XC4000E and XC4000X

XC4000X only

IOB

IOB

DIRECT

Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)

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6

IOB inputs and outputs interface with the octal lines via thesingle-length interconnect lines. Single-length lines arealso used for communication between the octals and dou-ble-length lines, quads, and longlines within the CLB array.

Segmentation into buffered octals was found to be optimalfor distributing signals over long distances around thedevice.

Global Nets and BuffersBoth the XC4000E and the XC4000X have dedicated glo-bal networks. These networks are designed to distributeclocks and other high fanout control signals throughout thedevices with minimal skew. The global buffers aredescribed in detail in the following sections. The textdescriptions and diagrams are summarized in Table 15.The table shows which CLB and IOB clock pins can besourced by which global buffers.

In both XC4000E and XC4000X devices, placement of alibrary symbol called BUFG results in the software choos-ing the appropriate clock buffer, based on the timingrequirements of the design. The detailed information inthese sections is included only for reference.

Global Nets and Buffers (XC4000E only)

Four vertical longlines in each CLB column are drivenexclusively by special global buffers. These longlines arein addition to the vertical longlines used for standard inter-connect. The four global lines can be driven by either of twotypes of global buffers. The clock pins of every CLB andIOB can also be sourced from local interconnect.

Two different types of clock buffers are available in theXC4000E:

• Primary Global Buffers (BUFGP)• Secondary Global Buffers (BUFGS)

Four Primary Global buffers offer the shortest delay andnegligible skew. Four Secondary Global buffers haveslightly longer delay and slightly more skew due to poten-tially heavier loading, but offer greater flexibility when usedto drive non-clock CLB inputs.

The Primary Global buffers must be driven by thesemi-dedicated pads. The Secondary Global buffers canbe sourced by either semi-dedicated pads or internal nets.

Each CLB column has four dedicated vertical Global lines.Each of these lines can be accessed by one particular Pri-mary Global buffer, or by any of the Secondary Global buff-ers, as shown in Figure 34. Each corner of the device hasone Primary buffer and one Secondary buffer.

IOBs along the left and right edges have four vertical globallonglines. Top and bottom IOBs can be clocked from theglobal lines in the adjacent CLB column.

A global buffer should be specified for all timing-sensitiveglobal signal distribution. To use a global buffer, place aBUFGP (primary buffer), BUFGS (secondary buffer), orBUFG (either primary or secondary buffer) element in aschematic or in HDL code. If desired, attach a LOCattribute or property to direct placement to the designatedlocation. For example, attach a LOC=L attribute or propertyto a BUFGS symbol to direct that a buffer be placed in oneof the two Secondary Global buffers on the left edge of thedevice, or a LOC=BL to indicate the Secondary Globalbuffer on the bottom edge of the device, on the left.

L = Left, R = Right, T = Top, B = Bottom

Table 15: Clock Pin Access

XC4000E XC4000X LocalInter-

connectBUFGP BUFGS BUFGLSL & R

BUFGET & B

BUFGEAll CLBs in Quadrant √ √ √ √ √ √All CLBs in Device √ √ √ √IOBs on Adjacent VerticalHalf Edge

√ √ √ √ √ √

IOBs on Adjacent VerticalFull Edge

√ √ √ √ √

IOBs on Adjacent HorizontalHalf Edge (Direct)

√ √

IOBs on Adjacent HorizontalHalf Edge (through CLB globals)

√ √ √ √ √ √

IOBs on Adjacent HorizontalFull Edge (through CLB globals)

√ √ √ √

May 14, 1999 (Version 1.6) 6-35

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X4 X4

X6604

X4

4

One BUFGP per Global Line

One BUFGP per Global Line

Any BUFGS Any BUFGS

BUFGP

PGCK4SGCK4

PGCK3SGCK3

BUFGS

BUFGP

BUFGS

IOB

IOB

IOBIOBIOBIOB

IOBIOBIOB

IOB

IOB

BUFGS

BUFGS

BUFGP

BUFGP

SGCK1

PGCK1

SGCK2PGCK2

IOB

X4locals

localslocals

locals

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

4

4 4

CLB

CLB

locals locals

CLB

CLBlocals locals

Figure 34: XC4000E Global Net Distribution

X4

4

IOB CLOCKS

CLB CLOCKS (PER COLUMN)




locals

locals

locals

locals

localsBUFGLS

localsBUFGLS

BUFGLS

BUFGLS BUFGLS

BUFGE

BUFGE

BUFGE

BUFGE

BUFGE

BUFGE

BUFGE BUFGE

BUFGLS BUFGLSIOB IOB IOB IOB

IOB IOB IOB IOB

BUFGLS BUFGLS

BUFGLS BUFGLS

GCK8 GCK7GCK1 GCK6

GCK2 GCK5GCK3 GCK4

IOB

IOB

IOB

IOB

locals

BUFGLSlocals

BUFGLSlocals

localsBUFGLS

localsBUFGLS

IOB CLOCKS

IOB CLOCKS

IOB CLOCKS

4

X8

X8X4

X9018

8

8

8 8

8 BUFGLSlocals

88 8

8 8

8

8

8

8

CLB

CLB

CLB

CLB

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

loca

ls

X8

X8

X8

X8

Figure 35: XC4000X Global Net Distribution

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6

Global Nets and Buffers (XC4000X only)

Eight vertical longlines in each CLB column are driven byspecial global buffers. These longlines are in addition to thevertical longlines used for standard interconnect. The glo-bal lines are broken in the center of the array, to allow fasterdistribution and to minimize skew across the whole array.Each half-column global line has its own buffered multi-plexer, as shown in Figure 35. The top and bottom globallines cannot be connected across the center of the device,as this connection might introduce unacceptable skew. Thetop and bottom halves of the global lines must be sepa-rately driven — although they can be driven by the sameglobal buffer.

The eight global lines in each CLB column can be driven byeither of two types of global buffers. They can also bedriven by internal logic, because they can be accessed bysingle, double, and quad lines at the top, bottom, half, andquarter points. Consequently, the number of differentclocks that can be used simultaneously in an XC4000Xdevice is very large.

There are four global lines feeding the IOBs at the left edgeof the device. IOBs along the right edge have eight globallines. There is a single global line along the top and bottomedges with access to the IOBs. All IOB global lines are bro-ken at the center. They cannot be connected across thecenter of the device, as this connection might introduceunacceptable skew.

IOB global lines can be driven from two types of global buff-ers, or from local interconnect. Alternatively, top and bottomIOBs can be clocked from the global lines in the adjacentCLB column.

Two different types of clock buffers are available in theXC4000X:

• Global Low-Skew Buffers (BUFGLS)• Global Early Buffers (BUFGE)

Global Low-Skew Buffers are the standard clock buffers.They should be used for most internal clocking, whenever alarge portion of the device must be driven.

Global Early Buffers are designed to provide a faster clockaccess, but CLB access is limited to one-fourth of thedevice. They also facilitate a faster I/O interface.

Figure 35 is a conceptual diagram of the global net struc-ture in the XC4000X.

Global Early buffers and Global Low-Skew buffers share asingle pad. Therefore, the same IPAD symbol can drive onebuffer of each type, in parallel. This configuration is particu-larly useful when using the Fast Capture latches, asdescribed in “IOB Input Signals” on page 20. Paired Global

Early and Global Low-Skew buffers share a common input;they cannot be driven by two different signals.

Choosing an XC4000X Clock Buffer

The clocking structure of the XC4000X provides a largevariety of features. However, it can be simple to use, with-out understanding all the details. The software automati-cally handles clocks, along with all other routing, when theappropriate clock buffer is placed in the design. In fact, if abuffer symbol called BUFG is placed, rather than a specifictype of buffer, the software even chooses the buffer mostappropriate for the design. The detailed information in thissection is provided for those users who want a finer level ofcontrol over their designs.

If fine control is desired, use the following summary andTable 15 on page 35 to choose an appropriate clock buffer.

• The simplest thing to do is to use a Global Low-Skewbuffer.

• If a faster clock path is needed, try a BUFG. Thesoftware will first try to use a Global Low-Skew Buffer. Iftiming requirements are not met, a faster buffer willautomatically be used.

• If a single quadrant of the chip is sufficient for theclocked logic, and the timing requires a faster clock thanthe Global Low-Skew buffer, use a Global Early buffer.

Global Low-Skew Buffers

Each corner of the XC4000X device has two GlobalLow-Skew buffers. Any of the eight Global Low-Skew buff-ers can drive any of the eight vertical Global lines in a col-umn of CLBs. In addition, any of the buffers can drive any ofthe four vertical lines accessing the IOBs on the left edge ofthe device, and any of the eight vertical lines accessing theIOBs on the right edge of the device. (See Figure 36 onpage 38.)

IOBs at the top and bottom edges of the device areaccessed through the vertical Global lines in the CLB array,as in the XC4000E. Any Global Low-Skew buffer can,therefore, access every IOB and CLB in the device.

The Global Low-Skew buffers can be driven by eithersemi-dedicated pads or internal logic.

To use a Global Low-Skew buffer, instantiate a BUFGLSelement in a schematic or in HDL code. If desired, attach aLOC attribute or property to direct placement to the desig-nated location. For example, attach a LOC=T attribute orproperty to direct that a BUFGLS be placed in one of thetwo Global Low-Skew buffers on the top edge of the device,or a LOC=TR to indicate the Global Low-Skew buffer on thetop edge of the device, on the right.

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Global Early Buffers

Each corner of the XC4000X device has two Global Earlybuffers. The primary purpose of the Global Early buffers isto provide an earlier clock access than the potentiallyheavily-loaded Global Low-Skew buffers. A clock sourceapplied to both buffers will result in the Global Early clockedge occurring several nanoseconds earlier than the Glo-bal Low-Skew buffer clock edge, due to the lighter loading.

Global Early buffers also facilitate the fast capture of deviceinputs, using the Fast Capture latches described in “IOBInput Signals” on page 20. For Fast Capture, take a singleclock signal, and route it through both a Global Early bufferand a Global Low-Skew buffer. (The two buffers share aninput pad.) Use the Global Early buffer to clock the FastCapture latch, and the Global Low-Skew buffer to clock thenormal input flip-flop or latch, as shown in Figure 17 onpage 23.

The Global Early buffers can also be used to provide a fastClock-to-Out on device output pins. However, an early clockin the output flip-flop IOB must be taken into considerationwhen calculating the internal clock speed for the design.

The Global Early buffers at the left and right edges of thechip have slightly different capabilities than the ones at thetop and bottom. Refer to Figure 37, Figure 38, andFigure 35 on page 36 while reading the following explana-tion.

Each Global Early buffer can access the eight vertical Glo-bal lines for all CLBs in the quadrant. Therefore, onlyone-fourth of the CLB clock pins can be accessed. Thisrestriction is in large part responsible for the faster speed ofthe buffers, relative to the Global Low-Skew buffers.

The left-side Global Early buffers can each drive two of thefour vertical lines accessing the IOBs on the entire left edgeof the device. The right-side Global Early buffers can eachdrive two of the eight vertical lines accessing the IOBs onthe entire right edge of the device. (See Figure 37.)

Each left and right Global Early buffer can also drive half ofthe IOBs along either the top or bottom edge of the device,using a dedicated line that can only be accessed throughthe Global Early buffers.

The top and bottom Global Early buffers can drive half ofthe IOBs along either the left or right edge of the device, asshown in Figure 38. They can only access the top and bot-tom IOBs via the CLB global lines.

1 6

2 5

3

8

4

7

CLB CLB

CLBCLB

I O B

I O B

I O B

I O B

IOB IOB

IOBIOB

X6753

Figure 36: Any BUFGLS (GCK1 - GCK8) CanDrive Any or All Clock Inputs on the Device

1 6

2 5

3

8

4

7

CLB CLB

CLBCLB

I O B

I O B

I O B

I O B

IOB IOB

IOBIOB

X6751

Figure 37: Left and Right BUFGEs Can Drive Any orAll Clock Inputs in Same Quadrant or Edge (GCK1 isshown. GCK2, GCK5 and GCK6 are similar.)

1 6

2 5

3

8

4

7

CLB CLB

CLBCLB

I O B

I O B

I O B

I O B

IOB IOB

IOBIOB

X6747

Figure 38: Top and Bottom BUFGEs Can Drive Anyor All Clock Inputs in Same Quadrant (GCK8 isshown. GCK3, GCK4 and GCK7 are similar.)

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The top and bottom Global Early buffers are about 1 nsslower clock to out than the left and right Global Early buff-ers.

The Global Early buffers can be driven by either semi-ded-icated pads or internal logic. They share pads with the Glo-bal Low-Skew buffers, so a single net can drive both globalbuffers, as described above.

To use a Global Early buffer, place a BUFGE element in aschematic or in HDL code. If desired, attach a LOCattribute or property to direct placement to the designatedlocation. For example, attach a LOC=T attribute or propertyto direct that a BUFGE be placed in one of the two GlobalEarly buffers on the top edge of the device, or a LOC=TR toindicate the Global Early buffer on the top edge of thedevice, on the right.

Power DistributionPower for the FPGA is distributed through a grid to achievehigh noise immunity and isolation between logic and I/O.Inside the FPGA, a dedicated Vcc and Ground ring sur-rounding the logic array provides power to the I/O drivers,as shown in Figure 39. An independent matrix of Vcc andGround lines supplies the interior logic of the device.

This power distribution grid provides a stable supply andground for all internal logic, providing the external packagepower pins are all connected and appropriately de-coupled.Typically, a 0.1 µF capacitor connected between each Vccpin and the board’s Ground plane will provide adequatede-coupling.

Output buffers capable of driving/sinking the specified 12mA loads under specified worst-case conditions may becapable of driving/sinking up to 10 times as much currentunder best case conditions.

Noise can be reduced by minimizing external load capaci-tance and reducing simultaneous output transitions in thesame direction. It may also be beneficial to locate heavilyloaded output buffers near the Ground pads. The I/O Blockoutput buffers have a slew-rate limited mode (default) whichshould be used where output rise and fall times are notspeed-critical.

Pin DescriptionsThere are three types of pins in the XC4000 Seriesdevices:

• Permanently dedicated pins• User I/O pins that can have special functions• Unrestricted user-programmable I/O pins.

Before and during configuration, all outputs not used for theconfiguration process are 3-stated with a 50 kΩ - 100 kΩpull-up resistor.

After configuration, if an IOB is unused it is configured asan input with a 50 kΩ - 100 kΩ pull-up resistor.

XC4000 Series devices have no dedicated Reset input.Any user I/O can be configured to drive the GlobalSet/Reset net, GSR. See “Global Set/Reset” on page 11for more information on GSR.

XC4000 Series devices have no Powerdown control input,as the XC3000 and XC2000 families do. TheXC3000/XC2000 Powerdown control also 3-stated all of thedeviceI/O pins. For XC4000 Series devices, use the global 3-statenet, GTS, instead. This net 3-states all outputs, but doesnot place the device in low-power mode. See “IOB OutputSignals” on page 23 for more information on GTS.

Device pins for XC4000 Series devices are described inTable 16. Pin functions during configuration for each of theseven configuration modes are summarized in Table 22 onpage 58, in the “Configuration Timing” section.

GND

Ground and Vcc Ring for I/O Drivers

Vcc

GND

Vcc

Logic Power Grid

X5422

Figure 39: XC4000 Series Power Distribution

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Table 16: Pin Descriptions

Pin Name

I/ODuringConfig.

I/OAfter

Config. Pin DescriptionPermanently Dedicated Pins

VCC I IEight or more (depending on package) connections to the nominal +5 V supply voltage(+3.3 V for low-voltage devices). All must be connected, and each must be decoupledwith a 0.01 - 0.1 µF capacitor to Ground.

GND I IEight or more (depending on package type) connections to Ground. All must be con-nected.

CCLK I or O I

During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheralmode. After configuration, CCLK has a weak pull-up resistor and can be selected as theReadback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-vices, except during Readback. See “Violating the Maximum High and Low Time Spec-ification for the Readback Clock” on page 56 for an explanation of this exception.

DONE I/O O

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, itindicates the completion of the configuration process. As an input, a Low level on DONEcan be configured to delay the global logic initialization and the enabling of outputs.The optional pull-up resistor is selected as an option in the XACTstep program that cre-ates the configuration bitstream. The resistor is included by default.

PROGRAM I I

PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGAfinishes the current clear cycle and executes another complete clear cycle, before itgoes into a WAIT state and releases INIT.The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulledup to Vcc.

User I/O Pins That Can Have Special Functions

RDY/BUSY O I/O

During Peripheral mode configuration, this pin indicates when it is appropriate to writeanother byte of data into the FPGA. The same status is also available on D7 in Asyn-chronous Peripheral mode, if a read operation is performed when the device is selected.After configuration, RDY/BUSY is a user-programmable I/O pin.RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.

RCLK O I/O

During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 forXC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK isuseful for clocked PROMs. It is rarely used during configuration. After configuration,RCLK is a user-programmable I/O pin.

M0, M1, M2 II (M0),O (M1),I (M2)

As Mode inputs, these pins are sampled after INIT goes High to determine the configu-ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1can be used as a 3-state output. These three pins have no associated input or outputregisters.During configuration, these pins have weak pull-up resistors. For the most popular con-figuration mode, Slave Serial, the mode pins can thus be left unconnected. The threemode inputs can be individually configured with or without weak pull-up or pull-down re-sistors. A pull-down resistor value of 4.7 kΩ is recommended.These pins can only be used as inputs or outputs when called out by special schematicdefinitions. To use these pins, place the library components MD0, MD1, and MD2 in-stead of the usual pad symbols. Input or output buffers must still be used.

TDO O O

If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,this pin is a 3-state output without a register, after configuration is completed.This pin can be user output only when called out by special schematic definitions. Touse this pin, place the library component TDO instead of the usual pad symbol. An out-put buffer must still be used.

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TDI, TCK,TMS

II/Oor I

(JTAG)

If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Selectinputs respectively. They come directly from the pads, bypassing the IOBs. These pinscan also be used as inputs to the CLB logic after configuration is completed.If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-ited once configuration is completed, and these pins become user-programmable I/O.In this case, they must be called out by special schematic definitions. To use these pins,place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-put or output buffers must still be used.

HDC O I/OHigh During Configuration (HDC) is driven High until the I/O go active. It is available asa control output indicating that configuration is not yet completed. After configuration,HDC is a user-programmable I/O pin.

LDC O I/OLow During Configuration (LDC) is driven Low until the I/O go active. It is available as acontrol output indicating that configuration is not yet completed. After configuration,LDC is a user-programmable I/O pin.

INIT I/O I/O

Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ externalpull-up resistor is recommended.As an active-Low open-drain output, INIT is held Low during the power stabilization andinternal clearing of the configuration memory. As an active-Low input, it can be usedto hold the FPGA in the internal WAIT state before the start of configuration. Mastermode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.During configuration, a Low on this output indicates that a configuration data error hasoccurred. After the I/O go active, INIT is a user-programmable I/O pin.

PGCK1 -PGCK4

(XC4000Eonly)

WeakPull-up

I or I/O

Four Primary Global inputs each drive a dedicated internal global net with short delayand minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-grammable I/O.The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbolconnected directly to the input of a BUFGP symbol is automatically placed on one ofthese pins.

SGCK1 -SGCK4

(XC4000Eonly)

WeakPull-up

I or I/O

Four Secondary Global inputs each drive a dedicated internal global net with short delayand minimal skew. These internal global nets can also be driven from internal logic. Ifnot used to drive a global net, any of these pins is a user-programmable I/O pin.The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-matically placed on one of these pins.

GCK1 -GCK8

(XC4000Xonly)

WeakPull-up

I or I/O

Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-bal Early buffer. Each pair of global buffers can also be driven from internal logic, butmust share an input signal. If not used to drive a global buffer, any of these pins is auser-programmable I/O.Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbolis automatically placed on one of these pins.

FCLK1 -FCLK4

(XC4000XLAand

XC4000XVonly)

WeakPull-up

I or I/O

Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signalto any IOB clock input in the octant of the die served by the Fast Clock buffer. Two FastClock buffers serve the two IOB octants on the left side of the die and the other two FastClock buffers serve the two IOB octants on the right side of the die. On each side of thedie, one Fast Clock buffer serves the upper octant and the other serves the lower octant.If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.

Table 16: Pin Descriptions (Continued)

Pin Name

I/ODuringConfig.

I/OAfter

Config. Pin Description

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Boundary ScanThe ‘bed of nails’ has been the traditional method of testingelectronic assemblies. This approach has become lessappropriate, due to closer pin spacing and more sophisti-cated assembly methods like surface-mount technologyand multi-layer boards. The IEEE Boundary Scan Standard1149.1 was developed to facilitate board-level testing ofelectronic assemblies. Design and test engineers canimbed a standard test logic structure in their device toachieve high fault coverage for I/O and internal logic. Thisstructure is easily implemented with a four-pin interface onany boundary scan-compatible IC. IEEE 1149.1-compati-ble devices may be serial daisy-chained together, con-nected in parallel, or a combination of the two.

The XC4000 Series implements IEEE 1149.1-compatibleBYPASS, PRELOAD/SAMPLE and EXTEST boundaryscan instructions. When the boundary scan configurationoption is selected, three normal user I/O pins become ded-icated inputs for these functions. Another user output pinbecomes the dedicated boundary scan output. The details

of how to enable this circuitry are covered later in this sec-tion.

By exercising these input signals, the user can serially loadcommands and data into these devices to control the driv-ing of their outputs and to examine their inputs. Thismethod is an improvement over bed-of-nails testing. Itavoids the need to over-drive device outputs, and it reducesthe user interface to four pins. An optional fifth pin, a resetfor the control logic, is described in the standard but is notimplemented in Xilinx devices.

The dedicated on-chip logic implementing the IEEE 1149.1functions includes a 16-state machine, an instruction regis-ter and a number of data registers. The functional detailscan be found in the IEEE 1149.1 specification and are alsodiscussed in the Xilinx application note XAPP 017: “Bound-ary Scan in XC4000 Devices.”

Figure 40 on page 43 shows a simplified block diagram ofthe XC4000E Input/Output Block with boundary scanimplemented. XC4000X boundary scan logic is identical.

CS0, CS1,WS, RS

I I/O

These four inputs are used in Asynchronous Peripheral mode. The chip is selectedwhen CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Lowon Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —and drives D0 - D6 High.In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.WS and RS should be mutually exclusive, but if both are Low simultaneously, the WriteStrobe overrides. After configuration, these are user-programmable I/O pins.

A0 - A17 O I/ODuring Master Parallel configuration, these 18 output pins address the configurationEPROM. After configuration, they are user-programmable I/O pins.

A18 - A21(XC4003XL to

XC4085XL)O I/O

During Master Parallel configuration with an XC4000X master, these 4 output pins add4 more bits to address the configuration EPROM. After configuration, they are user-pro-grammable I/O pins. (See Master Parallel Configuration section for additional details.)

D0 - D7 I I/ODuring Master Parallel and Peripheral configuration, these eight input pins receive con-figuration data. After configuration, they are user-programmable I/O pins.

DIN I I/ODuring Slave Serial or Master Serial configuration, DIN is the serial configuration datainput receiving data on the rising edge of CCLK. During Parallel configuration, DIN isthe D0 input. After configuration, DIN is a user-programmable I/O pin.

DOUT O I/O

During configuration in any mode but Express mode, DOUT is the serial configurationdata output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changeson the falling edge of CCLK, one-and-a-half CCLK periods after it was received at theDIN input.In Express modefor XC4000E and XC4000X only, DOUT is the status output that candrive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.After configuration, DOUT is a user-programmable I/O pin.

Unrestricted User-Programmable I/O Pins

I/OWeakPull-up

I/OThese pins can be configured to be input and/or output after configuration is completed.Before configuration is completed, these pins have an internal high-value pull-up resis-tor (25 kΩ - 100 kΩ) that defines the logic level as High.

Table 16: Pin Descriptions (Continued)

Pin Name

I/ODuringConfig.

I/OAfter

Config. Pin Description

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Figure 41 on page 44 is a diagram of the XC4000 Seriesboundary scan logic. It includes three bits of Data Registerper IOB, the IEEE 1149.1 Test Access Port controller, andthe Instruction Register with decodes.

XC4000 Series devices can also be configured through theboundary scan logic. See “Readback” on page 55.

Data RegistersThe primary data register is the boundary scan register. Foreach IOB pin in the FPGA, bonded or not, it includes threebits for In, Out and 3-State Control. Non-IOB pins haveappropriate partial bit population for In or Out only. PRO-GRAM, CCLK and DONE are not included in the boundaryscan register. Each EXTEST CAPTURE-DR state capturesall In, Out, and 3-state pins.

The data register also includes the following non-pin bits:TDO.T, and TDO.O, which are always bits 0 and 1 of the

data register, respectively, and BSCANT.UPD, which isalways the last bit of the data register. These three bound-ary scan bits are special-purpose Xilinx test signals.

The other standard data register is the single flip-flopBYPASS register. It synchronizes data being passedthrough the FPGA to the next downstream boundary scandevice.

The FPGA provides two additional data registers that canbe specified using the BSCAN macro. The FPGA providestwo user pins (BSCAN.SEL1 and BSCAN.SEL2) which arethe decodes of two user instructions. For these instructions,two corresponding pins (BSCAN.TDO1 andBSCAN.TDO2) allow user scan data to be shifted out onTDO. The data register clock (BSCAN.DRCK) is availablefor control of test logic which the user may wish to imple-ment with CLBs. The NAND of TCK and RUN-TEST-IDLEis also provided (BSCAN.IDLE).

Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).XC4000X Boundary Scan Logic is Identical.

D

EC

Q

M

M

QL

rd

M

DELAY

M M

M M

Input Clock IK

I - capture

I - update

GLOBAL S/R

FLIP-FLOP/LATCH

INVERT

S/R

Input Data 1 I1

Input Data 2 I2

X5792

PAD

VCC

SLEW RATE

PULL UP

M

OUT SEL

D

EC

Q

rd

M

M

M

INVERT OUTPUT

M

M

INVERT

S/R

Ouput Clock OK

Clock Enable

Ouput Data O

O - update

Q - captureO - capture

Boundary Scan

MEXTEST

TS - update

TS - capture

3-State TS

sd

sd

TS INV

OUTPUT

TS/OE

PULL DOWN

INPUT

Boundary Scan

Boundary Scan

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Instruction SetThe XC4000 Series boundary scan instruction set alsoincludes instructions to configure the device and read backthe configuration data. The instruction set is coded asshown in Table 17.

Bit SequenceThe bit sequence within each IOB is: In, Out, 3-State. Theinput-only M0 and M2 mode pins contribute only the In bitto the boundary scan I/O data register, while the out-put-only M1 pin contributes all three bits.

The first two bits in the I/O data register are TDO.T andTDO.O, which can be used for the capture of internal sig-nals. The final bit is BSCANT.UPD, which can be used todrive an internal net. These locations are primarily used byXilinx for internal testing.

From a cavity-up view of the chip (as shown in XDE orEpic), starting in the upper right chip corner, the boundaryscan data-register bits are ordered as shown in Figure 42.The device-specific pinout tables for the XC4000 Seriesinclude the boundary scan locations for each IOB pin.

BSDL (Boundary Scan Description Language) files forXC4000 Series devices are available on the Xilinx FTP site.

Including Boundary Scan in a SchematicIf boundary scan is only to be used during configuration, nospecial schematic elements need be included in the sche-matic or HDL code. In this case, the special boundary scanpins TDI, TMS, TCK and TDO can be used for user func-tions after configuration.

To indicate that boundary scan remain enabled after config-uration, place the BSCAN library symbol and connect theTDI, TMS, TCK and TDO pad symbols to the appropriatepins, as shown in Figure 43.

Even if the boundary scan symbol is used in a schematic,the input pins TMS, TCK, and TDI can still be used asinputs to be routed to internal logic. Care must be taken notto force the chip into an undesired boundary scan state byinadvertently applying boundary scan input patterns tothese pins. The simplest way to prevent this is to keep TMSHigh, and then apply whatever signal is desired to TDI andTCK.

D Q

D Q

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

M U X

BYPASS REGISTER

IOB IOB

TDO

TDI

IOB IOB IOB

1

0

1

0

1

0

1

0

1

0

sd

LE

D Q

D Q

D Q

1

0

1

0

1

0

1

0

D Q

LE

sd

sd

LE

D Q

sd

LE

D Q

IOB

D Q1

0D Q

LE

sd

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/ CAPTURE

CLOCK DATA REGISTER

DATAOUT UPDATE EXTEST

X9016

INSTRUCTION REGISTER

Figure 41: XC4000 Series Boundary Scan Logic

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Table 17: Boundary Scan Instructions

Avoiding Inadvertent Boundary ScanIf TMS or TCK is used as user I/O, care must be taken toensure that at least one of these pins is held constant dur-ing configuration. In some applications, a situation mayoccur where TMS or TCK is driven during configuration.This may cause the device to go into boundary scan modeand disrupt the configuration process.

To prevent activation of boundary scan during configura-tion, do either of the following:

• TMS: Tie High to put the Test Access Port controllerin a benign RESET state

• TCK: Tie High or Low—don't toggle this clock input.

For more information regarding boundary scan, refer to theXilinx Application Note XAPP 017.001, “Boundary Scan inXC4000E Devices.“

ConfigurationConfiguration is the process of loading design-specific pro-gramming data into one or more FPGAs to define the func-tional operation of the internal blocks and theirinterconnections. This is somewhat like loading the com-mand registers of a programmable peripheral chip. XC4000Series devices use several hundred bits of configurationdata per CLB and its associated interconnects. Each con-figuration bit defines the state of a static memory cell thatcontrols either a function look-up table bit, a multiplexerinput, or an interconnect pass transistor. The XACTstepdevelopment system translates the design into a netlist file.It automatically partitions, places and routes the logic andgenerates the configuration data in PROM format.

Special Purpose PinsThree configuration mode pins (M2, M1, M0) are sampledprior to configuration to determine the configuration mode.After configuration, these pins can be used as auxiliaryconnections. M2 and M0 can be used as inputs, and M1can be used as an output. The XACTstep development sys-tem does not use these resources unless they are explicitlyspecified in the design entry. This is done by placing a spe-cial pad symbol called MD2, MD1, or MD0 instead of theinput or output pad symbol.

In XC4000 Series devices, the mode pins have weakpull-up resistors during configuration. With all three modepins High, Slave Serial mode is selected, which is the mostpopular configuration mode. Therefore, for the most com-mon configuration mode, the mode pins can be left uncon-nected. (Note, however, that the internal pull-up resistorvalue can be as high as 100 kΩ.) After configuration, thesepins can individually have weak pull-up or pull-down resis-tors, as specified in the design. A pull-down resistor valueof 4.7 kΩ is recommended.

These pins are located in the lower left chip corner and arenear the readback nets. This location allows convenientrouting if compatibility with the XC2000 and XC3000 familyconventions of M0/RT, M1/RD is desired.

Instruction I2I1 I0

TestSelected

TDO SourceI/O DataSource

0 0 0 EXTEST DR DR0 0 1 SAMPLE/PR

ELOADDR Pin/Logic

0 1 0 USER 1 BSCAN.TDO1

User Logic

0 1 1 USER 2 BSCAN.TDO2

User Logic

1 0 0 READBACK ReadbackData

Pin/Logic

1 0 1 CONFIGURE DOUT Disabled1 1 0 Reserved — —1 1 1 BYPASS Bypass

Register—

Bit 0 ( TDO end) Bit 1 Bit 2

TDO.T TDO.O Top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Bottom-edge IOBs (Left to Right) Right-edge IOBs (Bottom to Top) B SCANT.UPD(TDI end)

X6075

Figure 42: Boundary Scan Bit Sequence

TDI TMS TCK TDO1 TDO2

TDO

DRCK

IDLE

SEL1

SEL2

TDI

TMS

TCK

TDO

BSCAN

To User Logic

IBUF

Optional

From User Logic

To User Logic

X2675

Figure 43: Boundary Scan Schematic Example

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Configuration ModesXC4000E devices have six configuration modes. XC4000Xdevices have the same six modes, plus an additional con-figuration mode. These modes are selected by a 3-bit inputcode applied to the M2, M1, and M0 inputs. There are threeself-loading Master modes, two Peripheral modes, and aSerial Slave mode, which is used primarily fordaisy-chained devices. The coding for mode selection isshown in Table 18.

A detailed description of each configuration mode, with tim-ing information, is included later in this data sheet. Duringconfiguration, some of the I/O pins are used temporarily forthe configuration process. All pins used during configura-tion are shown in Table 22 on page 58.

Master Modes

The three Master modes use an internal oscillator to gener-ate a Configuration Clock (CCLK) for driving potential slavedevices. They also generate address and timing for exter-nal PROM(s) containing the configuration data.

Master Parallel (Up or Down) modes generate the CCLKsignal and PROM addresses and receive byte parallel data.The data is internally serialized into the FPGA data-frameformat. The up and down selection generates startingaddresses at either zero or 3FFFF (3FFFFF when 22address lines are used), for compatibility with differentmicroprocessor addressing conventions. The Master Serialmode generates CCLK and receives the configuration datain serial form from a Xilinx serial-configuration PROM.

CCLK speed is selectable as either 1 MHz (default) or 8MHz. Configuration always starts at the default slow fre-quency, then can switch to the higher frequency during thefirst frame. Frequency tolerance is -50% to +25%.

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines(A18-A21) allowing the additional address space requiredto daisy-chain several large devices.

The extra address lines are programmable in XC4000EXdevices. By default these address lines are not activated. Inthe default mode, the devices are compatible with existingXC4000 and XC4000E products. If desired, the extraaddress lines can be used by specifying the address linesoption in bitgen as 22 (bitgen -g AddressLines:22). Thelines (A18-A21) are driven when a master device detects,via the bitstream, that it should be using all 22 addresslines. Because these pins will initially be pulled high byinternal pull-ups, designers using Master Parallel Up modeshould use external pull down resistors on pins A18-A21. IfMaster Parallel Down mode is used external resistors arenot necessary.

All 22 address lines are always active in Master Parallelmodes with XC4000XL devices. The additional addresslines behave identically to the lower order address lines. Ifthe Address Lines option in bitgen is set to 18, it will beignored by the XC4000XL device.

The additional address lines (A18-A21) are not available inthe PC84 package.

Peripheral Modes

The two Peripheral modes accept byte-wide data from abus. A RDY/BUSY status is available as a handshake sig-nal. In Asynchronous Peripheral mode, the internal oscilla-tor generates a CCLK burst signal that serializes thebyte-wide data. CCLK can also drive slave devices. In thesynchronous mode, an externally supplied clock input toCCLK serializes the data.

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial configura-tion data on the rising edge of CCLK and, after loading itsconfiguration, passes additional data out, resynchronizedon the next falling edge of CCLK.

Multiple slave devices with identical configurations can bewired with parallel DIN inputs. In this way, multiple devicescan be configured simultaneously.

Serial Daisy Chain

Multiple devices with different configurations can be con-nected together in a “daisy chain,” and a single combinedbitstream used to configure the chain of slave devices.

To configure a daisy chain of devices, wire the CCLK pinsof all devices in parallel, as shown in Figure 51 on page60. Connect the DOUT of each device to the DIN of thenext. The lead or master FPGA and following slaves eachpasses resynchronized configuration data coming from asingle source. The header data, including the length count,

Table 18: Configuration Modes

Mode M2 M1 M0 CCLK DataMaster Serial 0 0 0 output Bit-SerialSlave Serial 1 1 1 input Bit-SerialMasterParallel Up

1 0 0 output Byte-Wide,increment

from 00000MasterParallel Down

1 1 0 output Byte-Wide,decrement

from 3FFFFPeripheralSynchronous*

0 1 1 input Byte-Wide

PeripheralAsynchronous

1 0 1 output Byte-Wide

Reserved 0 1 0 — —Reserved 0 0 1 — —* Can be considered byte-wide Slave Parallel

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is passed through and is captured by each FPGA when itrecognizes the 0010 preamble. Following the length-countdata, each FPGA outputs a High on DOUT until it hasreceived its required number of data frames.

After an FPGA has received its configuration data, itpasses on any additional frame start bits and configurationdata on DOUT. When the total number of configurationclocks applied after memory initialization equals the valueof the 24-bit length count, the FPGAs begin the start-upsequence and become operational together. FPGA I/O arenormally released two CCLK cycles after the last configura-tion bit is received. Figure 47 on page 53 shows thestart-up timing for an XC4000 Series device.

The daisy-chained bitstream is not simply a concatenationof the individual bitstreams. The PROM file formatter mustbe used to combine the bitstreams for a daisy-chained con-figuration.

Multi-Family Daisy Chain

All Xilinx FPGAs of the XC2000, XC3000, and XC4000Series use a compatible bitstream format and can, there-fore, be connected in a daisy chain in an arbitrarysequence. There is, however, one limitation. The leaddevice must belong to the highest family in the chain. If thechain contains XC4000 Series devices, the master nor-mally cannot be an XC2000 or XC3000 device.

The reason for this rule is shown in Figure 47 on page 53.Since all devices in the chain store the same length countvalue and generate or receive one common sequence ofCCLK pulses, they all recognize length-count match on thesame CCLK edge, as indicated on the left edge ofFigure 47. The master device then generates additionalCCLK pulses until it reaches its finish point F. The differentfamilies generate or require different numbers of additionalCCLK pulses until they reach F. Not reaching F means thatthe device does not really finish its configuration, althoughDONE may have gone High, the outputs became active,and the internal reset was released. For the XC4000 Seriesdevice, not reaching F means that readback cannot be ini-

tiated and most boundary scan instructions cannot beused.

The user has some control over the relative timing of theseevents and can, therefore, make sure that they occur at theproper time and the finish point F is reached. Timing is con-trolled using options in the bitstream generation software.

XC3000 Master with an XC4000 Series Slave

Some designers want to use an inexpensive lead device inperipheral mode and have the more precious I/O pins of theXC4000 Series devices all available for user I/O. Figure 44provides a solution for that case.

This solution requires one CLB, one IOB and pin, and aninternal oscillator with a frequency of up to 5 MHz as aclock source. The XC3000 master device must be config-ured with late Internal Reset, which is the default option.

One CLB and one IOB in the lead XC3000-family deviceare used to generate the additional CCLK pulse required bythe XC4000 Series devices. When the lead device removesthe internal RESET signal, the 2-bit shift register respondsto its clock input and generates an active Low output signalfor the duration of the subsequent clock period. An externalconnection between this output and CCLK thus creates theextra CCLK pulse.

Output Connected to CCLK

OE/T

0 1 1 0 0 . .

0 0 1 1 1 . .

Reset

X5223etc

Active Low Output Active High Output

Figure 44: CCLK Generation for XC3000 MasterDriving an XC4000 Series Slave

May 14, 1999 (Version 1.6) 6-47

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Setting CCLK FrequencyFor Master modes, CCLK can be generated in either of twofrequencies. In the default slow mode, the frequencyranges from 0.5 MHz to 1.25 MHz for XC4000E andXC4000EX devices and from 0.6 MHz to 1.8 MHz forXC4000XL devices. In fast CCLK mode, the frequencyranges from 4 MHz to 10 MHz for XC4000EX devices andfrom 5 MHz to 15 MHz for XC4000XL devices. The fre-quency is selected by an option when running the bitstreamgeneration software. If an XC4000 Series Master is drivingan XC3000- or XC2000-family slave, slow CCLK modemust be used. In addition, an XC4000XL device driving aXC4000E or XC4000EX should use slow mode. Slow modeis the default.

Table 19: XC4000 Series Data Stream Formats

Data Stream FormatThe data stream (“bitstream”) format is identical for all con-figuration modes.

The data stream formats are shown in Table 19. Bit-serialdata is read from left to right, and byte-parallel data is effec-tively assembled from this serial bitstream, with the first bitin each byte assigned to D0.

The configuration data stream begins with a string of eightones, a preamble code, followed by a 24-bit length countand a separator field of ones. This header is followed by theactual configuration data in frames. The length and numberof frames depends on the device type (see Table 20 andTable 21). Each frame begins with a start field and endswith an error check. A postamble code is required to signalthe end of data for a single device. In all cases, additionalstart-up bytes of data are required to provide four clocks forthe startup sequence at the end of configuration. Longdaisy chains require additional startup bytes to shift the lastdata through the chain. All startup bytes are don’t-cares;these bytes are not included in bitstreams created by theXilinx software.

A selection of CRC or non-CRC error checking is allowedby the bitstream generation software. The non-CRC errorchecking tests for a designated end-of-frame field for eachframe. For CRC error checking, the software calculates arunning CRC and inserts a unique four-bit partial check atthe end of each frame. The 11-bit CRC check of the lastframe of an FPGA includes the last seven data bits.

Detection of an error results in the suspension of data load-ing and the pulling down of the INIT pin. In Master modes,CCLK and address signals continue to operate externally.The user must detect INIT and initialize a new configurationby pulsing the PROGRAM pin Low or cycling Vcc.

Data TypeAll Other

Modes (D0...)Fill Byte 11111111bPreamble Code 0010bLength Count COUNT(23:0)Fill Bits 1111bStart Field 0bData Frame DATA(n-1:0)CRC or ConstantField Check

xxxx (CRC)or 0110b

Extend Write Cycle —Postamble 01111111bStart-Up Bytes xxhLegend:Not shaded Once per bitstreamLight Once per data frameDark Once per device

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Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bitsNumber of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1Program Data = (Bits per Frame x Number of Frames) + 8 postamble bitsPROM Size = Program Data + 40 (header) + 8

2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end ofany frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”bits, even for extra leading ones at the beginning of the header.

Cyclic Redundancy Check (CRC) forConfiguration and ReadbackThe Cyclic Redundancy Check is a method of error detec-tion in data transmission applications. Generally, the trans-mitting system performs a calculation on the serialbitstream. The result of this calculation is tagged onto thedata stream as additional check bits. The receiving systemperforms an identical calculation on the bitstream and com-pares the result with the received checksum.

Each data frame of the configuration bitstream has fourerror bits at the end, as shown in Table 19. If a frame dataerror is detected during the loading of the FPGA, the con-

figuration process with a potentially corrupted bitstream isterminated. The FPGA pulls the INIT pin Low and goes intoa Wait state.

During Readback, 11 bits of the 16-bit checksum are addedto the end of the Readback data stream. The checksum iscomputed using the CRC-16 CCITT polynomial, as shownin Figure 45. The checksum consists of the 11 most signif-icant bits of the 16-bit code. A change in the checksum indi-cates a change in the Readback bitstream. A comparisonto a previous checksum is meaningful only if the readbackdata is independent of the current device state. CLB out-puts should not be included (Read Capture option not

Table 20: XC4000E Program Data

Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025EMax Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000CLBs(Row x Col.)

100(10 x 10)

196(14 x 14)

256(16 x 16)

324(18 x 18)

400(20 x 20)

576(24 x 24)

784(28 x 28)

1,024(32 x 32)

IOBs 80 112 128 144 160 192 224 256Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560Bits per Frame 126 166 186 206 226 266 306 346Frames 428 572 644 716 788 932 1,076 1,220Program Data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128PROM Size(bits)

53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176

Table 21: XC4000EX/XL Program Data

Device XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044 XC4052 XC4062 XC4085

Max LogicGates

2,000 5,000 10,000 13,000 20,000 28,000 36,000 44,000 52,000 62,000 85,000

CLBs(Row xColumn)

64(8 x 8)

196(14 x 14)

400(20 x 20)

576(24 x 24)

784(28 x 28)

1,024(32 x 32)

1,296(36 x 36)

1,600(40 x 40)

1,936(44 x 44)

2,304(48 x 48)

3,136(56 x 56)

IOBs 64 112 160 192 224 256 288 320 352 384 448

Flip-Flops 256 616 1,120 1,536 2,016 2,560 3,168 3,840 4,576 5,376 7,168

Bits perFrame

133 205 277 325 373 421 469 517 565 613 709

Frames 459 741 1,023 1,211 1,399 1,587 1,775 1,963 2,151 2,339 2,715

Program Data 61,052 151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940

PROM Size(bits)

61,104 151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992

Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.

Program data = (bits per frame x number of frames) + 5 postamble bits. PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end

of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”bits, even for extra leading “ones” at the beginning of the header.

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used), and if RAM is present, the RAM content must beunchanged.

Statistically, one error out of 2048 might go undetected.

Configuration SequenceThere are four major steps in the XC4000 Series power-upconfiguration sequence.

• Configuration Memory Clear• Initialization• Configuration• Start-Up

The full process is illustrated in Figure 46.

Configuration Memory Clear

When power is first applied or is reapplied to an FPGA, aninternal circuit forces initialization of the configuration logic.When Vcc reaches an operational level, and the circuitpasses the write and read test of a sample pair of configu-ration bits, a time delay is started. This time delay is nomi-nally 16 ms, and up to 10% longer in the low-voltagedevices. The delay is four times as long when in MasterModes (M0 Low), to allow ample time for all slaves to reacha stable Vcc. When all INIT pins are tied together, as rec-ommended, the longest delay takes precedence. There-fore, devices with different time delays can easily be mixedand matched in a daisy chain.

This delay is applied only on power-up. It is not appliedwhen re-configuring an FPGA by pulsing the PROGRAMpin

0

X2

2 3 4 5 6 7 8 9 10 11 12 13 141

X15X16

15

SERIAL DATA IN

1 0 15 14 13 12 11 10 9 8 7 6 51111

CRC – CHECKSUMLAST DATA FRAME

ST

AR

T B

IT

X1789

Polynomial: X16 + X15 + X2 + 1

Readback Data Stream

Figure 45: Circuit for Generating CRC-16

INIT High? if Master

Sample Mode Lines

Load One Configuration Data Frame

Frame Error

Pass Configuration

Data to DOUT

VCC >3.5 V

No

Yes

Yes

No

No

Yes

Operational

Start-Up Sequence

No

Yes

~1.3 µs per Frame

Master Waits 50 to 250 µs Before Sampling Mode Lines

Master CCLK Goes Active

F

Pull INIT Low and Stop

X6076

EXTEST* SAMPLE/PRELOAD

BYPASS CONFIGURE*

(* if PROGRAM = High)

SAMPLE/PRELOAD BYPASS

EXTEST SAMPLE PRELOAD

BYPASS USER 1 USER 2

CONFIGURE READBACK

If Boundary Scan is Selected

Config- uration memory

Full

CCLK Count Equals

Length Count

Completely Clear Configuration Memory

Once More

LDC

Out

put =

L, H

DC

Out

put =

H

Boundary Scan Instructions Available:

I/O A

ctiv

e

Keep Clearing Configuration Memory

Test M0 Generate One Time-Out Pulse

of 16 or 64 ms

PROGRAM = Low

No

Yes

Yes

Figure 46: Power-up Configuration Sequence

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Low. During this time delay, or as long as the PROGRAMinput is asserted, the configuration logic is held in a Config-uration Memory Clear state. The configuration-memoryframes are consecutively initialized, using the internal oscil-lator.

At the end of each complete pass through the frameaddressing, the power-on time-out delay circuitry and thelevel of the PROGRAM pin are tested. If neither is asserted,the logic initiates one additional clearing of the configura-tion frames and then tests the INIT input.

Initialization

During initialization and configuration, user pins HDC, LDC,INIT and DONE provide status outputs for the system inter-face. The outputs LDC, INIT and DONE are held Low andHDC is held High starting at the initial application of power.

The open drain INIT pin is released after the final initializa-tion pass through the frame addresses. There is a deliber-ate delay of 50 to 250 µs (up to 10% longer for low-voltagedevices) before a Master-mode device recognizes an inac-tive INIT. Two internal clocks after the INIT pin is recognizedas High, the FPGA samples the three mode lines to deter-mine the configuration mode. The appropriate interfacelines become active and the configuration preamble anddata can be loaded.Configuration

The 0010 preamble code indicates that the following 24 bitsrepresent the length count. The length count is the totalnumber of configuration clocks needed to load the com-plete configuration data. (Four additional configurationclocks are required to complete the configuration process,as discussed below.) After the preamble and the lengthcount have been passed through to all devices in the daisychain, DOUT is held High to prevent frame start bits fromreaching any daisy-chained devices.

A specific configuration bit, early in the first frame of a mas-ter device, controls the configuration-clock rate and canincrease it by a factor of eight. Therefore, if a fast configu-ration clock is selected by the bitstream, the slower clockrate is used until this configuration bit is detected.

Each frame has a start field followed by the frame-configu-ration data bits and a frame error field. If a frame data erroris detected, the FPGA halts loading, and signals the errorby pulling the open-drain INIT pin Low. After all configura-tion frames have been loaded into an FPGA, DOUT againfollows the input data so that the remaining data is passedon to the next device.

Delaying Configuration After Power-Up

There are two methods of delaying configuration afterpower-up: put a logic Low on the PROGRAM input, or pullthe bidirectional INIT pin Low, using an open-collector(open-drain) driver. (See Figure 46 on page 50.)

A Low on the PROGRAM input is the more radicalapproach, and is recommended when the power-supply

rise time is excessive or poorly defined. As long as PRO-GRAM is Low, the FPGA keeps clearing its configurationmemory. When PROGRAM goes High, the configurationmemory is cleared one more time, followed by the begin-ning of configuration, provided the INIT input is not exter-nally held Low. Note that a Low on the PROGRAM inputautomatically forces a Low on the INIT output. The XC4000Series PROGRAM pin has a permanent weak pull-up.

Using an open-collector or open-drain driver to hold INITLow before the beginning of configuration causes theFPGA to wait after completing the configuration memoryclear operation. When INIT is no longer held Low exter-nally, the device determines its configuration mode by cap-turing its mode pins, and is ready to start the configurationprocess. A master device waits up to an additional 250 µsto make sure that any slaves in the optional daisy chainhave seen that INIT is High.

Start-Up

Start-up is the transition from the configuration process tothe intended user operation. This transition involves achange from one clock source to another, and a changefrom interfacing parallel or serial configuration data wheremost outputs are 3-stated, to normal operation with I/O pinsactive in the user-system. Start-up must make sure that theuser-logic ‘wakes up’ gracefully, that the outputs becomeactive without causing contention with the configuration sig-nals, and that the internal flip-flops are released from theglobal Reset or Set at the right time.

Figure 47 describes start-up timing for the three Xilinx fam-ilies in detail. The configuration modes can use any of thefour timing sequences.

To access the internal start-up signals, place the STARTUPlibrary symbol.

Start-up Timing

Different FPGA families have different start-up sequences.

The XC2000 family goes through a fixed sequence. DONEgoes High and the internal global Reset is de-activated oneCCLK period after the I/O become active.

The XC3000A family offers some flexibility. DONE can beprogrammed to go High one CCLK period before or afterthe I/O become active. Independent of DONE, the internalglobal Reset is de-activated one CCLK period before orafter the I/O become active.

The XC4000 Series offers additional flexibility. The threeevents — DONE going High, the internal Set/Reset beingde-activated, and the user I/O going active — can all occurin any arbitrary sequence. Each of them can occur oneCCLK period before or after, or simultaneous with, any ofthe others. This relative timing is selected by means of soft-ware options in the bitstream generation software.

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The default option, and the most practical one, is for DONEto go High first, disconnecting the configuration data sourceand avoiding any contention when the I/Os become activeone clock later. Reset/Set is then released another clockperiod later to make sure that user-operation starts fromstable internal conditions. This is the most commonsequence, shown with heavy lines in Figure 47, but thedesigner can modify it to meet particular requirements.

Normally, the start-up sequence is controlled by the internaldevice oscillator output (CCLK), which is asynchronous tothe system clock.

XC4000 Series offers another start-up clocking option,UCLK_NOSYNC. The three events described above neednot be triggered by CCLK. They can, as a configurationoption, be triggered by a user clock. This means that thedevice can wake up in synchronism with the user system.

When the UCLK_SYNC option is enabled, the user canexternally hold the open-drain DONE output Low, and thusstall all further progress in the start-up sequence untilDONE is released and has gone High. This option can beused to force synchronization of several FPGAs to a com-mon user clock, or to guarantee that all devices are suc-cessfully configured before any I/Os go active.

If either of these two options is selected, and no user clockis specified in the design or attached to the device, the chipcould reach a point where the configuration of the device iscomplete and the Done pin is asserted, but the outputs donot become active. The solution is either to recreate the bit-stream specifying the start-up clock as CCLK, or to supplythe appropriate user clock.

Start-up Sequence

The Start-up sequence begins when the configurationmemory is full, and the total number of configuration clocks

received since INIT went High equals the loaded value ofthe length count.

The next rising clock edge sets a flip-flop Q0, shown inFigure 48. Q0 is the leading bit of a 5-bit shift register. Theoutputs of this register can be programmed to control threeevents.

• The release of the open-drain DONE output• The change of configuration-related pins to the user

function, activating all IOBs.• The termination of the global Set/Reset initialization of

all CLB and IOB storage elements.

The DONE pin can also be wire-ANDed with DONE pins ofother FPGAs or with other external signals, and can thenbe used as input to bit Q3 of the start-up register. This iscalled “Start-up Timing Synchronous to Done In” and isselected by either CCLK_SYNC or UCLK_SYNC.

When DONE is not used as an input, the operation is called“Start-up Timing Not Synchronous to DONE In,” and isselected by either CCLK_NOSYNC or UCLK_NOSYNC.

As a configuration option, the start-up control registerbeyond Q0 can be clocked either by subsequent CCLKpulses or from an on-chip user net called STARTUP.CLK.These signals can be accessed by placing the STARTUPlibrary symbol.

Start-up from CCLK

If CCLK is used to drive the start-up, Q0 through Q3 pro-vide the timing. Heavy lines in Figure 47 show the defaulttiming, which is compatible with XC2000 and XC3000devices using early DONE and late Reset. The thin linesindicate all other possible timing options.

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XC4000E/X UCLK_SYNC

XC4000E/X UCLK_NOSYNC

XC4000E/X CCLK_SYNC

XC4000E/X CCLK_NOSYNC

XC3000

XC2000

CCLK

GSR Active

UCLK Period

DONE IN

DONE IN

Di Di+1 Di+2

Di Di+1 Di+2

U2 U3 U4

U2 U3 U4

U2 U3 U4C1

Synchronization Uncertainty

Di Di+1

Di Di+1

DONE

I/O

GSR Active

DONE

I/O

GSR Active

DONE

C1 C2

C1 U2

C3 C4

C2 C3 C4

C2 C3 C4

I/O

GSR Active

DONE

I/O

DONE

Global Reset

I/O

DONE

Global Reset

I/O

F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing

CCLK PeriodLength Count Match

F

F

F

F

F

F

X9024

C1, C2 or C3

Figure 47: Start-up Timing

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Start-up from a User Clock (STARTUP.CLK)

When, instead of CCLK, a user-supplied start-up clock isselected, Q1 is used to bridge the unknown phase relation-ship between CCLK and the user clock. This arbitrationcauses an unavoidable one-cycle uncertainty in the timingof the rest of the start-up sequence.

DONE Goes High to Signal End of Configuration

XC4000 Series devices read the expected length countfrom the bitstream and store it in an internal register. Thelength count varies according to the number of devices andthe composition of the daisy chain. Each device also countsthe number of CCLKs during configuration.

Two conditions have to be met in order for the DONE pin togo high:

• the chip's internal memory must be full, and• the configuration length count must be met, exactly.

This is important because the counter that determineswhen the length count is met begins with the very firstCCLK, not the first one after the preamble.

Therefore, if a stray bit is inserted before the preamble, orthe data source is not ready at the time of the first CCLK,the internal counter that holds the number of CCLKs will beone ahead of the actual number of data bits read. At theend of configuration, the configuration memory will be full,but the number of bits in the internal counter will not matchthe expected length count.

As a consequence, a Master mode device will continue tosend out CCLKs until the internal counter turns over tozero, and then reaches the correct length count a secondtime. This will take several seconds [224 ∗ CCLK period] —which is sometimes interpreted as the device not configur-ing at all.

If it is not possible to have the data ready at the time of thefirst CCLK, the problem can be avoided by increasing thenumber in the length count by the appropriate value. TheXACT User Guide includes detailed information about man-ually altering the length count.

Note that DONE is an open-drain output and does not goHigh unless an internal pull-up is activated or an externalpull-up is attached. The internal pull-up is activated as thedefault by the bitstream generation software.

Release of User I/O After DONE Goes High

By default, the user I/O are released one CCLK cycle afterthe DONE pin goes High. If CCLK is not clocked afterDONE goes High, the outputs remain in their initial state —3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay fromDONE High to active user I/O is controlled by an option tothe bitstream generation software.

Release of Global Set/Reset After DONE GoesHigh

By default, Global Set/Reset (GSR) is released two CCLKcycles after the DONE pin goes High. If CCLK is notclocked twice after DONE goes High, all flip-flops are heldin their initial set or reset state. The delay from DONE Highto GSR inactive is controlled by an option to the bitstreamgeneration software.

Configuration Complete After DONE Goes High

Three full CCLK cycles are required after the DONE pingoes High, as shown in Figure 47 on page 53. If CCLK isnot clocked three times after DONE goes High, readbackcannot be initiated and most boundary scan instructionscannot be used.

Configuration Through the Boundary ScanPinsXC4000 Series devices can be configured through theboundary scan pins. The basic procedure is as follows:

• Power up the FPGA with INIT held Low (or drive thePROGRAM pin Low for more than 300 ns followed by aHigh while holding INIT Low). Holding INIT Low allowsenough time to issue the CONFIG command to theFPGA. The pin can be used as I/O after configuration ifa resistor is used to hold INIT Low.

• Issue the CONFIG command to the TMS input• Wait for INIT to go High• Sequence the boundary scan Test Access Port to the

SHIFT-DR state• Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INITgoes High, as all of these cycles affect the Length Countcompare.

For more detailed information, refer to the Xilinx applicationnote XAPP017, “Boundary Scan in XC4000 Devices.” Thisapplication note also applies to XC4000E and XC4000Xdevices.

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ReadbackThe user can read back the content of configuration mem-ory and the level of certain internal nodes without interfer-ing with the normal operation of the device.

Readback not only reports the downloaded configurationbits, but can also include the present state of the device,represented by the content of all flip-flops and latches inCLBs and IOBs, as well as the content of function genera-tors used as RAMs.

Note that in XC4000 Series devices, configuration data isnot inverted with respect to configuration as it is in XC2000and XC3000 families.

XC4000 Series Readback does not use any dedicatedpins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,RDBK.RIP and RDBK.CLK) that can be routed to any IOB.To access the internal Readback signals, place the READ-

BACK library symbol and attach the appropriate pad sym-bols, as shown in Figure 49.

After Readback has been initiated by a High level onRDBK.TRIG after configuration, the RDBK.RIP (Read InProgress) output goes High on the next rising edge ofRDBK.CLK. Subsequent rising edges of this clock shift outReadback data on the RDBK.DATA net.

Readback data does not include the preamble, but startswith five dummy bits (all High) followed by the Start bit(Low) of the first frame. The first two data bits of the firstframe are always High.

Each frame ends with four error check bits. They are readback as High. The last seven bits of the last frame are alsoread back as High. An additional Start bit (Low) and an11-bit Cyclic Redundancy Check (CRC) signature follow,before RDBK.RIP returns Low.

DONE

*

*

*

*

* *

Q S

R

1

0

0

1

1

0

1

0

1

0

0

1

GSR ENABLEGSR INVERTSTARTUP.GSR

STARTUP.GTSGTS INVERTGTS ENABLE

CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE)

GLOBAL SET/RESET OF ALL CLB AND IOB FLIP-FLOP

IOBs OPERATIONAL PER CONFIGURATION

GLOBAL 3-STATE OF ALL IOBs

Q2

Q3 Q1/Q4DONE IN

STARTUP

Q0 Q1 Q2 Q3 Q4

M

M

" FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR

K

S Q

K

D Q

K

D Q

K

D Q

K

D QFULL

LENGTH COUNT

CLEAR MEMORY

CCLK

STARTUP.CLK USER NET

CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"X1528

Figure 48: Start-up Logic

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Readback OptionsReadback options are: Read Capture, Read Abort, andClock Select. They are set with the bitstream generationsoftware.

Read Capture

When the Read Capture option is selected, the readbackdata stream includes sampled values of CLB and IOB sig-nals. The rising edge of RDBK.TRIG latches the invertedvalues of the four CLB outputs, the IOB output flip-flops andthe input signals I1 and I2. Note that while the bits describ-ing configuration (interconnect, function generators, andRAM content) are not inverted, the CLB and IOB output sig-nals are inverted.

When the Read Capture option is not selected, the valuesof the capture bits reflect the configuration data originallywritten to those memory locations.

If the RAM capability of the CLBs is used, RAM data areavailable in readback, since they directly overwrite the Fand G function-table configuration of the CLB.

RDBK.TRIG is located in the lower-left corner of the device,as shown in Figure 50.

Read Abort

When the Read Abort option is selected, a High-to-Lowtransition on RDBK.TRIG terminates the readback opera-tion and prepares the logic to accept another trigger.

After an aborted readback, additional clocks (up to onereadback clock per configuration frame) may be required tore-initialize the control logic. The status of readback is indi-cated by the output control net RDBK.RIP. RDBK.RIP isHigh whenever a readback is in progress.

Clock Select

CCLK is the default clock. However, the user can insertanother clock on RDBK.CLK. Readback control and dataare clocked on rising edges of RDBK.CLK. If readbackmust be inhibited for security reasons, the readback controlnets are simply not connected.

RDBK.CLK is located in the lower right chip corner, asshown in Figure 50.

Violating the Maximum High and Low TimeSpecification for the Readback ClockThe readback clock has a maximum High and Low timespecification. In some cases, this specification cannot bemet. For example, if a processor is controlling readback, aninterrupt may force it to stop in the middle of a readback.This necessitates stopping the clock, and thus violating thespecification.

The specification is mandatory only on clocking data at theend of a frame prior to the next start bit. The transfer mech-anism will load the data to a shift register during the last sixclock cycles of the frame, prior to the start bit of the follow-ing frame. This loading process is dynamic, and is thesource of the maximum High and Low time requirements.

Therefore, the specification only applies to the six clockcycles prior to and including any start bit, including theclocks before the first start bit in the readback data stream.At other times, the frame data is already in the register andthe register is not dynamic. Thus, it can be shifted out justlike a regular shift register.

The user must precisely calculate the location of the read-back data relative to the frame. The system must keep trackof the position within a data frame, and disable interruptsbefore frame boundaries. Frame lengths and data formatsare listed in Table 19, Table 20 and Table 21.

Readback with the XChecker CableThe XChecker Universal Download/Readback Cable andLogic Probe uses the readback feature for bitstream verifi-cation. It can also display selected internal signals on thePC or workstation screen, functioning as a low-cost in-cir-cuit emulator.

READBACK

DATA

RIPTRIG

CLK READ_DATA

OBUF

MD1

MD0READ_TRIGGER

IBUF X1786

IF UNCONNECTED, DEFAULT IS CCLK

Figure 49: Readback Schematic Example

I/O I/O I/Ordbk

PROGRAMMABLE INTERCONNECT

rdclk

I/O I/O

X1787

TR

IGD

AT

AR

IP I

Figure 50: READBACK Symbol in Graphical Editor

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XC4000E/EX/XL Program Readback Switching Characteristic GuidelinesTesting of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patternsthat are taken at device introduction, prior to any process improvements.

The following guidelines reflect worst-case values over the recommended operating conditions.

Note 1: Timing parameters apply to all speed grades.Note 2: If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.

Note 1: Timing parameters apply to all speed grades.Note 2: If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.

RTRCTRCRTT RCRTT

2 2

RCLT4

RCRRT6

RCHT 5

RCRDT7

DUMMY DUMMYrdbk.DATA

rdbk.RIP

rdclk.I

rdbk.TRIG

Finished Internal Net

VALID

X1790

VALID

1 RTRCT1

E/EXDescription Symbol Min Max Units

rdbk.TRIG rdbk.TRIG setup to initiate and abort Readbackrdbk.TRIG hold to initiate and abort Readback

12

TRTRCTRCRT

20050

--

nsns

rdclk.1 rdbk.DATA delayrdbk.RIP delayHigh timeLow time

7654

TRCRDTRCRRTRCHTRCL

--

250250

250250500500

nsnsnsns

XLDescription Symbol Min Max Units

rdbk.TRIG rdbk.TRIG setup to initiate and abort Readbackrdbk.TRIG hold to initiate and abort Readback

12

TRTRCTRCRT

20050

--

nsns

rdclk.1 rdbk.DATA delayrdbk.RIP delayHigh timeLow time

7654

TRCRDTRCRRTRCHTRCL

--

250250

250250500500

nsnsnsns

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Table 22: Pin Functions During Configuration

CONFIGURATION MODE <M2:M1:M0>SLAVESERIAL<1:1:1>

MASTERSERIAL<0:0:0>

SYNCH.PERIPHERAL

<0:1:1>

ASYNCH.PERIPHERAL

<1:0:1>

MASTERPARALLEL DOWN

<1:1:0>

MASTERPARALLEL UP

<1:0:0>

USEROPERATION

M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) (I)M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) (O)M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) (I)HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/OLDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O

INIT INIT INIT INIT INIT INIT I/ODONE DONE DONE DONE DONE DONE DONE

PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAMCCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I)

RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/ORS (I) I/O

CS0 (I) I/ODATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/ODATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/ODATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/ODATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/ODATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/ODATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/ODATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O

DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/ODOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O

TDI TDI TDI TDI TDI TDI TDI-I/OTCK TCK TCK TCK TCK TCK TCK-I/OTMS TMS TMS TMS TMS TMS TMS-I/OTDO TDO TDO TDO TDO TDO TDO-(O)

WS (I) A0 A0 I/OA1 A1 PGCK4-GCK6-I/O

CS1 A2 A2 I/OA3 A3 I/OA4 A4 I/OA5 A5 I/OA6 A6 I/OA7 A7 I/OA8 A8 I/OA9 A9 I/O

A10 A10 I/OA11 A11 I/OA12 A12 I/OA13 A13 I/OA14 A14 I/OA15 A15 SGCK1-GCK7-I/OA16 A16 PGCK1-GCK8-I/OA17 A17 I/OA18* A18* I/OA19* A19* I/OA20* A20* I/OA21* A21* I/O

ALL OTHERS

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Table 23: Pin Functions During Configuration

CONFIGURATION MODE <M2:M1:M0>SLAVESERIAL<1:1:1>

MASTERSERIAL<0:0:0>

SYNCH.PERIPHERAL

<0:1:1>

ASYNCH.PERIPHERAL

<1:0:1>

MASTERPARALLEL DOWN

<1:1:0>

MASTERPARALLEL UP

<1:0:0>

USEROPERATION

M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) (I)M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) (O)M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) (I)HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/OLDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O

INIT INIT INIT INIT INIT INIT I/ODONE DONE DONE DONE DONE DONE DONE

PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAMCCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I)

RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/ORS (I) I/O

CS0 (I) I/ODATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/ODATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/ODATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/ODATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/ODATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/ODATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/ODATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O

DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/ODOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O

TDI TDI TDI TDI TDI TDI TDI-I/OTCK TCK TCK TCK TCK TCK TCK-I/OTMS TMS TMS TMS TMS TMS TMS-I/OTDO TDO TDO TDO TDO TDO TDO-(O)

WS (I) A0 A0 I/OA1 A1 PGCK4-GCK6-I/O

CS1 A2 A2 I/OA3 A3 I/OA4 A4 I/OA5 A5 I/OA6 A6 I/OA7 A7 I/OA8 A8 I/OA9 A9 I/O

A10 A10 I/OA11 A11 I/OA12 A12 I/OA13 A13 I/OA14 A14 I/OA15 A15 SGCK1-GCK7-I/OA16 A16 PGCK1-GCK8-I/OA17 A17 I/OA18* A18* I/OA19* A19* I/OA20* A20* I/OA21* A21* I/O

ALL OTHERS* XC4000X onlyNotes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during configuration.

2. (I) represents an input; (O) represents an output.3. INIT is an open-drain output during configuration.

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Configuration TimingThe seven configuration modes are discussed in detail inthis section. Timing specifications are included.

Slave Serial ModeIn Slave Serial mode, an external signal drives the CCLKinput of the FPGA. The serial configuration bitstream mustbe available at the DIN input of the lead FPGA a shortsetup time before each rising CCLK edge.

The lead FPGA then presents the preamble data—and alldata that overflows the lead device—on its DOUT pin.

There is an internal delay of 0.5 CCLK periods, whichmeans that DOUT changes on the falling CCLK edge, andthe next FPGA in the daisy chain accepts data on the sub-sequent rising CCLK edge.

Figure 51 shows a full master/slave system. An XC4000Series device in Slave Serial mode should be connected asshown in the third device from the left.

Slave Serial mode is selected by a <111> on the mode pins(M2, M1, M0). Slave Serial is the default mode if the modepins are left unconnected, as they have weak pull-up resis-tors during configuration.

Figure 52: Slave Serial Mode Programming Switching Characteristics

XC4000E/X MASTER SERIAL

XC4000E/X, XC5200 SLAVE

XC3100A SLAVE

XC1700D

PROGRAM

NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O

NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O

M2

M0 M1

DOUT

CCLK CLK

VCC

+5 V

DATA

CE CEO

VPP

RESET/OE DONE

DIN

LDC

INIT INITDONE

PROGRAM PROGRAM

D/P INIT

RESET

CCLK

DIN

CCLK

DINDOUT DOUT

M2M0 M1 M1 PWRDNM0

M2

(Low Reset Option Used)

4.7 KΩ

4.7 KΩ4.7 KΩ4.7 KΩ 4.7 KΩ4.7 KΩ4.7 KΩ

VCC

X9025

N/C

N/C

Figure 51: Master/Slave Serial Mode Circuit Diagram

4 TCCH

Bit n Bit n + 1

Bit nBit n - 1

3 TCCO

5 TCCL2 TCCD1 TDCC

DIN

CCLK

DOUT (Output)

X5379

Description Symbol Min Max Units

CCLK

DIN setup 1 TDCC 20 nsDIN hold 2 TCCD 0 nsDIN to DOUT 3 TCCO 30 nsHigh time 4 TCCH 45 nsLow time 5 TCCL 45 nsFrequency FCC 10 MHz

Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

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Master Serial ModeIn Master Serial mode, the CCLK output of the lead FPGAdrives a Xilinx Serial PROM that feeds the FPGA DIN input.Each rising edge of the CCLK output increments the SerialPROM internal address counter. The next data bit is put onthe SPROM data output, connected to the FPGA DIN pin.The lead FPGA accepts this data on the subsequent risingCCLK edge.

The lead FPGA then presents the preamble data—and alldata that overflows the lead device—on its DOUT pin.There is an internal pipeline delay of 1.5 CCLK periods,which means that DOUT changes on the falling CCLKedge, and the next FPGA in the daisy chain accepts dataon the subsequent rising CCLK edge.

In the bitstream generation software, the user can specifyFast ConfigRate, which, starting several bits into the firstframe, increases the CCLK frequency by a factor of eight.

For actual timing values please refer to “ConfigurationSwitching Characteristics” on page 68. Be sure that theserial PROM and slaves are fast enough to support thisdata rate. XC2000, XC3000/A, and XC3100A devices donot support the Fast ConfigRate option.

The SPROM CE input can be driven from either LDC orDONE. Using LDC avoids potential contention on the DINpin, if this pin is configured as user-I/O, but LDC is thenrestricted to be a permanently High user output after con-figuration. Using DONE can also avoid contention on DIN,provided the early DONE option is invoked.

Figure 51 on page 60 shows a full master/slave system.The leftmost device is in Master Serial mode.

Master Serial mode is selected by a <000> on the modepins (M2, M1, M0).

Figure 53: Master Serial Mode Programming Switching Characteristics


CCLKDIN setup 1 TDSCK 20 nsDIN hold 2 TCKDS 0 ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAMLow until Vcc is valid.

2. Master Serial mode timing is based on testing in slave mode.

Serial Data In

CCLK (Output)

Serial DOUT (Output)

1 TDSCK

2 TCKDS

n n + 1 n + 2

n – 3 n – 2 n – 1 n

X3223

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Master Parallel ModesIn the two Master Parallel modes, the lead FPGA directlyaddresses an industry-standard byte-wide EPROM, andaccepts eight data bits just before incrementing or decre-menting the address outputs.

The eight data bits are serialized in the lead FPGA, whichthen presents the preamble data—and all data that over-flows the lead device—on its DOUT pin. There is an inter-nal delay of 1.5 CCLK periods, after the rising CCLK edgethat accepts a byte of data (and also changes the EPROMaddress) until the falling CCLK edge that makes the LSB(D0) of this byte appear at DOUT. This means that DOUTchanges on the falling CCLK edge, and the next FPGA inthe daisy chain accepts data on the subsequent risingCCLK edge.

The PROM address pins can be incremented or decre-mented, depending on the mode pin settings. This optionallows the FPGA to share the PROM with a wide variety ofmicroprocessors and micro controllers. Some processorsmust boot from the bottom of memory (all zeros) while oth-ers must boot from the top. The FPGA is flexible and canload its configuration bitstream from either end of the mem-ory.

Master Parallel Up mode is selected by a <100> on themode pins (M2, M1, M0). The EPROM addresses start at00000 and increment.

Master Parallel Down mode is selected by a <110> on themode pins. The EPROM addresses start at 3FFFF anddecrement.

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines(A18-A21) allowing the additional address space requiredto daisy-chain several large devices.

The extra address lines are programmable in XC4000EXdevices. By default these address lines are not activated. Inthe default mode, the devices are compatible with existingXC4000 and XC4000E products. If desired, the extraaddress lines can be used by specifying the address linesoption in bitgen as 22 (bitgen -g AddressLines:22). Thelines (A18-A21) are driven when a master device detects,via the bitstream, that it should be using all 22 addresslines. Because these pins will initially be pulled high byinternal pull-ups, designers using Master Parallel Up modeshould use external pull down resistors on pins A18-A21. IfMaster Parallel Down mode is used external resistors arenot necessary.

All 22 address lines are always active in Master Parallelmodes with XC4000XL devices. The additional addresslines behave identically to the lower order address lines. Ifthe Address Lines option in bitgen is set to 18, it will beignored by the XC4000XL device.

The additional address lines (A18-A21) are not available inthe PC84 package.

M0 M1

DOUT

VCC

M2

PROGRAM

D7

D6

D5

D4

D3

D2

D1

D0

PROGRAM

CCLK

DIN

M0 M1 M2

DOUT

PROGRAM

EPROM (8K x 8)

(OR LARGER)

A10

A11

A12

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

DONE

D6

D5

D4

D3

D2

D1

D0

N/C

N/C

CE

OE

XC4000E/X SLAVE

8DATA BUS

CCLK

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

INIT

INIT

. . .

. . .

. . .USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS

DONE

TO DIN OF OPTIONAL DAISY-CHAINED FPGAS

A16 . . .

A17 . . .

HIGH or

LOW

X9026

TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS

4.7KΩ

4.7KΩ

NOTE:M0 can be shorted to Ground if not used as I/O.

Figure 54: Master Parallel Mode Circuit Diagram

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Figure 55: Master Parallel Mode Programming Switching Characteristics

Address for Byte n

Byte

2 TDRC

Address for Byte n + 1

D7D6

A0-A17 (output)

D0-D7

RCLK (output)

CCLK (output)

DOUT (output)

1 TRAC

7 CCLKs CCLK

3 TRCD

Byte n - 1 X6078


RCLKDelay to Address valid 1 TRAC 0 200 nsData setup time 2 TDRC 60 nsData hold time 3 TRCD 0 ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAMLow until Vcc is valid.

2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than500 ns. EPROM data output has no hold-time requirements.

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Synchronous Peripheral ModeSynchronous Peripheral mode can also be consideredSlave Parallel mode. An external signal drives the CCLKinput(s) of the FPGA(s). The first byte of parallel configura-tion data must be available at the Data inputs of the leadFPGA a short setup time before the rising CCLK edge.Subsequent data bytes are clocked in on every eighth con-secutive rising CCLK edge.

The same CCLK edge that accepts data, also causes theRDY/BUSY output to go High for one CCLK period. The pinname is a misnomer. In Synchronous Peripheral mode it isreally an ACKNOWLEDGE signal. Synchronous operationdoes not require this response, but it is a meaningful signalfor test purposes. Note that RDY/BUSY is pulled High witha high-impedance pullup prior to INIT going High.

The lead FPGA serializes the data and presents the pre-amble data (and all data that overflows the lead device) onits DOUT pin. There is an internal delay of 1.5 CCLK peri-ods, which means that DOUT changes on the falling CCLKedge, and the next FPGA in the daisy chain accepts dataon the subsequent rising CCLK edge.

In order to complete the serial shift operation, 10 additionalCCLK rising edges are required after the last data byte hasbeen loaded, plus one more CCLK cycle for eachdaisy-chained device.

Synchronous Peripheral mode is selected by a <011> onthe mode pins (M2, M1, M0).

X9027

CONTROL SIGNALS

DATA BUS

PROGRAM

DOUT

M0 M1 M2

D0-7

INIT DONE

PROGRAM

4.7 kΩ

4.7 kΩ

4.7 kΩ

RDY/BUSY

VCC

OPTIONAL DAISY-CHAINED FPGAs

NOTE: M2 can be shorted to Ground if not used as I/O

CCLKCLOCK

PROGRAM

DOUT

XC4000E/X SLAVE

XC4000E/X SYNCHRO-

NOUS PERIPHERAL

M0 M1

N/C

8

M2

DIN

INIT DONE

CCLK

N/C

Figure 56: Synchronous Peripheral Mode Circuit Diagram

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Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics

0DOUT

CCLK

1 2 3 4 5 6 7

BYTE 0

BYTE 1

BYTE 0 OUT BYTE 1 OUT

RDY/BUSY

INIT

10

X6096


CCLK

INIT (High) setup time TIC 5 µsD0 - D7 setup time TDC 60 nsD0 - D7 hold time TCD 0 nsCCLK High time TCCH 50 nsCCLK Low time TCCL 60 nsCCLK Frequency FCC 8 MHz

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in thefirst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on everyeighth consecutive rising edge of CCLK.

2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation doesnot require such a response.

3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,

additional CCLK pulses are clearly required after the last byte has been loaded.

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Asynchronous Peripheral Mode

Write to FPGA

Asynchronous Peripheral mode uses the trailing edge ofthe logic AND condition of WS and CS0 being Low and RSand CS1 being High to accept byte-wide data from a micro-processor bus. In the lead FPGA, this data is loaded into adouble-buffered UART-like parallel-to-serial converter andis serially shifted into the internal logic.

The lead FPGA presents the preamble data (and all datathat overflows the lead device) on its DOUT pin. TheRDY/BUSY output from the lead FPGA acts as a hand-shake signal to the microprocessor. RDY/BUSY goes Lowwhen a byte has been received, and goes High again whenthe byte-wide input buffer has transferred its informationinto the shift register, and the buffer is ready to receive newdata. A new write may be started immediately, as soon asthe RDY/BUSY output has gone Low, acknowledgingreceipt of the previous data. Write may not be terminateduntil RDY/BUSY is High again for one CCLK period. Notethat RDY/BUSY is pulled High with a high-impedancepull-up prior to INIT going High.

The length of the BUSY signal depends on the activity inthe UART. If the shift register was empty when the new bytewas received, the BUSY signal lasts for only two CCLKperiods. If the shift register was still full when the new bytewas received, the BUSY signal can be as long as nineCCLK periods.

Note that after the last byte has been entered, only seven ofits bits are shifted out. CCLK remains High with DOUTequal to bit 6 (the next-to-last bit) of the last byte entered.

The READY/BUSY handshake can be ignored if the delayfrom any one Write to the end of the next Write is guaran-teed to be longer than 10 CCLK periods.

Status Read

The logic AND condition of the CS0, CS1and RS inputsputs the device status on the Data bus.

• D7 High indicates Ready• D7 Low indicates Busy• D0 through D6 go unconditionally High

It is mandatory that the whole start-up sequence be startedand completed by one byte-wide input. Otherwise, the pinsused as Write Strobe or Chip Enable might become activeoutputs and interfere with the final byte transfer. If thistransfer does not occur, the start-up sequence is not com-pleted all the way to the finish (point F in Figure 47 on page53).

In this case, at worst, the internal reset is not released. Atbest, Readback and Boundary Scan are inhibited. Thelength-count value, as generated by the XACTstep soft-ware, ensures that these problems never occur.

Although RDY/BUSY is brought out as a separate signal,microprocessors can more easily read this information onone of the data lines. For this purpose, D7 represents theRDY/BUSY status when RS is Low, WS is High, and thetwo chip select lines are both active.

Asynchronous Peripheral mode is selected by a <101> onthe mode pins (M2, M1, M0).

ADDRESS BUS

DATA BUS

ADDRESS DECODE

LOGIC

CS0...

RDY/BUSY

WS

PROGRAM

D0–7 CCLK

DOUT DIN

M2M0 M1

N/C N/CN/C

RS

CS1

CONTROL SIGNALS

INIT

REPROGRAM

OPTIONAL DAISY-CHAINED FPGAs

VCC

DONE

8

X9028

4.7 kΩ

4.7 kΩ 4.7 kΩ

4.7 kΩ

XC4000E/X ASYNCHRO-

NOUS PERIPHERAL

PROGRAM

CCLK

DOUT

M2M0 M1

INIT

DONE

XC4000E/X SLAVE

Figure 58: Asynchronous Peripheral Mode Circuit Diagram

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Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics

Previous Byte D6 D7 D0 D1 D2

1 TCA

2 TDC

4TWTRB

3 TCD

6 TBUSY

READY BUSY

RS, CS0

WS, CS1

D7

WS/CS0

RS, CS1

D0-D7

CCLK

RDY/BUSY

DOUT

Write to LCA Read Status

X6097

7 4


Write

Effective Write time(CS0, WS=Low; RS, CS1=High)

1 TCA 100 ns

DIN setup time 2 TDC 60 nsDIN hold time 3 TCD 0 ns

RDY

RDY/BUSY delay after end ofWrite or Read

4 TWTRB 60 ns

RDY/BUSY active after beginningof Read

7 60 ns

RDY/BUSY Low output (Note 4) 6 TBUSY 2 9 CCLKperiods

Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte

processing and the phase of the internal timing generator for CCLK.3. CCLK and DOUT timing is tested in slave mode.4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest

TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new wordis loaded into the input register before the second-level buffer has started shifting out data

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY willgo active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but writemay not be terminated until RDY/BUSY has been High for one CCLK period.

May 14, 1999 (Version 1.6) 6-67

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Configuration Switching Characteristics

Master Modes (XC4000E/EX)

Master Modes (XC4000XL)

Slave and Peripheral Modes (All)


Power-On ResetM0 = High TPOR 10 40 msM0 = Low TPOR 40 130 ms

Program Latency TPI 30 200 µs perCLB column

CCLK (output) Delay TICCK 40 250 µsCCLK (output) Period, slow TCCLK 640 2000 nsCCLK (output) Period, fast TCCLK 80 250 ns


Power-On ResetM0 = High TPOR 10 40 msM0 = Low TPOR 40 130 ms

Program Latency TPI 30 200 µs perCLB column

CCLK (output) Delay TICCK 40 250 µsCCLK (output) Period, slow TCCLK 540 1600 nsCCLK (output) Period, fast TCCLK 67 200 ns

Description Symbol Min Max UnitsPower-On Reset TPOR 10 33 msProgram Latency TPI 30 200 µs per

CLB columnCCLK (input) Delay (required) TICCK 4 µsCCLK (input) Period (required) TCCLK 100 ns

VALID

PROGRAM

INIT

Vcc

PIT

PORT

ICCKT CCLKT

CCLK OUTPUT or INPUT

M0, M1, M2 DONE RESPONSE

<300 ns

<300 ns

>300 ns

RE-PROGRAM

X1532

(Required)

I /O

6-68 May 14, 1999 (Version 1.6)

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6

Product AvailabilityTable 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your localsales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision ofthe specifications.

Table 24: Component Availability Chart for XC4000XL FPGAs

PINS 84 100 100 144 144 160 160 176 176 208 208 240 240 256 299 304 352 411 432 475 559 560

TYPE

Pla

st.

PLC

C

Pla

st.

PQ

FP

Pla

st.

VQ

FP

Pla

st.

TQ

FP

Hig

h-P

erf.

TQ

FP

Hig

h-P

erf.

QF

P

Pla

st.

PQ

FP

Pla

st.

TQ

FP

Hig

h-P

erf.

TQ

FP

Hig

h-P

erf.

QF

P

Pla

st.

PQ

FP

Hig

h-P

erf.

QF

P

Pla

st.

PQ

FP

Pla

st.

BG

A

Cer

am.

PG

A

Hig

h-P

erf.

QF

P

Pla

st.

BG

A

Cer

am.

PG

A

Pla

st.

BG

A

Cer

am.

PG

A

Cer

am.

PG

A

Pla

st.

BG

A

CODE

PC

84

PQ

100

VQ

100

TQ

144

HT

144

HQ

160

PQ

160

TQ

176

HT

176

HQ

208

PQ

208

HQ

240

PQ

240

BG

256

PG

299

HQ

304

BG

352

PG

411

BG

432

PG

475

PG

559

BG

560

XC4002XL

-3 C I C I C I

-2 C I C I C I

-1 C I C I C I

-09C C C C

XC4005XL

-3 C I C I C I C I C I C I

-2 C I C C I C I C I C I


-09C C C C C C C

XC4010XL

-3 C I C I C I C I C I C I C I



-09C C C C C C C C

XC4013XL




-09C C C C C C C

-08C C C C C C C

XC4020XL




-09C C C C C C C

XC4028XL




-09C C C C C C C C

XC4036XL


-2 C I C I C C I C I C I C I


-09C C C C C C C C

-08C C C C C C C C

XC4044XL




-09C C C C C C C C

XC4052XL

-3 C I C I C I C I C I



-09C C C C C C

XC4062XL




-09C C C C C C

-08C C C C C C

XC4085XL

-3 C I C I C I

-2 C I C I C I

-1 C I C I C I

-09C C C C

1/29/99

C = Commercial TJ = 0° to +85°CI= Industrial TJ = -40°C to +100°C

May 14, 1999 (Version 1.6) 6-69

http://www.xilinx.com/partinfo/databook.htm#XC4000

R


Table 25: Component Availability Chart for XC4000E FPGAs

PINS 84 100 100 120 144 156 160 191 208 208 223 225 240 240 299 304

TYPE

Pla

st.

PLC

C

Pla

st.

PQ

FP

Pla

st.

VQ

FP

Cer

am.

PG

A

Pla

st.

TQ

FP

Cer

am.

PG

A

Pla

st.

PQ

FP

Cer

am.

PG

A

Hig

h-P

erf.

QF

P

Pla

st.

PQ

FP

Cer

am.

PG

A

Pla

st.

BG

A

Hig

h-P

erf.

QF

P

Pla

st.

PQ

FP

Cer

am.

PG

A

Hig

h-P

erf.

QF

CODEP

C84

PQ

100

VQ

100

PG

120

TQ

144

PG

156

PQ

160

PG

191

HQ

208

PQ

208

PG

223

BG

225

HQ

240

PQ

240

PG

299

HQ

304

XC4003E

-4 C I C I C I C I

-3 C I C I C I C I

-2 C I C I C I C I

-1 C C C C

XC4005E




-1 C C C C C C

XC4006E




-1 C C C C C

XC4008E

-4 C I C I C I C I

-3 C I C I C I C I

-2 C I C I C I C I

-1 C C C C

XC4010E




-1 C C C C C C

XC4013E




-1 C C C C C C C

XC4020E

-4 C I C I C I

-3 C I C I C I

-2 C I C I C I

-1 C C C

XC4025E-4 C I C I C I C I

-3 C I C I C I C I

-2 C C C C

1/29/99


Table 26: Component Availability Chart for XC4000EX FPGAs

PINS 208 240 299 304 352 411 432

TYPEHigh-Perf.

QFPHigh-Perf.

QFPCeram.

PGAHigh-Perf.

QFPPlast.BGA

Ceram.PGA

Plast.BGA

CODE HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432

XC4028EX-4 C I C I C I C I C I


-2 C C C C C

XC4036EX-4 C I C I C I C I C I


-2 C C C C C

1/29/99


6-70 May 14, 1999 (Version 1.6)

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6

User I/O Per PackageTable 27, Table 28, and Table 29 show the number of user I/Os available in each package for XC4000-Series devices. Callyour local sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latestrevision of the specifications.

Table 27: User I/O Chart for XC4000XL FPGAs

MaxI/O

Maximum User Accessible I/O by Package Type

Device PC

84

PQ

100

VQ

100

TQ

144

HT

144

HQ

160

PQ

160

TQ

176

HT

176

HQ

208

PQ

208

HQ

240

PQ

240

BG

256

PG

299

HQ

304

BG

352

PG

411

BG

432

PG

475

PG

559

BG

560

XC4002XL 64 61 64 64

XC4005XL 112 61 77 77 112 112 112

XC4010XL 160 61 77 113 129 145 160 160

XC4013XL 192 113 129 145 160 192 192

XC4020XL 224 113 129 145 160 192 205

XC4028XL 256 129 160 193 205 256 256 256

XC4036XL 288 129 160 193 256 288 288 288

XC4044XL 320 129 160 193 256 289 320 320

XC4052XL 352 193 256 352 352 352

XC4062XL 384 193 256 352 384 384

XC4085XL 448 352 448 448

1/29/99

Table 28: User I/O Chart for XC4000E FPGAs

MaxI/O

Maximum User Accessible I/O by Package Type

Device PC

84

PQ

100

VQ

100

PG

120

TQ

144

PG

156

PQ

160

PG

191

HQ

208

PQ

208

PG

223

BG

225

HQ

240

PQ

240

PG

299

HQ

304

XC4003E 80 61 77 77 80

XC4005E 112 61 77 112 112 112 112

XC4006E 128 61 113 125 128 128

XC4008E 144 61 129 144 144

XC4010E 160 61 129 160 160 160 160

XC4013E 192 129 160 160 192 192 192 192

XC4020E 224 160 192 193

XC4025E 256 192 193 256 256

1/29/99

Table 29: User I/O Chart for XC4000EX FPGAs

MaxI/O

Maximum User Accessible I/O by Package TypeDevice HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432

XC4028EX 256 160 193 256 256 256

XC4036EX 288 193 256 288 288 288

1/29/99

May 14, 1999 (Version 1.6) 6-71

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XC4000 Series Electrical Characteristics and Device-Specific Pinout TableFor the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at


Ordering Information

XC4013E-3HQ240C

Device Type

Speed Grade -6 -5 -4 -3 -2 -1

Number of Pins

Package Type

Temperature RangeC = Commercial (TJ = 0 to +85°C) I = Industrial (TJ = -40 to +100°C) M = Military (TC = -55 to+125°C)

PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack VQ = Very Thin Quad Flat Pack TQ = Thin Quad Flat Pack

BG = Ball Grid Array PG = Ceramic Pin Grid Array HQ = High Heat Dissipation Quad Flat Pack MQ = Metal Quad Flat Pack CB = Top Brazed Ceramic Quad Flat Pack

X9020

Example:

Revision ControlVersion Description

3/30/98 (1.5) Updated XC4000XL timing and added XC4002XL1/29/99 (1.5) Updated pin diagrams5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and

added URL link for electrical specifications/pinouts for WebLINX users

6-72 May 14, 1999 (Version 1.6)


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XC4000E and XC4000X Series Field Programmable Gate Arrays0

Device-Specific Pinout TablesDevice-specific tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locationsaround the die, and include boundary scan register locations..

XC4002XL Device Pinout Tables

Additional XC4002XL Package Pins

•

•

XC4002XLPad Names PC84 PQ100 VQ100 PG120 Boundary

Scan

VCC P2 P92 P89 G3I/O (A8) P3 P93 P90 G1 26I/O (A9) P4 P94 P91 F1 29I/O (A10) P5 P97 P94 F3 32I/O (A11) P6 P98 P95 D1 35I/O (A12) P7 P99 P96 C1 38I/O (A13) P8 P100 P97 D2 41I/O (A14) P9 P1 P98 C2 44I/O,GCK8 (A15) P10 P2 P99 D3 47VCC P11 P3 P100 C3GND P12 P4 P1 C4I/O, GCK1(A16) P13 P5 P2 B2 50I/O (A17) P14 P6 P3 B3 53I/O, TDI P15 P7 P4 C5 56I/O, TCK P16 P8 P5 B4 59I/O, TMS P17 P9 P6 B5 62I/O P18 P10 P7 A4 65I/O P19 P12 P9 B6 68I/O P20 P13 P10 A6 71GND P21 P14 P11 B7VCC P22 P15 P12 C7I/O P23 P16 P13 A7 74I/O P24 P17 P14 A8 77I/O P25 P19 P16 C8 80I/O P26 P20 P17 A10 83I/O P27 P21 P18 B9 86I/O - P22 P19 A11 89I/O P28 P23 P20 C9 92I/O, GCK2 P29 P24 P21 A12 95O (M1) P30 P25 P22 B11 98GND P31 P26 P23 C10I (M0) P32 P27 P24 C11 101VCC P33 P28 P25 D11I (M2) P34 P29 P26 B12 102I/O, GCK3 P35 P30 P27 C12 103I/O (HDC) P36 P31 P28 A13 106I/O - P32 P29 D12 109I/O (LDC) P37 P33 P30 C13 112I/O P38 P34 P31 E12 115I/O P39 P35 P32 D13 118I/O P40 P38 P35 F12 121I/O (INIT) P41 P39 P36 F13 124VCC P42 P40 P37 G12GND P43 P41 P38 G11I/O P44 P42 P39 G13 127I/O P45 P43 P40 H13 130I/O P46 P46 P43 H11 133I/O P47 P47 P44 K13 136I/O P48 P48 P45 J12 139I/O P49 P49 P46 L13 142I/O P50 P50 P47 M13 145I/O, GCK4 P51 P51 P48 L12 148GND P52 P52 P49 K11DONE P53 P53 P50 L11VCC P54 P54 P51 L10PROGRAM P55 P55 P52 M12I/O (D7) P56 P56 P53 M11 151I/O, GCK5 P57 P57 P54 N13 154I/O (D6) P58 P58 P55 M10 157

I/O - P59 P56 N11 160I/O (D5) P59 P60 P57 M9 163I/O (CS0) P60 P61 P58 N10 166I/O (D4) P61 P64 P61 M8 169I/O P62 P65 P62 N8 172VCC P63 P66 P63 M7GND P64 P67 P64 L7I/O (D3) P65 P68 P65 N7 175I/O (RS) P66 P69 P66 N6 178I/O (D2) P67 P71 P68 L6 181I/O P68 P72 P69 N4 184I/O (D1) P69 P73 P70 M5 187I/O (RCLK,RDY/BUSY)

P70 P74 P71 N3 190

I/O (D0, DIN) P71 P75 P72 N2 193I/O, GCK6 (DOUT) P72 P76 P73 M3 196CCLK P73 P77 P74 L4VCC P74 P78 P75 L3O, TDO P75 P79 P76 M2GND P76 P80 P77 K3I/O (A0, WS) P77 P81 P78 L2 2I/O, GCK7(A1) P78 P82 P79 N1 5I/O (CS1, A2) P79 P83 P80 K2 8I/O (A3) P80 P84 P81 L1 11I/O (A4) P81 P85 P82 J2 14I/O (A5) P82 P86 P83 K1 17I/O (A6) P83 P89 P86 H2 20I/O (A7) P84 P90 P87 H1 23GND P1 P91 P88 G21/22/99

PG120N.C. Pins

E1 F2 E2 E3 B1 A1A2 A3 C6 A5 A9 B8

B10 B13 E11 E13 J13 H12K12 J11 N12 L9 L8 N9N5 M6 M4 L5 M1 J3H3 J1

1/22/99

PQ100N.C. Pins

P11 P18 P36 P37 P44 P45P62 P63 P70 P87 P88 P95P96

1/22//99

VQ100N.C. Pins

P8 P15 P33 P34 P41 P42P59 P60 P67 P84 P85 P92P93

1/22//99

XC4002XLPad Names PC84 PQ100 VQ100 PG120 Boundary

Scan

DS006 (v. 1.7) October 4, 1999 - Product Specification 6-117

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XC4003E Device Pinout Tables

Additional XC4003E Package Pins

XC4003EPad Name PC84 PQ100 VQ100 PG120 Bndry Scan

VCC P2 P92 P89 G3 -I/O (A8) P3 P93 P90 G1 32I/O (A9) P4 P94 P91 F1 35I/O - P95 P92 E1 38I/O - P96 P93 F2 41I/O (A10) P5 P97 P94 F3 44I/O (A11) P6 P98 P95 D1 47I/O (A12) P7 P99 P96 C1 50I/O (A13) P8 P100 P97 D2 53I/O (A14) P9 P1 P98 C2 56I/O, SGCK1 (A15) P10 P2 P99 D3 59VCC P11 P3 P100 C3 -GND P12 P4 P1 C4 -I/O, PGCK1 (A16) P13 P5 P2 B2 62I/O (A17) P14 P6 P3 B3 65I/O, TDI P15 P7 P4 C5 68I/O, TCK P16 P8 P5 B4 71I/O, TMS P17 P9 P6 B5 74I/O P18 P10 P7 A4 77I/O - - - C6 80I/O - P11 P8 A5 83I/O P19 P12 P9 B6 86I/O P20 P13 P10 A6 89GND P21 P14 P11 B7 -VCC P22 P15 P12 C7 -I/O P23 P16 P13 A7 92I/O P24 P17 P14 A8 95I/O - P18 P15 A9 98I/O - - - B8 101I/O P25 P19 P16 C8 104I/O P26 P20 P17 A10 107I/O P27 P21 P18 B9 110I/O - P22 P19 A11 113I/O P28 P23 P20 C9 116I/O, SGCK2 P29 P24 P21 A12 119O (M1) P30 P25 P22 B11 122GND P31 P26 P23 C10 -I (M0) P32 P27 P24 C11 125VCC P33 P28 P25 D11 -I (M2) P34 P29 P26 B12 126I/O, PGCK2 P35 P30 P27 C12 127I/O (HDC) P36 P31 P28 A13 130I/O - P32 P29 D12 133I/O (LDC) P37 P33 P30 C13 136I/O P38 P34 P31 E12 139I/O P39 P35 P32 D13 142I/O - P36 P33 F11 145I/O - P37 P34 E13 148I/O P40 P38 P35 F12 151I/O (INIT) P41 P39 P36 F13 154VCC P42 P40 P37 G12 -GND P43 P41 P38 G11 -I/O P44 P42 P39 G13 157I/O P45 P43 P40 H13 160I/O - P44 P41 J13 163I/O - P45 P42 H12 166

I/O P46 P46 P43 H11 169I/O P47 P47 P44 K13 172I/O P48 P48 P45 J12 175I/O P49 P49 P46 L13 178I/O P50 P50 P47 M13 181I/O, SGCK3 P51 P51 P48 L12 184GND P52 P52 P49 K11 -DONE P53 P53 P50 L11 -VCC P54 P54 P51 L10 -PROGRAM P55 P55 P52 M12 -I/O (D7) P56 P56 P53 M11 187I/O, PGCK3 P57 P57 P54 N13 190I/O (D6) P58 P58 P55 M10 193I/O - P59 P56 N11 196I/O (D5) P59 P60 P57 M9 199I/O (CS0) P60 P61 P58 N10 202I/O - P62 P59 L8 205I/O - P63 P60 N9 208I/O (D4) P61 P64 P61 M8 211I/O P62 P65 P62 N8 214VCC P63 P66 P63 M7 -GND P64 P67 P64 L7 -I/O (D3) P65 P68 P65 N7 217I/O (RS) P66 P69 P66 N6 220I/O - P70 P67 N5 223I/O - - - M6 226I/O (D2) P67 P71 P68 L6 229I/O P68 P72 P69 N4 232I/O (D1) P69 P73 P70 M5 235I/O (RCLK,RDY/BUSY)

P70 P74 P71 N3 238

I/O (D0, DIN) P71 P75 P72 N2 241I/O, SGCK4 (DOUT) P72 P76 P73 M3 244CCLK P73 P77 P74 L4 -VCC P74 P78 P75 L3 -O, TDO P75 P79 P76 M2 0GND P76 P80 P77 K3 -I/O (A0, WS) P77 P81 P78 L2 2I/O, PGCK4 (A1) P78 P82 P79 N1 5I/O (CS1, A2) P79 P83 P80 K2 8I/O (A3) P80 P84 P81 L1 11I/O (A4) P81 P85 P82 J2 14I/O (A5) P82 P86 P83 K1 17I/O - P87 P84 H3 20I/O - P88 P85 J1 23I/O (A6) P83 P89 P86 H2 26I/O (A7) P84 P90 P87 H1 29GND P1 P91 P88 G2 -5/5/97

PG120Not Connected Pins

A1 A2 A3 B1 B10 B13E2 E3 E11 J3 J11 K12L5 L9 M1 M4 N12 -

5/5/97

XC4003EPad Name PC84 PQ100 VQ100 PG120 Bndry Scan

6-118 DS006 (v. 1.7) October 4, 1999 - Product Specification

R


XC4005E/XL Device Pnout TablesThe following table may contain pinout information for unsupported device/package combinations. Please see the availabilitycharts elsewhere in the XC4000 Series data sheet for availability information.

XC4005E/XLPad Name

PC84

PQ100

VQ100††

TQ144

PG156†

PQ160

PQ208

BndryScan

VCC P2 P92 P89 P128 H3 P142 P183 -I/O (A8) P3 P93 P90 P129 H1 P143 P184 44I/O (A9) P4 P94 P91 P130 G1 P144 P185 47I/O (A19) †† - P95 P92 P131 G2 P145 P186 50I/O (A18) †† - P96 P93 P132 G3 P146 P187 53I/O (A10) P5 P97 P94 P133 F1 P147 P190 56I/O (A11) P6 P98 P95 P134 F2 P148 P191 59I/O - - - P135 E1 P149 P192 62I/O - - - P136 E2 P150 P193 65GND - - - P137 F3 P151 P194 -I/O (A12) P7 P99 P96 P138 E3 P154 P199 68I/O (A13) P8 P100 P97 P139 C1 P155 P200 71I/O - - - P140 C2 P156 P201 74I/O - - - P141 D3 P157 P202 77I/O (A14) P9 P1 P98 P142 B1 P158 P203 80I/O, SGCK1 †,GCK8 †† (A15)

P10 P2 P99 P143 B2 P159 P204 83

VCC P11 P3 P100 P144 C3 P160 P205 -GND P12 P4 P1 P1 C4 P1 P2 -I/O, PGCK1†,GCK1†† (A16)

P13 P5 P2 P2 B3 P2 P4 86

I/O (A17) P14 P6 P3 P3 A1 P3 P5 89I/O - - - P4 A2 P4 P6 92I/O - - - P5 C5 P5 P7 95I/O, TDI P15 P7 P4 P6 B4 P6 P8 98I/O, TCK P16 P8 P5 P7 A3 P7 P9 101GND - - - P8 C6 P10 P14 -I/O - - - P9 B5 P11 P15 104I/O - - - P10 B6 P12 P16 107I/O, TMS P17 P9 P6 P11 A5 P13 P17 110I/O P18 P10 P7 P12 C7 P14 P18 113I/O - - - P13 B7 P15 P21 116I/O - P11 P8 P14 A6 P16 P22 119I/O P19 P12 P9 P15 A7 P17 P23 122I/O P20 P13 P10 P16 A8 P18 P24 125GND P21 P14 P11 P17 C8 P19 P25 -VCC P22 P15 P12 P18 B8 P20 P26 -I/O P23 P16 P13 P19 C9 P21 P27 128I/O P24 P17 P14 P20 B9 P22 P28 131I/O - P18 P15 P21 A9 P23 P29 134I/O - - - P22 B10 P24 P30 137I/O P25 P19 P16 P23 C10 P25 P33 140I/O P26 P20 P17 P24 A10 P26 P34 143I/O - - - P25 A11 P27 P35 146I/O - - - P26 B11 P28 P36 149GND - - - P27 C11 P29 P37 -I/O P27 P21 P18 P28 B12 P32 P42 152I/O - P22 P19 P29 A13 P33 P43 155I/O - - - P30 A14 P34 P44 158I/O - - - P31 C12 P35 P45 161I/O P28 P23 P20 P32 B13 P36 P46 164I/O, SGCK2 †,GCK2 ††

P29 P24 P21 P33 B14 P37 P47 167

O (M1) P30 P25 P22 P34 A15 P38 P48 170GND P31 P26 P23 P35 C13 P39 P49 -I (M0) P32 P27 P24 P36 A16 P40 P50 173VCC P33 P28 P25 P37 C14 P41 P55 -I (M2) P34 P29 P26 P38 B15 P42 P56 174I/O, PGCK2 †,GCK3 ††

P35 P30 P27 P39 B16 P43 P57 175

I/O (HDC) P36 P31 P28 P40 D14 P44 P58 178I/O - - - P41 C15 P45 P59 181I/O - - - P42 D15 P46 P60 184I/O - P32 P29 P43 E14 P47 P61 187I/O (LDC) P37 P33 P30 P44 C16 P48 P62 190

GND - - - P45 F14 P51 P67 -I/O - - - P46 F15 P52 P68 193I/O - - - P47 E16 P53 P69 196I/O P38 P34 P31 P48 F16 P54 P70 199I/O P39 P35 P32 P49 G14 P55 P71 202I/O - P36 P33 P50 G15 P56 P74 205I/O - P37 P34 P51 G16 P57 P75 208I/O P40 P38 P35 P52 H16 P58 P76 211I/O (INIT) P41 P39 P36 P53 H15 P59 P77 214VCC P42 P40 P37 P54 H14 P60 P78 -GND P43 P41 P38 P55 J14 P61 P79 -I/O P44 P42 P39 P56 J15 P62 P80 217I/O P45 P43 P40 P57 J16 P63 P81 220I/O - P44 P41 P58 K16 P64 P82 223I/O - P45 P42 P59 K15 P65 P83 226I/O P46 P46 P43 P60 K14 P66 P86 229I/O P47 P47 P44 P61 L16 P67 P87 232I/O - - - P62 M16 P68 P88 235I/O - - - P63 L15 P69 P89 238GND - - - P64 L14 P70 P90 -I/O P48 P48 P45 P65 P16 P73 P95 241I/O P49 P49 P46 P66 M14 P74 P96 244I/O - - - P67 N15 P75 P97 247I/O - - - P68 P15 P76 P98 250I/O P50 P50 P47 P69 N14 P77 P99 253I/O, SGCK3 †,GCK4 ††

P51 P51 P48 P70 R16 P78 P100 256

GND P52 P52 P49 P71 P14 P79 P101 -DONE P53 P53 P50 P72 R15 P80 P103 -VCC P54 P54 P51 P73 P13 P81 P106 -PROGRAM P55 P55 P52 P74 R14 P82 P108 -I/O (D7) P56 P56 P53 P75 T16 P83 P109 259I/O, PGCK3†,GCK5††

P57 P57 P54 P76 T15 P84 P110 262

I/O - - - P77 R13 P85 P111 265I/O - - - P78 P12 P86 P112 268I/O (D6) P58 P58 P55 P79 T14 P87 P113 271I/O - P59 P56 P80 T13 P88 P114 274GND - - - P81 P11 P91 P119 -I/O - - - P82 R11 P92 P120 277I/O - - - P83 T11 P93 P121 280I/O (D5) P59 P60 P57 P84 T10 P94 P122 283I/O (CS0) P60 P61 P58 P85 P10 P95 P123 286I/O - P62 P59 P86 R10 P96 P126 289I/O - P63 P60 P87 T9 P97 P127 292I/O (D4) P61 P64 P61 P88 R9 P98 P128 295I/O P62 P65 P62 P89 P9 P99 P129 298VCC P63 P66 P63 P90 R8 P100 P130 -GND P64 P67 P64 P91 P8 P101 P131 -I/O (D3) P65 P68 P65 P92 T8 P102 P132 301I/O (RS) P66 P69 P66 P93 T7 P103 P133 304I/O - P70 P67 P94 T6 P104 P134 307I/O - - - P95 R7 P105 P135 310I/O (D2) P67 P71 P68 P96 P7 P106 P138 313I/O P68 P72 P69 P97 T5 P107 P139 316I/O - - - P98 R6 P108 P140 319I/O - - - P99 T4 P109 P141 322GND - - - P100 P6 P110 P142 -I/O (D1) P69 P73 P70 P101 T3 P113 P147 325I/O (RCLK,RDY/BUSY)

P70 P74 P71 P102 P5 P114 P148 328

I/O - - - P103 R4 P115 P149 331I/O - - - P104 R3 P116 P150 334I/O (D0, DIN) P71 P75 P72 P105 P4 P117 P151 337

XC4005E/XLPad Name

PC84

PQ100

VQ100††

TQ144

PG156†

PQ160

PQ208

BndryScan


R


† = E only†† = XL only

Additional XC4005E/XL Package Pins


I/O, SGCK4 †,GCK6 †† (DOUT)

P72 P76 P73 P106 T2 P118 P152 340

CCLK P73 P77 P74 P107 R2 P119 P153 -VCC P74 P78 P75 P108 P3 P120 P154 -O, TDO P75 P79 P76 P109 T1 P121 P159 0GND P76 P80 P77 P110 N3 P122 P160 -I/O (A0, WS) P77 P81 P78 P111 R1 P123 P161 2I/O, PGCK4 †,GCK7 †† (A1)

P78 P82 P79 P112 P2 P124 P162 5

I/O - - - P113 N2 P125 P163 8I/O - - - P114 M3 P126 P164 11I/O (CS1, A2) P79 P83 P80 P115 P1 P127 P165 14I/O (A3) P80 P84 P81 P116 N1 P128 P166 17GND - - - P118 L3 P131 P171 -I/O - - - P119 L2 P132 P172 20I/O - - - P120 L1 P133 P173 23I/O (A4) P81 P85 P82 P121 K3 P134 P174 26I/O (A5) P82 P86 P83 P122 K2 P135 P175 29I/O (A21) †† - P87 P84 P123 K1 P137 P178 32I/O (A20) †† - P88 P85 P124 J1 P138 P179 35I/O (A6) P83 P89 P86 P125 J2 P139 P180 38I/O (A7) P84 P90 P87 P126 J3 P140 P181 41GND P1 P91 P88 P127 H2 P141 P182 -6/10/97

TQ144Not Connected Pins

P117 - - - - -5/5/97

XC4005E/XLPad Name

PC84

PQ100

VQ100††

TQ144

PG156†

PQ160

PQ208

BndryScan


A4 A12 D1 D2 D16 E15M1 M2 M15 N16 R5 R12T12 - - - - -

5/5/97

PQ160Not Connected Pins

P8 P9 P30 P31 P49 P50P71 P72 P89 P90 P111 P112

P129 P130 P136 P152 P153 -6/16/97


P1 P3 P10 P11 P12 P13P19 P20 P31 P32 P38 P39P40 P41 P51 P52 P53 P54P63 P64 P65 P66 P72 P73P84 P85 P91 P92 P93 P94

P102 P104 P105 P107 P115 P116P117 P118 P124 P125 P136 P137P143 P144 P145 P146 P155 P156P157 P158 P167 P168 P169 P170P176 P177 P188 P189 P195 P196P197 P198 P206 P207 P208 -

6/5/97

XC4006EPad Name

PC84

TQ144

PG156

PQ160

PQ208

BndryScan

VCC P2 P128 H3 P142 P183 -I/O (A8) P3 P129 H1 P143 P184 50I/O (A9) P4 P130 G1 P144 P185 53I/O - P131 G2 P145 P186 56I/O - P132 G3 P146 P187 59I/O (A10) P5 P133 F1 P147 P190 62I/O (A11) P6 P134 F2 P148 P191 65I/O - P135 E1 P149 P192 68I/O - P136 E2 P150 P193 71GND - P137 F3 P151 P194 -I/O - - D1 P152 P197 74I/O - - D2 P153 P198 77I/O (A12) P7 P138 E3 P154 P199 80I/O (A13) P8 P139 C1 P155 P200 83I/O - P140 C2 P156 P201 86I/O - P141 D3 P157 P202 89I/O (A14) P9 P142 B1 P158 P203 92I/O, SGCK1 (A15) P10 P143 B2 P159 P204 95VCC P11 P144 C3 P160 P205 -GND P12 P1 C4 P1 P2 -I/O, PGCK1 (A16) P13 P2 B3 P2 P4 98I/O (A17) P14 P3 A1 P3 P5 101I/O - P4 A2 P4 P6 104I/O - P5 C5 P5 P7 107I/O, TDI P15 P6 B4 P6 P8 110I/O, TCK P16 P7 A3 P7 P9 113I/O - - A4 P8 P10 116I/O - - - P9 P11 119GND - P8 C6 P10 P14 -

I/O - P9 B5 P11 P15 122I/O - P10 B6 P12 P16 125I/O, TMS P17 P11 A5 P13 P17 128I/O P18 P12 C7 P14 P18 131I/O - P13 B7 P15 P21 134I/O - P14 A6 P16 P22 137I/O P19 P15 A7 P17 P23 140I/O P20 P16 A8 P18 P24 143GND P21 P17 C8 P19 P25 -VCC P22 P18 B8 P20 P26 -I/O P23 P19 C9 P21 P27 146I/O P24 P20 B9 P22 P28 149I/O - P21 A9 P23 P29 152I/O - P22 B10 P24 P30 155I/O P25 P23 C10 P25 P33 158I/O P26 P24 A10 P26 P34 161I/O - P25 A11 P27 P35 164I/O - P26 B11 P28 P36 167GND - P27 C11 P29 P37 -I/O - - A12 P30 P40 170I/O - - - P31 P41 173I/O P27 P28 B12 P32 P42 176I/O - P29 A13 P33 P43 179I/O - P30 A14 P34 P44 182I/O - P31 C12 P35 P45 185I/O P28 P32 B13 P36 P46 188I/O, SGCK2 P29 P33 B14 P37 P47 191O (M1) P30 P34 A15 P38 P48 194GND P31 P35 C13 P39 P49 -

XC4006EPad Name

PC84

TQ144

PG156

PQ160

PQ208

BndryScan


R



I (M0) P32 P36 A16 P40 P50 197VCC P33 P37 C14 P41 P55 -I (M2) P34 P38 B15 P42 P56 198I/O, PGCK2 P35 P39 B16 P43 P57 199I/O (HDC) P36 P40 D14 P44 P58 202I/O - P41 C15 P45 P59 205I/O - P42 D15 P46 P60 208I/O - P43 E14 P47 P61 211I/O (LDC) P37 P44 C16 P48 P62 214I/O - - E15 P49 P63 217I/O - - D16 P50 P64 220GND - P45 F14 P51 P67 -I/O - P46 F15 P52 P68 223I/O - P47 E16 P53 P69 226I/O P38 P48 F16 P54 P70 229I/O P39 P49 G14 P55 P71 232I/O - P50 G15 P56 P74 235I/O - P51 G16 P57 P75 238I/O P40 P52 H16 P58 P76 241I/O (INIT) P41 P53 H15 P59 P77 244VCC P42 P54 H14 P60 P78 -GND P43 P55 J14 P61 P79 -I/O P44 P56 J15 P62 P80 247I/O P45 P57 J16 P63 P81 250I/O - P58 K16 P64 P82 253I/O - P59 K15 P65 P83 256I/O P46 P60 K14 P66 P86 259I/O P47 P61 L16 P67 P87 262I/O - P62 M16 P68 P88 265I/O - P63 L15 P69 P89 268GND - P64 L14 P70 P90 -I/O - - N16 P71 P93 271I/O - - M15 P72 P94 274I/O P48 P65 P16 P73 P95 277I/O P49 P66 M14 P74 P96 280I/O - P67 N15 P75 P97 283I/O - P68 P15 P76 P98 286I/O P50 P69 N14 P77 P99 289I/O, SGCK3 P51 P70 R16 P78 P100 292GND P52 P71 P14 P79 P101 -DONE P53 P72 R15 P80 P103 -VCC P54 P73 P13 P81 P106 -PROGRAM P55 P74 R14 P82 P108 -I/O (D7) P56 P75 T16 P83 P109 295I/O, PGCK3 P57 P76 T15 P84 P110 298I/O - P77 R13 P85 P111 301I/O - P78 P12 P86 P112 304I/O (D6) P58 P79 T14 P87 P113 307I/O - P80 T13 P88 P114 310I/O - - R12 P89 P115 313I/O - - T12 P90 P116 316GND - P81 P11 P91 P119 -I/O - P82 R11 P92 P120 319I/O - P83 T11 P93 P121 322I/O (D5) P59 P84 T10 P94 P122 325I/O (CS0) P60 P85 P10 P95 P123 328I/O - P86 R10 P96 P126 331I/O - P87 T9 P97 P127 334I/O (D4) P61 P88 R9 P98 P128 337I/O P62 P89 P9 P99 P129 340VCC P63 P90 R8 P100 P130 -GND P64 P91 P8 P101 P131 -I/O (D3) P65 P92 T8 P102 P132 343I/O (RS) P66 P93 T7 P103 P133 346

XC4006EPad Name

PC84

TQ144

PG156

PQ160

PQ208

BndryScan

I/O - P94 T6 P104 P134 349I/O - P95 R7 P105 P135 352I/O (D2) P67 P96 P7 P106 P138 355I/O P68 P97 T5 P107 P139 358I/O - P98 R6 P108 P140 361I/O - P99 T4 P109 P141 364GND - P100 P6 P110 P142 -I/O - - R5 P111 P145 367I/O - - - P112 P146 370I/O (D1) P69 P101 T3 P113 P147 373I/O (RCLK,RDY/BUSY)

P70 P102 P5 P114 P148 376

I/O - P103 R4 P115 P149 379I/O - P104 R3 P116 P150 382I/O (D0, DIN) P71 P105 P4 P117 P151 385I/O, SGCK4 (DOUT) P72 P106 T2 P118 P152 388CCLK P73 P107 R2 P119 P153 -VCC P74 P108 P3 P120 P154 -O, TDO P75 P109 T1 P121 P159 0GND P76 P110 N3 P122 P160 -I/O (A0, WS) P77 P111 R1 P123 P161 2I/O, PGCK4 (A1) P78 P112 P2 P124 P162 5I/O - P113 N2 P125 P163 8I/O - P114 M3 P126 P164 11I/O (CS1, A2) P79 P115 P1 P127 P165 14I/O (A3) P80 P116 N1 P128 P166 17I/O - P117 M2 P129 P167 20I/O - - M1 P130 P168 23GND - P118 L3 P131 P171 -I/O - P119 L2 P132 P172 26I/O - P120 L1 P133 P173 29I/O (A4) P81 P121 K3 P134 P174 32I/O (A5) P82 P122 K2 P135 P175 35I/O - P123 K1 P137 P178 38I/O - P124 J1 P138 P179 41I/O (A6) P83 P125 J2 P139 P180 44I/O (A7) P84 P126 J3 P140 P181 47GND P1 P127 H2 P141 P182 -5/5/97


P136 - - - -5/5/97


P1 P3 P12 P13 P19P20 P31 P32 P38 P39P51 P52 P53 P54 P65P66 P72 P73 P84 P85P91 P92 P102 P104 P105

P107 P117 P118 P124 P125P136 P137 P143 P144 P155P156 P157 P158 P169 P170P176 P177 P188 P189 P195P196 P206 P207 P208 -

6/5/97

XC4006EPad Name

PC84

TQ144

PG156

PQ160

PQ208

BndryScan


R



XC4008E Pad Name PC84 PQ160 PG191 PQ208 Bndry ScanVCC P2 P142 J4 P183 -I/O (A8) P3 P143 J3 P184 56I/O (A9) P4 P144 J2 P185 59I/O - P145 J1 P186 62I/O - P146 H1 P187 65I/O - - H2 P188 68I/O - - H3 P189 71I/O (A10) P5 P147 G1 P190 74I/O (A11) P6 P148 G2 P191 77I/O - P149 F1 P192 80I/O - P150 E1 P193 83GND - P151 G3 P194 -I/O - P152 C1 P197 86I/O - P153 E2 P198 89I/O (A12) P7 P154 F3 P199 92I/O (A13) P8 P155 D2 P200 95I/O - P156 B1 P201 98I/O - P157 E3 P202 101I/O (A14) P9 P158 C2 P203 104I/O, SGCK1 (A15) P10 P159 B2 P204 107VCC P11 P160 D3 P205 -GND P12 P1 D4 P2 -I/O, PGCK1 (A16) P13 P2 C3 P4 110I/O (A17) P14 P3 C4 P5 113I/O - P4 B3 P6 116I/O - P5 C5 P7 119I/O, TDI P15 P6 A2 P8 122I/O, TCK P16 P7 B4 P9 125I/O - P8 C6 P10 128I/O - P9 A3 P11 131GND - P10 C7 P14 -I/O - P11 A4 P15 134I/O - P12 A5 P16 137I/O, TMS P17 P13 B7 P17 140I/O P18 P14 A6 P18 143I/O - - C8 P19 146I/O - - A7 P20 149I/O - P15 B8 P21 152I/O - P16 A8 P22 155I/O P19 P17 B9 P23 158I/O P20 P18 C9 P24 161GND P21 P19 D9 P25 -VCC P22 P20 D10 P26 -I/O P23 P21 C10 P27 164I/O P24 P22 B10 P28 167I/O - P23 A9 P29 170I/O - P24 A10 P30 173I/O - - A11 P31 176I/O - - C11 P32 179I/O P25 P25 B11 P33 182I/O P26 P26 A12 P34 185I/O - P27 B12 P35 188I/O - P28 A13 P36 191GND - P29 C12 P37 -I/O - P30 A15 P40 194I/O - P31 C13 P41 197I/O P27 P32 B14 P42 200I/O - P33 A16 P43 203I/O - P34 B15 P44 206I/O - P35 C14 P45 209I/O P28 P36 A17 P46 212I/O, SGCK2 P29 P37 B16 P47 215O (M1) P30 P38 C15 P48 218GND P31 P39 D15 P49 -I (M0) P32 P40 A18 P50 221VCC P33 P41 D16 P55 -I (M2) P34 P42 C16 P56 222I/O, PGCK2 P35 P43 B17 P57 223

I/O (HDC) P36 P44 E16 P58 226I/O - P45 C17 P59 229I/O - P46 D17 P60 232I/O - P47 B18 P61 235I/O (LDC) P37 P48 E17 P62 238I/O - P49 F16 P63 241I/O - P50 C18 P64 244GND - P51 G16 P67 -I/O - P52 E18 P68 247I/O - P53 F18 P69 250I/O P38 P54 G17 P70 253I/O P39 P55 G18 P71 256I/O - - H16 P72 259I/O - - H17 P73 262I/O - P56 H18 P74 265I/O - P57 J18 P75 268I/O P40 P58 J17 P76 271I/O (INIT) P41 P59 J16 P77 274VCC P42 P60 J15 P78 -GND P43 P61 K15 P79 -I/O P44 P62 K16 P80 277I/O P45 P63 K17 P81 280I/O - P64 K18 P82 283I/O - P65 L18 P83 286I/O - - L17 P84 289I/O - - L16 P85 292I/O P46 P66 M18 P86 295I/O P47 P67 M17 P87 298I/O - P68 N18 P88 301I/O - P69 P18 P89 304GND - P70 M16 P90 -I/O - P71 T18 P93 307I/O - P72 P17 P94 310I/O P48 P73 N16 P95 313I/O P49 P74 T17 P96 316I/O - P75 R17 P97 319I/O - P76 P16 P98 322I/O P50 P77 U18 P99 325I/O, SGCK3 P51 P78 T16 P100 328GND P52 P79 R16 P101 -DONE P53 P80 U17 P103 -VCC P54 P81 R15 P106 -PROGRAM P55 P82 V18 P108 -I/O (D7) P56 P83 T15 P109 331I/O, PGCK3 P57 P84 U16 P110 334I/O - P85 T14 P111 337I/O - P86 U15 P112 340I/O (D6) P58 P87 V17 P113 343I/O - P88 V16 P114 346I/O - P89 T13 P115 349I/O - P90 U14 P116 352GND - P91 T12 P119 -I/O - P92 U13 P120 355I/O - P93 V13 P121 358I/O (D5) P59 P94 U12 P122 361I/O (CS0) P60 P95 V12 P123 364I/O - - T11 P124 367I/O - - U11 P125 370I/O - P96 V11 P126 373I/O - P97 V10 P127 376I/O (D4) P61 P98 U10 P128 379I/O P62 P99 T10 P129 382VCC P63 P100 R10 P130 -GND P64 P101 R9 P131 -I/O (D3) P65 P102 T9 P132 385I/O (RS) P66 P103 U9 P133 388I/O - P104 V9 P134 391I/O - P105 V8 P135 394I/O - - U8 P136 397

XC4008E Pad Name PC84 PQ160 PG191 PQ208 Bndry Scan


R



I/O - - T8 P137 400I/O (D2) P67 P106 V7 P138 403I/O P68 P107 U7 P139 406I/O - P108 V6 P140 409I/O - P109 U6 P141 412GND - P110 T7 P142 -I/O - P111 U5 P145 415I/O - P112 T6 P146 418I/O (D1) P69 P113 V3 P147 421I/O (RCLK, RDY/BUSY) P70 P114 V2 P148 424I/O - P115 U4 P149 427I/O - P116 T5 P150 430I/O (D0, DIN) P71 P117 U3 P151 433I/O, SGCK4 (DOUT) P72 P118 T4 P152 436CCLK P73 P119 V1 P153 -VCC P74 P120 R4 P154 -O, TDO P75 P121 U2 P159 0GND P76 P122 R3 P160 -I/O (A0, WS) P77 P123 T3 P161 2I/O, PGCK4 (A1) P78 P124 U1 P162 5I/O - P125 P3 P163 8I/O - P126 R2 P164 11I/O (CS1, A2) P79 P127 T2 P165 14I/O (A3) P80 P128 N3 P166 17I/O - P129 P2 P167 20I/O - P130 T1 P168 23GND - P131 M3 P171 -I/O - P132 P1 P172 26I/O - P133 N1 P173 29

XC4008E Pad Name PC84 PQ160 PG191 PQ208 Bndry ScanI/O (A4) P81 P134 M2 P174 32I/O (A5) P82 P135 M1 P175 35I/O - - L3 P176 38I/O - P136 L2 P177 41I/O - P137 L1 P178 44I/O - P138 K1 P179 47I/O (A6) P83 P139 K2 P180 50I/O (A7) P84 P140 K3 P181 53GND P1 P141 K4 P182 -5/5/97


A14 B5 B6 B13 D1 D18F2 F17 N2 N17 R1 R18V4 V5 V14 V15 - -

6/3/97


P1 P3 P12 P13 P38 P39P51 P52 P53 P54 P65 P66P91 P92 P102 P104 P105 P107

P117 P118 P143 P144 P155 P156P157 P158 P169 P170 P195 P196P206 P207 P208 - - -

XC4008E Pad Name PC84 PQ160 PG191 PQ208 Bndry Scan


R


XC4010E/XL Device Pinout TablesThe following table may contain pinout information for unsupported device/package combinations. Please see the availabilitycharts elsewhere in the XC4000 Series data sheet for availability information.

XC4010E/XLPad Name

PC84

PQ100††

TQ144††

PQ160

TQ176††

PG191†

PQ/HQ

208

BG225†

BG256††

BndryScan

VCC P2 P92 P128 P142 P155 VCC* P183 VCC* VCC* -I/O (A8) P3 P93 P129 P143 P156 J3 P184 E8 C10 62I/O (A9) P4 P94 P130 P144 P157 J2 P185 B7 D10 65I/O (19) - P95 P131 P145 P158 J1 P186 A7 A9 68I/O (18) - P96 P132 P146 P159 H1 P187 C7 B9 71I/O - - - - P160 H2 P188 D7 C9 74I/O - - - - P161 H3 P189 E7 D9 77I/O (A10) P5 P97 P133 P147 P162 G1 P190 A6 A8 80I/O (A11) P6 P98 P134 P148 P163 G2 P191 B6 B8 83VCC - - - - - VCC* - VCC* VCC* -I/O - - P135 P149 P164 F1 P192 A5 B6 86I/O - - P136 P150 P165 E1 P193 B5 A5 89GND - - P137 P151 P166 GND* P194 GND* GND* -I/O - - - - - F2 P195 D6 C6 92I/O - - - - P167 D1 P196 C5 B5 95I/O - - - P152 P168 C1 P197 A4 A4 98I/O - - - P153 P169 E2 P198 E6 C5 101I/O (A12) P7 P99 P138 P154 P170 F3 P199 B4 B4 104I/O (A13) P8 P100 P139 P155 P171 D2 P200 D5 A3 107I/O - - P140 P156 P172 B1 P201 B3 B3 110I/O - - P141 P157 P173 E3 P202 F6 B2 113I/O (A14) P9 P1 P142 P158 P174 C2 P203 A2 A2 116I/O, SGCK1 †,GCK8 ††(A15)

P10 P2 P143 P159 P175 B2 P204 C3 C3 119

VCC P11 P3 P144 P160 P176 VCC* P205 VCC* VCC* -GND P12 P4 P1 P1 P1 GND* P2 GND* GND* -I/O, PGCK1†,GCK1††(A16)

P13 P5 P2 P2 P2 C3 P4 D4 B1 122

I/O (A17) P14 P6 P3 P3 P3 C4 P5 B1 C2 125I/O - - P4 P4 P4 B3 P6 C2 D2 128I/O - - P5 P5 P5 C5 P7 E5 D3 131I/O, TDI P15 P7 P6 P6 P6 A2 P8 D3 E4 134I/O, TCK P16 P8 P7 P7 P7 B4 P9 C1 C1 137I/O - - - P8 P8 C6 P10 D2 D1 140I/O - - - P9 P9 A3 P11 G6 E3 143I/O - - - - - B5 P12 E4 E2 146I/O - - - - - B6 P13 D1 E1 149GND - - P8 P10 P10 GND* P14 GND* GND* -I/O - - P9 P11 P11 A4 P15 F5 G3 152I/O - - P10 P12 P12 A5 P16 E1 G2 155I/O, TMS P17 P9 P11 P13 P13 B7 P17 F4 G1 158I/O P18 P10 P12 P14 P14 A6 P18 F3 H3 161VCC - - - - - VCC* - VCC* VCC* -I/O - - - - P15 C8 P19 G4 J2 164I/O - - - - P16 A7 P20 G3 J1 167I/O - - P13 P15 P17 B8 P21 G2 K2 170I/O - P11 P14 P16 P18 A8 P22 G1 K3 173I/O P19 P12 P15 P17 P19 B9 P23 G5 K1 176I/O P20 P13 P16 P18 P20 C9 P24 H3 L1 179GND P21 P14 P17 P19 P21 GND* P25 GND* GND* -VCC P22 P15 P18 P20 P22 VCC* P26 VCC* VCC* -I/O P23 P16 P19 P21 P23 C10 P27 H4 L2 182I/O P24 P17 P20 P22 P24 B10 P28 H5 L3 185I/O - P18 P21 P23 P25 A9 P29 J2 L4 188I/O - - P22 P24 P26 A10 P30 J1 M1 191I/O - - - - P27 A11 P31 J3 M2 194I/O - - - - P28 C11 P32 J4 M3 197VCC - - - - - VCC* - VCC* VCC* -I/O P25 P19 P23 P25 P29 B11 P33 K2 P1 200I/O P26 P20 P24 P26 P30 A12 P34 K3 P2 203I/O - - P25 P27 P31 B12 P35 J6 R1 206I/O - - P26 P28 P32 A13 P36 L1 P3 209GND - - P27 P29 P33 GND* P37 GND* GND* -I/O - - - - - B13 P38 L3 T2 212I/O - - - - - A14 P39 M1 U1 215I/O - - - P30 P34 A15 P40 K5 T3 218I/O - - - P31 P35 C13 P41 M2 U2 221

I/O P27 P21 P28 P32 P36 B14 P42 L4 V1 224I/O - P22 P29 P33 P37 A16 P43 N1 T4 227I/O - - P30 P34 P38 B15 P44 M3 U3 230I/O - - P31 P35 P39 C14 P45 N2 V2 233I/O P28 P23 P32 P36 P40 A17 P46 K6 W1 236I/O, SGCK2 †,GCK2 ††

P29 P24 P33 P37 P41 B16 P47 P1 V3 239

O (M1) P30 P25 P34 P38 P42 C15 P48 N3 W2 242GND P31 P26 P35 P39 P43 GND* P49 GND* GND* -I (M0) P32 P27 P36 P40 P44 A18 P50 P2 Y1 245VCC P33 P28 P37 P41 P45 VCC* P55 VCC* VCC* -I (M2) P34 P29 P38 P42 P46 C16 P56 M4 W3 246I/O, PGCK2 †,GCK3 ††

P35 P30 P39 P43 P47 B17 P57 R2 Y2 247

I/O (HDC) P36 P31 P40 P44 P48 E16 P58 P3 W4 250I/O - - P41 P45 P49 C17 P59 L5 V4 253I/O - - P42 P46 P50 D17 P60 N4 U5 256I/O - P32 P43 P47 P51 B18 P61 R3 Y3 259I/O (LDC) P37 P33 P44 P48 P52 E17 P62 P4 Y4 262I/O - - - P49 P53 F16 P63 K7 V5 265I/O - - - P50 P54 C18 P64 M5 W5 268I/O - - - - - D18 P65 R4 Y5 271I/O - - - - - F17 P66 N5 V6 274GND - - P45 P51 P55 GND* P67 GND* GND* -I/O - - P46 P52 P56 E18 P68 R5 W7 277I/O - - P47 P53 P57 F18 P69 M6 Y7 280I/O P38 P34 P48 P54 P58 G17 P70 N6 V8 283I/O P39 P35 P49 P55 P59 G18 P71 P6 W8 286VCC - - - - - VCC* - VCC* VCC* -I/O - - - - P60 H16 P72 R6 Y8 289I/O - - - - P61 H17 P73 M7 U9 292I/O - P36 P50 P56 P62 H18 P74 R7 V10 295I/O - P37 P51 P57 P63 J18 P75 L7 Y10 298I/O P40 P38 P52 P58 P64 J17 P76 N8 Y11 301I/O (INIT) P41 P39 P53 P59 P65 J16 P77 P8 W11 304VCC P42 P40 P54 P60 P66 VCC* P78 VCC* VCC* -GND P43 P41 P55 P61 P67 GND* P79 GND* GND* -I/O P44 P42 P56 P62 P68 K16 P80 L8 V11 307I/O P45 P43 P57 P63 P69 K17 P81 P9 U11 310I/O - P44 P58 P64 P70 K18 P82 R9 Y12 313I/O - P45 P59 P65 P71 L18 P83 N9 W12 316I/O - - - - P72 L17 P84 M9 V12 319I/O - - - - P73 L16 P85 L9 U12 322VCC - - - - - VCC* - VCC* VCC* -I/O P46 P46 P60 P66 P74 M18 P86 N10 Y15 325I/O P47 P47 P61 P67 P75 M17 P87 K9 V14 328I/O - - P62 P68 P76 N18 P88 R11 W15 331I/O - - P63 P69 P77 P18 P89 P11 Y16 334GND - - P64 P70 P78 GND* P90 GND* GND* -I/O - - - - - N17 P91 R12 Y17 337I/O - - - - - R18 P92 L10 V16 340I/O - - - P71 P79 T18 P93 P12 W17 343I/O - - - P72 P80 P17 P94 M11 Y18 346I/O P48 P48 P65 P73 P81 N16 P95 R13 U16 349I/O P49 P49 P66 P74 P82 T17 P96 N12 V17 352I/O - - P67 P75 P83 R17 P97 P13 W18 355I/O - - P68 P76 P84 P16 P98 K10 Y19 358I/O P50 P50 P69 P77 P85 U18 P99 R14 V18 361I/O, SGCK3 †,GCK4 ††

P51 P51 P70 P78 P86 T16 P100 N13 W19 364

GND P52 P52 P71 P79 P87 GND* P101 GND* GND* -DONE P53 P53 P72 P80 P88 U17 P103 P14 Y20 -VCC P54 P54 P73 P81 P89 VCC* P106 VCC* VCC* -PROGRAM P55 P55 P74 P82 P90 V18 P108 M12 V19 -I/O (D7) P56 P56 P75 P83 P91 T15 P109 P15 U19 367I/O, PGCK3 †,GCK5 ††

P57 P57 P76 P84 P92 U16 P110 N14 U18 370

I/O - - P77 P85 P93 T14 P111 L11 T17 373I/O - - P78 P86 P94 U15 P112 M13 V20 376

XC4010E/XLPad Name

PC84

PQ100††

TQ144††

PQ160

TQ176††

PG191†

PQ/HQ

208

BG225†

BG256††

BndryScan


R


* Pads labelled GND* or VCC* are internally bonded to Ground orVCC planes within the package. They have no direct connection toany specific package pin.† = E only†† = XL only


I/O (D6) P58 P58 P79 P87 P95 V17 P113 J10 T19 379I/O - P59 P80 P88 P96 V16 P114 L12 T20 382I/O - - - P89 P97 T13 P115 M15 R18 385I/O - - - P90 P98 U14 P116 L13 R19 388I/O - - - - - V15 P117 L14 R20 391I/O - - - - - V14 P118 K11 P18 394GND - - P81 P91 P99 GND* P119 GND* GND* -I/O - - P82 P92 P100 U13 P120 K13 N19 397I/O - - P83 P93 P101 V13 P121 K14 N20 400VCC - - - - - VCC* - VCC* VCC* -I/O (D5) P59 P60 P84 P94 P102 U12 P122 K15 M17 403I/O (CS0) P60 P61 P85 P95 P103 V12 P123 J12 M18 406I/O - - - - P104 T11 P124 J13 M20 409I/O - - - - P105 U11 P125 J14 L19 412I/O - P62 P86 P96 P106 V11 P126 J15 L18 415I/O - P63 P87 P97 P107 V10 P127 J11 L20 418I/O (D4) P61 P64 P88 P98 P108 U10 P128 H13 K20 421I/O P62 P65 P89 P99 P109 T10 P129 H14 K19 424VCC P63 P66 P90 P100 P110 VCC* P130 VCC* VCC* -GND P64 P67 P91 P101 P111 GND* P131 GND* GND* -I/O (D3) P65 P68 P92 P102 P112 T9 P132 H12 K18 427I/O (RS) P66 P69 P93 P103 P113 U9 P133 H11 K17 430I/O - P70 P94 P104 P114 V9 P134 G14 J20 433I/O - - P95 P105 P115 V8 P135 G15 J19 436I/O - - - - P116 U8 P136 G13 J18 439I/O - - - - P117 T8 P137 G12 J17 442I/O (D2) P67 P71 P96 P106 P118 V7 P138 G11 H19 445I/O P68 P72 P97 P107 P119 U7 P139 F15 H18 448VCC - - - - - VCC* - VCC* VCC* -I/O - - P98 P108 P120 V6 P140 F14 G19 451I/O - - P99 P109 P121 U6 P141 F13 F20 454GND - - P100 P110 P122 GND* P142 GND* GND* -I/O - - - - - V5 P143 E13 D20 457I/O - - - - - V4 P144 D15 E18 460I/O - - - P111 P123 U5 P145 F11 D19 463I/O - - - P112 P124 T6 P146 D14 C20 466I/O (D1) P69 P73 P101 P113 P125 V3 P147 E12 E17 469I/O (RCLK,RDY/BUSY)

P70 P74 P102 P114 P126 V2 P148 C15 D18 472

I/O - - P103 P115 P127 U4 P149 D13 C19 475I/O - - P104 P116 P128 T5 P150 C14 B20 478I/O (D0, DIN) P71 P75 P105 P117 P129 U3 P151 F10 C18 481I/O, SGCK4 †,GCK6 ††(DOUT)

P72 P76 P106 P118 P130 T4 P152 B15 B19 484

CCLK P73 P77 P107 P119 P131 V1 P153 C13 A20 -VCC P74 P78 P108 P120 P132 VCC* P154 VCC* VCC* -O, TDO P75 P79 P109 P121 P133 U2 P159 A15 A19 0GND P76 P80 P110 P122 P134 GND* P160 GND* GND* -I/O (A0, WS) P77 P81 P111 P123 P135 T3 P161 A14 B18 2I/O, PGCK4 †,GCK7 †† (A1)

P78 P82 P112 P124 P136 U1 P162 B13 B17 5

I/O - - P113 P125 P137 P3 P163 E11 C17 8I/O - - P114 P126 P138 R2 P164 C12 D16 11I/O (CS1, A2) P79 P83 P115 P127 P139 T2 P165 A13 A18 14I/O (A3) P80 P84 P116 P128 P140 N3 P166 B12 A17 17I/O - - P117 P129 P141 P2 P167 A12 A16 20I/O - - - P130 P142 T1 P168 C11 C15 23I/O - - - - - R1 P169 B11 B15 26I/O - - - - - N2 P170 E10 A15 29GND - - P118 P131 P143 GND* P171 GND* GND* -I/O - - P119 P132 P144 P1 P172 A11 B14 32I/O - - P120 P133 P145 N1 P173 D10 A14 35VCC - - - - - VCC* - VCC* VCC* -I/O (A4) P81 P85 P121 P134 P146 M2 P174 A10 C12 38I/O (A5) P82 P86 P122 P135 P147 M1 P175 D9 B12 41I/O - - - - P148 L3 P176 C9 A12 44I/O - - - P136 P149 L2 P177 B9 B11 47I/O (A21)†† - P87 P123 P137 P150 L1 P178 A9 C11 50I/O (A20)†† - P88 P124 P138 P151 K1 P179 E9 A11 53I/O (A6) P83 P89 P125 P139 P152 K2 P180 C8 A10 56I/O (A7) P84 P90 P126 P140 P153 K3 P181 B8 B10 59GND P1 P91 P127 P141 P154 GND* P182 GND* GND* -6/19/97

XC4010E/XLPad Name

PC84

PQ100††

TQ144††

PQ160

TQ176††

PG191†

PQ/HQ

208

BG225†

BG256††

BndryScan

PQ/HQ208Not Connected Pins

P1 P3 P51 P52 P53 P54 P102P104 P105 P107 P155 P156 P157 P158P206 P207 P208 - - - -

5/27/97

PG191VCC Pins

D3 D10 D16 J4 J15 R4 R10R15 - - - - - -

GND PinsC7 C12 D4 D9 D15 G3 G16K4 K15 M3 M16 R3 R9 R16T7 T12 - - - - -

5/27/97


R



BG225VCC Pins

B2 B14 D8 H1 H15 R1 R8R15 - - - - - -

GND PinsA1 A8 D12 F8 G7 G8 G9H2 H6 H7 H8 H9 H10 J7J8 J9 K8 M8 - - -

Not Connected PinsA3 B10 C4 C6 C10 D11 E2E3 E14 E15 F1 F2 F7 F9F12 G10 J5 K1 K4 K12 L2L6 L15 M10 M14 N7 N11 N15P5 P7 P10 R10 - - -

6/16/97

BG256

VCC PinsC14 D6 D7 D11 D14 D15 E20F1 F4 F17 G4 G17 K4 L17P4 P17 P19 R2 R4 R17 U6U7 U10 U14 U15 V7 W20 -

GND PinsA1 B7 D4 D8 D13 D17 G20H4 H17 N3 N4 N17 U4 U8

U13 U17 W14 - - - -Not Connected Pins

A6 A7 A13 B13 B16 C4 C7C8 C13 C16 D5 D12 E19 F2F3 F18 F19 G18 H1 H2 H20J3 J4 M4 M19 N1 N2 N18

P20 R3 T1 T18 U20 V9 V13V15 W6 W9 W10 W13 W16 Y6Y9 Y13 Y14 - - - -

5/27/97

XC4013E/XL

Pad Name

HT144††

PQ160

HT176††

PQ/HQ208

PG223†

BG225†

PQ/HQ

240

BG256††

BndryScan

VCC P128 P142 P155 P183 VCC* VCC* P212 VCC* -I/O (A8) P129 P143 P156 P184 J3 E8 P213 C10 74I/O (A9) P130 P144 P157 P185 J2 B7 P214 D10 77I/O(A19) ††

P131 P145 P158 P186 J1 A7 P215 A9 80

I/O(A18) ††

P132 P146 P159 P187 H1 C7 P216 B9 83

I/O - - P160 P188 H2 D7 P217 C9 86I/O - - P161 P189 H3 E7 P218 D9 89I/O (A10) P133 P147 P162 P190 G1 A6 P220 A8 92I/O (A11) P134 P148 P163 P191 G2 B6 P221 B8 95VCC - - - - VCC* VCC* P222 VCC* -I/O - - - - H4 C6 P223 A6 98I/O - - - - G4 F7 P224 C7 101I/O P135 P149 P164 P192 F1 A5 P225 B6 104I/O P136 P150 P165 P193 E1 B5 P226 A5 107GND P137 P151 P166 P194 GND* GND* P227 GND* -I/O - - - P195 F2 D6 P228 C6 110I/O - - P167 P196 D1 C5 P229 B5 113I/O - P152 P168 P197 C1 A4 P230 A4 116I/O - P153 P169 P198 E2 E6 P231 C5 119I/O (A12) P138 P154 P170 P199 F3 B4 P232 B4 122I/O (A13) P139 P155 P171 P200 D2 D5 P233 A3 125I/O - - - - F4 A3 P234 D5 128I/O - - - - E4 C4 P235 C4 131I/O P140 P156 P172 P201 B1 B3 P236 B3 134I/O P141 P157 P173 P202 E3 F6 P237 B2 137I/O (A14) P142 P158 P174 P203 C2 A2 P238 A2 140I/O,SGCK1 †,GCK8 ††(A15)

P143 P159 P175 P204 B2 C3 P239 C3 143

VCC P144 P160 P176 P205 VCC* VCC* P240 VCC* -GND P1 P1 P1 P2 GND* GND* P1 GND* -I/O,PGCK1 †,GCK1 ††(A16)

P2 P2 P2 P4 C3 D4 P2 B1 146

I/O (A17) P3 P3 P3 P5 C4 B1 P3 C2 149I/O P4 P4 P4 P6 B3 C2 P4 D2 152I/O P5 P5 P5 P7 C5 E5 P5 D3 155I/O, TDI P6 P6 P6 P8 A2 D3 P6 E4 158I/O, TCK P7 P7 P7 P9 B4 C1 P7 C1 161I/O - P8 P8 P10 C6 D2 P8 D1 164I/O - P9 P9 P11 A3 G6 P9 E3 167I/O - - - P12 B5 E4 P10 E2 170

I/O - - - P13 B6 D1 P11 E1 173I/O - - - - D5 E3 P12 F3 176I/O - - - - D6 E2 P13 F2 179GND P8 P10 P10 P14 GND* GND* P14 GND* -I/O P9 P11 P11 P15 A4 F5 P15 G3 182I/O P10 P12 P12 P16 A5 E1 P16 G2 185I/O, TMS P11 P13 P13 P17 B7 F4 P17 G1 188I/O P12 P14 P14 P18 A6 F3 P18 H3 191VCC - - - - VCC* VCC* P19 VCC* -I/O - - - - D7 F2 P20 H2 194I/O - - - - D8 F1 P21 H1 197I/O - - P15 P19 C8 G4 P23 J2 200I/O - - P16 P20 A7 G3 P24 J1 203I/O P13 P15 P17 P21 B8 G2 P25 K2 206I/O P14 P16 P18 P22 A8 G1 P26 K3 209I/O P15 P17 P19 P23 B9 G5 P27 K1 212I/O P16 P18 P20 P24 C9 H3 P28 L1 215GND P17 P19 P21 P25 GND* GND* P29 GND* -VCC P18 P20 P22 P26 VCC* VCC* P30 VCC* -I/O P19 P21 P23 P27 C10 H4 P31 L2 218I/O P20 P22 P24 P28 B10 H5 P32 L3 221I/O P21 P23 P25 P29 A9 J2 P33 L4 224I/O P22 P24 P26 P30 A10 J1 P34 M1 227I/O - - P27 P31 A11 J3 P35 M2 230I/O - - P28 P32 C11 J4 P36 M3 233I/O - - - - D11 J5 P38 N1 236I/O - - - - D12 K1 P39 N2 239VCC - - - - VCC* VCC* P40 VCC* -I/O P23 P25 P29 P33 B11 K2 P41 P1 242I/O P24 P26 P30 P34 A12 K3 P42 P2 245I/O P25 P27 P31 P35 B12 J6 P43 R1 248I/O P26 P28 P32 P36 A13 L1 P44 P3 251GND P27 P29 P33 P37 GND* GND* P45 GND* -I/O - - - - D13 L2 P46 T1 254I/O - - - - D14 K4 P47 R3 257I/O - - - P38 B13 L3 P48 T2 260I/O - - - P39 A14 M1 P49 U1 263I/O - P30 P34 P40 A15 K5 P50 T3 266I/O - P31 P35 P41 C13 M2 P51 U2 269I/O P28 P32 P36 P42 B14 L4 P52 V1 272I/O P29 P33 P37 P43 A16 N1 P53 T4 275I/O P30 P34 P38 P44 B15 M3 P54 U3 278I/O P31 P35 P39 P45 C14 N2 P55 V2 281I/O P32 P36 P40 P46 A17 K6 P56 W1 284

XC4013E/XL

Pad Name

HT144††

PQ160

HT176††

PQ/HQ208

PG223†

BG225†

PQ/HQ

240

BG256††

BndryScan


R


I/O,SGCK2 †,GCK2 ††

P33 P37 P41 P47 B16 P1 P57 V3 287

O (M1) P34 P38 P42 P48 C15 N3 P58 W2 290GND P35 P39 P43 P49 GND* GND* P59 GND* -I (M0) P36 P40 P44 P50 A18 P2 P60 Y1 293VCC P37 P41 P45 P55 VCC* VCC* P61 VCC* -I (M2) P38 P42 P46 P56 C16 M4 P62 W3 294I/O,PGCK2 †,GCK3 ††

P39 P43 P47 P57 B17 R2 P63 Y2 295

I/O (HDC) P40 P44 P48 P58 E16 P3 P64 W4 298I/O P41 P45 P49 P59 C17 L5 P65 V4 301I/O P42 P46 P50 P60 D17 N4 P66 U5 304I/O P43 P47 P51 P61 B18 R3 P67 Y3 307I/O (LDC) P44 P48 P52 P62 E17 P4 P68 Y4 310I/O - P49 P53 P63 F16 K7 P69 V5 313I/O - P50 P54 P64 C18 M5 P70 W5 316I/O - - - P65 D18 R4 P71 Y5 319I/O - - - P66 F17 N5 P72 V6 322I/O - - - - E15 P5 P73 W6 325I/O - - - - F15 L6 P74 Y6 328GND P45 P51 P55 P67 GND* GND* P75 GND* -I/O P46 P52 P56 P68 E18 R5 P76 W7 331I/O P47 P53 P57 P69 F18 M6 P77 Y7 334I/O P48 P54 P58 P70 G17 N6 P78 V8 337I/O P49 P55 P59 P71 G18 P6 P79 W8 340VCC - - - - VCC* VCC* P80 VCC* -I/O - - P60 P72 H16 R6 P81 Y8 343I/O - - P61 P73 H17 M7 P82 U9 346I/O - - - - G15 N7 P84 Y9 349I/O - - - - H15 P7 P85 W10 352I/O P50 P56 P62 P74 H18 R7 P86 V10 355I/O P51 P57 P63 P75 J18 L7 P87 Y10 358I/O P52 P58 P64 P76 J17 N8 P88 Y11 361I/O (INIT) P53 P59 P65 P77 J16 P8 P89 W11 364VCC P54 P60 P66 P78 VCC* VCC* P90 VCC* -GND P55 P61 P67 P79 GND* GND* P91 GND* -I/O P56 P62 P68 P80 K16 L8 P92 V11 367I/O P57 P63 P69 P81 K17 P9 P93 U11 370I/O P58 P64 P70 P82 K18 R9 P94 Y12 373I/O P59 P65 P71 P83 L18 N9 P95 W12 376I/O - - P72 P84 L17 M9 P96 V12 379I/O - - P73 P85 L16 L9 P97 U12 382I/O - - - - L15 R10 P99 V13 385I/O - - - - M15 P10 P100 Y14 388VCC - - - - VCC* VCC* P101 VCC* -I/O P60 P66 P74 P86 M18 N10 P102 Y15 391I/O P61 P67 P75 P87 M17 K9 P103 V14 394I/O P62 P68 P76 P88 N18 R11 P104 W15 397I/O P63 P69 P77 P89 P18 P11 P105 Y16 400GND P64 P70 P78 P90 GND* GND* P106 GND* -I/O - - - - N15 M10 P107 V15 403I/O - - - - P15 N11 P108 W16 406I/O - - - P91 N17 R12 P109 Y17 409I/O - - - P92 R18 L10 P110 V16 412I/O - P71 P79 P93 T18 P12 P111 W17 415I/O - P72 P80 P94 P17 M11 P112 Y18 418I/O P65 P73 P81 P95 N16 R13 P113 U16 421I/O P66 P74 P82 P96 T17 N12 P114 V17 424I/O P67 P75 P83 P97 R17 P13 P115 W18 427I/O P68 P76 P84 P98 P16 K10 P116 Y19 430I/O P69 P77 P85 P99 U18 R14 P117 V18 433I/O,SGCK3 †,GCK4 ††

P70 P78 P86 P100 T16 N13 P118 W19 436

GND P71 P79 P87 P101 GND* GND* P119 GND* -DONE P72 P80 P88 P103 U17 P14 P120 Y20 -VCC P73 P81 P89 P106 VCC* VCC* P121 VCC* -PRO-GRAM

P74 P82 P90 P108 V18 M12 P122 V19 -

I/O (D7) P75 P83 P91 P109 T15 P15 P123 U19 439I/O,PGCK3 †,GCK5 ††

P76 P84 P92 P110 U16 N14 P124 U18 442

XC4013E/XL

Pad Name

HT144††

PQ160

HT176††

PQ/HQ208

PG223†

BG225†

PQ/HQ

240

BG256††

BndryScan

I/O P77 P85 P93 P111 T14 L11 P125 T17 445I/O P78 P86 P94 P112 U15 M13 P126 V20 448I/O - - - - R14 N15 P127 U20 451I/O - - - - R13 M14 P128 T18 454I/O (D6) P79 P87 P95 P113 V17 J10 P129 T19 457I/O P80 P88 P96 P114 V16 L12 P130 T20 460I/O - P89 P97 P115 T13 M15 P131 R18 463I/O - P90 P98 P116 U14 L13 P132 R19 466I/O - - - P117 V15 L14 P133 R20 469I/O - - - P118 V14 K11 P134 P18 472GND P81 P91 P99 P119 GND* GND* P135 GND* -I/O - - - - R12 L15 P136 P20 475I/O - - - - R11 K12 P137 N18 478I/O P82 P92 P100 P120 U13 K13 P138 N19 481I/O P83 P93 P101 P121 V13 K14 P139 N20 484VCC - - - - VCC* VCC* P140 VCC* -I/O (D5) P84 P94 P102 P122 U12 K15 P141 M17 487I/O (CS0) P85 P95 P103 P123 V12 J12 P142 M18 490I/O - - P104 P124 T11 J13 P144 M20 493I/O - - P105 P125 U11 J14 P145 L19 496I/O P86 P96 P106 P126 V11 J15 P146 L18 499I/O P87 P97 P107 P127 V10 J11 P147 L20 502I/O (D4) P88 P98 P108 P128 U10 H13 P148 K20 505I/O P89 P99 P109 P129 T10 H14 P149 K19 508VCC P90 P100 P110 P130 VCC* VCC* P150 VCC* -GND P91 P101 P111 P131 GND* GND* P151 GND* -I/O (D3) P92 P102 P112 P132 T9 H12 P152 K18 511I/O (RS) P93 P103 P113 P133 U9 H11 P153 K17 514I/O P94 P104 P114 P134 V9 G14 P154 J20 517I/O P95 P105 P115 P135 V8 G15 P155 J19 520I/O - - P116 P136 U8 G13 P156 J18 523I/O - - P117 P137 T8 G12 P157 J17 526I/O (D2) P96 P106 P118 P138 V7 G11 P159 H19 529I/O P97 P107 P119 P139 U7 F15 P160 H18 532VCC - - - - VCC* VCC* P161 VCC* -I/O P98 P108 P120 P140 V6 F14 P162 G19 535I/O P99 P109 P121 P141 U6 F13 P163 F20 538I/O - - - - R8 G10 P164 G18 541I/O - - - - R7 E15 P165 F19 544GND P100 P110 P122 P142 GND* GND* P166 GND* -I/O - - - - R6 E14 P167 F18 547I/O - - - - R5 F12 P168 E19 550I/O - - - P143 V5 E13 P169 D20 553I/O - - - P144 V4 D15 P170 E18 556I/O - P111 P123 P145 U5 F11 P171 D19 559I/O - P112 P124 P146 T6 D14 P172 C20 562I/O (D1) P101 P113 P125 P147 V3 E12 P173 E17 565I/O (RCLK,RDY/BUSY)

P102 P114 P126 P148 V2 C15 P174 D18 568

I/O P103 P115 P127 P149 U4 D13 P175 C19 571I/O P104 P116 P128 P150 T5 C14 P176 B20 574I/O (D0,DIN)

P105 P117 P129 P151 U3 F10 P177 C18 577

I/O,SGCK4 †,GCK6 ††(DOUT)

P106 P118 P130 P152 T4 B15 P178 B19 580

CCLK P107 P119 P131 P153 V1 C13 P179 A20 -VCC P108 P120 P132 P154 VCC* VCC* P180 VCC* -O, TDO P109 P121 P133 P159 U2 A15 P181 A19 0GND P110 P122 P134 P160 GND* GND* P182 GND* -I/O (A0,WS)

P111 P123 P135 P161 T3 A14 P183 B18 2

I/O,PGCK4 †,GCK7 ††(A1)

P112 P124 P136 P162 U1 B13 P184 B17 5

I/O P113 P125 P137 P163 P3 E11 P185 C17 8I/O P114 P126 P138 P164 R2 C12 P186 D16 11I/O (CS1,A2)

P115 P127 P139 P165 T2 A13 P187 A18 14

I/O (A3) P116 P128 P140 P166 N3 B12 P188 A17 17I/O - - - - P4 F9 P189 C16 20I/O - - - - N4 D11 P190 B16 23

XC4013E/XL

Pad Name

HT144††

PQ160

HT176††

PQ/HQ208

PG223†

BG225†

PQ/HQ

240

BG256††

BndryScan


R


* Pads labelled GND* or VCC* are internally bonded to Ground orVCC planes within the package. They have no direct connection toany specific package pin.† = E only, †† = XL only


The BG225 package pins in this table are bonded to an internalGround plane on the XC4013E die. They must all be externally con-nected to Ground.

‡ Pins marked with this symbol are used for Ground connections onsome revisions of the device. These pins may not physically con-nect to anything on the current device revision. However, theyshould be externally connected to Ground, if possible.

I/O P117 P129 P141 P167 P2 A12 P191 A16 26I/O - P130 P142 P168 T1 C11 P192 C15 29I/O - - - P169 R1 B11 P193 B15 32I/O - - - P170 N2 E10 P194 A15 35GND P118 P131 P143 P171 GND* GND* P196 GND* -I/O P119 P132 P144 P172 P1 A11 P197 B14 38I/O P120 P133 P145 P173 N1 D10 P198 A14 41I/O - - - - M4 C10 P199 C13 44I/O - - - - L4 B10 P200 B13 47VCC - - - - VCC* VCC* P201 VCC* -I/O (A4) P121 P134 P146 P174 M2 A10 P202 C12 50I/O (A5) P122 P135 P147 P175 M1 D9 P203 B12 53I/O - - P148 P176 L3 C9 P205 A12 56I/O - P136 P149 P177 L2 B9 P206 B11 59I/O(A21) ††

P123 P137 P150 P178 L1 A9 P207 C11 62

I/O(A20) ††

P124 P138 P151 P179 K1 E9 P208 A11 65

I/O (A6) P125 P139 P152 P180 K2 C8 P209 A10 68I/O (A7) P126 P140 P153 P181 K3 B8 P210 B10 71GND P127 P141 P154 P182 GND* GND* P211 GND* -6/9/97


P1 P3 P51 P52 P53 P54P102 P104 P105 P107 P155 P156P157 P158 P206 P207 P208 -

5/5/97

PG223VCC Pins

D3 D10 D16 J4 J15 R4R10 R15 - - - -

GND PinsC7 C12 D4 D9 D15 G3

G16 K4 K15 M3 M16 R3R9 R16 T7 T12 - -

5/5/97

XC4013E/XL

Pad Name

HT144††

PQ160

HT176††

PQ/HQ208

PG223†

BG225†

PQ/HQ

240

BG256††

BndryScan BG225

VCC PinsB2 B14 D8 H1 H15R1 R8 R15 - -

GND PinsA1 A8 D12 F8 G7G8 G9 H2 H6 H7H8 H9 H10 J7 J8J9 K8 M8 - -

5/5/97

PQ/HQ240GND Pins

P22‡ P37‡ P83‡ P98‡ P143‡ P158‡P204‡ P219‡ - - - -

Not Connected PinsP195 - - - - -

6/9/97

BG256VCC Pins

C14 D6 D7 D11 D14 D15E20 F1 F4 F17 G4 G17K4 L17 P4 P17 P19 R2R4 R17 U6 U7 U10 U14

U15 V7 W20 - - -GND Pins

A1 B7 D4 D8 D13 D17G20 H4 H17 N3 N4 N17U4 U8 U13 U17 W14 -

Not Connected PinsA7 A13 C8 D12 H20 J3J4 M4 M19 V9 W9 W13

Y13 - - - - -6/4/97


R



XC4020E/XLPad Name

HT144††

PQ160††

HT176††

HQ208†PQ208††

PG223†

HQ240†PQ240††

BG256††

BndryScan

VCC P128 P142 P155 P183 VCC* P212 VCC* -I/O (A8) P129 P143 P156 P184 J3 P213 C10 86I/O (A9) P130 P144 P157 P185 J2 P214 D10 89I/O (A19) †† P131 P145 P158 P186 J1 P215 A9 92I/O (A18) †† P132 P146 P159 P187 H1 P216 B9 95I/O - - P160 P188 H2 P217 C9 98I/O - - P161 P189 H3 P218 D9 101I/O (A10) P133 P147 P162 P190 G1 P220 A8 104I/O (A11) P134 P148 P163 P191 G2 P221 B8 107I/O - - - - - - C8 110I/O - - - - - - A7 113VCC - - - - VCC* P222 VCC* -I/O - - - - H4 P223 A6 116I/O - - - - G4 P224 C7 119I/O P135 P149 P164 P192 F1 P225 B6 122I/O P136 P150 P165 P193 E1 P226 A5 125GND P137 P151 P166 P194 GND* P227 GND* -I/O - - - P195 F2 P228 C6 128I/O - - P167 P196 D1 P229 B5 131I/O - P152 P168 P197 C1 P230 A4 134I/O - P153 P169 P198 E2 P231 C5 137I/O (A12) P138 P154 P170 P199 F3 P232 B4 140I/O (A13) P139 P155 P171 P200 D2 P233 A3 143I/O - - - - F4 P234 D5 152I/O - - - - E4 P235 C4 155I/O P140 P156 P172 P201 B1 P236 B3 158I/O P141 P157 P173 P202 E3 P237 B2 161I/O (A14) P142 P158 P174 P203 C2 P238 A2 164I/O, SGCK1 †,GCK8 †† (A15)

P143 P159 P175 P204 B2 P239 C3 167

VCC P144 P160 P176 P205 VCC* P240 VCC* -GND P1 P1 P1 P2 GND* P1 GND* -I/O, PGCK1 †,GCK1 †† (A16)

P2 P2 P2 P4 C3 P2 B1 170

I/O (A17) P3 P3 P3 P5 C4 P3 C2 173I/O P4 P4 P4 P6 B3 P4 D2 176I/O P5 P5 P5 P7 C5 P5 D3 179I/O, TDI P6 P6 P6 P8 A2 P6 E4 182I/O, TCK P7 P7 P7 P9 B4 P7 C1 185I/O - P8 P8 P10 C6 P8 D1 194I/O - P9 P9 P11 A3 P9 E3 197I/O - - - P12 B5 P10 E2 200I/O - - - P13 B6 P11 E1 203I/O - - - - D5 P12 F3 206I/O - - - - D6 P13 F2 209GND P8 P10 P10 P14 GND* P14 GND* -I/O P9 P11 P11 P15 A4 P15 G3 212I/O P10 P12 P12 P16 A5 P16 G2 215I/O, TMS P11 P13 P13 P17 B7 P17 G1 218I/O P12 P14 P14 P18 A6 P18 H3 221VCC - - - - VCC* P19 VCC* -I/O - - - - D7 P20 H2 224I/O - - - - D8 P21 H1 227I/O - - - - - - J4 230I/O - - - - - - J3 233I/O - - P15 P19 C8 P23 J2 236I/O - - P16 P20 A7 P24 J1 239I/O P13 P15 P17 P21 B8 P25 K2 242I/O P14 P16 P18 P22 A8 P26 K3 245I/O P15 P17 P19 P23 B9 P27 K1 248I/O P16 P18 P20 P24 C9 P28 L1 251GND P17 P19 P21 P25 GND* P29 GND* -VCC P18 P20 P22 P26 VCC* P30 VCC* -I/O P19 P21 P23 P27 C10 P31 L2 254I/O P20 P22 P24 P28 B10 P32 L3 257I/O P21 P23 P25 P29 A9 P33 L4 260I/O P22 P24 P26 P30 A10 P34 M1 263I/O - - P27 P31 A11 P35 M2 266I/O - - P28 P32 C11 P36 M3 269I/O - - - - - - M4 272I/O - - - - D11 P38 N1 278I/O - - - - D12 P39 N2 281VCC - - - - VCC* P40 VCC* -I/O P23 P25 P29 P33 B11 P41 P1 284

I/O P24 P26 P30 P34 A12 P42 P2 287I/O P25 P27 P31 P35 B12 P43 R1 290I/O P26 P28 P32 P36 A13 P44 P3 293GND P27 P29 P33 P37 GND* P45 GND* -I/O - - - - D13 P46 T1 296I/O - - - - D14 P47 R3 299I/O - - - P38 B13 P48 T2 302I/O - - - P39 A14 P49 U1 305I/O - P30 P34 P40 A15 P50 T3 308I/O - P31 P35 P41 C13 P51 U2 311I/O P28 P32 P36 P42 B14 P52 V1 320I/O P29 P33 P37 P43 A16 P53 T4 323I/O P30 P34 P38 P44 B15 P54 U3 326I/O P31 P35 P39 P45 C14 P55 V2 329I/O P32 P36 P40 P46 A17 P56 W1 332I/O, SGCK2 †,GCK2 ††

P33 P37 P41 P47 B16 P57 V3 335

O (M1) P34 P38 P42 P48 C15 P58 W2 338GND P35 P39 P43 P49 GND* P59 GND* -I (M0) P36 P40 P44 P50 A18 P60 Y1 341VCC P37 P41 P45 P55 VCC* P61 VCC* -I (M2) P38 P42 P46 P56 C16 P62 W3 342I/O PGCK2 †,GCK3 ††

P39 P43 P47 P57 B17 P63 Y2 343

I/O (HDC) P40 P44 P48 P58 E16 P64 W4 346I/O P41 P45 P49 P59 C17 P65 V4 349I/O P42 P46 P50 P60 D17 P66 U5 352I/O P43 P47 P51 P61 B18 P67 Y3 355I/O (LDC) P44 P48 P52 P62 E17 P68 Y4 358I/O - P49 P53 P63 F16 P69 V5 367I/O - P50 P54 P64 C18 P70 W5 370I/O - - - P65 D18 P71 Y5 373I/O - - - P66 F17 P72 V6 376I/O - - - - E15 P73 W6 379I/O - - - - F15 P74 Y6 382GND P45 P51 P55 P67 GND* P75 GND* -I/O P46 P52 P56 P68 E18 P76 W7 385I/O P47 P53 P57 P69 F18 P77 Y7 388I/O P48 P54 P58 P70 G17 P78 V8 391I/O P49 P55 P59 P71 G18 P79 W8 394VCC - - - - VCC* P80 VCC* -I/O - - P60 P72 H16 P81 Y8 397I/O - - P61 P73 H17 P82 U9 400I/O - - - - - - V9 403I/O - - - - - - W9 406I/O - - - - G15 P84 Y9 409I/O - - - - H15 P85 W10 412I/O P50 P56 P62 P74 H18 P86 V10 415I/O P51 P57 P63 P75 J18 P87 Y10 418I/O P52 P58 P64 P76 J17 P88 Y11 421I/O (INIT) P53 P59 P65 P77 J16 P89 W11 424VCC P54 P60 P66 P78 VCC* P90 VCC* -GND P55 P61 P67 P79 GND* P91 GND* -I/O P56 P62 P68 P80 K16 P92 V11 427I/O P57 P63 P69 P81 K17 P93 U11 430I/O P58 P64 P70 P82 K18 P94 Y12 433I/O P59 P65 P71 P83 L18 P95 W12 436I/O - - P72 P84 L17 P96 V12 439I/O - - P73 P85 L16 P97 U12 442I/O - - - - - - Y13 445I/O - - - - - - W13 448I/O - - - - L15 P99 V13 451I/O - - - - M15 P100 Y14 454VCC - - - - VCC* P101 VCC* -I/O P60 P66 P74 P86 M18 P102 Y15 457I/O P61 P67 P75 P87 M17 P103 V14 460I/O P62 P68 P76 P88 N18 P104 W15 463I/O P63 P69 P77 P89 P18 P105 Y16 466GND P64 P70 P78 P90 GND* P106 GND* -I/O - - - - N15 P107 V15 469I/O - - - - P15 P108 W16 472I/O - - - P91 N17 P109 Y17 475I/O - - - P92 R18 P110 V16 478I/O - P71 P79 P93 T18 P111 W17 481I/O - P72 P80 P94 P17 P112 Y18 484

XC4020E/XLPad Name

HT144††

PQ160††

HT176††

HQ208†PQ208††

PG223†

HQ240†PQ240††

BG256††

BndryScan


R


† = E only†† = XL only


‡ Pins marked with this symbol are used for Ground connections onsome revisions of the device. These pins may not physically con-nect to anything on the current device revision. However, theyshould be externally connected to Ground, if possible.

I/O P65 P73 P81 P95 N16 P113 U16 493I/O P66 P74 P82 P96 T17 P114 V17 496I/O P67 P75 P83 P97 R17 P115 W18 499I/O P68 P76 P84 P98 P16 P116 Y19 502I/O P69 P77 P85 P99 U18 P117 V18 505I/O, SGCK3 †,GCK4 ††

P70 P78 P86 P100 T16 P118 W19 508

GND P71 P79 P87 P101 GND* P119 GND* -DONE P72 P80 P88 P103 U17 P120 Y20 -VCC P73 P81 P89 P106 VCC* P121 VCC* -PROGRAM P74 P82 P90 P108 V18 P122 V19 -I/O (D7) P75 P83 P91 P109 T15 P123 U19 511I/O, PGCK3 †,GCK5 ††

P76 P84 P92 P110 U16 P124 U18 514

I/O P77 P85 P93 P111 T14 P125 T17 517I/O P78 P86 P94 P112 U15 P126 V20 520I/O - - - - R14 P127 U20 523I/O - - - - R13 P128 T18 526I/O (D6) P79 P87 P95 P113 V17 P129 T19 535I/O P80 P88 P96 P114 V16 P130 T20 538I/O - P89 P97 P115 T13 P131 R18 541I/O - P90 P98 P116 U14 P132 R19 544I/O - - - P117 V15 P133 R20 547I/O - - - P118 V14 P134 P18 550GND P81 P91 P99 P119 GND* P135 GND* -I/O - - - - R12 P136 P20 553I/O - - - - R11 P137 N18 556I/O P82 P92 P100 P120 U13 P138 N19 559I/O P83 P93 P101 P121 V13 P139 N20 562VCC - - - - VCC* P140 VCC* -I/O (D5) P84 P94 P102 P122 U12 P141 M17 565I/O (CS0) P85 P95 P103 P123 V12 P142 M18 568I/O - - - - - - M19 574I/O - - P104 P124 T11 P144 M20 577I/O - - P105 P125 U11 P145 L19 580I/O P86 P96 P106 P126 V11 P146 L18 583I/O P87 P97 P107 P127 V10 P147 L20 586I/O (D4) P88 P98 P108 P128 U10 P148 K20 589I/O P89 P99 P109 P129 T10 P149 K19 592VCC P90 P100 P110 P130 VCC* P150 VCC* -GND P91 P101 P111 P131 GND* P151 GND* -I/O (D3) P92 P102 P112 P132 T9 P152 K18 595I/O (RS) P93 P103 P113 P133 U9 P153 K17 598I/O P94 P104 P114 P134 V9 P154 J20 601I/O P95 P105 P115 P135 V8 P155 J19 604I/O - - P116 P136 U8 P156 J18 607I/O - - P117 P137 T8 P157 J17 610I/O - - - - - - H20 613I/O (D2) P96 P106 P118 P138 V7 P159 H19 619I/O P97 P107 P119 P139 U7 P160 H18 622VCC - - - VCC* P161 VCC* -I/O P98 P108 P120 P140 V6 P162 G19 625I/O P99 P109 P121 P141 U6 P163 F20 628I/O - - - - R8 P164 G18 631I/O - - - - R7 P165 F19 634GND P100 P110 P122 P142 GND* P166 GND* -I/O - - - - R6 P167 F18 637I/O - - - - R5 P168 E19 640I/O - - - P143 V5 P169 D20 643I/O - - - P144 V4 P170 E18 646I/O - P111 P123 P145 U5 P171 D19 649I/O - P112 P124 P146 T6 P172 C20 652I/O (D1) P101 P113 P125 P147 V3 P173 E17 655I/O (RCLK,RDY/BUSY)

P102 P114 P126 P148 V2 P174 D18 658

I/O P103 P115 P127 P149 U4 P175 C19 667I/O P104 P116 P128 P150 T5 P176 B20 670I/O (D0, DIN) P105 P117 P129 P151 U3 P177 C18 673I/O, SGCK4 †,GCK6 †† (DOUT)

P106 P118 P130 P152 T4 P178 B19 676

CCLK P107 P119 P131 P153 V1 P179 A20 -VCC P108 P120 P132 P154 VCC* P180 VCC* -O, TDO P109 P121 P133 P159 U2 P181 A19 0GND P110 P122 P134 P160 GND* P182 GND* -I/O (A0, WS) P111 P123 P135 P161 T3 P183 B18 2I/O, PGCK4 †,GCK7 †† (A1)

P112 P124 P136 P162 U1 P184 B17 5

I/O P113 P125 P137 P163 P3 P185 C17 8I/O P114 P126 P138 P164 R2 P186 D16 11I/O (CS1, A2) P115 P127 P139 P165 T2 P187 A18 14I/O (A3) P116 P128 P140 P166 N3 P188 A17 17

XC4020E/XLPad Name

HT144††

PQ160††

HT176††

HQ208†PQ208††

PG223†

HQ240†PQ240††

BG256††

BndryScan

I/O - - - - P4 P189 C16 26I/O - - - - N4 P190 B16 29I/O P117 P129 P141 P167 P2 P191 A16 32I/O - P130 P142 P168 T1 P192 C15 35I/O - - - P169 R1 P193 B15 38I/O - - - P170 N2 P194 A15 41GND P118 P131 P143 P171 GND* P196 GND* -I/O P119 P132 P144 P172 P1 P197 B14 44I/O P120 P133 P145 P173 N1 P198 A14 47I/O - - - - M4 P199 C13 50I/O - - - - L4 P200 B13 53VCC - - - - VCC* P201 VCC* -I/O - - - - - - A13 56I/O - - - - - - D12 59I/O (A4) P121 P134 P146 P174 M2 P202 C12 62I/O (A5) P122 P135 P147 P175 M1 P203 B12 65I/O - - P148 P176 L3 P205 A12 68I/O - P136 P149 P177 L2 P206 B11 71I/O (A21) †† P123 P137 P150 P178 L1 P207 C11 74I/O (A20) †† P124 P138 P151 P179 K1 P208 A11 77I/O (A6) P125 P139 P152 P180 K2 P209 A10 80I/O (A7) P126 P140 P153 P181 K3 P210 B10 83GND P127 P141 P154 P182 GND* P211 GND* -

6/24/97


P1 P3 P51 P52 P53 P54P102 P104 P105 P107 P155 P156P157 P158 P206 P207 P208 -

5/5/97

PG223VCC Pins

D3 D10 D16 J4 J15 R4R10 R15 - - - -

GND PinsC7 C12 D4 D9 D15 G3

G16 K4 K15 M3 M16 R3R9 R16 T7 T12 - -

5/5/97

PQ/HQ240GND Pins

P22‡ P37‡ P83‡ P98‡ P143‡ P158‡P204‡ P219‡ - - - -

Not Connected PinsP195 - - - - -

6/9/97

BG256VCC Pins

C14 D6 D7 D11 D14 D15E20 F1 F4 F17 G4 G17K4 L17 P4 P17 P19 R2R4 R17 U6 U7 U10 U14

U15 V7 W20 - - -GND Pins

A1 B7 D4 D8 D13 D17G20 H4 H17 N3 N4 N17U4 U8 U13 U17 W14 -

6/17/97

XC4020E/XLPad Name

HT144††

PQ160††

HT176††

HQ208†PQ208††

PG223†

HQ240†PQ240††

BG256††

BndryScan


R


XC4025E, XC4028EX/XL Device Pinout TablesThe following table may contain pinout information for unsupported device/package combinations. Please see the availabilitycharts elsewhere in the XC4000 Series data sheet for availability information.

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan

VCC P142 P183 VCC* P212 VCC* VCC* P38 VCC* -I/O (A8) P143 P184 J3 P213 C10 K2 P37 D14 98I/O (A9) P144 P185 J2 P214 D10 K3 P36 C14 101I/O (A19) ‡ P145 P186 J1 P215 A9 K5 P35 A15 104I/O (A18) ‡ P146 P187 H1 P216 B9 K4 P34 B15 107I/O - P188 H2 P217 C9 J1 P33 C15 110I/O - P189 H3 P218 D9 J2 P32 D15 113I/O (A10) P147 P190 G1 P220 A8 H1 P31 A16 116I/O (A11) P148 P191 G2 P221 B8 J3 P30 B16 119GND - - - - GND* GND* - GND* -I/O - - - - - J4 P29 C16 122I/O - - - - - J5 P28 B17 125I/O - - - - C8 H2 P27 C17 128I/O - - - - A7 G1 P26 B18 131VCC - - VCC* P222 VCC* VCC* P25 VCC* -I/O - - H4 P223 A6 H3 P23 C18 134I/O - - G4 P224 C7 G2 P22 D17 137I/O P149 P192 F1 P225 B6 H4 P21 A20 140I/O P150 P193 E1 P226 A5 F2 P20 B19 143GND P151 P194 GND* P227 GND* GND* P19 GND* -I/O - - - - - H5 P18 C19 146I/O - - - - - G3 P17 D18 149I/O - P195 F2 P228 C6 D1 P16 A21 152I/O - P196 D1 P229 B5 G4 P15 B20 155I/O P152 P197 C1 P230 A4 E2 P14 C20 158I/O P153 P198 E2 P231 C5 F3 P13 B21 161I/O (A12) P154 P199 F3 P232 B4 G5 P12 B22 164I/O (A13) P155 P200 D2 P233 A3 C1 P10 C21 167GND - - - - GND* GND* - GND* -VCC - - - - VCC* VCC* - VCC* -I/O - - - - - F4 P9 D20 170I/O - - - - - E3 P8 A23 173I/O - - F4 P234 D5 D2 P7 D21 176I/O - - E4 P235 C4 C2 P6 C22 179I/O P156 P201 B1 P236 B3 F5 P5 B24 182I/O P157 P202 E3 P237 B2 E4 P4 C23 185I/O (A14) P158 P203 C2 P238 A2 D3 P3 D22 188I/O,SGCK1 †,GCK8 ‡(A15)

P159 P204 B2 P239 C3 C3 P2 C24 191

VCC P160 P205 VCC* P240 VCC* VCC* P1 VCC* -GND P1 P2 GND* P1 GND* GND* P304 GND* -I/O,PGCK1 †,GCK1 ‡(A16)

P2 P4 C3 P2 B1 D4 P303 D23 194

I/O (A17) P3 P5 C4 P3 C2 B2 P302 C25 197I/O P4 P6 B3 P4 D2 B3 P301 D24 200I/O P5 P7 C5 P5 D3 E6 P300 E23 203I/O, TDI P6 P8 A2 P6 E4 D5 P299 C26 206I/O, TCK P7 P9 B4 P7 C1 C4 P298 E24 209I/O - - - - - A3 P297 F24 212I/O - - - - - D6 P296 E25 215VCC - - - - VCC* VCC* - VCC* -GND - - - - GND* GND* - GND* -I/O P8 P10 C6 P8 D1 E7 P295 D26 218I/O P9 P11 A3 P9 E3 B4 P294 G24 221I/O - P12 B5 P10 E2 C5 P293 F25 224I/O - P13 B6 P11 E1 A4 P292 F26 227I/O - - D5 P12 F3 D7 P291 H23 230I/O - - D6 P13 F2 C6 P290 H24 233I/O - - - - - E8 P289 G25 236

I/O - - - - - B5 P288 G26 239GND P10 P14 GND* P14 GND* GND* P287 GND* -I/O P11 P15 A4 P15 G3 B6 P286 J23 242I/O P12 P16 A5 P16 G2 D8 P285 J24 245I/O, TMS P13 P17 B7 P17 G1 C7 P284 H25 248I/O P14 P18 A6 P18 H3 B7 P283 K23 251VCC - - VCC* P19 VCC* VCC* P282 VCC* -I/O - - D7 P20 H2 C8 P280 K24 254I/O - - D8 P21 H1 E9 P279 J25 257I/O - - - - - A7 P278 L24 260I/O - - - - - D9 P277 K25 263GND - - - P22 GND* GND* - GND* -I/O - - - - J4 B8 P276 L25 266I/O - - - - J3 A8 P275 L26 269I/O - P19 C8 P23 J2 C9 P274 M23 272I/O - P20 A7 P24 J1 B9 P273 M24 275I/O P15 P21 B8 P25 K2 E10 P272 M25 278I/O P16 P22 A8 P26 K3 A9 P271 M26 281I/O P17 P23 B9 P27 K1 D10 P270 N24 284I/O P18 P24 C9 P28 L1 C10 P269 N25 287GND P19 P25 GND* P29 GND* GND* P268 GND* -VCC P20 P26 VCC* P30 VCC* VCC* P267 VCC* -I/O P21 P27 C10 P31 L2 B10 P266 N26 290I/O P22 P28 B10 P32 L3 B11 P265 P25 293I/O P23 P29 A9 P33 L4 C11 P264 P23 296I/O P24 P30 A10 P34 M1 E11 P263 P24 299I/O - P31 A11 P35 M2 D11 P262 R26 302I/O - P32 C11 P36 M3 A12 P261 R25 305I/O - - - - M4 B12 P260 R24 308I/O - - - - - A13 P259 R23 311GND - - - P37 GND* GND* - GND* -I/O - - - - - C12 P258 T26 314I/O - - - - - D12 P257 T25 317I/O - - D11 P38 N1 E12 P256 T23 320I/O - - D12 P39 N2 B13 P255 V26 323VCC - - VCC* P40 VCC* VCC* P253 VCC* -I/O P25 P33 B11 P41 P1 A14 P252 U24 326I/O P26 P34 A12 P42 P2 C13 P251 V25 329I/O P27 P35 B12 P43 R1 B14 P250 V24 332I/O P28 P36 A13 P44 P3 D13 P249 U23 335GND P29 P37 GND* P45 GND* GND* P248 GND* -I/O - - - - - B15 P247 Y26 338I/O - - - - - E13 P246 W25 341I/O - - D13 P46 T1 C14 P245 W24 344I/O - - D14 P47 R3 A17 P244 V23 347I/O - P38 B13 P48 T2 D14 P243 AA26 350I/O - P39 A14 P49 U1 B16 P242 Y25 353I/O P30 P40 A15 P50 T3 C15 P241 Y24 356I/O P31 P41 C13 P51 U2 E14 P240 AA25 359GND - - - - GND* GND* - GND* -VCC - - - - VCC* VCC* - VCC* -I/O - - - - - A18 P239 AB25 362I/O - - - - - D15 P238 AA24 365I/O P32 P42 B14 P52 V1 C16 P237 Y23 368I/O P33 P43 A16 P53 T4 B17 P236 AC26 371I/O P34 P44 B15 P54 U3 B18 P235 AA23 374I/O P35 P45 C14 P55 V2 E15 P234 AB24 377I/O P36 P46 A17 P56 W1 D16 P233 AD25 380I/O,SGCK2 †,GCK2 ‡

P37 P47 B16 P57 V3 C17 P232 AC24 383

O (M1) P38 P48 C15 P58 W2 A20 P231 AB23 386GND P39 P49 GND* P59 GND* GND* P230 GND* -

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan


R


I (M0) P40 P50 A18 P60 Y1 C18 P229 AD24 389VCC P41 P55 VCC* P61 VCC* VCC* P228 VCC* -I (M2) P42 P56 C16 P62 W3 D17 P227 AC23 390I/O,PGCK2 †,GCK3 ‡

P43 P57 B17 P63 Y2 B19 P226 AE24 391

I/O (HDC) P44 P58 E16 P64 W4 C19 P225 AD23 394I/O P45 P59 C17 P65 V4 F16 P224 AC22 397I/O P46 P60 D17 P66 U5 E17 P223 AF24 400I/O P47 P61 B18 P67 Y3 D18 P222 AD22 403I/O (LDC) P48 P62 E17 P68 Y4 C20 P221 AE23 406I/O - - - - - F17 P220 AE22 409I/O - - - - - G16 P219 AF23 412VCC - - - - VCC* VCC* - VCC* -GND - - - - GND* GND* - GND* -I/O P49 P63 F16 P69 V5 D19 P218 AD20 415I/O P50 P64 C18 P70 W5 E18 P217 AE21 418I/O - P65 D18 P71 Y5 D20 P216 AF21 421I/O - P66 F17 P72 V6 G17 P215 AC19 424I/O - - E15 P73 W6 F18 P214 AD19 427I/O - - F15 P74 Y6 H16 P213 AE20 430I/O - - - - - E19 P212 AF20 433I/O - - - - - F19 P211 AC18 436GND P51 P67 GND* P75 GND* GND* P210 GND* -I/O P52 P68 E18 P76 W7 H17 P209 AD18 439I/O P53 P69 F18 P77 Y7 G18 P208 AE19 442I/O P54 P70 G17 P78 V8 G19 P207 AC17 445I/O P55 P71 G18 P79 W8 H18 P206 AD17 448VCC - - VCC* P80 VCC* VCC* P204 VCC* -I/O - P72 H16 P81 Y8 J16 P203 AE18 451I/O - P73 H17 P82 U9 G20 P202 AF18 454I/O - - - - - J17 P201 AE17 457I/O - - - - - H19 P200 AE16 460GND - - - P83 GND* GND* - GND* -I/O - - - - V9 H20 P199 AF16 463I/O - - - - W9 J18 P198 AC15 466I/O - - G15 P84 Y9 J19 P197 AD15 469I/O - - H15 P85 W10 K16 P196 AE15 472I/O P56 P74 H18 P86 V10 J20 P195 AF15 475I/O P57 P75 J18 P87 Y10 K17 P194 AD14 478I/O P58 P76 J17 P88 Y11 K18 P193 AE14 481I/O (INIT) P59 P77 J16 P89 W11 K19 P192 AF14 484VCC P60 P78 VCC* P90 VCC* VCC* P191 VCC* -GND P61 P79 GND* P91 GND* GND* P190 GND* -I/O P62 P80 K16 P92 V11 L19 P189 AE13 487I/O P63 P81 K17 P93 U11 L18 P188 AC13 490I/O P64 P82 K18 P94 Y12 L16 P187 AD13 493I/O P65 P83 L18 P95 W12 L17 P186 AF12 496I/O - P84 L17 P96 V12 M20 P185 AE12 499I/O - P85 L16 P97 U12 M19 P184 AD12 502I/O - - - - Y13 N20 P183 AC12 505I/O - - - - W13 M18 P182 AF11 508GND - - - P98 GND* GND* - GND* -I/O - - - - - M17 P181 AE11 511I/O - - - - - M16 P180 AD11 514I/O - - L15 P99 V13 N19 P179 AF9 517I/O - - M15 P100 Y14 P20 P178 AD10 520VCC - - VCC* P101 VCC* VCC* P177 VCC* -I/O P66 P86 M18 P102 Y15 N18 P175 AE9 523I/O P67 P87 M17 P103 V14 P19 P174 AD9 526I/O P68 P88 N18 P104 W15 N17 P173 AC10 529I/O P69 P89 P18 P105 Y16 R19 P172 AF7 532GND P70 P90 GND* P106 GND* GND* P171 GND* -I/O - - - - - N16 P170 AE8 535I/O - - - - - P18 P169 AD8 538I/O - - N15 P107 V15 U20 P168 AC9 541I/O - - P15 P108 W16 P17 P167 AF6 544I/O - P91 N17 P109 Y17 T19 P166 AE7 547

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan

I/O - P92 R18 P110 V16 R18 P165 AD7 550I/O P71 P93 T18 P111 W17 P16 P164 AE6 553I/O P72 P94 P17 P112 Y18 V20 P163 AE5 556GND - - - - GND* GND* - GND* -VCC - - - - VCC* VCC* - VCC* -I/O - - - - - R17 P162 AD6 559I/O - - - - - T18 P161 AC7 562I/O P73 P95 N16 P113 U16 U19 P160 AF4 565I/O P74 P96 T17 P114 V17 V19 P159 AF3 568I/O P75 P97 R17 P115 W18 R16 P158 AD5 571I/O P76 P98 P16 P116 Y19 T17 P157 AE3 574I/O P77 P99 U18 P117 V18 U18 P156 AD4 577I/O,SGCK3 †,GCK4 ‡

P78 P100 T16 P118 W19 X20 P155 AC5 580

GND P79 P101 GND* P119 GND* GND* P154 GND* -DONE P80 P103 U17 P120 Y20 V18 P153 AD3 -VCC P81 P106 VCC* P121 VCC* VCC* P152 VCC* -PRO-GRAM

P82 P108 V18 P122 V19 U17 P151 AC4 -

I/O (D7) P83 P109 T15 P123 U19 W19 P150 AD2 583I/O,PGCK3 †,GCK5 ‡

P84 P110 U16 P124 U18 W18 P149 AC3 586

I/O P85 P111 T14 P125 T17 T15 P148 AB4 589I/O P86 P112 U15 P126 V20 U16 P147 AD1 592I/O - - R14 P127 U20 V17 P146 AA4 595I/O - - R13 P128 T18 X18 P145 AA3 598I/O - - - - - U15 P144 AB2 601I/O - - - - - T14 P143 AC1 604VCC - - - - VCC* VCC* - VCC* -GND - - - - GND* GND* - GND* -I/O (D6) P87 P113 V17 P129 T19 W17 P142 Y3 607I/O P88 P114 V16 P130 T20 V16 P141 AA2 610I/O P89 P115 T13 P131 R18 X17 P140 AA1 613I/O P90 P116 U14 P132 R19 U14 P139 W4 616I/O - P117 V15 P133 R20 V15 P138 W3 619I/O - P118 V14 P134 P18 T13 P137 Y2 622I/O - - - - - W16 P136 Y1 625I/O - - - - - W15 P135 V4 628GND P91 P119 GND* P135 GND* GND* P134 GND* -I/O - - R12 P136 P20 U13 P133 V3 631I/O - - R11 P137 N18 V14 P132 W2 634I/O P92 P120 U13 P138 N19 W14 P131 U4 637I/O P93 P121 V13 P139 N20 V13 P130 U3 640VCC - - VCC* P140 VCC* VCC* P129 VCC* -I/O (D5) P94 P122 U12 P141 M17 T12 P127 V2 643I/O (CS0) P95 P123 V12 P142 M18 X14 P126 V1 646I/O - - - - - U12 P125 U2 649I/O - - - - - W13 P124 T2 652GND - - - P143 GND* GND* - GND* -I/O - - - - - X13 P123 T1 655I/O - - - - M19 V12 P122 R4 658I/O - P124 T11 P144 M20 W12 P121 R3 661I/O - P125 U11 P145 L19 T11 P120 R2 664I/O P96 P126 V11 P146 L18 X12 P119 R1 667I/O P97 P127 V10 P147 L20 U11 P118 P3 670I/O (D4) P98 P128 U10 P148 K20 V11 P117 P2 673I/O P99 P129 T10 P149 K19 W11 P116 P1 676VCC P100 P130 VCC* P150 VCC* VCC* P115 VCC* -GND P101 P131 GND* P151 GND* GND* P114 GND* -I/O (D3) P102 P132 T9 P152 K18 W10 P113 N2 679I/O (RS) P103 P133 U9 P153 K17 V10 P112 N4 682I/O P104 P134 V9 P154 J20 T10 P111 N3 685I/O P105 P135 V8 P155 J19 U10 P110 M1 688I/O - P136 U8 P156 J18 X9 P109 M2 691I/O - P137 T8 P157 J17 W9 P108 M3 694I/O - - - - H20 X8 P107 M4 697

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan


R


* Pads labelled GND* or VCC* are internally bonded to Ground orVCC planes within the associated package. They have no directconnection to any specific package pin.

** XC4028XL in the BG256 package has 16 extra GND balls in cen-ter of package.

† = E only†† = XL only‡ = EX, XL only

Additional XC4025E, XC4028EX/XL PackagePins

Note: These pins may be Not Connected for this device revision,however for compatability with other devices in this package, thesepins should be tied to GND.

I/O - - - - - V9 P106 L1 700GND - - - P158 GND* GND* - GND* -I/O - - - - - U9 P105 L2 703I/O - - - - - T9 P104 L3 706I/O (D2) P106 P138 V7 P159 H19 W8 P103 J1 709I/O P107 P139 U7 P160 H18 X7 P102 K3 712VCC - - VCC* P161 VCC* VCC* P101 VCC* -I/O P108 P140 V6 P162 G19 V8 P99 J2 715I/O P109 P141 U6 P163 F20 W7 P98 J3 718I/O - - R8 P164 G18 U8 P97 K4 721I/O - - R7 P165 F19 W6 P96 G1 724GND P110 P142 GND* P166 GND* GND* P95 GND* -I/O - - - - - T8 P94 H2 727I/O - - - - - V7 P93 H3 730I/O - - R6 P167 F18 X4 P92 J4 733I/O - - R5 P168 E19 U7 P91 F1 736I/O - P143 V5 P169 D20 W5 P90 G2 739I/O - P144 V4 P170 E18 V6 P89 G3 742I/O P111 P145 U5 P171 D19 T7 P88 F2 745I/O P112 P146 T6 P172 C20 X3 P87 E2 748GND - - - - GND* GND* - GND* -VCC - - - - VCC* VCC* - VCC* -I/O (D1) P113 P147 V3 P173 E17 U6 P86 F3 751I/O (RCLK,RDY/BUSY)

P114 P148 V2 P174 D18 V5 P85 G4 754

I/O - - - - - W4 P84 D2 757I/O - - - - - W3 P83 F4 760I/O P115 P149 U4 P175 C19 T6 P82 E3 763I/O P116 P150 T5 P176 B20 U5 P81 C2 766I/O (D0,DIN)

P117 P151 U3 P177 C18 V4 P80 D3 769

I/O,SGCK4 †,GCK6 ‡(DOUT)

P118 P152 T4 P178 B19 X1 P79 E4 772

CCLK P119 P153 V1 P179 A20 V3 P78 C3 -VCC P120 P154 VCC* P180 VCC* VCC* P77 VCC* -O, TDO P121 P159 U2 P181 A19 U4 P76 D4 0GND P122 P160 GND* P182 GND* GND* P75 GND* -I/O (A0,WS)

P123 P161 T3 P183 B18 W2 P74 B3 2

I/O,PGCK4 †,GCK7 ‡(A1)

P124 P162 U1 P184 B17 V2 P73 C4 5

I/O P125 P163 P3 P185 C17 R5 P72 D5 8I/O P126 P164 R2 P186 D16 T4 P71 A3 11I/O (CS1,A2)

P127 P165 T2 P187 A18 U3 P70 D6 14

I/O (A3) P128 P166 N3 P188 A17 V1 P69 C6 17I/O - - - - - R4 P68 B5 20I/O - - - - - P5 P67 A4 23VCC - - - - VCC* VCC* - VCC* -GND - - - - GND* GND* - GND* -I/O - - P4 P189 C16 U2 P66 C7 26I/O - - N4 P190 B16 T3 P65 B6 29I/O P129 P167 P2 P191 A16 U1 P64 A6 32I/O P130 P168 T1 P192 C15 P4 P63 D8 35I/O - P169 R1 P193 B15 R3 P62 B7 38I/O - P170 N2 P194 A15 N5 P61 A7 41I/O - - - P195 - T2 P60 D9 44I/O - - - - - R2 P59 C9 47GND P131 P171 GND* P196 GND* GND* P58 GND* -I/O P132 P172 P1 P197 B14 N4 P57 B8 50I/O P133 P173 N1 P198 A14 P3 P56 D10 53I/O - - M4 P199 C13 P2 P55 C10 56I/O - - L4 P200 B13 N3 P54 B9 59VCC - - VCC* P201 VCC* VCC* P52 VCC* -

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan

I/O - - - - A13 M5 P51 A9 62I/O - - - - D12 P1 P50 D11 65I/O - - - - - M4 P49 B11 68I/O - - - - - N2 P48 A11 71GND - - - - GND* GND* - GND* -I/O (A4) P134 P174 M2 P202 C12 N1 P47 D12 74I/O (A5) P135 P175 M1 P203 B12 M3 P46 C12 77I/O - P176 L3 P205 A12 M2 P45 B12 80I/O P136 P177 L2 P206 B11 L5 P44 A12 83I/O (A21) ‡ P137 P178 L1 P207 C11 M1 P43 C13 86I/O (A20) ‡ P138 P179 K1 P208 A11 L4 P42 B13 89I/O (A6) P139 P180 K2 P209 A10 L3 P41 A13 92I/O (A7) P140 P181 K3 P210 B10 L2 P40 B14 95GND P141 P182 GND* P211 GND* GND* P39 GND* -6/19/97

HQ208Not Connected Pins

P1 P52 P102 P107 P157 P207P3 P53 P104 P155 P158 P208

P51 P54 P105 P156 P2065/9/97

PG223VCC Pins

D3 D10 D16 J4J15 R4 R10 R15

GND PinsC7 C12 D4 D9

D15 G3 G16 K4K15 M3 M16 R3R9 R16 T7 T12

5/9/97

HQ240GND Pins

P204 P2195/9/97

XC4025E,XC4028**

EX/XLPad Name

HQ160††

HQ208‡

PG223†

HQ240

BG256††

PG299

HQ304

BG352‡

BndryScan


R


Note: In XC4025 (no extension) devices in the HQ304 package,P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E andXC4028EX/XL devices. Where necessary for compatibility, this pincan be left unconnected.

XC4036EX/XLDevice Pinout TablesThe following table may contain pinout information for unsupported device/package combinations. Please see the availabilitycharts elsewhere in the XC4000 Series data sheet for availability information.

BG256VCC Pins

C14 D6 D7 D11D14 D15 E20 F1F4 F17 G4 G17K4 L17 P4 P17P19 R2 R4 R17U6 U7 U10 U14

U15 V7 W20 -GND Pins

A1 B7 D4 D8D13 D17 G20 H4H17 N3 N4 N17U4 U8 U13 U17

W14 - - -5/9/97

PG299VCC Pins

A2 A6 A11 A16B20 E1 E5 F20K1 L20 R1 T16T20 W1 X5 X10X15 X19 - -

GND PinsA5 A10 A15 A19B1 E16 E20 F1K20 L1 R20 T1T5 W20 X2 X6

X11 X16 - -6/18/97


P11 P53 P128 P205 P281P24 P100 P176 P254 -

5/15/97

BG352VCC Pins

A10 A17 B2 B25 D7 D13D19 G23 H4 K1 K26 N23P4 U1 U26 W23 Y4 AC8

AC14 AC20 AE2 AE25 AF10 AF17GND Pins

A1 A2 A5 A8 A14 A19A22 A25 A26 B1 B26 E1E26 H1 H26 N1 P26 W1W26 AB1 AB26 AE1 AE26 AF1AF2 AF5 AF8 AF13 AF19 AF22

AF25 AF26 - - - -Not Connected Pins

A18 A24 B4 B10 B23 C1C5 C8 C11 D1 D16 D25F23 J26 K2 L4 L23 T3T4 T24 U25 AB3 AC2 AC6

AC11 AC16 AC21 AC25 AD16 AD21AD26 AE4 AE10 - - -

5/9/97

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan

VCC P142 P183 P212 P38 VCC* VCC* VCC* -I/O (A8) P143 P184 P213 P37 D14 W3 D17 110I/O (A9) P144 P185 P214 P36 C14 Y2 A17 113I/O (A19) P145 P186 P215 P35 A15 V4 C18 116I/O (A18) P146 P187 P216 P34 B15 T2 D18 119I/O - P188 P217 P33 C15 U1 B18 122I/O - P189 P218 P32 D15 V6 A19 125I/O (A10) P147 P190 P220 P31 A16 U3 B19 128I/O (A11) P148 P191 P221 P30 B16 R1 C19 131VCC - - - - VCC* VCC* VCC* -GND - - - - GND* GND* GND* -I/O - - - P29 C16 U5 D19 134I/O - - - P28 B17 T4 A20 137I/O - - - - D16 P2 B20 140I/O - - - - A18 N1 C20 143I/O - - - P27 C17 R5 C21 146I/O - - - P26 B18 M2 A22 149VCC - - P222 P25 VCC* VCC* VCC* -I/O - - P223 P23 C18 L3 B22 152I/O - - P224 P22 D17 T6 C22 155I/O P149 P192 P225 P21 A20 N5 B23 158I/O P150 P193 P226 P20 B19 M4 A24 161GND P151 P194 P227 P19 GND* GND* GND* -I/O - - - P18 C19 K2 D22 164I/O - - - P17 D18 K4 C23 167I/O - P195 P228 P16 A21 P6 B24 170I/O - P196 P229 P15 B20 M6 C24 173I/O P152 P197 P230 P14 C20 J3 A26 176I/O P153 P198 P231 P13 B21 H2 C25 179I/O (A12) P154 P199 P232 P12 B22 H4 D24 182

I/O (A13) P155 P200 P233 P10 C21 G3 B26 185GND - - - - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P9 D20 K6 A27 188I/O - - - P8 A23 G1 D25 191I/O - - - - A24 E1 C26 194I/O - - - - B23 E3 B27 197I/O - - P234 P7 D21 J7 C27 200I/O - - P235 P6 C22 H6 B28 203I/O P156 P201 P236 P5 B24 C3 D27 206I/O P157 P202 P237 P4 C23 D2 B29 209I/O (A14) P158 P203 P238 P3 D22 E5 C28 212I/O, GCK8 (A15) P159 P204 P239 P2 C24 G7 D28 215VCC P160 P205 P240 P1 VCC* VCC* VCC* -GND P1 P2 P1 P304 GND* GND* GND* -I/O, GCK1 (A16) P2 P4 P2 P303 D23 H8 D29 218I/O (A17) P3 P5 P3 P302 C25 F6 C30 221I/O P4 P6 P4 P301 D24 B4 E28 224I/O P5 P7 P5 P300 E23 D4 E29 227I/O, TDI P6 P8 P6 P299 C26 B2 D30 230I/O, TCK P7 P9 P7 P298 E24 G9 D31 233I/O - - - - D25 F8 E30 236I/O - - - - F23 C5 E31 239I/O - - - P297 F24 A7 G28 242I/O - - - P296 E25 A5 G29 245VCC - - - - VCC* VCC* VCC* -GND - - - - GND* GND* GND* -I/O P8 P10 P8 P295 D26 B8 H28 248I/O P9 P11 P9 P294 G24 C9 H29 251I/O - P12 P10 P293 F25 E9 G30 254

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan


R


I/O - P13 P11 P292 F26 F12 H30 257I/O - - P12 P291 H23 D10 J28 260I/O - - P13 P290 H24 B10 J29 263I/O - - - P289 G25 F10 H31 266I/O - - - P288 G26 F14 J30 269GND P10 P14 P14 P287 GND* GND* GND* -I/O P11 P15 P15 P286 J23 C11 K28 272I/O P12 P16 P16 P285 J24 B12 K29 275I/O, TMS P13 P17 P17 P284 H25 E11 K30 278I/O P14 P18 P18 P283 K23 E15 K31 281VCC - - P19 P282 VCC* VCC* VCC* -I/O - - P20 P280 K24 F16 L29 284I/O - - P21 P279 J25 C13 L30 287I/O - - - - J26 B14 M29 290I/O - - - - L23 E17 M31 293I/O - - - P278 L24 E13 N31 296I/O - - - P277 K25 A15 N28 299GND - - P22 - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P276 L25 B16 P30 302I/O - - - P275 L26 D16 P28 305I/O - P19 P23 P274 M23 D18 P29 308I/O - P20 P24 P273 M24 A17 R31 311I/O P15 P21 P25 P272 M25 E19 R30 314I/O P16 P22 P26 P271 M26 B18 R28 317I/O P17 P23 P27 P270 N24 C17 R29 320I/O P18 P24 P28 P269 N25 C19 T31 323GND P19 P25 P29 P268 GND* GND* GND* -VCC P20 P26 P30 P267 VCC* VCC* VCC* -I/O P21 P27 P31 P266 N26 F20 T30 326I/O P22 P28 P32 P265 P25 B20 T29 329I/O P23 P29 P33 P264 P23 C21 U31 332I/O P24 P30 P34 P263 P24 B22 U30 335I/O - P31 P35 P262 R26 E21 U28 338I/O - P32 P36 P261 R25 D22 U29 341I/O - - - P260 R24 A23 V30 344I/O - - - P259 R23 B24 V29 347VCC - - - - VCC* VCC* VCC* -GND - - P37 - GND* GND* GND* -I/O - - - P258 T26 A25 W30 350I/O - - - P257 T25 D24 W29 353I/O - - - - T24 B26 Y30 356I/O - - - - U25 A27 Y29 359I/O - - P38 P256 T23 C27 Y28 362I/O - - P39 P255 V26 F24 AA30 365VCC - - P40 P253 VCC* VCC* VCC* -I/O P25 P33 P41 P252 U24 E25 AA29 368I/O P26 P34 P42 P251 V25 E27 AB31 371I/O P27 P35 P43 P250 V24 B28 AB30 374I/O P28 P36 P44 P249 U23 C29 AB29 377GND P29 P37 P45 P248 GND* GND* GND* -I/O - - - P247 Y26 F26 AB28 380I/O - - - P246 W25 D28 AC30 383I/O - - P46 P245 W24 B30 AC29 386I/O - - P47 P244 V23 E29 AC28 389I/O - P38 P48 P243 AA26 F28 AD29 392I/O - P39 P49 P242 Y25 F30 AD28 395I/O P30 P40 P50 P241 Y24 C31 AE30 398I/O P31 P41 P51 P240 AA25 E31 AE29 401GND - - - - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P239 AB25 B32 AF31 404I/O - - - P238 AA24 A33 AE28 407I/O P32 P42 P52 P237 Y23 A35 AG31 410I/O P33 P43 P53 P236 AC26 F32 AF28 413I/O - - - - AD26 C35 AG30 416I/O - - - - AC25 B38 AG29 419I/O P34 P44 P54 P235 AA23 E33 AH31 422I/O P35 P45 P55 P234 AB24 G31 AG28 425I/O P36 P46 P56 P233 AD25 H32 AH30 428I/O, GCK2 P37 P47 P57 P232 AC24 B36 AJ30 431O (M1) P38 P48 P58 P231 AB23 A39 AH29 434GND P39 P49 P59 P230 GND* GND* GND* -I (M0) P40 P50 P60 P229 AD24 E35 AH28 437VCC P41 P55 P61 P228 VCC* VCC* VCC* -

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan

I (M2) P42 P56 P62 P227 AC23 G33 AJ28 438I/O, GCK3 P43 P57 P63 P226 AE24 D36 AK29 439I/O (HDC) P44 P58 P64 P225 AD23 C37 AH27 442I/O P45 P59 P65 P224 AC22 F34 AK28 445I/O P46 P60 P66 P223 AF24 J33 AJ27 448I/O P47 P61 P67 P222 AD22 D38 AL28 451I/O (LDC) P48 P62 P68 P221 AE23 G35 AH26 454I/O - - - - AC21 E39 AL27 457I/O - - - - AD21 K34 AH25 460I/O - - - P220 AE22 F38 AK26 463I/O - - - P219 AF23 G37 AL26 466VCC - - - - VCC* VCC* VCC* -GND - - - - GND* GND* GND* -I/O P49 P63 P69 P218 AD20 H38 AH24 469I/O P50 P64 P70 P217 AE21 J37 AJ25 472I/O - P65 P71 P216 AF21 G39 AK25 475I/O - P66 P72 P215 AC19 M34 AJ24 478I/O - - P73 P214 AD19 N35 AL24 481I/O - - P74 P213 AE20 P34 AH22 484I/O - - - P212 AF20 J35 AJ23 487I/O - - - P211 AC18 L37 AK23 490GND P51 P67 P75 P210 GND* GND* GND* -I/O P52 P68 P76 P209 AD18 M38 AJ22 493I/O P53 P69 P77 P208 AE19 R35 AK22 496I/O P54 P70 P78 P207 AC17 H36 AL22 499I/O P55 P71 P79 P206 AD17 T34 AJ21 502VCC - - P80 P204 VCC* VCC* VCC* -I/O - P72 P81 P203 AE18 N37 AH20 505I/O - P73 P82 P202 AF18 N39 AK21 508I/O - - - - AC16 U35 AK20 511I/O - - - - AD16 R39 AJ19 514I/O - - - P201 AE17 M36 AL20 517I/O - - - P200 AE16 V34 AH18 520GND - - P83 - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P199 AF16 R37 AK19 523I/O - - - P198 AC15 T38 AJ18 526I/O - - P84 P197 AD15 T36 AL19 529I/O - - P85 P196 AE15 V36 AK18 532I/O P56 P74 P86 P195 AF15 U37 AH17 535I/O P57 P75 P87 P194 AD14 U39 AJ17 538I/O P58 P76 P88 P193 AE14 V38 AJ16 541I/O (INIT) P59 P77 P89 P192 AF14 W37 AK16 544VCC P60 P78 P90 P191 VCC* VCC* VCC* -GND P61 P79 P91 P190 GND* GND* GND* -I/O P62 P80 P92 P189 AE13 Y34 AL16 547I/O P63 P81 P93 P188 AC13 AC37 AH15 550I/O P64 P82 P94 P187 AD13 AB38 AK15 553I/O P65 P83 P95 P186 AF12 AD36 AJ14 556I/O - P84 P96 P185 AE12 AA35 AH14 559I/O - P85 P97 P184 AD12 AE37 AK14 562I/O - - - P183 AC12 AB36 AL13 565I/O - - - P182 AF11 AD38 AK13 568VCC - - - - VCC* VCC* VCC* -GND - - P98 - GND* GND* GND* -I/O - - - P181 AE11 AB34 AJ13 571I/O - - - P180 AD11 AE39 AH13 574I/O - - - - AE10 AM36 AL12 577I/O - - - - AC11 AC35 AK12 580I/O - - P99 P179 AF9 AG39 AH12 583I/O - - P100 P178 AD10 AG37 AJ11 586VCC - - P101 P177 VCC* VCC* VCC* -I/O P66 P86 P102 P175 AE9 AD34 AL10 589I/O P67 P87 P103 P174 AD9 AN39 AK10 592I/O P68 P88 P104 P173 AC10 AE35 AJ10 595I/O P69 P89 P105 P172 AF7 AH38 AK9 598GND P70 P90 P106 P171 GND* GND* GND* -I/O - - - P170 AE8 AJ37 AL8 601I/O - - - P169 AD8 AG35 AH10 604I/O - - P107 P168 AC9 AF34 AJ9 607I/O - - P108 P167 AF6 AH36 AK8 610I/O - P91 P109 P166 AE7 AK36 AK7 613I/O - P92 P110 P165 AD7 AM34 AL6 616I/O P71 P93 P111 P164 AE6 AH34 AJ7 619I/O P72 P94 P112 P163 AE5 AJ35 AH8 622

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan


R


GND - - - - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P162 AD6 AL37 AK6 625I/O - - - P161 AC7 AT38 AL5 628I/O P73 P95 P113 P160 AF4 AM38 AH7 631I/O P74 P96 P114 P159 AF3 AN37 AJ6 634I/O - - - - AE4 AK34 AK5 637I/O - - - - AC6 AR39 AL4 640I/O P75 P97 P115 P158 AD5 AN35 AK4 643I/O P76 P98 P116 P157 AE3 AL33 AH5 646I/O P77 P99 P117 P156 AD4 AV38 AK3 649I/O, GCK4 P78 P100 P118 P155 AC5 AT36 AJ4 652GND P79 P101 P119 P154 GND* GND* GND* -DONE P80 P103 P120 P153 AD3 AR35 AH4 -VCC P81 P106 P121 P152 VCC* VCC* VCC* -PROGRAM P82 P108 P122 P151 AC4 AN33 AH3 -I/O (D7) P83 P109 P123 P150 AD2 AM32 AJ2 655I/O, GCK5 P84 P110 P124 P149 AC3 AP34 AG4 658I/O P85 P111 P125 P148 AB4 AW39 AG3 661I/O P86 P112 P126 P147 AD1 AN31 AH2 664I/O - - - - AB3 AV36 AH1 667I/O - - - - AC2 AR33 AF4 670I/O - - P127 P146 AA4 AP32 AF3 673I/O - - P128 P145 AA3 AU35 AG2 676I/O - - - P144 AB2 AW33 AE3 679I/O - - - P143 AC1 AU33 AF2 682VCC - - - - VCC* VCC* VCC* -GND - - - - GND* GND* GND* -I/O (D6) P87 P113 P129 P142 Y3 AV32 AF1 685I/O P88 P114 P130 P141 AA2 AU31 AD4 688I/O P89 P115 P131 P140 AA1 AR31 AD3 691I/O P90 P116 P132 P139 W4 AP28 AE2 694I/O - P117 P133 P138 W3 AT32 AC3 697I/O - P118 P134 P137 Y2 AV30 AD1 700I/O - - - P136 Y1 AR29 AC2 703I/O - - - P135 V4 AP26 AB4 706GND P91 P119 P135 P134 GND* GND* GND* -I/O - - P136 P133 V3 AU29 AB3 709I/O - - P137 P132 W2 AV28 AB2 712I/O P92 P120 P138 P131 U4 AT28 AB1 715I/O P93 P121 P139 P130 U3 AR25 AA3 718VCC - - P140 P129 VCC* VCC* VCC* -I/O (D5) P94 P122 P141 P127 V2 AP24 AA2 721I/O (CS0) P95 P123 P142 P126 V1 AU27 Y2 724I/O - - - - T4 AR27 Y4 727I/O - - - - T3 AW27 Y3 730I/O - - - P125 U2 AT24 W4 733I/O - - - P124 T2 AR23 W3 736GND - - P143 - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O - - - P123 T1 AP22 V4 739I/O - - - P122 R4 AV24 V3 742I/O - P124 P144 P121 R3 AU23 U1 745I/O - P125 P145 P120 R2 AT22 U2 748I/O P96 P126 P146 P119 R1 AR21 U4 751I/O P97 P127 P147 P118 P3 AV22 U3 754I/O (D4) P98 P128 P148 P117 P2 AP20 T1 757I/O P99 P129 P149 P116 P1 AU21 T2 760VCC P100 P130 P150 P115 VCC* VCC* VCC* -GND P101 P131 P151 P114 GND* GND* GND* -I/O (D3) P102 P132 P152 P113 N2 AU19 T3 763I/O (RS) P103 P133 P153 P112 N4 AV20 R1 766I/O P104 P134 P154 P111 N3 AV18 R2 769I/O P105 P135 P155 P110 M1 AR19 R4 772I/O - P136 P156 P109 M2 AT18 R3 775I/O - P137 P157 P108 M3 AW17 P2 778I/O - - - P107 M4 AV16 P3 781I/O - - - P106 L1 AP18 P4 784VCC - - - - VCC* VCC* VCC* -GND - - P158 - GND* GND* GND* -I/O - - - P105 L2 AR17 N3 787I/O - - - P104 L3 AT16 N4 790I/O - - - - K2 AV14 M1 793I/O - - - - L4 AW13 M2 796I/O (D2) P106 P138 P159 P103 J1 AR15 L2 799

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan

I/O P107 P139 P160 P102 K3 AP16 L3 802VCC - - P161 P101 VCC* VCC* VCC* -I/O P108 P140 P162 P99 J2 AV12 K1 805I/O P109 P141 P163 P98 J3 AR13 K2 808I/O - - P164 P97 K4 AU11 K3 811I/O - - P165 P96 G1 AT12 K4 814GND P110 P142 P166 P95 GND* GND* GND* -I/O - - - P94 H2 AP14 J2 817I/O - - - P93 H3 AR11 J3 820I/O - - P167 P92 J4 AV10 J4 823I/O - - P168 P91 F1 AT8 H1 826I/O - P143 P169 P90 G2 AT10 H2 829I/O - P144 P170 P89 G3 AP10 H3 832I/O P111 P145 P171 P88 F2 AP12 H4 835I/O P112 P146 P172 P87 E2 AR9 G2 838GND - - - - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O (D1) P113 P147 P173 P86 F3 AU7 G4 841I/O (RCLK,RDY/BUSY)

P114 P148 P174 P85 G4 AW7 F2 844

I/O - - - - D1 AW5 F3 847I/O - - - - C1 AV6 E1 850I/O - - - P84 D2 AR7 E3 853I/O - - - P83 F4 AV4 D1 856I/O P115 P149 P175 P82 E3 AN9 E4 859I/O P116 P150 P176 P81 C2 AW1 D2 862I/O (D0, DIN) P117 P151 P177 P80 D3 AP6 C2 865I/O, GCK6(DOUT)

P118 P152 P178 P79 E4 AU3 D3 868

CCLK P119 P153 P179 P78 C3 AR5 D4 -VCC P120 P154 P180 P77 VCC* VCC* VCC* -O, TDO P121 P159 P181 P76 D4 AN7 C4 0GND P122 P160 P182 P75 GND* GND* GND* -I/O (A0, WS) P123 P161 P183 P74 B3 AT4 B3 2I/O, GCK7 (A1) P124 P162 P184 P73 C4 AV2 D5 5I/O P125 P163 P185 P72 D5 AM8 B4 8I/O P126 P164 P186 P71 A3 AL7 C5 11I/O - - - - C5 AR3 B5 14I/O - - - - B4 AR1 C6 17I/O (CS1, A2) P127 P165 P187 P70 D6 AK6 A5 20I/O (A3) P128 P166 P188 P69 C6 AN3 D7 23I/O - - - P68 B5 AM6 B6 26I/O - - - P67 A4 AM2 A6 29VCC - - - - VCC* VCC* VCC* -GND - - - - GND* GND* GND* -I/O - - P189 P66 C7 AL3 D8 32I/O - - P190 P65 B6 AH6 C7 35I/O P129 P167 P191 P64 A6 AP2 B7 38I/O P130 P168 P192 P63 D8 AK4 D9 41I/O - P169 P193 P62 B7 AG5 D10 44I/O - P170 P194 P61 A7 AF6 C9 47I/O - - P195 P60 D9 AL5 B9 50I/O - - - P59 C9 AJ3 C10 53GND P131 P171 P196 P58 GND* GND* GND* -I/O P132 P172 P197 P57 B8 AH2 B10 56I/O P133 P173 P198 P56 D10 AE5 A10 59I/O - - P199 P55 C10 AM4 C11 62I/O - - P200 P54 B9 AD6 D12 65VCC - - P201 P52 VCC* VCC* VCC* -I/O - - - P51 A9 AG3 B11 68I/O - - - P50 D11 AG1 C12 71I/O - - - - C11 AC5 C13 74I/O - - - - B10 AE1 A12 77I/O - - - P49 B11 AH4 D14 80I/O - - - P48 A11 AB6 B13 83GND - - - - GND* GND* GND* -VCC - - - - VCC* VCC* VCC* -I/O (A4) P134 P174 P202 P47 D12 AD2 C14 86I/O (A5) P135 P175 P203 P46 C12 AB4 A13 89I/O - P176 P205 P45 B12 AE3 B14 92I/O P136 P177 P206 P44 A12 AC1 D15 95I/O (A21) P137 P178 P207 P43 C13 AD4 C15 98I/O (A20) P138 P179 P208 P42 B13 AA5 B15 101I/O (A6) P139 P180 P209 P41 A13 AA3 B16 104I/O (A7) P140 P181 P210 P40 B14 Y6 A16 107

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan


R


* Pads labelled GND* or VCC* are internally bonded to Ground or VCCplanes within the associated package. They have no direct connection toany specific package pin.

†† = XL only

Additional XC4036EX/XL Package Pins

The Ground (GND) package pins in the above table should beexternally connected to Ground if possible; however, they can beleft unconnected if necessary for compatibility with other devices.

XC4044XL Device Pinout Tables(Note: XC4044XL is also available in the HQ304 package.The pinout is identical to the XC4036XL in the HQ304. )

GND P141 P182 P211 P39 GND* GND* GND* -6/17/97


P1 P3 P51 P52 P53P54 P102 P104 P105 P107

P155 P156 P157 P158 P206P207 P208 - - -

5/15/97

HQ240GND Pins

P204 P219 - - -6/17/97


P11 P24 P53 P100 P128P176 P205 P254 P281 -

5/15/97

BG352VCC Pins

A10 A17 B2 B25 D7 D13D19 G23 H4 K1 K26 N23P4 U1 U26 W23 Y4 AC8

AC14 AC20 AE2 AE25 AF10 AF17GND Pins

A1 A2 A5 A8 A14 A19A22 A25 A26 B1 B26 E1E26 H1 H26 N1 P26 W1W26 AB1 AB26 AE1 AE26 AF1AF2 AF5 AF8 AF13 AF19 AF22

AF25 AF26 - - - -Not Connected Pins

C8 - - - -6/16/97

XC4036EX/XLPad Name

PQ160††

HQ208††

HQ240

HQ304

BG352

PG411

BG432

BndryScan

PG411VCC Pins

A3 A11 A21 A31 C39 D6F36 J1 L39 W1 AA39 AJ1

AL39 AP4 AT34 AU1 AW9 AW19AW29 AW37 - - - -

GND PinsA9 A19 A29 A37 C1 D14

D20 D26 D34 F4 J39 L1P4 P36 W39 Y4 Y36 AA1

AF4 AF36 AJ39 AL1 AP36 AT6AT14 AT20 AT26 AU39 AW3 AW11AW21 AW31 - - - -

Not Connected PinsA13 B6 B34 C7 C15 C23C25 C33 D8 D12 D30 D32E7 E23 E37 F2 F18 F22G5 H34 J5 K36 K38 L5L35 N3 P38 R3 V2 W5W35 Y38 AA37 AB2 AC3 AC39AF2 AF38 AJ5 AK2 AK38 AL35AN1 AN5 AP8 AP30 AP38 AR37AT2 AT30 AU5 AU9 AU13 AU15

AU17 AU25 AU37 AV8 AV26 AV34AW15 AW23 AW25 AW35 - -

6/16/97

BG432VCC Pins

A1 A11 A21 A31 C3 C29D11 D21 L1 L4 L28 L31AA1 AA4 AA28 AA31 AH11 AH21AJ3 AJ29 AL1 AL11 AL21 AL31

GND PinsA2 A3 A7 A9 A14 A18

A23 A25 A29 A30 B1 B2B30 B31 C1 C31 D16 G1G31 J1 J31 P1 P31 T4T28 V1 V31 AC1 AC31 AE1

AE31 AH16 AJ1 AJ31 AK1 AK2AK30 AK31 AL2 AL3 AL7 AL9AL14 AL18 AL23 AL25 AL29 AL30

Not Connected PinsA4 A8 A15 A28 B8 B12

B17 B21 B25 C8 C16 C17D6 D13 D20 D23 D26 E2F1 F4 F28 F29 F30 F31G3 M3 M4 M28 M30 N1N2 N29 N30 V2 V28 W1W2 W28 W31 Y1 Y31 AC4AD2 AD30 AD31 AE4 AF29 AF30AG1 AH6 AH9 AH19 AH23 AJ5AJ8 AJ12 AJ15 AJ20 AJ26 AK11

AK17 AK24 AK27 AL15 AL17 -5/15/97

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432

VCC P142 P183 P212 VCC* VCC* VCC*I/O (A8) P143 P184 P213 D14 W3 D17I/O (A9) P144 P185 P214 C14 Y2 A17I/O - - - - V2 C17I/O - - - - W5 B17I/O (A19) P145 P186 P215 A15 V4 C18

I/O (A18) P146 P187 P216 B15 T2 D18I/O - P188 P217 C15 U1 B18I/O - P189 P218 D15 V6 A19I/O (A10) P147 P190 P220 A16 U3 B19I/O (A11) P148 P191 P221 B16 R1 C19VCC - - - VCC* VCC* VCC*GND - - - GND* GND* GND*I/O - - - C16 U5 D19I/O - - - B17 T4 A20

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432


R


I/O - - - D16 P2 B20I/O - - - A18 N1 C20I/O - - - C17 R5 C21I/O - - - B18 M2 A22VCC - - P222 VCC* VCC* VCC*I/O - - P223 C18 L3 B22I/O - - P224 D17 T6 C22I/O P149 P192 P225 A20 N5 B23I/O P150 P193 P226 B19 M4 A24GND P151 P194 P227 GND* GND* GND*I/O - - - C19 K2 D22I/O - - - D18 K4 C23I/O - P195 P228 A21 P6 B24I/O - P196 P229 B20 M6 C24I/O - - - - L5 D23I/O - - - - J5 B25I/O P152 P197 P230 C20 J3 A26I/O P153 P198 P231 B21 H2 C25I/O (A12) P154 P199 P232 B22 H4 D24I/O (A13) P155 P200 P233 C21 G3 B26GND - - - GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - D20 K6 A27I/O - - - A23 G1 D25I/O - - - A24 E1 C26I/O - - - B23 E3 B27I/O - - P234 D21 J7 C27I/O - - P235 C22 H6 B28I/O P156 P201 P236 B24 C3 D27I/O P157 P202 P237 C23 D2 B29I/O (A14) P158 P203 P238 D22 E5 C28I/O, GCK8 (A15) P159 P204 P239 C24 G7 D28VCC P160 P205 P240 VCC* VCC* VCC*GND P1 P2 P1 GND* GND* GND*I/O, GCK1 (A16) P2 P4 P2 D23 H8 D29I/O (A17) P3 P5 P3 C25 F6 C30I/O P4 P6 P4 D24 B4 E28I/O P5 P7 P5 E23 D4 E29I/O, TDI P6 P8 P6 C26 B2 D30I/O, TCK P7 P9 P7 E24 G9 D31I/O - - - D25 F8 E30I/O - - - F23 C5 E31I/O - - - F24 A7 G28I/O - - - E25 A5 G29VCC - - - VCC* VCC* VCC*GND - - - GND* GND* GND*I/O - - - - C7 F30I/O - - - - D8 F31I/O P8 P10 P8 D26 B8 H28I/O P9 P11 P9 G24 C9 H29I/O - P12 P10 F25 E9 G30I/O - P13 P11 F26 F12 H30I/O - - P12 H23 D10 J28I/O - - P13 H24 B10 J29I/O - - - G25 F10 H31I/O - - - G26 F14 J30GND P10 P14 P14 GND* GND* GND*I/O P11 P15 P15 J23 C11 K28I/O P12 P16 P16 J24 B12 K29I/O, TMS P13 P17 P17 H25 E11 K30I/O P14 P18 P18 K23 E15 K31VCC - - P19 VCC* VCC* VCC*I/O - - P20 K24 F16 L29I/O - - P21 J25 C13 L30I/O - - - J26 B14 M29I/O - - - L23 E17 M31I/O - - - L24 E13 N31I/O - - - K25 A15 N28GND - - P22 GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - - F18 N29I/O - - - - C15 N30I/O - - - L25 B16 P30I/O - - - L26 D16 P28I/O - P19 P23 M23 D18 P29

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432

I/O - P20 P24 M24 A17 R31I/O P15 P21 P25 M25 E19 R30I/O P16 P22 P26 M26 B18 R28I/O P17 P23 P27 N24 C17 R29I/O P18 P24 P28 N25 C19 T31GND P19 P25 P29 GND* GND* GND*VCC P20 P26 P30 VCC* VCC* VCC*I/O P21 P27 P31 N26 F20 T30I/O P22 P28 P32 P25 B20 T29I/O P23 P29 P33 P23 C21 U31I/O P24 P30 P34 P24 B22 U30I/O - P31 P35 R26 E21 U28I/O - P32 P36 R25 D22 U29I/O - - - R24 A23 V30I/O - - - R23 B24 V29I/O - - - - C23 V28I/O - - - - F22 W31VCC - - - VCC* VCC* VCC*GND - - P37 GND* GND* GND*I/O - - - T26 A25 W30I/O - - - T25 D24 W29I/O - - - T24 B26 Y30I/O - - - U25 A27 Y29I/O - - P38 T23 C27 Y28I/O - - P39 V26 F24 AA30VCC - - P40 VCC* VCC* VCC*I/O P25 P33 P41 U24 E25 AA29I/O P26 P34 P42 V25 E27 AB31I/O P27 P35 P43 V24 B28 AB30I/O P28 P36 P44 U23 C29 AB29GND P29 P37 P45 GND* GND* GND*I/O - - - Y26 F26 AB28I/O - - - W25 D28 AC30I/O - - P46 W24 B30 AC29I/O - - P47 V23 E29 AC28I/O - - - - D30 AD31I/O - - - - D32 AD30I/O - P38 P48 AA26 F28 AD29I/O - P39 P49 Y25 F30 AD28I/O P30 P40 P50 Y24 C31 AE30I/O P31 P41 P51 AA25 E31 AE29GND - - - GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - AB25 B32 AF31I/O - - - AA24 A33 AE28I/O P32 P42 P52 Y23 A35 AG31I/O P33 P43 P53 AC26 F32 AF28I/O - - - AD26 C35 AG30I/O - - - AC25 B38 AG29I/O P34 P44 P54 AA23 E33 AH31I/O P35 P45 P55 AB24 G31 AG28I/O P36 P46 P56 AD25 H32 AH30I/O, GCK2 P37 P47 P57 AC24 B36 AJ30O (M1) P38 P48 P58 AB23 A39 AH29GND P39 P49 P59 GND* GND* GND*I (M0) P40 P50 P60 AD24 E35 AH28VCC P41 P55 P61 VCC* VCC* VCC*I (M2) P42 P56 P62 AC23 G33 AJ28I/O, GCK3 P43 P57 P63 AE24 D36 AK29I/O (HDC) P44 P58 P64 AD23 C37 AH27I/O P45 P59 P65 AC22 F34 AK28I/O P46 P60 P66 AF24 J33 AJ27I/O P47 P61 P67 AD22 D38 AL28I/O (LDC) P48 P62 P68 AE23 G35 AH26I/O - - - AC21 E39 AL27I/O - - - AD21 K34 AH25I/O - - - AE22 F38 AK26I/O - - - AF23 G37 AL26VCC - - - VCC* VCC* VCC*GND - - - GND* GND* GND*I/O P49 P63 P69 AD20 H38 AH24I/O P50 P64 P70 AE21 J37 AJ25I/O - P65 P71 AF21 G39 AK25I/O - P66 P72 AC19 M34 AJ24I/O - - - - K36 AH23

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432


R


I/O - - - - K38 AK24I/O - - P73 AD19 N35 AL24I/O - - P74 AE20 P34 AH22I/O - - - AF20 J35 AJ23I/O - - - AC18 L37 AK23GND P51 P67 P75 GND* GND* GND*I/O P52 P68 P76 AD18 M38 AJ22I/O P53 P69 P77 AE19 R35 AK22I/O P54 P70 P78 AC17 H36 AL22I/O P55 P71 P79 AD17 T34 AJ21VCC - - P80 VCC* VCC* VCC*I/O - P72 P81 AE18 N37 AH20I/O - P73 P82 AF18 N39 AK21I/O - - - AC16 U35 AK20I/O - - - AD16 R39 AJ19I/O - - - AE17 M36 AL20I/O - - - AE16 V34 AH18GND - - P83 GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - AF16 R37 AK19I/O - - - AC15 T38 AJ18I/O - - P84 AD15 T36 AL19I/O - - P85 AE15 V36 AK18I/O P56 P74 P86 AF15 U37 AH17I/O P57 P75 P87 AD14 U39 AJ17I/O - - - - W35 AK17I/O - - - - AC39 AL17I/O P58 P76 P88 AE14 V38 AJ16I/O (INIT) P59 P77 P89 AF14 W37 AK16VCC P60 P78 P90 VCC* VCC* VCC*GND P61 P79 P91 GND* GND* GND*I/O P62 P80 P92 AE13 Y34 AL16I/O P63 P81 P93 AC13 AC37 AH15I/O - - - - Y38 AL15I/O - - - - AA37 AJ15I/O P64 P82 P94 AD13 AB38 AK15I/O P65 P83 P95 AF12 AD36 AJ14I/O - P84 P96 AE12 AA35 AH14I/O - P85 P97 AD12 AE37 AK14I/O - - - AC12 AB36 AL13I/O - - - AF11 AD38 AK13VCC - - - VCC* VCC* VCC*GND - - P98 GND* GND* GND*I/O - - - AE11 AB34 AJ13I/O - - - AD11 AE39 AH13I/O - - - AE10 AM36 AL12I/O - - - AC11 AC35 AK12I/O - - P99 AF9 AG39 AH12I/O - - P100 AD10 AG37 AJ11VCC - - P101 VCC* VCC* VCC*I/O P66 P86 P102 AE9 AD34 AL10I/O P67 P87 P103 AD9 AN39 AK10I/O P68 P88 P104 AC10 AE35 AJ10I/O P69 P89 P105 AF7 AH38 AK9GND P70 P90 P106 GND* GND* GND*I/O - - - AE8 AJ37 AL8I/O - - - AD8 AG35 AH10I/O - - P107 AC9 AF34 AJ9I/O - - P108 AF6 AH36 AK8I/O - - - - AK38 AJ8I/O - - - - AP38 AH9I/O - P91 P109 AE7 AK36 AK7I/O - P92 P110 AD7 AM34 AL6I/O P71 P93 P111 AE6 AH34 AJ7I/O P72 P94 P112 AE5 AJ35 AH8GND - - - GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - AD6 AL37 AK6I/O - - - AC7 AT38 AL5I/O P73 P95 P113 AF4 AM38 AH7I/O P74 P96 P114 AF3 AN37 AJ6I/O - - - AE4 AK34 AK5I/O - - - AC6 AR39 AL4I/O P75 P97 P115 AD5 AN35 AK4I/O P76 P98 P116 AE3 AL33 AH5

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432

I/O P77 P99 P117 AD4 AV38 AK3I/O, GCK4 P78 P100 P118 AC5 AT36 AJ4GND P79 P101 P119 GND* GND* GND*DONE P80 P103 P120 AD3 AR35 AH4VCC P81 P106 P121 VCC* VCC* VCC*PROGRAM P82 P108 P122 AC4 AN33 AH3I/O (D7) P83 P109 P123 AD2 AM32 AJ2I/O, GCK5 P84 P110 P124 AC3 AP34 AG4I/O P85 P111 P125 AB4 AW39 AG3I/O P86 P112 P126 AD1 AN31 AH2I/O - - - AB3 AV36 AH1I/O - - - AC2 AR33 AF4I/O - - P127 AA4 AP32 AF3I/O - - P128 AA3 AU35 AG2I/O - - - AB2 AW33 AE3I/O - - - AC1 AU33 AF2VCC - - - VCC* VCC* VCC*GND - - - GND* GND* GND*I/O (D6) P87 P113 P129 Y3 AV32 AF1I/O P88 P114 P130 AA2 AU31 AD4I/O P89 P115 P131 AA1 AR31 AD3I/O P90 P116 P132 W4 AP28 AE2I/O - - - - AP30 AD2I/O - - - - AT30 AC4I/O - P117 P133 W3 AT32 AC3I/O - P118 P134 Y2 AV30 AD1I/O - - - Y1 AR29 AC2I/O - - - V4 AP26 AB4GND P91 P119 P135 GND* GND* GND*I/O - - P136 V3 AU29 AB3I/O - - P137 W2 AV28 AB2I/O P92 P120 P138 U4 AT28 AB1I/O P93 P121 P139 U3 AR25 AA3VCC - - P140 VCC* VCC* VCC*I/O (D5) P94 P122 P141 V2 AP24 AA2I/O (CS0) P95 P123 P142 V1 AU27 Y2I/O - - - T4 AR27 Y4I/O - - - T3 AW27 Y3I/O - - - U2 AT24 W4I/O - - - T2 AR23 W3GND - - P143 GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O - - - - AW25 W2I/O - - - - AW23 V2I/O - - - T1 AP22 V4I/O - - - R4 AV24 V3I/O - P124 P144 R3 AU23 U1I/O - P125 P145 R2 AT22 U2I/O P96 P126 P146 R1 AR21 U4I/O P97 P127 P147 P3 AV22 U3I/O (D4) P98 P128 P148 P2 AP20 T1I/O P99 P129 P149 P1 AU21 T2VCC P100 P130 P150 VCC* VCC* VCC*GND P101 P131 P151 GND* GND* GND*I/O (D3) P102 P132 P152 N2 AU19 T3I/O (RS) P103 P133 P153 N4 AV20 R1I/O P104 P134 P154 N3 AV18 R2I/O P105 P135 P155 M1 AR19 R4I/O - P136 P156 M2 AT18 R3I/O - P137 P157 M3 AW17 P2I/O - - - M4 AV16 P3I/O - - - L1 AP18 P4I/O - - - - AU17 N1I/O - - - - AW15 N2VCC - - - VCC* VCC* VCC*GND - - P158 GND* GND* GND*I/O - - - L2 AR17 N3I/O - - - L3 AT16 N4I/O - - - K2 AV14 M1I/O - - - L4 AW13 M2I/O (D2) P106 P138 P159 J1 AR15 L2I/O P107 P139 P160 K3 AP16 L3VCC - - P161 VCC* VCC* VCC*I/O P108 P140 P162 J2 AV12 K1I/O P109 P141 P163 J3 AR13 K2

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432


R





I/O - - P164 K4 AU11 K3I/O - - P165 G1 AT12 K4GND P110 P142 P166 GND* GND* GND*I/O - - - H2 AP14 J2I/O - - - H3 AR11 J3I/O - - P167 J4 AV10 J4I/O - - P168 F1 AT8 H1I/O - P143 P169 G2 AT10 H2I/O - P144 P170 G3 AP10 H3I/O P111 P145 P171 F2 AP12 H4I/O P112 P146 P172 E2 AR9 G2I/O - - - - AU9 G3I/O - - - - AV8 F1GND - - - GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O (D1) P113 P147 P173 F3 AU7 G4I/O (RCLK, RDY/BUSY) P114 P148 P174 G4 AW7 F2I/O - - - D1 AW5 F3I/O - - - C1 AV6 E1I/O - - - D2 AR7 E3I/O - - - F4 AV4 D1I/O P115 P149 P175 E3 AN9 E4I/O P116 P150 P176 C2 AW1 D2I/O (D0, DIN) P117 P151 P177 D3 AP6 C2I/O, GCK6 (DOUT) P118 P152 P178 E4 AU3 D3CCLK P119 P153 P179 C3 AR5 D4VCC P120 P154 P180 VCC* VCC* VCC*O, TDO P121 P159 P181 D4 AN7 C4GND P122 P160 P182 GND* GND* GND*I/O (A0, WS) P123 P161 P183 B3 AT4 B3I/O, GCK7 (A1) P124 P162 P184 C4 AV2 D5I/O P125 P163 P185 D5 AM8 B4I/O P126 P164 P186 A3 AL7 C5I/O - - - C5 AR3 B5I/O - - - B4 AR1 C6I/O (CS1,A2) P127 P165 P187 D6 AK6 A5I/O (A3) P128 P166 P188 C6 AN3 D7I/O - - - B5 AM6 B6I/O - - - A4 AM2 A6VCC - - - VCC* VCC* VCC*GND - - - GND* GND* GND*I/O - - P189 C7 AL3 D8I/O - - P190 B6 AH6 C7I/O P129 P167 P191 A6 AP2 B7I/O P130 P168 P192 D8 AK4 D9I/O - - - C8 AN1 B8I/O - - - - AK2 A8I/O - P169 P193 B7 AG5 D10I/O - P170 P194 A7 AF6 C9I/O - - P195 D9 AL5 B9I/O - - - C9 AJ3 C10GND P131 P171 P196 GND* GND* GND*I/O P132 P172 P197 B8 AH2 B10I/O P133 P173 P198 D10 AE5 A10I/O - - P199 C10 AM4 C11I/O - - P200 B9 AD6 D12VCC - - P201 VCC* VCC* VCC*I/O - - - A9 AG3 B11I/O - - - D11 AG1 C12I/O - - - C11 AC5 C13I/O - - - B10 AE1 A12I/O - - - B11 AH4 D14I/O - - - A11 AB6 B13GND - - - GND* GND* GND*VCC - - - VCC* VCC* VCC*I/O (A4) P134 P174 P202 D12 AD2 C14I/O (A5) P135 P175 P203 C12 AB4 A13I/O - P176 P205 B12 AE3 B14I/O P136 P177 P206 A12 AC1 D15I/O (A21) P137 P178 P207 C13 AD4 C15I/O (A20) P138 P179 P208 B13 AA5 B15I/O - - - - AB2 A15I/O - - - - AC3 C16I/O (A6) P139 P180 P209 A13 AA3 B16I/O (A7) P140 P181 P210 B14 Y6 A16

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432

GND P141 P182 P211 GND* GND* GND*6/18//97


P1 P3 P51 P52 P53 P54 P102P104 P105 P107 P155 P156 P157 P158P206 P207 P208 - - - -

5/29/97

HQ240GND Pins

P204 P219 - - - - -5/29/97

BG352VCC Pins

A10 A17 B2 B25 D7 D13 D19G23 H4 K1 K26 N23 P4 U1U26 W23 Y4 AC8 AC14 AC20 AE2

AE25 AF10 AF17 - - - -GND Pins

A1 A2 A5 A8 A14 A19 A22A25 A26 B1 B26 E1 E26 H1H26 N1 P26 W1 W26 AB1 AB26AE1 AE26 AF1 AF2 AF5 AF8 AF13AF19 AF22 AF25 AF26 - - -

6/13/97

PG411VCC Pins

A3 A11 A21 A31 C39 D6 F36J1 L39 W1 AA39 AJ1 AL39 AP4

AT34 AU1 AW9 AW19 AW29 AW37 -GND Pins

A9 A19 A29 A37 C1 D14 D20D26 D34 F4 J39 L1 P4 P36W39 Y4 Y36 AA1 AF4 AF36 AJ39AL1 AP36 AT6 AT14 AT20 AT26 AU39AW3 AW11 AW21 AW31 - - -

Not Connected PinsA13 B6 B34 C25 C33 D12 E7E23 E37 F2 G5 H34 L35 N3P38 R3 AF2 AF38 AJ5 AL35 AN5AP8 AR37 AT2 AU5 AU13 AU15 AU25

AU37 AV26 AV34 AW35 - - -6/2/97

XC4044XLPad Name

HQ160

HQ208

HQ240

BG352

PG411

BG432


R


XC4052XL Device Pinout Tables(Note: XC4052XL is also available in the HQ304 package.The pinout is identical to the XC4036XL in HQ304.)

BG432VCC Pins

A1 A11 A21 A31 C3 C29 D11D21 L1 L4 L28 L31 AA1 AA4

AA28 AA31 AH11 AH21 AJ3 AJ29 AL1AL11 AL21 AL31 - - - -

GND PinsA2 A3 A7 A9 A14 A18 A23

A25 A29 A30 B1 B2 B30 B31C1 C31 D16 G1 G31 J1 J31P1 P31 T4 T28 V1 V31 AC1

AC31 AE1 AE31 AH16 AJ1 AJ31 AK1AK2 AK30 AK31 AL2 AL3 AL7 AL9AL14 AL18 AL23 AL25 AL29 AL30 -

Not Connected PinsA4 A28 B12 B21 C8 D6 D13

D20 D26 E2 F4 F28 F29 M3M4 M28 M30 W1 W28 Y1 Y31AE4 AF29 AF30 AG1 AH6 AH19 AJ5AJ12 AJ20 AJ26 AK11 AK27 - -

5/29/97

XC4052XLPad Name

HQ240

PG411

BG432

BG560

VCC P212 VCC* VCC* VCC*I/O (A8) P213 W3 D17 A17I/O (A9) P214 Y2 A17 B18I/O - V2 C17 C18I/O - W5 B17 E18GND - GND* GND* GND*I/O (A19) P215 V4 C18 C19I/O (A18) P216 T2 D18 D19I/O P217 U1 B18 E19I/O P218 V6 A19 B20I/O (A10) P220 U3 B19 C20I/O (A11) P221 R1 C19 D20VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O - U5 D19 A21I/O - T4 A20 E20I/O - P2 B20 B21I/O - N1 C20 C21I/O - R3 B21 D21I/O - N3 D20 B22GND - GND* GND* GND*I/O - R5 C21 C23I/O - M2 A22 E22VCC P222 VCC* VCC* VCC*I/O P223 L3 B22 B24I/O P224 T6 C22 D23I/O P225 N5 B23 C24I/O P226 M4 A24 A25GND P227 GND* GND* GND*I/O - K2 D22 E23I/O - K4 C23 B25I/O P228 P6 B24 D24I/O P229 M6 C24 C25GND - GND* GND* GND*I/O - L5 D23 E25I/O - J5 B25 C27I/O P230 J3 A26 D26I/O P231 H2 C25 B28I/O (A12) P232 H4 D24 B29I/O (A13) P233 G3 B26 E26

GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - K6 A27 C28I/O - G1 D25 D27I/O - E1 C26 B30I/O - E3 B27 C29I/O - F2 A28 E27I/O - G5 D26 A31GND - GND* GND* GND*I/O P234 J7 C27 D28I/O P235 H6 B28 C30I/O P236 C3 D27 D29I/O P237 D2 B29 E28I/O (A14) P238 E5 C28 D30I/O, GCK8 (A15) P239 G7 D28 E29VCC P240 VCC* VCC* VCC*GND P1 GND* GND* GND*I/O, GCK1 (A16) P2 H8 D29 B33I/O (A17) P3 F6 C30 F29I/O P4 B4 E28 E30I/O P5 D4 E29 D31I/O, TDI P6 B2 D30 F30I/O, TCK P7 G9 D31 C33GND - GND* GND* GND*I/O - E7 F28 G29I/O - B6 F29 E31I/O - F8 E30 D32I/O - C5 E31 G30I/O - A7 G28 F31I/O - A5 G29 H29VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O - C7 F30 H30I/O - D8 F31 G31I/O P8 B8 H28 J29I/O P9 C9 H29 F33I/O P10 E9 G30 G32I/O P11 F12 H30 J30GND - GND* GND* GND*I/O P12 D10 J28 K30I/O P13 B10 J29 H33I/O - F10 H31 L29I/O - F14 J30 K31GND P14 GND* GND* GND*I/O P15 C11 K28 L30

XC4052XLPad Name

HQ240

PG411

BG432

BG560


R


I/O P16 B12 K29 K32I/O, TMS P17 E11 K30 J33I/O P18 E15 K31 M29VCC P19 VCC* VCC* VCC*I/O P20 F16 L29 L32I/O P21 C13 L30 M31GND - GND* GND* GND*I/O - A13 M30 N29I/O - D12 M28 L33I/O - B14 M29 M32I/O - E17 M31 P29I/O - E13 N31 P30I/O - A15 N28 N33GND P22 GND* GND* GND*VCC - VCC* VCC* VCC*I/O - F18 N29 P31I/O - C15 N30 P32I/O - B16 P30 R29I/O - D16 P28 R30I/O P23 D18 P29 R31I/O P24 A17 R31 R33GND - GND* GND* GND*I/O P25 E19 R30 T31I/O P26 B18 R28 T29I/O P27 C17 R29 U32I/O P28 C19 T31 U31GND P29 GND* GND* GND*VCC P30 VCC* VCC* VCC*I/O P31 F20 T30 U29I/O P32 B20 T29 U30I/O P33 C21 U31 V31I/O P34 B22 U30 V29GND - GND* GND* GND*I/O P35 E21 U28 V30I/O P36 D22 U29 W33I/O - A23 V30 W31I/O - B24 V29 W30I/O - C23 V28 W29I/O - F22 W31 Y32VCC - VCC* VCC* VCC*GND P37 GND* GND* GND*I/O - A25 W30 Y31I/O - D24 W29 Y30I/O - E23 W28 AA32I/O - C25 Y31 AA31I/O - B26 Y30 AA30I/O - A27 Y29 AB32GND - GND* GND* GND*I/O P38 C27 Y28 AA29I/O P39 F24 AA30 AB31VCC P40 VCC* VCC* VCC*I/O P41 E25 AA29 AC31I/O P42 E27 AB31 AB29I/O P43 B28 AB30 AD32I/O P44 C29 AB29 AC30GND P45 GND* GND* GND*I/O - F26 AB28 AD31I/O - D28 AC30 AE33I/O P46 B30 AC29 AC29I/O P47 E29 AC28 AE32GND - GND* GND* GND*I/O - D30 AD31 AG33I/O - D32 AD30 AH33I/O P48 F28 AD29 AE29I/O P49 F30 AD28 AG31I/O P50 C31 AE30 AF30I/O P51 E31 AE29 AH32GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - B32 AF31 AJ32

XC4052XLPad Name

HQ240

PG411

BG432

BG560

I/O - A33 AE28 AF29I/O - C33 AF30 AH31I/O - B34 AF29 AG30I/O P52 A35 AG31 AK32I/O P53 F32 AF28 AJ31GND - GND* GND* GND*I/O - C35 AG30 AG29I/O - B38 AG29 AL33I/O P54 E33 AH31 AH30I/O P55 G31 AG28 AK31I/O P56 H32 AH30 AJ30I/O, GCK2 P57 B36 AJ30 AH29O (M1) P58 A39 AH29 AK30GND P59 GND* GND* GND*I (M0) P60 E35 AH28 AJ29VCC P61 VCC* VCC* VCC*I (M2) P62 G33 AJ28 AN32I/O, GCK3 P63 D36 AK29 AJ28I/O (HDC) P64 C37 AH27 AK29I/O P65 F34 AK28 AL30I/O P66 J33 AJ27 AK28I/O P67 D38 AL28 AM31I/O (LDC) P68 G35 AH26 AJ27GND - GND* GND* GND*I/O - E37 AK27 AN31I/O - H34 AJ26 AL29I/O - E39 AL27 AK27I/O - K34 AH25 AL28I/O - F38 AK26 AJ26I/O - G37 AL26 AM30VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O P69 H38 AH24 AM29I/O P70 J37 AJ25 AK26I/O P71 G39 AK25 AL27I/O P72 M34 AJ24 AJ25I/O - K36 AH23 AN29I/O - K38 AK24 AN28GND - GND* GND* GND*I/O P73 N35 AL24 AL25I/O P74 P34 AH22 AJ23I/O - J35 AJ23 AN26I/O - L37 AK23 AL24GND P75 GND* GND* GND*I/O P76 M38 AJ22 AK23I/O P77 R35 AK22 AN25I/O P78 H36 AL22 AJ22I/O P79 T34 AJ21 AL23VCC P80 VCC* VCC* VCC*I/O P81 N37 AH20 AM24I/O P82 N39 AK21 AK22GND - GND* GND* GND*I/O - P38 AJ20 AK21I/O - L35 AH19 AM22I/O - U35 AK20 AJ20I/O - R39 AJ19 AL21I/O - M36 AL20 AN21I/O - V34 AH18 AK20GND P83 GND* GND* GND*VCC - VCC* VCC* VCC*I/O - R37 AK19 AL20I/O - T38 AJ18 AJ19I/O P84 T36 AL19 AM20I/O P85 V36 AK18 AK19I/O P86 U37 AH17 AL19I/O P87 U39 AJ17 AN19GND - GND* GND* GND*I/O - W35 AK17 AL18I/O - AC39 AL17 AM18I/O P88 V38 AJ16 AK17

XC4052XLPad Name

HQ240

PG411

BG432

BG560


R


I/O (INIT) P89 W37 AK16 AJ17VCC P90 VCC* VCC* VCC*GND P91 GND* GND* GND*I/O P92 Y34 AL16 AL17I/O P93 AC37 AH15 AM17I/O - Y38 AL15 AN17I/O - AA37 AJ15 AK16GND - GND* GND* GND*I/O P94 AB38 AK15 AM16I/O P95 AD36 AJ14 AL15I/O P96 AA35 AH14 AK15I/O P97 AE37 AK14 AJ15I/O - AB36 AL13 AN15I/O - AD38 AK13 AM14VCC - VCC* VCC* VCC*GND P98 GND* GND* GND*I/O - AB34 AJ13 AL14I/O - AE39 AH13 AK14I/O - AM36 AL12 AJ14I/O - AC35 AK12 AN13I/O - AL35 AJ12 AM13I/O - AF38 AK11 AL13GND - GND* GND* GND*I/O P99 AG39 AH12 AK12I/O P100 AG37 AJ11 AN11VCC P101 VCC* VCC* VCC*I/O P102 AD34 AL10 AJ12I/O P103 AN39 AK10 AL11I/O P104 AE35 AJ10 AK11I/O P105 AH38 AK9 AM10GND P106 GND* GND* GND*I/O - AJ37 AL8 AL10I/O - AG35 AH10 AJ11I/O P107 AF34 AJ9 AN9I/O P108 AH36 AK8 AK10GND - GND* GND* GND*I/O - AK38 AJ8 AN7I/O - AP38 AH9 AJ9I/O P109 AK36 AK7 AL7I/O P110 AM34 AL6 AK8I/O P111 AH34 AJ7 AN6I/O P112 AJ35 AH8 AM6GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - AL37 AK6 AJ8I/O - AT38 AL5 AL6I/O P113 AM38 AH7 AK7I/O P114 AN37 AJ6 AM5I/O - AK34 AK5 AM4I/O - AR39 AL4 AJ7GND - GND* GND* GND*I/O - AR37 AH6 AL5I/O - AU37 AJ5 AK6I/O P115 AN35 AK4 AN3I/O P116 AL33 AH5 AK5I/O P117 AV38 AK3 AJ6I/O, GCK4 P118 AT36 AJ4 AL4GND P119 GND* GND* GND*DONE P120 AR35 AH4 AJ5VCC P121 VCC* VCC* VCC*PROGRAM P122 AN33 AH3 AM1I/O (D7) P123 AM32 AJ2 AH5I/O, GCK5 P124 AP34 AG4 AJ4I/O P125 AW39 AG3 AK3I/O P126 AN31 AH2 AH4I/O - AV36 AH1 AL1I/O - AR33 AF4 AG5GND - GND* GND* GND*I/O P127 AP32 AF3 AJ3I/O P128 AU35 AG2 AK2

XC4052XLPad Name

HQ240

PG411

BG432

BG560

I/O - AV34 AG1 AG4I/O - AW35 AE4 AH3I/O - AW33 AE3 AF5I/O - AU33 AF2 AJ2VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O (D6) P129 AV32 AF1 AJ1I/O P130 AU31 AD4 AF4I/O P131 AR31 AD3 AG3I/O P132 AP28 AE2 AE5I/O - AP30 AD2 AH1I/O - AT30 AC4 AF3GND - GND* GND* GND*I/O P133 AT32 AC3 AE3I/O P134 AV30 AD1 AC5I/O - AR29 AC2 AE1I/O - AP26 AB4 AD3GND P135 GND* GND* GND*I/O P136 AU29 AB3 AC4I/O P137 AV28 AB2 AD2I/O P138 AT28 AB1 AB5I/O P139 AR25 AA3 AC3VCC P140 VCC* VCC* VCC*I/O (D5) P141 AP24 AA2 AA5I/O (CS0) P142 AU27 Y2 AB3GND - GND* GND* GND*I/O - AR27 Y4 AB2I/O - AW27 Y3 AA4I/O - AU25 Y1 AA3I/O - AV26 W1 Y5I/O - AT24 W4 Y3I/O - AR23 W3 Y2GND P143 GND* GND* GND*VCC - VCC* VCC* VCC*I/O - AW25 W2 W5I/O - AW23 V2 W4I/O - AP22 V4 W3I/O - AV24 V3 W1I/O P144 AU23 U1 V3I/O P145 AT22 U2 V5GND - GND* GND* GND*I/O P146 AR21 U4 V4I/O P147 AV22 U3 V2I/O (D4) P148 AP20 T1 U5I/O P149 AU21 T2 U4VCC P150 VCC* VCC* VCC*GND P151 GND* GND* GND*I/O (D3) P152 AU19 T3 U3I/O (RS) P153 AV20 R1 T2I/O P154 AV18 R2 T4I/O P155 AR19 R4 R1GND - GND* GND* GND*I/O P156 AT18 R3 R3I/O P157 AW17 P2 R4I/O - AV16 P3 R5I/O - AP18 P4 P2I/O - AU17 N1 P3I/O - AW15 N2 P4VCC - VCC* VCC* VCC*GND P158 GND* GND* GND*I/O - AR17 N3 N1I/O - AT16 N4 P5I/O - AV14 M1 N2I/O - AW13 M2 N3I/O - AU15 M3 N5I/O - AU13 M4 M3GND - GND* GND* GND*I/O (D2) P159 AR15 L2 M4I/O P160 AP16 L3 L1VCC P161 VCC* VCC* VCC*

XC4052XLPad Name

HQ240

PG411

BG432

BG560


R





I/O P162 AV12 K1 K2I/O P163 AR13 K2 L4I/O P164 AU11 K3 J1I/O P165 AT12 K4 K3GND P166 GND* GND* GND*I/O - AP14 J2 L5I/O - AR11 J3 J2I/O P167 AV10 J4 K4I/O P168 AT8 H1 J3GND - GND* GND* GND*I/O P169 AT10 H2 G1I/O P170 AP10 H3 F1I/O P171 AP12 H4 J5I/O P172 AR9 G2 G3I/O - AU9 G3 H4I/O - AV8 F1 F2GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O (D1) P173 AU7 G4 F3I/O (RCLK, RDY/BUSY) P174 AW7 F2 G4I/O - AW5 F3 D2I/O - AV6 E1 E3I/O - AU5 F4 G5I/O - AP8 E2 C1GND - GND* GND* GND*I/O - AR7 E3 F4I/O - AV4 D1 D3I/O P175 AN9 E4 B3I/O P176 AW1 D2 F5I/O (D0, DIN) P177 AP6 C2 E4I/O, GCK6 (DOUT) P178 AU3 D3 D4CCLK P179 AR5 D4 C4VCC P180 VCC* VCC* VCC*O, TDO P181 AN7 C4 E6GND P182 GND* GND* GND*I/O (A0, WS) P183 AT4 B3 D5I/O, GCK7 (A1) P184 AV2 D5 A2I/O P185 AM8 B4 D6I/O P186 AL7 C5 A3I/O - AT2 A4 E7I/O - AN5 D6 C5GND - GND* GND* GND*I/O - AR3 B5 B4I/O - AR1 C6 D7I/O (CS1, A2) P187 AK6 A5 C6I/O (A3) P188 AN3 D7 E8I/O - AM6 B6 B5I/O - AM2 A6 A5VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O P189 AL3 D8 D8I/O P190 AH6 C7 C7I/O P191 AP2 B7 E9I/O P192 AK4 D9 A6I/O - AN1 B8 B7I/O - AK2 A8 D9GND - GND* GND* GND*I/O P193 AG5 D10 E11I/O P194 AF6 C9 A9I/O P195 AL5 B9 C10I/O - AJ3 C10 D11GND P196 GND* GND* GND*I/O P197 AH2 B10 B10I/O P198 AE5 A10 E12I/O P199 AM4 C11 C11I/O P200 AD6 D12 B11VCC P201 VCC* VCC* VCC*I/O - AG3 B11 D12I/O - AG1 C12 A11GND - GND* GND* GND*

XC4052XLPad Name

HQ240

PG411

BG432

BG560

I/O - AF2 D13 C13I/O - AJ5 B12 E14I/O - AC5 C13 A13I/O - AE1 A12 D14I/O - AH4 D14 C14I/O - AB6 B13 B14GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O (A4) P202 AD2 C14 E15I/O (A5) P203 AB4 A13 D15I/O P205 AE3 B14 C15I/O P206 AC1 D15 A15I/O (A21) P207 AD4 C15 C16I/O (A20) P208 AA5 B15 E16GND - GND* GND* GND*I/O - AB2 A15 B17I/O - AC3 C16 C17I/O (A6) P209 AA3 B16 E17I/O (A7) P210 Y6 A16 D17GND P211 GND* GND* GND*6/20/97

HQ240GND Pins

P204 P219 - - - - -6/3/97

PG411VCC Pins

A3 A11 A21 A31 C39 D6 F36J1 L39 W1 AA39 AJ1 AL39 AP4

AT34 AU1 AW9 AW19 AW29 AW37 -GND Pins

A9 A19 A29 A37 C1 D14 D20D26 D34 F4 J39 LI P4 P36W39 Y4 Y36 AA1 AF4 AF36 AJ39AL1 AP36 AT6 AT14 AT20 AT26 AU39AW3 AW11 AW21 AW31 - - -

6/3/97

BG432VCC Pins






Not Connected PinsC8 - - - - - -

6/3/97

XC4052XLPad Name

HQ240

PG411

BG432

BG560


R


XC4062XL Device Pinout Tables(Note: XC4062XL is also available in the HQ304 package.The pinout is identical to the XC4036XL in HQ304.)

PG560VCC Pins

A4 A10 A16 A22 A26 A30 B2B13 B19 B32 C3 C31 C32 D1D33 E5 H1 K33 M1 N32 R2T33 V1 W32 AA2 AB33 AD1 AF33AK1 AK4 AK33 AL2 AL3 AL31 AM2

AM15 AM21 AM32 AN4 AN8 AN12 AN18AN24 AN30 - - - - -


A32 B1 B6 B9 B15 B23 B27B31 C2 E1 F32 G2 G33 J32K1 L2 M33 P1 P33 R32 T1

V33 W2 Y1 Y33 AB1 AC32 AD33AE2 AG1 AG32 AH2 AJ33 AL32 AM3AM7 AM11 AM19 AM25 AM28 AM33 AN2AN5 AN10 AN14 AN16 AN20 AN22 AN27

Not Connected PinsA1 A8 A19 A23 A27 A28 A33B8 B12 B16 B26 C8 C9 C12

C22 C26 D10 D13 D16 D18 D22D25 E2 E10 E13 E21 E24 E32E33 H2 H3 H5 H31 H32 J4J31 K5 K29 L3 L31 M2 M5M30 N4 N30 N31 T3 T5 T30T32 U1 U2 U33 V32 Y4 Y29AA1 AA33 AB4 AB30 AC1 AC2 AC33AD4 AD5 AD29 AD30 AE4 AE30 AE31AF1 AF2 AF31 AF32 AG2 AJ10 AJ13AJ16 AJ18 AJ21 AJ24 AK9 AK13 AK18AK24 AK25 AL8 AL9 AL12 AL16 AL22AL26 AM8 AM9 AM12 AM23 AM26 AM27AN1 AN23 AN33 - - - -

6/20/97

XC4062XLPad Name HQ240 BG432 PG475 BG560

VCC P212 VCC* VCC* VCC*I/O (A8) P213 D17 Y2 A17I/O (A9) P214 A17 Y4 B18I/O - C17 W5 C18I/O - B17 Y6 E18I/O - - U3 D18I/O - - W3 A19GND - GND* GND* GND*I/O (A19) P215 C18 W1 C19I/O (A18) P216 D18 U5 D19I/O P217 B18 W7 E19I/O P218 A19 U7 B20I/O (A10) P220 B19 V2 C20I/O (A11) P221 C19 V4 D20VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O - D19 V6 A21I/O - A20 R1 E20I/O - B20 T6 B21I/O - C20 R3 C21I/O - B21 R5 D21I/O - D20 T4 B22GND - GND* GND* GND*I/O - C21 P2 C23I/O - A22 N1 E22VCC P222 VCC* VCC* VCC*I/O P223 B22 N3 B24

I/O P224 C22 P4 D23I/O P225 B23 R7 C24I/O P226 A24 M2 A25GND P227 GND* GND* GND*I/O - D22 M4 E23I/O - C23 L3 B25I/O P228 B24 N5 D24I/O P229 C24 K2 C25I/O - - L5 B26I/O - - J1 E24GND - GND* GND* GND*I/O - D23 M6 E25I/O - B25 K4 C27I/O P230 A26 J3 D26I/O P231 C25 J5 B28I/O (A12) P232 D24 H2 B29I/O (A13) P233 B26 G1 E26GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - A27 L7 C28I/O - D25 K6 D27I/O - C26 E1 B30I/O - B27 H4 C29I/O - A28 G5 E27I/O - D26 F2 A31GND - GND* GND* GND*I/O P234 C27 H6 D28I/O P235 B28 C3 C30I/O P236 D27 F4 D29I/O P237 B29 C5 E28



R


I/O (A14) P238 C28 E3 D30I/O GCK8 (A15) P239 D28 E5 E29VCC P240 VCC* VCC* VCC*GND P1 GND* GND* GND*I/O, GCK1 (A16) P2 D29 G7 B33I/O (A17) P3 C30 D4 F29I/O P4 E28 A5 E30I/O P5 E29 B4 D31I/O, TDI P6 D30 D6 F30I/O, TCK P7 D31 F8 C33GND - GND* GND* GND*I/O - F28 B6 G29I/O - F29 E7 E31I/O - E30 D8 D32I/O - E31 G9 G30I/O - G28 E9 F31I/O - G29 A7 H29VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O - F30 B8 H30I/O - F31 C9 G31I/O P8 H28 G11 J29I/O P9 H29 D10 F33I/O P10 G30 E11 G32I/O P11 H30 A9 J30GND - GND* GND* GND*I/O - - B10 H32I/O - - C11 J31I/O P12 J28 F12 K30I/O P13 J29 D12 H33I/O - H31 A11 L29I/O - J30 G15 K31GND P14 GND* GND* GND*I/O P15 K28 B12 L30I/O P16 K29 E13 K32I/O, TMS P17 K30 C13 J33I/O P18 K31 A13 M29VCC P19 VCC* VCC* VCC*I/O P20 L29 B14 L32I/O P21 L30 C15 M31GND - GND* GND* GND*I/O - M30 G17 N29I/O - M28 F14 L33I/O - M29 D16 M32I/O - M31 D14 P29I/O - N31 A15 P30I/O - N28 C17 N33GND P22 GND* GND* GND*VCC - VCC* VCC* VCC*I/O - N29 D18 P31I/O - N30 B18 P32I/O - P30 F16 R29I/O - P28 G19 R30I/O P23 P29 E17 R31I/O P24 R31 E19 R33GND - GND* GND* GND*I/O P25 R30 A19 T31I/O P26 R28 F18 T29I/O - - C19 T30I/O - - D20 T32I/O P27 R29 F20 U32I/O P28 T31 B20 U31GND P29 GND* GND* GND*VCC P30 VCC* VCC* VCC*I/O P31 T30 C21 U29I/O P32 T29 A21 U30I/O - - D22 U33I/O - - B22 V32I/O P33 U31 E23 V31I/O P34 U30 F22 V29


GND - GND* GND* GND*I/O P35 U28 C23 V30I/O P36 U29 F24 W33I/O - V30 A23 W31I/O - V29 E25 W30I/O - V28 G23 W29I/O - W31 B24 Y32VCC - VCC* VCC* VCC*GND P37 GND* GND* GND*I/O - W30 D24 Y31I/O - W29 C25 Y30I/O - W28 D28 AA32I/O - Y31 A27 AA31I/O - Y30 E29 AA30I/O - Y29 C27 AB32GND - GND* GND* GND*I/O P38 Y28 G25 AA29I/O P39 AA30 D26 AB31VCC P40 VCC* VCC* VCC*I/O P41 AA29 F26 AC31I/O P42 AB31 B28 AB29I/O P43 AB30 D30 AD32I/O P44 AB29 A29 AC30GND P45 GND* GND* GND*I/O - AB28 C29 AD31I/O - AC30 G27 AE33I/O P46 AC29 F30 AC29I/O P47 AC28 B30 AE32I/O - - E31 AD30I/O - - C31 AE31GND - GND* GND* GND*I/O - AD31 F28 AG33I/O - AD30 D32 AH33I/O P48 AD29 B32 AE29I/O P49 AD28 G31 AG31I/O P50 AE30 A33 AF30I/O P51 AE29 C33 AH32GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - AF31 B34 AJ32I/O - AE28 A35 AF29I/O - AF30 E33 AH31I/O - AF29 D34 AG30I/O P52 AG31 D36 AK32I/O P53 AF28 B36 AJ31GND - GND* GND* GND*I/O - AG30 F34 AG29I/O - AG29 D38 AL33I/O P54 AH31 C37 AH30I/O P55 AG28 G37 AK31I/O P56 AH30 B38 AJ30I/O, GCK2 P57 AJ30 F38 AH29O (M1) P58 AH29 A39 AK30GND P59 GND* GND* GND*I (M0) P60 AH28 E35 AJ29VCC P61 VCC* VCC* VCC*I (M2) P62 AJ28 G33 AN32I/O, GCK3 P63 AK29 J37 AJ28I/O (HDC) P64 AH27 G35 AK29I/O P65 AK28 K36 AL30I/O P66 AJ27 C39 AK28I/O P67 AL28 K38 AM31I/O (LDC) P68 AH26 C41 AJ27GND - GND* GND* GND*I/O - AK27 D40 AN31I/O - AJ26 L37 AL29I/O - AL27 H36 AK27I/O - AH25 M36 AL28I/O - AK26 J35 AJ26I/O - AL26 E41 AM30



R


VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O P69 AH24 F40 AM29I/O P70 AJ25 H38 AK26I/O P71 AK25 N37 AL27I/O P72 AJ24 L35 AJ25I/O - AH23 R35 AN29I/O - AK24 G41 AN28GND - GND* GND* GND*I/O - - H40 AM26I/O - - P38 AK24I/O P73 AL24 J39 AL25I/O P74 AH22 R37 AJ23I/O - AJ23 J41 AN26I/O - AK23 K40 AL24GND P75 GND* GND* GND*I/O P76 AJ22 L39 AK23I/O P77 AK22 M38 AN25I/O P78 AL22 T36 AJ22I/O P79 AJ21 M40 AL23VCC P80 VCC* VCC* VCC*I/O P81 AH20 N39 AM24I/O P82 AK21 N41 AK22GND - GND* GND* GND*I/O - AJ20 P40 AK21I/O - AH19 T38 AM22I/O - AK20 U35 AJ20I/O - AJ19 U37 AL21I/O - AL20 R39 AN21I/O - AH18 R41 AK20GND P83 GND* GND* GND*VCC - VCC* VCC* VCC*I/O - AK19 V36 AL20I//O - AJ18 U39 AJ19I/O P84 AL19 V38 AM20I/O P85 AK18 V40 AK19I/O P86 AH17 W37 AL19I/O P87 AJ17 W35 AN19GND - GND* GND* GND*I/O - - W41 AJ18I/O - - Y36 AK18I/O - AK17 W39 AL18I/O - AL17 AB36 AM18I/O P88 AJ16 Y40 AK17I/O (INIT) P89 AK16 Y38 AJ17VCC P90 VCC* VCC* VCC*GND P91 GND* GND* GND*I/O P92 AL16 AA39 AL17I/O P93 AH15 AB38 AM17I/O - AL15 AB40 AN17I/O - AJ15 AC37 AK16I/O - - AC39 AJ16I/O - - AC41 AL16GND - GND* GND* GND*I/O P94 AK15 AD36 AM16I/O P95 AJ14 AC35 AL15I/O P96 AH14 AE37 AK15I/O P97 AK14 AD40 AJ15I/O - AL13 AD38 AN15I/O - AK13 AE39 AM14VCC - VCC* VCC* VCC*GND P98 GND* GND* GND*I/O - AJ13 AG41 AL14I/O - AH13 AG39 AK14I/O - AL12 AG37 AJ14I/O - AK12 AE35 AN13I/O - AJ12 AH38 AM13I/O - AK11 AF38 AL13GND - GND* GND* GND*I/O P99 AH12 AF36 AK12


I/O P100 AJ11 AH40 AN11VCC P101 VCC* VCC* VCC*I/O P102 AL10 AJ41 AJ12I/O P103 AK10 AJ39 AL11I/O P104 AJ10 AJ37 AK11I/O P105 AK9 AG35 AM10GND P106 GND* GND* GND*I/O - AL8 AK40 AL10I/O - AH10 AK38 AJ11I/O P107 AJ9 AL37 AN9I/O P108 AK8 AL39 AK10I/O - - AM38 AM9I/O - - AM40 AL9GND - GND* GND* GND*I/O - AJ8 AN41 AN7I/O - AH9 AM36 AJ9I/O P109 AK7 AK36 AL7I/O P110 AL6 AU41 AK8I/O P111 AJ7 AN39 AN6I/O P112 AH8 AP40 AM6GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - AK6 AR41 AJ8I/O - AL5 AL35 AL6I/O P113 AH7 AV40 AK7I/O P114 AJ6 AN37 AM5I/O - AK5 AT38 AM4I/O - AL4 AP38 AJ7GND - GND* GND* GND*I/O - AH6 AT40 AL5I/O - AJ5 AW39 AK6I/O P115 AK4 AP36 AN3I/O P116 AH5 AU37 AK5I/O P117 AK3 AR37 AJ6I/O, GCK4 P118 AJ4 AU39 AL4GND P119 GND* GND* GND*DONE P120 AH4 AR35 AJ5VCC P121 VCC* VCC* VCC*PROGRAM P122 AH3 AN35 AM1I/O (D7) P123 AJ2 AU35 AH5I/O, GCK5 P124 AG4 AV38 AJ4I/O P125 AG3 AT34 AK3I/O P126 AH2 BA39 AH4I/O - AH1 AU33 AL1I/O - AF4 AY38 AG5GND - GND* GND* GND*I/O P127 AF3 AV36 AJ3I/O P128 AG2 AR31 AK2I/O - AG1 AR33 AG4I/O - AE4 AV32 AH3I/O - AE3 BA37 AF5I/O - AF2 AY36 AJ2VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O (D6) P129 AF1 AV34 AJ1I/O P130 AD4 BA35 AF4I/O P131 AD3 AU31 AG3I/O P132 AE2 AY34 AE5I/O - AD2 AT30 AH1I/O - AC4 AW33 AF3GND - GND* GND* GND*I/O - - BA33 AF1I/O - - AV30 AD4I/O P133 AC3 AY32 AE3I/O P134 AD1 AU29 AC5I/O - AC2 AW31 AE1I/O - AB4 BA31 AD3GND P135 GND* GND* GND*I/O P136 AB3 AR27 AC4I/O P137 AB2 AT28 AD2



R


I/O P138 AB1 AY30 AB5I/O P139 AA3 AW29 AC3VCC P140 VCC* VCC* VCC*I/O (D5) P141 AA2 BA29 AA5I/O (CS0) P142 Y2 AY28 AB3GND P143 GND* GND* GND*I/O - Y4 AR25 AB2I/O - Y3 AV28 AA4I/O - Y1 AW27 AA3I/O - W1 AT26 Y5I/O - W4 AV26 Y3I/O - W3 BA27 Y2GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O - W2 AW25 W5I/O - V2 AV24 W4I/O - V4 AU25 W3I/O - V3 AR23 W1I/O P144 U1 AT24 V3I/O P145 U2 AY24 V5GND - GND* GND* GND*I/O P146 U4 BA23 V4I/O P147 U3 AU23 V2I/O - - AW23 U2I/O - - AV20 U1I/O (D4) P148 T1 AY22 U5I/O P149 T2 AV22 U4VCC P150 VCC* VCC* VCC*GND P151 GND* GND* GND*I/O (D3) P152 T3 AW21 U3I/O (RS) P153 R1 BA21 T2I/O - - AU19 T3I/O - - AY20 T5I/O P154 R2 AU17 T4I/O P155 R4 AW19 R1GND - GND* GND* GND*I/O P156 R3 BA19 R3I/O P157 P2 AT16 R4I/O - P3 AR19 R5I/O - P4 AV14 P2I/O - N1 AY18 P3I/O - N2 AV18 P4VCC - VCC* VCC* VCC*GND P158 GND* GND* GND*I/O - N3 AT18 N1I/O - N4 AW17 P5I/O - M1 AR15 N2I/O - M2 BA15 N3I/O - M3 AT14 N5I/O - M4 AR17 M3GND - GND* GND* GND*I/O (D2) P159 L2 AW15 M4I/O P160 L3 AV16 L1VCC P161 VCC* VCC* VCC*I/O P162 K1 AY14 K2I/O P163 K2 BA13 L4I/O P164 K3 AU13 J1I/O P165 K4 AW13 K3GND P166 GND* GND* GND*I/O - J2 AY12 L5I/O - J3 BA11 J2I/O P167 J4 AV12 K4I/O P168 H1 AT12 J3I/O - - AW11 H2I/O - - AY10 K5GND - GND* GND* GND*I/O P169 H2 BA9 G1I/O P170 H3 AU11 F1I/O P171 H4 AW9 J5I/O P172 G2 AV10 G3


I/O - G3 AY8 H4I/O - F1 BA7 F2GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O (D1) P173 G4 AV8 F3I/O (RCLK, RDY/BUSY) P174 F2 AY6 G4I/O - F3 AR11 D2I/O - E1 AT8 E3I/O - F4 AU9 G5I/O - E2 AW5 C1GND - GND* GND* GND*I/O - E3 AY4 F4I/O - D1 BA5 D3I/O P175 E4 AV4 B3I/O P176 D2 AR9 F5I/O (D0, DIN) P177 C2 AU5 E4I/O, GCK6 (DOUT) P178 D3 AV6 D4CCLK P179 D4 AR5 C4VCC P180 VCC* VCC* VCC*O, TDO P181 C4 AN7 E6GND P182 GND* GND* GND*I/O (A0, WS) P183 B3 AR7 D5I/O, GCK7 (A1) P184 D5 AW3 A2I/O P185 B4 AU3 D6I/O P186 C5 AW1 A3I/O - A4 AP6 E7I/O - D6 AV2 C5GND - GND* GND* GND*I/O - B5 AT4 B4I/O - C6 AN5 D7I/O (CS1, A2) P187 A5 AU1 C6I/O (A3) P188 D7 AM6 E8I/O - B6 AT2 B5I/O - A6 AL7 A5VCC - VCC* VCC* VCC*GND - GND* GND* GND*I/O P189 D8 AR1 D8I/O P190 C7 AP2 C7I/O P191 B7 AM4 E9I/O P192 D9 AN3 A6I/O - B8 AL5 B7I/O - A8 AK6 D9GND - GND* GND* GND*I/O - - AN1 D10I/O - - AJ5 C9I/O P193 D10 AM2 E11I/O P194 C9 AH4 A9I/O P195 B9 AL3 C10I/O - C10 AK4 D11GND P196 GND* GND* GND*I/O P197 B10 AG7 B10I/O P198 A10 AG5 E12I/O P199 C11 AK2 C11I/O P200 D12 AJ3 B11VCC P201 VCC* VCC* VCC*I/O - B11 AJ1 D12I/O - C12 AF6 A11GND - GND* GND* GND*I/O - D13 AH2 C13I/O - B12 AF4 E14I/O - C13 AE7 A13I/O - A12 AE5 D14I/O - D14 AG3 C14I/O - B13 AG1 B14GND - GND* GND* GND*VCC - VCC* VCC* VCC*I/O (A4) P202 C14 AD6 E15I/O (A5) P203 A13 AD4 D15I/O P205 B14 AE3 C15I/O P206 D15 AC5 A15



R


* Pads labelled GND* or VCC* are internally bonded to Ground orVCC planes within the package. They have no direct connection toany specific package pin.



XC4085XL Device Pinout Tables

I/O (A21) P207 C15 AD2 C16I/O (A20) P208 B15 AC7 E16GND - GND* GND* GND*I/O - - AC1 D16I/O - - AC3 B16I/O - A15 AB6 B17I/O - C16 AB2 C17I/O (A6) P209 B16 AB4 E17I/O (A7) P210 A16 AA3 D17GND P211 GND* GND* GND*6/16/97

HQ240GND Pins

P204 P219 - - - -5/5/97

BG432VCC Pins






Not Connected PinsC8 - - - - - -

5/5/97

XC4062XLPad Name HQ240 BG432 PG475 BG560 PG475

VCC PinsA37 B2 B16 B26 B40 D2E21 F6 F36 G13 G29 N7N35 T2 T40 AA1 AA5 AA37

AA41 AF2 AF40 AJ7 AJ35 AR13AR29 AT6 AT22 AT36 AU21 AW37AW41 AY2 AY16 AY26 AY40 BA3

GND PinsA3 C1 C7 G3 L1 P6U1 A17 A25 A41 AA7 AE1

AH6 AL1 AR3 AW7 BA1 C35E15 E27 F10 F32 G21 G39L41 P36 U41 AA35 AE41 AH36

AL41 AR21 AR39 AT10 AT20 AT32AU15 AU27 AW35 BA17 BA25 BA41E37 E39 A31 J7 AP4 AU7

5/5/97

BG560VCC Pins





V33 W2 Y1 Y33 AB1 AC32 AD33AE2 AG1 AG32 AH2 AJ33 AL32 AM3

AM11 AM19 AM25 AM28 AM33 AM7 AN2AN5 AN10 AN14 AN16 AN20 AN22 AN27

Not Connected PinsA1 A8 A23 A27 A28 A33 B8

B12 C8 C12 C22 C26 D13 D22D25 E2 E10 E13 E21 E32 E33H3 H5 H31 J4 K29 L3 L31M2 M5 M30 N4 N30 N31 Y4Y29 AA1 AA33 AB4 AB30 AC1 AC2

AC33 AD5 AD29 AE4 AE30 AF2 AF31AF32 AG2 AJ10 AJ13 AJ21 AJ24 AK9AK13 AK25 AL8 AL12 AL22 AL26 AM8AM12 AM23 AM27 AN1 AN23 AN33 -

5/5/97

XC4085XLPad Name BG432 BG560 PG559

VCC VCC VCC* VCC*I/O (A8) D17 A17 AB6I/O (A9) A17 B18 AB4I/O C17 C18 AA7I/O B17 E18 AC1I/O - D18 AA5I/O - A19 AA3GND GND* GND* GND*I/O (A19) C18 C19 Y8I/O (A18) D18 D19 AB2I/O B18 E19 Y6I/O A19 B20 AA1I/O (A10) B19 C20 Y4

I/O (A11) C19 D20 W7VCC VCC* VCC* VCC*GND GND* GND* GND*I/O D19 A21 W5I/O A20 E20 V6I/O B20 B21 V4I/O C20 C21 Y2I/O B21 D21 U3I/O D20 B22 U7I/O - E21 V2I/O - C22 U5GND GND* GND* GND*I/O - D22 T4



R


I/O - A23 U1I/O C21 C23 R3I/O A22 E22 R5VCC VCC VCC* VCC*I/O B22 B24 T8I/O C22 D23 T2I/O B23 C24 P4I/O A24 A25 R7GND GND* GND* GND*I/O D22 E23 N3I/O C23 B25 R1I/O B24 D24 N5I/O C24 C25 P2I/O - B26 M4I/O - E24 L1I/O - C26 L3I/O - D25 P8GND GND* GND* GND*VCC VCC* VCC* VCC*I/O - A27 N7I/O - A28 K2I/O D23 E25 M6I/O B25 C27 J1I/O A26 D26 L5I/O C25 B28 H2I/O (A12) D24 B29 K4I/O (A13) B26 E26 J3GND GND* GND* GND*VCC VCC* VCC* VCC*I/O A27 C28 L7I/O D25 D27 J5I/O C26 B30 G1I/O B27 C29 H4I/O A28 E27 F2I/O D26 A31 G5GND GND* GND* GND*I/O C27 D28 H6I/O B28 C30 K8I/O D27 D29 D2I/O B29 E28 J7I/O (A14) C28 D30 F4I/O, GCK8(A15)

D28 E29 E3

VCC VCC* VCC* VCC*GND GND* GND* GND*I/O, GCK1(A16)

D29 B33 C1

I/O (A17) C30 F29 C3I/O E28 E30 F6I/O E29 D31 A3I/O (TDI) D30 F30 H8I/O (TCK) D31 C33 D4GND GND* GND* GND*I/O F28 G29 D6I/O F29 E31 C5I/O E30 D32 E7I/O E31 G30 B4I/O G28 F31 H10I/O G29 H29 G9VCC VCC* VCC* VCC*GND GND* GND* GND*I/O - E32 F8


I/O - E33 D8I/O F30 H30 B6I/O F31 G31 E9I/O H28 J29 A7I/O H29 F33 G11I/O G30 G32 H14I/O H30 J30 F12VCC VCC* VCC* VCC*GND GND* GND* GND*I/O - H31 G13I/O - K29 E11I/O - H32 B8I/O - J31 D10I/O J28 K30 A9I/O J29 H33 G15I/O H31 L29 B10I/O J30 K31 H16GND GND* GND* GND*I/O K28 L30 C9I/O K29 K32 E13I/O (TMS) K30 J33 A11I/O K31 M29 D12VCC VCC* VCC* VCC*I/O - L31 C11I/O - M30 B14I/O L29 L32 G17I/O L30 M31 E15GND GND* GND* GND*I/O M30 N29 D14I/O M28 L33 A15I/O - N30 C13I/O - N31 B16I/O M29 M32 E17I/O M31 P29 F18I/O N31 P30 A17I/O N28 N33 G19GND GND* GND* GND*VCC VCC* VCC* VCC*I/O N29 P31 D16I/O N30 P32 C15I/O P30 R29 B18I/O P28 R30 H20I/O P29 R31 B20I/O R31 R33 E19GND GND* GND* GND*I/O R30 T31 D18I/O R28 T29 F20I/O - T30 G21I/O - T32 C17I/O R29 U32 D20I/O T31 U31 E21GND GND* GND* GND*VCC VCC* VCC* VCC*I/O T30 U29 C21I/O T29 U30 F22I/O - U33 A21I/O - V32 D22I/O U31 V31 B22I/O U30 V29 G23GND GND* GND* GND*I/O U28 V30 E23



R


I/O U29 W33 C23I/O V30 W31 A23I/O V29 W30 D24I/O V28 W29 B24I/O W31 Y32 H24VCC VCC* VCC* VCC*GND GND* GND* GND*I/O W30 Y31 F24I/O W29 Y30 E25I/O - AA33 B26I/O - Y29 D26I/O W28 AA32 A27I/O Y31 AA31 G25I/O Y30 AA30 B28I/O Y29 AB32 C27GND GND* GND* GND*I/O Y28 AA29 F26I/O AA30 AB31 E27I/O - AB30 A29I/O - AC33 D28VCC VCC* VCC* VCC*I/O AA29 AC31 G27I/O AB31 AB29 B30I/O AB30 AD32 C29I/O AB29 AC30 E29GND GND* GND* GND*I/O AB28 AD31 D30I/O AC30 AE33 A33I/O AC29 AC29 C31I/O AC28 AE32 B34I/O - AD30 H28I/O - AE31 A35I/O - AF32 G29I/O - AD29 E31GND GND* GND* GND*VCC VCC* VCC* VCC*I/O - AF31 D32I/O - AE30 C35I/O AD31 AG33 C33I/O AD30 AH33 B36I/O AD29 AE29 H30I/O AD28 AG31 A37I/O AE30 AF30 G31I/O AE29 AH32 F32GND GND* GND* GND*VCC VCC* VCC* VCC*I/O AF31 AJ32 E33I/O AE28 AF29 D34I/O AF30 AH31 B38I/O AF29 AG30 G33I/O AG31 AK32 A41I/O AF28 AJ31 E35GND GND* GND* GND*I/O AG30 AG29 D36I/O AG29 AL33 F36I/O AH31 AH30 G35I/O AG28 AK31 H34I/O AH30 AJ30 B40I/O, GCK2 AJ30 AH29 E37O (M1) AH29 AK30 D38GND GND* GND* GND*


I (M0) AH28 AJ29 C39VCC VCC* VCC* VCC*I (M2) AJ28 AN32 H36I/O, GCK3 AK29 AJ28 F38I/O (HDC) AH27 AK29 C41I/O AK28 AL30 D40I/O AJ27 AK28 B42I/O AL28 AM31 J37I/O (LDC) AH26 AJ27 K36GND GND* GND* GND*I/O AK27 AN31 H38I/O AJ26 AL29 D42I/O AL27 AK27 G39I/O AH25 AL28 C43I/O AK26 AJ26 F40I/O AL26 AM30 E41VCC VCC* VCC* VCC*GND GND* GND* GND*I/O AH24 AM29 L37I/O AJ25 AK26 J39I/O AK25 AL27 F42I/O AJ24 AJ25 H40I/O AH23 AN29 G43I/O AK24 AN28 J41I/O - AK25 H42I/O - AL26 N37VCC VCC* VCC* VCC*GND GND* GND* GND*I/O - AJ24 P36I/O - AM27 M38I/O - AM26 J43I/O - AK24 L39I/O AL24 AL25 K42I/O AH22 AJ23 K40I/O AJ23 AN26 L43I/O AK23 AL24 L41GND GND* GND* GND*I/O AJ22 AK23 R37I/O AK22 AN25 P42I/O AL22 AJ22 T36I/O AJ21 AL23 N39VCC VCC* VCC* VCC*I/O AH20 AM24 M40I/O AK21 AK22 R43I/O - AM23 N41I/O - AJ21 R39GND GND* GND* GND*I/O - AL22 U37I/O - AN23 T42I/O AJ20 AK21 P40I/O AH19 AM22 U43I/O AK20 AJ20 R41I/O AJ19 AL21 V42I/O AL20 AN21 U39I/O AH18 AK20 V38GND GND* GND* GND*VCC VCC* VCC* VCC*I/O AK19 AL20 W37I/O AJ18 AJ19 T40I/O AL19 AM20 Y42I/O AK18 AK19 U41



R


I/O AH17 AL19 Y36I/O AJ17 AN19 V40GND GND* GND* GND*I/O - AJ18 W39I/O - AK18 AA43I/O AK17 AL18 Y38I/O AL17 AM18 Y40I/O AJ16 AK17 AA37I/O (INIT) AK16 AJ17 AA39VCC VCC* VCC* VCC*GND GND* GND* GND*I/O AL16 AL17 AA41I/O AH15 AM17 AB38I/O AL15 AN17 AB42I/O AJ15 AK16 AB40I/O - AJ16 AC37I/O - AL16 AC39GND GND* GND* GND*I/O AK15 AM16 AD36I/O AJ14 AL15 AC41I/O AH14 AK15 AD38I/O AK14 AJ15 AC43I/O AL13 AN15 AD40I/O AK13 AM14 AE39VCC VCC* VCC* VCC*GND GND* GND* GND*I/O AJ13 AL14 AE37I/O AH13 AK14 AF40I/O AL12 AJ14 AD42I/O AK12 AN13 AF42I/O AJ12 AM13 AF38I/O AK11 AL13 AG39I/O - AK13 AG43I/O - AJ13 AG37GND GND* GND* GND*I/O - AM12 AH40I/O - AL12 AJ41I/O AH12 AK12 AG41I/O AJ11 AN11 AK40VCC VCC* VCC* VCC*I/O AL10 AJ12 AJ39I/O AK10 AL11 AH42I/O AJ10 AK11 AH36I/O AK9 AM10 AL39GND GND* GND* GND*I/O AL8 AL10 AJ37I/O AH10 AJ11 AJ43I/O AJ9 AN9 AM40I/O AK8 AK10 AK42I/O - AM9 AN41I/O - AL9 AL41I/O - AJ10 AR41I/O - AM8 AK36GND GND* GND* GND*VCC VCC* VCC* VCC*I/O - AK9 AL37I/O - AL8 AN43I/O AJ8 AN7 AM38I/O AH9 AJ9 AP42I/O AK7 AL7 AN39I/O AL6 AK8 AR43


I/O AJ7 AN6 AP40I/O AH8 AM6 AT40GND GND* GND* GND*VCC VCC* VCC* VCC*I/O AK6 AJ8 AN37I.O AL5 AL6 AR39I/O AH7 AK7 AT42I/O AJ6 AM5 BA43I/O AK5 AM4 AU43I/O AL4 AJ7 AU39GND GND* GND* GND*I/O AH6 AL5 AT38I/O AJ5 AK6 AP36I/O AK4 AN3 AR37I/O AH5 AK5 AV42I/O AK3 AJ6 AV40I/O, GCK4 AJ4 AL4 AW41GND GND* GND* GND*DONE AH4 AJ5 AY42VCC VCC* VCC* VCC*PROGRAM AH3 AM1 BB42I/O (D7) AJ2 AH5 BC41I/O, GCK5 AG4 AJ4 AV38I/O AG3 AK3 BA39I/O AH2 AH4 AT36I/O AH1 AL1 BB40I/O AF4 AG5 AY40GND GND* GND* GND*I/O AF3 AJ3 BA41I/O AG2 AK2 BB38I/O AG1 AG4 AY38I/O AE4 AH3 BC37I/O AE3 AF5 AW37I/O AF2 AJ2 AT34VCC VCC* VCC* VCC*GND GND* GND* GND*I/O (D6) AF1 AJ1 AU35I/O AD4 AF4 AV36I/O AD3 AG3 BB36I/O AE2 AE5 AY36I/O AD2 AH1 BC35I/O AC4 AF3 AW35I/O - AE4 AU33I/O - AG2 AT30VCC VCC* VCC* VCC*GND GND* GND* GND*I/O - AD5 AV32I/O - AF2 AU31I/O - AF1 AW33I/O - AD4 BB34I/O AC3 AE3 AY34I/O AD1 AC5 BC33I/O AC2 AE1 AU29I/O AB4 AD3 AT28GND GND* GND* GND*I/O AB3 AC4 BA35I/O AB2 AD2 BB30I/O AB1 AB5 AW31I/O AA3 AC3 AY32VCC VCC* VCC* VCC*I/O - AB4 BA33



R


I/O - AC1 AU27I/O (D5) AA2 AA5 BC29I/O (CS0) Y2 AB3 AW29GND GND* GND* GND*I/O Y4 AB2 AY30I/O Y3 AA4 BA31I/O Y1 AA3 BB28I/O W1 Y5 AW27I/O - AA1 BC27I/O - Y4 AV26I/O W4 Y3 AU25I/O W3 Y2 AY28GND GND* GND* GND*VCC VCC* VCC* VCC*I/O W2 W5 BA29I/O V2 W4 AT24I/O V4 W3 BB26I/O V3 W1 AW25I/O U1 V3 BB24I/O U2 V5 AY26GND GND* GND* GND*I/O U4 V4 AV24I/O U3 V2 AU23I/O - U2 BA27I/O - U1 BC23I/O (D4) T1 U5 AY24I/O T2 U4 AW23VCC VCC* VCC* VCC*GND GND* GND* GND*I/O (D3) T3 U3 BA23I/O (RS) R1 T2 AV22I/O - T3 AY22I/O - T5 BB22I/O R2 T4 AU21I/O R4 R1 AW21GND GND* GND* GND*I/O R3 R3 BA21I/O P2 R4 BC21I/O P3 R5 AY20I/O P4 P2 BB20I/O N1 P3 AT20I/O N2 P4 AV20VCC VCC* VCC* VCC*GND GND* GND* GND*I/O N3 N1 AW19I/O N4 P5 AY18I/O M1 N2 BB18I/O M2 N3 AU19I/O - N4 BC17I/O - M2 BA17I/O M3 N5 AV18I/O M4 M3 AW17GND GND* GND* GND*I/O (D2) L2 M4 AY16I/O L3 L1 BB16I/O - L3 AU17I/O - M5 BA15VCC VCC* VCC* VCC*I/O K1 K2 AW15I/O K2 L4 BC15I/O K3 J1 AY14


I/O K4 K3 BA13GND GND* GND* GND*I/O J2 L5 AT16I/O J3 J2 BB14I/O J4 K4 AU15I/O H1 J3 BC11I/O - H2 AW13I/O - K5 BB10I/O - H3 AY12I/O - J4 BA11GND GND* GND* GND*VCC VCC* VCC* VCC*I/O H2 G1 AT14I/O H3 F1 AU13I/O H4 J5 AV12I/O G2 G3 BC9I/O G3 H4 AW11I/O F1 F2 BB8I/O - E2 AY10I/O - H5 AU11GND GND* GND* GND*VCC VCC* VCC* VCC*I/O (D1) G4 F3 BA9I/O (RCLKRDY/BUSY)

F2 G4 AW9

I/O F3 D2 BC7I/O E1 E3 AY8I/O F4 G5 AV8I/O E2 C1 AT10GND GND* GND* GND*I/O E3 F4 AU9I/O D1 D3 BB6I/O E4 B3 AW7I/O D2 F5 BC3I/O (D0, DIN) C2 E4 AY6I/O, GCK6(DOUT)

D3 D4 BB4

CCLK D4 C4 BA5VCC VCC* VCC* VCC*O, TDO C4 E6 BA3GND GND* GND* GND*I/O (A0, WS) B3 D5 AT8I/O, GCK7 (A1) D5 A2 AV6I/O B4 D6 BB2I/O C5 A3 AY4I/O A4 E7 AR7I/O D6 C5 AP8GND GND* GND* GND*I/O B5 B4 AT6I/O C6 D7 AY2I/O (CS1, A2) A5 C6 AU5I/O (A3) D7 E8 BA1I/O B6 B5 AV4I/O A6 A5 AW3VCC VCC* VCC* VCC*GND GND* GND* GND*I/O D8 D8 AN7I/O C7 C7 AR5I/O B7 E9 AV2I/O D9 A6 AT4I/O B8 B7 AU1I/O A8 D9 AR3



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*Pads labelled GND* or VCC* are internally bonded to Ground orVCC planes within the package. They have no direct connection toany specific package pin.


I/O - C8 AT2I/O - E10 AL7VCC VCC* VCC* VCC*GND GND* GND* GND*I/O - B8 AK8I/O - A8 AM6I/O - D10 AN5I/O - C9 AR1I/O D10 E11 AP4I/O C9 A9 AN3I/O B9 C10 AP2I/O C10 D11 AJ7GND GND* GND* GND*I/O B10 B10 AH8I/O A10 E12 AL5I/O C11 C11 AN1I/O D12 B11 AM4VCC VCC* VCC* VCC*I/O B11 D12 AL3I/O C12 A11 AJ5I/O - E13 AK2I/O - C12 AG7GND GND* GND* GND*I/O - B12 AK4I/O - D13 AJ3I/O D13 C13 AG5I/O B12 E14 AJ1I/O C13 A13 AF6I/O A12 D14 AH2I/O D14 C14 AE7I/O B13 B14 AH4GND GND* GND* GND*VCC VCC* VCC* VCC*I/O (A4) C14 E15 AG3I/O (A5) A13 D15 AD8I/O B14 C15 AG1I/O D15 A15 AF4I/O (A21) C15 C16 AE5I/O (A20) B15 E16 AD6GND GND* GND* GND*I/O - D16 AD4I/O - B16 AF2I/O A15 B17 AC7I/O C16 C17 AD2I/O (A6) B16 E17 AC5I/O (A7) A16 D17 AC3GND GND* GND* GND*6/13/97


BG560VCC Pins





V33 W2 Y1 Y33 AB1 AC32 AD33AE2 AG1 AG32 AH2 AJ33 AL32 AM3

AM11 AM19 AM25 AM28 AM33 AM7 AN2AN5 AN10 AN14 AN16 AN20 AN22 AN27

Not Connected PinsA1 A33 AC2 AN1 AN33 - -

6/4/97

PG559VCC Pins

A13 A31 A43 B2 C7 C19 C25C37 F14 F30 G3 G7 G37 G41H12 H18 H26 H32 M8 M36 N1N43 P6 P38 V8 V36 W3 W41AE3 AE41 AF8 AF36 AK6 AK38 AL1AL43 AM8 AM36 AT12 AT18 AT26 AT32AU3 AU7 AU37 AU41 AV14 AV30 BA7BA19 BA25 BA37 BC1 BC13 BC31 BC43

GND PinsA5 A19 A25 A39 B12 B32 E1E5 E39 E43 F10 F16 F28 F34

H22 K6 K38 M2 M42 T6 T38W1 W43 AB8 AB36 AE1 AE43 AH6

AH38 AM2 AM42 AP6 AP38 AT22 AV10AV16 AV28 AV34 AW1 AW5 AW39 AW43BB12 BB32 BC5 BC19 BC25 BC39 -

5/8/97


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VG432VCC Pins

A1 A11 A21 A31 D11 D21 L1L4 L28 L31 AA1 AA4 AA28 AA31

AH11 AH21 AL1 AL11 AL21 AL31 C3C29 AJ3 AJ29

GND PinsA2 A3 A7 A9 A14 A18 A23A25 A29 A30 B1 B2 B30 B31C1 C31 D16 G1 G31 J1 J31P1 P31 T4 T28 V1 V31 AC1

AC31 AE1 AE31 AH16 AJ1 AJ31 AK1AK2 AK30 AK31 AL2 AL3 AL7 AL9AL14 AL18 AL23 AL25 AL29 AL30

Not Connected PinsC8

3/3/98


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Revision ControlVersion Description

3/30/98 (1.5) Added XC4002XL1/29/99 (1.5) Updated pin diagrams5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and

added URL link on placeholder page for electrical specifications/pinouts for WebLINX users10/4/99 (1.7) Added Note about extra grounds in center of BG256 package for XC4028XL (page 6-133).


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Package Information

Inches vs. Millimeters

The JEDEC standards for PLCC, CQFP, and PGA pack-ages define package dimensions in inches. The lead spac-ing is specified as 25, 50, or 100 mils (0.025", 0.050" or0.100").

The JEDEC standards for PQFP, HQFP, TQFP, and VQFPpackages define package dimensions in millimeters. These

packages have a lead spacing of 0.5 mm, 0.65 mm, or 0.8mm.

Because of the potential for measurement discrepancies,this Data Book provides measurements in the controllingstandard only, either inches or millimeters. (See Table 1 forpackage dimensions.)

Notes: 1. Dimensions in millimeters2. For 3.2 mm footprint per MS022, JEDEC Publication 95.

0

Packages and Thermal Characteristics

February 15, 2000 (Version 2.1) 0 8*

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Figure 1: EIA Standard Board Layout of Soldered Pads for QFP Devices

Table 1: Dimensions for Xilinx Quad Flat Packs(1)

Dim. VQ44 VQ64 PQ100HQ160PQ160

HQ208PQ208

VQ100TQ100

TQ144 TQ176HQ240PQ240

HQ304

MID 9.80 9.80 20.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20

MIE 9.80 9.80 14.40 28.40 28.20 13.80 19.80 23.80 32.20 40.20

e 0.80 0.50 0.65 0.65 0.50 0.50 0.50 0.50 0.50 0.50

b2 0.4 - 0.6 0.3 - 0.4 0.3 - 0.5 0.3 - 0.5 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4 0.3 - 0.4

I2 1.60 1.60 1.802 1.80 1.60 1.60 1.60 1.60 1.60 1.60

b2

M ID

MIE

el 2

ee

e

February 15, 2000 (Version 2.1) 8-1

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Suggested Board Layout of Soldered Pads for BGA, CS and FG Packages

Figure 2: Suggested Board Layout of Soldered Pads for BGA, CS and FG Packages

Table 2: Soldering Dimensions for BG, CS, and FG Packages

BG225 *BG256 BG352 BG432 BG560 CS48 CS144 CS280Solder Land (L) diameter 0.89 0.79 0.79 0.79 0.79 0.33 0.33 0.33Opening in Solder Mask (M) diameter 0.65 0.58 0.58 0.58 0.58 0.44 0.44 0.44Solder (Ball) Land Pitch (e) 1.5 1.27 1.27 1.27 1.27 0.8 0.8 0.8Line Width between Via and Land (w) 0.3 0.3 0.3 0.3 0.3 0.13 0.13 0.13Distance between Via and Land (D) 1.06 0.9 0.9 0.9 0.9 0.56 0.56 0.56Via Land (VL) diameter 0.65 0.65 0.65 0.65 0.65 0.51 0.51 0.51Through Hole (VH) diameter 0.3 0.3 0.3 0.3 0.3 0.25 0.25 0.25Pad Array Full - - - - - - -Matrix or External Row 15 x 15 20 x 20 26 x 26 31 x 31 33 x 33 7 x 7 13 x 13 19 x 19Periphery rows - 4 4 4 5 3 4 5

FG256 FG456 FG556 FG676 FG680 FG860 FG900 FG1156Solder Land (L) diameter 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4Opening in Solder Mask (M) diameter 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5Solder (Ball) Land Pitch (e) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0Line Width between Via and Land (w) 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13Distance between Via and Land (D) 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7Via Land (VL) diameter 0.61 0.61 0.61 0.61 0.61 0.56 0.61 0.61Through Hole (VH), diameter 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3Pad Array Full Full - Full - - Full FullMatrix or External Row 16 x 16 22 x 22 30 x 30 26 x 26 39 x 39 42 x 42 30 x 30 34 x 34

Suggested Board Layout of Soldered Pads for BGA, CS and FG Packages

8-2 February 15, 2000 (Version 2.1)

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Cavity Up or Cavity DownMost Xilinx devices attach the die against the inside bottomof the package (the side that does not carry the Xilinx logo).This is called cavity-up, and has been the standard ICassembly method for over 25 years. This method does notprovide the best thermal characteristics. Pin Grid Arrays(greater than 130 pins) and Ceramic Quad Flat Packs areassembled "Cavity Down", with the die attached to theinside top of the package, for optimal heat transfer to theambient air.

For most packages this information does not affect how thepackage is used because the user has no choice in how thepackage is mounted on a board. For Ceramic Quad FlatPack (CQFP) packages however, the leads can be formedto either side. Therefore, for best heat transfer to the sur-rounding air, CQFP packages should be mounted with thelogo up, facing away from the PC board.

Clockwise or Counterclockwise

The orientation of the die in the package and the orientationof the package on the PC board affect the PC board layout.PLCC and PQFP packages specify pins in a counterclock-wise direction, when viewed from the top of the package(the surface with the Xilinx logo). PLCCs have pin 1 in thecenter of the beveled edge while all other packages havepin 1 in one corner, with one exception: The 100- and165-pin CQFPs (CB100 and CB164) for the XC3000devices have pin 1 in the center of one edge.

CQFP packages specify pins in a clockwise direction, whenviewed from the top of the package. The user can make thepins run counterclockwise by forming the leads such thatthe logo mounts against the PC board. However, heat flowto the surrounding air is impaired if the logo is mounteddown.

Thermal ManagementModern high speed logic devices consume an appreciableamount of electrical energy. This energy invariably turnsinto heat. Higher device integration drives technologies toproduce smaller device geometry and interconnections.With smaller chip sizes and higher circuit densities, heatgeneration on a fast switching CMOS circuit can be verysignificant. The heat removal needs for these moderndevices must be addressed.

Managing heat generation in a modern CMOS logic deviceis an industry-wide pursuit. However, unlike the powerneeds of a typical Application Specific Integrated Circuit(ASIC) gate array, the power requirements for FPGAs arenot determined as the device leaves the factory. Designsvary in power needs.

There is no way of anticipating the power needs of anFPGA device short of depending on compiled data fromprevious designs. For each device type, primary packagesare chosen to handle "typica" designs and gate utilizationrequirements. For the most part the choice of a package asthe primary heat removal casing works well.

Occasionally designers exercise an FPGA device, particu-larly the high gate count variety, beyond "typical" designs.The use of the primary package without enhancement maynot adequately address the device’s heat removal needs.Heat removal management through external means or analternative enhanced package should be considered.

Removing heat ensures the functional and maximumdesign temperature limits are maintained. The device maygo outside the temperature limits if heat build up becomesexcessive. As a consequence, the device may fail to meetelectrical performance specifications. It is also necessaryto satisfy reliability objectives by operating at a lower tem-perature. Failure mechanisms and the failure rate ofdevices depend on device operating temperature. Controlof the package and the device temperature ensures prod-uct reliability.

Package Thermal Characterization Methods & Conditions

Method and CalibrationXilinx uses the indirect electrical method for package ther-mal resistance characterization. The forward-voltage dropof an isolated diode residing on a special test die is cali-brated at constant forcing current of 0.520mA with respectto temperature over a correlation temperature range of22°C to 125°C (degree Celsius). The calibrated device isthen mounted in an appropriate environment (still air,forced convection, circulating FC-40, etc.) Depending onthe package, between 0.5 to 4 watts of power (Pd) isapplied. Power (Pd) is applied to the device through dif-fused resistors on the same thermal die. The resulting risein junction temperature is monitored with the forward-volt-age drop of the precalibrated diode. Typically, three identi-cal samples are tested at each data point. Thereproducibility error in the set-up is within 6%.

Definition of Terms

TJ Junction Temperature — the maximum temperatureon the die, expressed in °C (degree Celsius)

TA Ambient Temperature — expressed in °C.

TC The temperature of the package body taken at adefined location on the body. This is taken at the pri-

Periphery rows - - 7 - 5 6 - -

Table 2: Soldering Dimensions for BG, CS, and FG Packages


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mary heat flow path on the package and representsthe hottest part on the package — expressed in °C.

Tl The isothermal fluid temperature when junction tocase temperature is taken — expressed in °C.

Pd The total device power dissipation — expressed inwatts.

Junction-to-Reference General Setup

Junction-to-Case Measurement — ΘJC

ΘJC is measured in a 3M Flourinert (FC-40) isothermal cir-culating fluid stabilized at 25°C. The Device Under Test(DUT) is completely immersed in the fluid and initial stableconditions are recorded. Pd is then applied. Case temper-ature (TC) is measured at the primary heat-flow path of theparticular package. Junction temperature (TJ) is calculatedfrom the diode forward-voltage drop from the initial stablecondition before power was applied.

ΘJC = (TJ - TC)/Pd

The junction-to-isothermal-fluid measurement (ΘJI) is alsocalculated from the same data.

ΘJL = (TJ - TI)/Pd

The latter data is considered as the ideal ΘJA data for thepackage that can be obtained with the most efficient heatremoval scheme. Other schemes such as airflow, heat-sinks, use of copper clad board, or some combination of allthese will tend towards this ideal figure. Since this is not awidely used parameter in the industry, and it is not veryrealistic for normal application of Xilinx packages, the ΘJIdata is not published. The thermal lab keeps such data forpackage comparisons.

Junction-to-Ambient Measurement — ΘJA

ΘJA is measured on FR4 based PC boards measuring 4.5”x 6.0” x .0625” (114.3mm x 152.4mm x 1.6mm) with edgeconnectors. There are two main board types.

Type I, 2L/0P board, is single layer with 2 signal planes(one on each surface) and no internal Power/GND planes.The trace density on this board is less than 10% per side.Type II, the 4L/2P board, has 2 internal copper planes (onepower, one ground) and 2 signal trace layers on both sur-faces.

Data may be taken with the package mounted in a socket orwith the package mounted directly on the board. Socketmeasurements typically use the 2L/0P boards. SMTdevices may use either board. Published data alwaysreflects the board and mount conditions used.

Data is taken at the prevailing temperature and pressureconditions (22°C to 25°C ambient). The board with the DUTis mounted in a cylindrical enclosure. The power applica-tion and signal monitoring are the same as ΘJC measure-ments. The enclosure (ambient) thermocouple issubstituted for the fluid thermocouple and two extra ther-mocouples brought in to monitor room and board tempera-tures. The junction to ambient thermal resistance iscalculated as follows:

ΘJA = (TJ - TA)/Pd

The setup described herein lends itself to the application ofvarious airflow velocities from 0 - 800 Linear Feet perMinute (LFM), i.e., 0 - 4.06 m/s. Since the board selection(copper trace density, absence or presence of groundplanes, etc.) affects the results of the thermal resistance,the data from these tests shall always be qualified with theboard mounting information.

Data Acquisition and Package Thermal DatabaseXilinx gathers data for a package type in die sizes, powerlevels and cooling modes (air flow and sometimes heatsinkeffects) with a Data Acquisition and Control system (DAS).The DAS controls the power supplies and other ancillaryequipment for hands-free data taking. Different setupswithin the DAS software are used to run calibration, ΘJA,ΘJC, fan tests, as well as the power effect characteristics ofa package.A package is characterized with respect to the major vari-ables that influence the thermal resistance. The results arestored in a database. Thermal resistance data is interpo-lated as typical values for the individual Xilinx devices thatare assembled in the characterized package. Table 3shows the typical values for different packages. Specificdevice data may not be the same as the typical data. How-ever, the data will fall within the given minimum and maxi-mum ranges. The more widely used packages will have awider range. Customers may contact the Xilinx applicationgroup for specific device data.

Figure 3: Thermal Measurement Set-Up (Schematic for Junction to Reference)


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Table 3: Summary of Thermal Resistance for Packages

PKG-CODEΘJA

still air(Max)

ΘJAstill air(Typ)

ΘJAstill air(Min)

ΘJA250 LFM

(Typ)

ΘJA500 LFM

(Typ)

ΘJA750 LFM

(Typ)

ΘJC(Typ)

Comments

°C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt

BG225 37 30 24 19 17 16 3.3 Various

BG256 32 29 24 19 17 16 3.2 4L/2P-SMT

BG352 14 12 10 8 7 6 0.8 4L/2P-SMT

BG432 13 11 9 8 6 6 0.8 4L/2P-SMT

BG560 10 9 8 7 6 5 0.8 Estimated

CB100 44 41 38 25 19 17 5.1 Socketed

CB164 29 26 25 17 12 11 3.6 Socketed

CB196 25 24 24 15 11 10 1.8 Socketed

CB228 19 18 17 11 8 7 1.3 Socketed

CS48 45 Estimated

CS144 65 Estimated

DD8 114 109 97 90 73 60 8.2 Socketed

HQ160 14 14 14 10 8 7 1.0 4L/2P-SMT

FG256 27 25 23 21 20 19 3.9 4L/2P-SMT

FG456 19 18 17 14 13 13 1.5 4L/2P-SMT

FG556 14 14 14 10 9 9 0.8 4L/2P-SMT

FG676 17 17 17 13 12 12 0.9 4L/2P-SMT

FG680 11 11 10 8 6 6 0.9 4L/2P-SMT

FG860 10 10 10 7 6 5 0.8 4L/2P-SMT

FG900 14 14 14 10 9 9 0.8 Estimated

FG1156 14 13 13 10 9 9 0.8 Estimated

HQ208 15 14 14 10 8 7 1.7 4L/2P-SMT

HQ240 13 12 12 9 7 6 1.5 4L/2P-SMT

HQ304 11 11 10 7 5 5 0.9 4L/2P-SMT

HT144 - 10.9 - 7.3 5.7 5.0 0.9 4L/2P-SMT

HT176 - 16.0 - - - - 2.0 Estimated

PC20 86 84 76 63 56 53 25.8 2L/0P-SMT

PC44 51 46 42 35 31 29 13.7 2L/0P-SMT

PC68 46 42 38 31 28 26 9.3 2L/0P-SMT

PC84 41 33 28 25 21 17 5.3 2L/0P-SMT

PD8 82 79 73 60 54 50 22.2 Socketed

PG84 37 34 31 24 18 16 5.8 Socketed

PG120 32 27 25 19 15 13 3.6 Socketed

PG132 32 28 24 20 17 15 2.8 Socketed

PG156 25 23 21 15 11 10 2.6 Socketed

PG175 25 23 20 14 11 10 2.6 Socketed

PG191 24 21 18 15 12 11 1.5 Socketed

PG223 24 20 18 15 12 11 1.5 Socketed

PG299 18 17 16 10 9 8 1.9 Socketed

PG411 16 15 14 9 8 7 1.2 Socketed

PG475 14 13 12 9 8 7 1.2 Socketed

PG559 - 12.00 - - - - - Estimated

PP132 35 34 33 23 18 17 6.0 Socketed


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Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time of compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data in a package may be obtained from the factory.

2. Package configurations and drawings are in the package section of the data book.3. 2L/0P - SMT: the data is from a surface mount type I board -- no internal planes on the board.4. 4L/2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket.5. Air flow is given Linear Feet per Minute (LFM). 500 LFM = 2.5 Meters per Second

Application of Thermal Resistance DataThermal resistance data gauges the IC package thermalperformance. ΘJC measures the internal package resis-tance to heat conduction from the die surface, through thedie mount material to the package exterior. ΘJC stronglydepends on the package’s heat conductivity, architectureand geometrical considerations.

ΘJA measures the total package thermal resistance includ-ing ΘJC. ΘJA depends on the package material propertiesand such external conditions as convective efficiency andboard mount conditions. For example, a package mountedon a socket may have a ΘJA value 20% higher than thesame package mounted on a 4 layer board with power andground planes.

By specifying a few constraints, devices are ensured tooperate within the intended temperature range. This alsoensures device reliability and functionality. The systemambient temperature needs to be specified. A maximum TJalso needs to be established for the system. The followinginequality will hold.

TJ(max) > ΘJA* Pd +TA

The following two examples illustrates the use of this ine-quality.

Example 1: The manufacturer’s goal is TJ (max) < 100°C

A module is designed for a TA = 45°C max.A XC3042 in a PLCC 84 has a ΘJA = 32°C/watt.

Given a XC3042 with a logic design with a rated power Pd of 0.75watt.

With this information, the maximum die temperature can be calculated as:

TJ = 45 + (32 x .75) ==> 69°C.

The system manufacturer’s goal of TJ < 100°C is met.

Example 2: A module has a TA = 55°C max.

The Xilinx XC4013E is in a PQ240 package (HQ240 is also considered).A XC4013E, in an example logic design, has a rated power of 2.50 watts. The module manufacturers goal is TJ(max.) < 100°C.

Table 4 shows the package and thermal enhancement combinations required to meet the goal of TJ < 100°C.

PP175 29 29 28 19 15 13 2.5 Socketed

PQ100 35 33 32 29 28 27 5.5 4L/2P-SMT

PQ160 37 32 22 24 21 20 4.6 2L/0P-SMT

PQ208 35 32 26 23 21 19 4.3 2L/0P-SMT

PQ240 28 23 19 17 15 14 2.8 2L/0P-SMT

SO8 147 147 147 112 105 98 48.3 IEEE-(Ref)

TQ100 37 31 31 26 24 23 7.5 4L/2P-SMT

TQ144 35 32 30 25 21 20 5.3 4L/2P-SMT

TQ176 29 28 27 21 18 17 5.3 4L/2P-SMT

VO8 162 162 162 123 116 108 48.3 Estimated

VQ44 44 44 44 36 34 33 8.2 4L/2P-SMT

VQ64 44 41 39 34 32 31 8.2 4L/2P-SMT

VQ100 47 38 32 32 30 29 9.0 4L/2P-SMT

Table 3: Summary of Thermal Resistance for Packages (Continued)

PKG-CODEΘJA

still air(Max)

ΘJAstill air(Typ)

ΘJAstill air(Min)

ΘJA250 LFM

(Typ)

ΘJA500 LFM

(Typ)

ΘJA750 LFM

(Typ)

ΘJC(Typ)

Comments

°C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt °C/Watt


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Notes: Possible Solutions to meet the module requirements of 100°C :1a.Using the standard PQ240; TJ = 55 + (23.7 x 2.50) ==> 114.25 °C.1b.Using standard PQ240 with 250LFM forced air; TJ = 55 + (17.5 x 2.50) ==> 98.75 °C2a.Using standard HQ240TJ = 55 + (12.5 x 2.50) ==> 86.25 °C2b.Using HQ240 with 250 LFM forced air; TJ = 55 + (8.6 x 2.50) ==> 76.5 °C

For all solutions, the junction temperature is calculated as:TJ = Power x ΘJA + TA. All solutions meet the modulerequirement of less than 100°C, with the exception of thePQ240 package in still air. In general, depending on ambi-

ent and board temperatures conditions, and most impor-tantly the total power dissipation, thermal enhancements --such as forced air cooling, heat sinking, etc. may be neces-sary to meet the TJ(max) conditions set.

PQ/HQ Thermal Data Comparison

Table 4: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages

DeviceName Package

ΘJA

still airΘJA

(250 LFM)ΘJA

(500 LFM)ΘJA

(750 LFM) ΘJC CommentsXC4013E PQ240 23.7 17.5 15.4 14.3 2.7 Cu, SMT 2L/0P

XC4013E HQ240 12.5 8.6 6.9 6.2 1.5 4 Layer Board data

5

10

15

20

25

30

35

ΘJA

(°C

/wat

t)

200 300 400 500 600 700

Die size (mils)

HQ208

HQ240

HQ304

PQ208

PQ240

HQ/PQ Thermal Data

Size effect on ΘJA


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10

15

20

25

30 Θ

JA

(°C

/wa

tt)

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Airflow - LFM

XC4010E-HQ208 XC4013E-HQ240 XC4025E-HQ304XC4010E-PQ208 XC4013E-PQ240

HQ/PQ Thermal DataEffect of Forced Air on ΘJA

0

5

10

15

20

25

ΘJA

(°C

/wa

tt)

0 100 200 300 400 500 600 700

Air Flow - LFM

PG191-XC4010E PG223-XC4013E

PG299-XC4025E PG299-FHS(XC4025E)

PGA 299 Thermal ResistanceEffect of Air Flow on ΘJA


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5

10

15

20

ΘJA

(°C

/wat

t)

A B C D E FPG299 - Various Enhancements

PG299 Thermal ResistanceEffects of Active & Passive Heat sinks

Pkg+Active Fan (V=12)DStandard PkgAStd Pkg +250LFMEPkg+Finned HS (Passive)BPkg+Finned HS+ 250LFMFPkg+Active Fan (V=0)C

10

15

20

25

30

35

40

ΘJA

(°C

/watt)

0 200 400 600 800 Air Flow - LFM

XC4010E-BG225 (2L) XC4013E-BG225(4L) XC73144-BG225(4L)

XC73108-BG225(2L) XC5210-BG225(2L)

BGA Thermal ResistanceEffect of Air Flow on ΘJA


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Some Power Management OptionsFPGA devices are usually not the dominating power con-sumers in a system, and do not have a big impact on powersupply designs. There are obvious exceptions. When theactual or estimated power dissipation appears to be morethan the specification of the chosen package, some optionscan be considered. Details on the engineering designs andanalysis of some of these suggested considerations maybe obtained from the references listed at the end of the sec-tion. The options include:

• A Xilinx low power (L) version of the circuit in the same package. With the product and speed grade of choice, up to a 40% power reduction can be anticipated. For more information, contact the Xilinx Hotline group.

• Explore thermally enhanced package options available for the same device. As illustrated above, the HQ240 package has a thermal impedance of about 50% of the equivalent PQ240. Besides, the 240 lead, the 208 lead and the 304 lead Quad packages have equivalent heatsink enhanced versions. Typically 25% to 40% improvement in thermal performance can be expected from these heatsink enhanced packages. Most of the high gate count devices above the XC4013 level come either exclusively in heat enhanced packages or have these packages as options. If the use of a standard PQ appears to be a handicap in this respect, a move to the equivalent HQ package if available may resolve the issue. The heat enhanced packages are pin to pin compatible and they use the same board layout.

• The use of forced air is an effective way to improve thermal performance. As seen on the graphs and the calculations above, forced air (200 -- 300 LFM) can reduce junction to ambient thermal resistance by 30%.

• If space will allow, the use of finned external heatsinks can be effective. If implemented with forced air as well, the benefit can be a 40% to 50% reduction. The HQ304, all cavity down PGAs, and the BG352 with exposed heatsink lend themselves to the application of external heatsinks for further heat removal efficiency.

• Outside the package itself, the board on which the package sits can have a significant impact. Board designs may be implemented to take advantage of this. Heat flows to the outside of a board mounted package and is sunk into the board to radiate. The effect of the board will be dependent on the size and how it conducts heat. Board size, the level of copper traces on it, the number of buried copper planes all lower the junction-to-ambient thermal resistance for a package. Some of the heatsink packages with the exposed heatsink on the board side can be glued to the board with thermal compound to enhance heat removal.

References

Forced Air Cooling Application Engineering

COMAIR ROTRON2675 Custom House CourtSan Ysidro, CA 921731-619-661-6688

Heatsink Application Engineering

The following facilities provide heatsink solutions for indus-try standard packages.

AAVID Thermal Technologies1 Kool PathBox 400Laconia, NH 03247-04001-603-528-3400

Thermalloy, Inc.2021 W. Valley View LaneBox 810839Dallas, TX 75381-08391-214-243-4321

Wakefield Engineering, Inc.60 Audubon RoadWakefield MA 01880-12551-617-245-5900

Xilinx does not endorse these vendors nor their products.They are listed here for reference only. Any materials orservices received from the vendors should be evaluated forcompatibility with Xilinx components.

Package Electrical CharacterizationIn high-speed systems, the effects of electrical packageparasitics become very critical when optimizing for systemperformance. Such problems as ground bounce andcrosstalk can occur due to the inductance, capacitance,and resistance of package interconnects. In digital sys-tems, such phenomena can cause logic error, delay, andreduced system speed. A solid understanding and properusage of package characterization data during systemdesign simulation can help prevent such problems.

Theoretical Background

There are three major electrical parameters which are usedto describe the package performance: resistance, capaci-tance, and inductance. Also known as interconnect parasit-ics, they can cause many serious problems in digitalsystems. For example, a large resistance can cause RC &RL off-chip delays, power dissipation, and edge-rate degra-dation. Large capacitance can cause RC delays, crosstalk,edge-rate degradation, and signal distortion. The leadinductance, perhaps the most damaging parasitic in digital


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circuitry, can cause such problems as ground bounce (alsoknown as simultaneous switching noise or delta-I noise),RL delays, crosstalk, edge rate degradation, and signal dis-tortion.

Ground bounce is the voltage difference between any twogrounds (typically between an IC and circuit board ground)induced by simultaneously switching current through bond-wire, lead, or other interconnect inductance.

When IC outputs change state, large current spikes resultfrom charging or discharging the load capacitance. Thelarger the load capacitance and faster the rise/fall times,the larger the current spikes are: I = C * dv/dt. Currentspikes through the IC pin and bondwire induces a voltagedrop across the leads and bondwires: V = L * di/dt. Theresult is a momentary voltage difference between the inter-nal IC ground and system ground, which show up as volt-age spikes and unswitched outputs.

Factors that affect ground bounce:

- rise and fall times- load capacitance- package inductance- number of output drivers sharing the same ground

path- device type

Analytical Formulas for Lead Inductance

1. Rectangular Leadframe/Trace (straight)

Lself = nH

(no ground)

Lself = nH

(above ground)

l = lead/trace lengthw = lead/trace widtht = lead/trace thicknessh = ground heightunit = inches

2. Bondwire (gold wire)

Lwire = nH

L = wire lengthr = wire radiusunit = inches

General Measurement Procedure

Xilinx uses the Time-Domain Reflectometry (TDR) methodfor parasitic inductance and capacitance measurements.The main components of a TDR setup includes: a digitizingsampling oscilloscope, a fast rise time step generator (<17ps), a device-under-test (DUT) interface, and an imped-ance-profile analysis software to extract parasitic modelsfrom the TDR reflection waveforms. In this method, a volt-age step is propagated down the package under test, andthe incident and reflected voltage waves are monitored bythe oscilloscope at a particular point on the line. The result-ing characteristic impedance of the package interconnectshows the nature (resistive, inductive, and capacitive) ofeach discontinuity.

Package and Fixture Preparation

Before performing the measurements, the package and theDUT interface must be fixtured. Proper fixturing ensuresaccurate and repeatable measurements. The mechanicalsample for all inductance (self & mutual) measurementsare finished units with all leads shorted to the internalground. For packages without an internal ground (i.e. QFP,PLCC, etc.) the die-paddle is used instead. The mechanicalsample for all capacitance (self & mutual) measurementsare finished units with all internal leads floating. The DUTinterface provides a physical connection between the oscil-loscope and the DUT with minimum crosstalk andprobe/DUT reflection. It also provides small ground loop tominimize ground inductance of the fixture.

Inductance and Capacitance Measurement Pro-cedure

For inductance measurements, a minimum of 25% andmaximum of 50% of packages leads, including all leadsthat are adjacent to the lead(s) under test, are insulatedfrom the DUT fixture ground. All other leads, except for thelead(s) under test, are grounded. This insulation forces thecurrent to return through a low impedance path created onthe opposite side of the package. It also eliminates mutualcoupling from the neighboring leads. Self-inductance ismeasured by sending a fast risetime step waveformthrough the lead under test. The inductive reflection wave-form through the lead and the bondwire is then obtained.This reflection waveform, which includes the inductance ofthe die-paddle (for QFP and PLCC-type packages) andparallel combination of leads in the return path, is theself-inductance. The parasitic effects of the return path aresmall enough to ignore in the context of this method. Formutual-inductance measurement, two adjacent leads areprobed. A fast risetime step waveform is sent through oneof the leads. The current travels through the lead/bondwireand returns by the path of the low-impedance ground. Onthe adjacent “quiet” lead, a waveform is induced due tomutual coupling. This waveform is measured as the mutualinductance.

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For capacitance measurements, all external leads exceptfor the lead(s) under test are grounded to the DUT fixture.For QFP, PLCC, and Power Quad-type of packages, thedie-paddle and the heat slug are left floating. Self-capaci-tance is measured by sending a fast risetime step wave-form through the lead under test. The reflection waveformfrom the lead, which includes the sum of all capacitive cou-pling with respect to the lead under test, is then measured.Appropriately, the self-capacitance can also be called the“bulk” capacitance since the measured value includes thecapacitance between the lead under test and all surround-ing metal, including the ground plane and the heat slug. Formutual-capacitance measurement, two adjacent leads areprobed. An incident waveform is sent through one lead, andthe induced waveform on the neighboring lead is measuredas the mutual capacitance.

In order to de-embed the electrical parasitics of the DUTfixture and the measuring probes, the short and the opencompensation waveforms are also measured after eachpackage measurement. This procedure compensates theDUT fixture to the very tip of the probes.

Inductance & Capacitance Model Extraction

All measured reflection waveforms are downloaded to a PCrunning the analysis software for package parasitic model

extraction. The software uses a method called the Z-profilealgorithm, or the impedance-profile algorithm, for parasiticanalysis. This method translates the downloaded reflectionwaveforms into true impedance waveforms, from whichpackage models for inductance and capacitance areextracted.

Data Acquisition and Package Electrical DatabaseXilinx acquires electrical parasitic data only on the longestand the shortest lead/traces of the package. This providesthe best and the worst case for each package type (definedby package design, lead/ball count, pad size, and vendor).For convenience, the corner interconnects are usuallyselected as the longest interconnect, while the center inter-connects are usually selected as the shortest.

For symmetrical quad packages, all four sides of the pack-age are measured and averaged. Three to five samples areusually measured for accuracy and continuity purposes.The average of these samples is then kept as the officialmeasured parasitic data of that package type in the data-base.

Component Mass (Weight) by Package Type

Package Description JEDEC Outline # Xilinx # Mass (g)BG225 MOLDED BGA 27 mm FULL MATRIX MO-151-CAL OBG0001 2.2

BG256 MOLDED BGA 27 mm SQ MO-151-CAL OBG0011 2.2

BG352 SUPERBGA - 35 X 35 mm PERIPHERAL MO-151-BAR OBG0008 7.1

BG432 SUPERBGA - 40 X 40 mm PERIPHERAL MO-151-BAU OBG0009 9.1

BG560 SUPERBGA - 42.5 X 42.5 mm SQ MO-192-BAV OBG0010 11.5

CB100 NCTB TOP BRAZE 3K VER MO-113-AD3 OCQ0008 10.8


CB164 NCTB TOP BRAZE 3K VER MO-113-AA-AD3 OCQ0003 11.5

CB164 NCTB TOP BRAZE 4K VER MO-113-AA-AD3 OCQ0007 11.5

CB196 NCTB TOP BRAZE 4K VER MO-113-AB-AD3 OCQ0005 15.3


DD8 .300 CERDIP PACKAGE MO-036-AA OPD0005 1.1

HQ160 METRIC 28 28 -.65 mm 1.6H/S DIE UP MO-108-DDI OPQ0021 10.8

HQ208 METRIC 28 X 28 - H/S DIE UP MO-143-FA1 OPQ0020 10.8

HQ240 METRIC QFP 32 32 - H/S DIE UP MO-143-GA OPQ0019 15.0

HQ304 METRIC QFP 40 40-H/S DIE DOWN MO-143-JA OPQ0014 26.2

PC20 PLCC JEDEC MO-047 MO-047-AA OPC0006 0.8

PC44 PLCC JEDEC MO-047 MO-047-AC OPC0005 1.2

PC68 PLCC JEDEC MO-047 MO-047-AE OPC0001 4.8

PC84 PLCC JEDEC MO-047 MO-047-AF OPC0001 6.8

PD8 DIP .300 STANDARD MO-001-AA OPD0002 0.5

PG84 CERAMIC PGA CAV UP 11X11 MO-067-AC OPG0003 7.2

PG120 CERAMIC PGA 13 X 13 MATRIX MO-067-AE OPG0012 11.5

PG132 CERAMIC PGA 14 X 14 MATRIX MO-067-AF OPG0004 11.8


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Notes: 1. Data represents average values for typical packages with typical devices. The accuracy is between 7% to 10%.2. More precise numbers (below 5% accuracy) for specific devices may be obtained from Xilinx through a factory

representative or by calling the Xilinx Hotline.3. Tie-bar details are specific to Xilinx package. Lead width minimum is 0.056”.

Xilinx Thermally Enhanced Packaging

The Package Offering

PG156 CERAMIC PGA 16 X 16 MATRIX MO-067-AH OPG0007 17.1

PG175 CERAMIC PGA 16 X 16 STD VER. MO-067-AH OPG0009 17.7

PG191 CERAMIC PGA 18 X 18 STD - ALL MO-067-AK OPG0008 21.8

PG223 CERAMIC PGA 18 X 18 TYPE MO-067-AK OPG0016 26.0

PG299 CERAMIC PGA 20 X 20 HEATSINK MO-067-AK OPG0022 37.5

PG299 CERAMIC PGA 20 X 20 TYPE MO-067-AK OPG0015 29.8

PG411 CERAMIC PGA 39 X 39 STAGGER MO-128-AM OPG0019 36.7

PG475 CERAMIC PGA 41 X 41 STAGGER MO-128-AM OPG0023 39.5

PG559 CERAMIC PGA 43 x 43 MO-128 OPG0025 44.50

PP132 PLASTIC PGA 14 X 14 MATRIX MO-83-AF OPG0001 8.1

PP175 PLASTIC PGA 16 X 16 BURIED MO-83-AH OPG0006 11.1

PQ100 EIAJ 14 X 20 QFP - 1.60 MO-108-CC1 OPQ0013 1.6

PQ160 EIAJ 28 X 28 .65 mm 1.60 MO-108-DD1 OPQ0002 5.8

PQ208 EIAJ 28 X 28 .5 mm 1.30 MO-143-FAI OPQ0003 5.3

PQ240 EIAJ 32 X 32 .5 mm MO-143-GA OPQ0010 7.1

SO8 VERSION 1 - .150/55MIL MO-150 OPD0006 0.1

TQ100 THIN QFP 1.4 mm thick MS-026-BDE OPQ0004 0.7

TQ144 THIN QFP 1.4 mm thick MS-026-BFB OPQ0007 1.4

TQ176 THIN QFP 1.4 mm thick MS-026-BGA OPQ0008 1.9

CS48 Chip Scale 7 x 7 mm, 0.8 mm ball pitch - OBG0012 0.2

CS144 Chip Scale 12 x 12 mm, 0.8 mm ball pitch MO-205-BE OBG0015 0.3

FG256 Fine Pitch BGA 17 x 17 mm, 1.0 mm ball pitch MO-151-AAF-1 OBG0021 0.8

FG456 Fine PItch BGA 23 x 23 mm, 1.0 mm ball pitch MO-151-AAJ-1 OBG0019 2.1

FG556 Fine Pitch BGA 31 x 31 mm, 1.0 mm ball pitch MO-151-AAN-1 OBG0020 3.92

FG676 Fine PItch BGA, 27 x 27 mm, 1.0 mm ball pitch MO-151-AAL-1 OBG0018 3.3

FG680 Fine PItch BGA 40 x 40 mm, 1.0 mm ball pitch MO-151-AAU-1 OBG0022 10.3

FG900 Fine Pitch BGA, 31 x 31 mm, 1.0 mm ball pitch MO-151-AAN-1 OBG0027 4.0

FG1156 Fine Pitch BGA, 35 x 35 mm, 1.0 mm ball pitch MO-151-AAR-1 OBG0028 5.5

VO8 THIN SOIC-II N/A OPD0007 0.1

VQ44 THIN QFP 1.0 thick MS-026-ACB OPQ0017 0.4

VQ64 THIN QFP 1.0 thick MS-026-ACD OPQ0009 0.5

VQ100 THIN QFP 1.0 thick MS-026-AED OPQ0012 0.6

Component Mass (Weight) by Package Type (Continued)

Package Description JEDEC Outline # Xilinx # Mass (g)

Xilinx Code Body (mm) THK (mm) Mass (gm)Heatsink Location

JEDEC No. Xilinx No.

HQ160 28x28 3.40 10.8 DOWN MO-108-DD1 OPQ0021

HQ208 28x28 3.40 10.0 DOWN MO-143-FA OPQ0020

HQ240 32x32 3.40 15.0 DOWN MO-143-GA OPQ0019

HQ304 40x40 3.80 26.2 TOP MO-143-JA OPQ0014


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Overview

Xilinx offers thermally enhanced quad flat pack packageson certain devices. This section discusses the performanceand usage of these packages (designated HQ). In sum-mary:

• The HQ-series and the regular PQ packages conform to the same JEDEC drawings.

• The HQ and PQ packages use the same PCB land patterns.

• The HQ packages have more mass • Thermal performance is better for the HQ packages

Where and When Offered - HQ packages are offered as the thermally enhanced

equivalents of PQ packages. They are used for high gate count or high l/O count devices in packages, where heat dissipation without the enhancement may be a handicap for device performance. Such devices include XC4013E, XC4020E, XC4025E, and XC5215.

- They are also being used in place of MQUAD (MQ) packages of the same lead count for new devices.

- The HQ series at the 240 pin count level or below are offered with the heatsink at the bottom of the package. This was done to ensure pin to pin compatibility with the existing PQ and MQ packages.

- At the 304 pin count level, the HQ is offered with the heatsink up. This arrangement offers a better potential for further thermal enhancement by the designer.

Mass Comparison

Because of the copper heatsink, the HQ series of packagesare about twice as heavy as the equivalent PQ. Here is aquick comparison.

Thermal Data for the HQ

The data for individual devices may be obtained from Xilinx.

Note: ΘJC is typically between 1 and 2 °C/Watt for HQ and MQ Packages. For PQ’s, it is between 2 and 7 °C/Watt.

Other Information- Leadframe: Copper EFTEC-64 or C7025- Heat Slug: Copper - Nickel plated → Heatsink metal

is Grounded- Lead Finish 85/15 Sn/Pb 300 microinches minimum- D/A material - Same as PQ; Epoxy 84-1LMISR4- Mold Cpd. Same as PQ - EME7304LC- Packed in the same JEDEC trays

Moisture Sensitivity of PSMCs

Moisture Induced Cracking During Solder Reflow

The surface mount reflow processing step subjects thePlastic Surface Mount Components (PSMC) to high ther-mal exposure and chemicals from solder fluxes and clean-ing fluids during user’s board mount assembly. The plasticmold compounds used for device encapsulation are, uni-versally, hygroscopic and absorb moisture at a level deter-mined by storage environment and other factors.Entrapped moisture can vaporize during rapid heating inthe solder reflow process generating internal hydrostaticpressure. Additional stress is added due to thermal mis-match, and the Thermal Coefficient of Expansion (TCE) ofplastic, metal lead frame, and silicon die. The resultantpressure may be sufficient to cause delamination within thepackage, or worse, an internal or external crack in the plas-tic package. Cracks in the plastic package can allow highmoisture penetration, inducing transport of ionic contami-

nants to the die surface and increasing the potential for early device failure.

HQ (gm) PQ (gm)160 Pin 10.8 5.8

208 Pin 10.8 5.3

240 Pin 15.0 7.1

304 Pin 26.2 N/A

A Die Up/Heatsink Down

A – Heatsink down orientationB – Heatsink up orientation

B Die Down/Heatsink Up

X5962

Still Air Data ComparisonHQ

ΘJA (°C/Watt)PQ

ΘJA (°C/watt)

160 Pin 13.5-14.5 20.5-38.5

208 Pin 14-15 26-35

240 Pin 12-13 19-28

304 Pin 10-11 N/A

Data Comparison at Airflow - 250 LFMHQ

ΘJA (°C/watt)PQ

ΘJA (°C/watt)

160 Pin 9-10 15-28.5

208 Pin 9-10 14-26

240 Pin 8-9 11-21

304 Pin 6.5-8 N/A


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How the effects of moisture in plastic packages and the crit-ical moisture content result in package damage or failure isa complex function of several variables. Among them arepackage construction details -- materials, design, geome-try, die size, encapsulant thickness, encapsulant proper-ties, TCE, and the amount of moisture absorbed. ThePSMC moisture sensitivity has, in addition to packagecracking, been identified as a contributor to delamina-tion-related package failure artifacts. These package failureartifacts include bond lifting and breaking, wire neckdown,bond cratering, die passivation, and metal breakage.

Because of the importance of the PSMC moisture sensitiv-ity, both device suppliers and device users have ownershipand responsibility. The background for present conditions,moisture sensitivity standardized test and handling proce-dures have been published by two national organizations.Users and suppliers are urged to obtain copies of both doc-uments (listed below) and use them rigorously. Xilinxadheres to both.

• JEDEC STANDARD JESD22-A112. Test Method A112 “Moisture-Induced Stress Sensitivity for Plastic Surface Mounted Devices”.Available through Global Engineering Documents Phone: USA and Canada 800-854-7179, International 1-303-792-2181

• IPC Standard IPC-SM-786A “Procedures for Characterizing and Handling of Moisture/Reflow Sensitive ICs”.

Available through IPC Phone: 1-708-677-2850

None of the previously stated or following recommenda-tions apply to parts in a socketed application. For boardmounted parts careful handling by the supplier and the useris vital. Each of the above publications has addressed thesensitivity issue and has established 6 levels of sensitivity(based on the variables identified). A replication of thoselistings, including the preconditioning and test require-ments, and the factory floor life conditions for each level areoutlined in Table 5. Xilinx devices are characterized to theirproper level as listed. This information is conveyed to theuser via special labeling on the Moisture Barrier Bag(MBB).

In Table 5, the level number is entered on the MBB prior toshipment. This establishes the user’s factory floor life con-ditions as listed in the time column. The soak requirementis the test limit used by Xilinx to determine the level number.This time includes manufacturer’s exposure time or the timeit will take for Xilinx to bag the product after baking.

Notes: X =Default value of semiconductor manufacturer’s time between bake and bag. If the semiconductor manufacturer’s actual time between bake and bag is different from the default value, use the actual time.

Y = Floor life of package after it is removed from dry pack bag.Z = Total soak time for evaluation.

Table 5: Package Moisture Sensitivity Levels per J-STD-020

Level Factory Floor Life Soak Requirements (Preconditioning)Conditions Time Time Conditions

1 ≤30°C / 90% RH

Unlimited 168 hours 85°C / 85% RH

2 ≤30°C / 60% RH

1 year 168 hours 85°C / 60% RH

Time (hours)

X + Y = Z

3 ≤30°C / 60% RH

168 hours 24 168 192 30°C / 60% RH

4 ≤30°C / 60% RH

72 hours 24 72 96 30°C / 60% RH

5 ≤30°C / 60% RH

24/28 hours 24 24/48 48/72 30°C / 60% RH

6 ≤30°C / 60% RH

6 hours 0 6 6 30°C / 60% RH


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Factory Floor Life

Factory floor life conditions for Xilinx devices are clearlystated on MBB containing moisture sensitive PSMCs.These conditions have been ascertained by following TestMethods outlined in JEDEC JESD22-A112 and are repli-cated in Table 5. If factory floor conditions are outside thestated environmental conditions (30°C/90% RH for level 1,and 30°C/60% RH for Levels 2-6) or if time limits have beenexceeded, then recovery can be achieved by baking thedevices before the reflow step. Identified in the next sectionare two acceptable bake schedules. Either can be used forrecovery to the required factory floor level.

Dry Bake Recommendation and Dry Bag PolicyXilinx recommends, as do the mentioned publications andother industry studies, that all moisture sensitive PSMCs bebaked prior to use in surface mount applications, or complystrictly with requirements as specified on the MBB. Tapeand Reeled parts are universally dry packed. Level 1 partsare shipped without the need for, or use of, an MBB.

Two bake schedules have been identified as acceptableand equivalent. The first is 24 hours in air at 125°C., in ship-ping media capable of handling that temperature. The sec-ond bake schedule is for 192 hours in a controlledatmosphere of 40°C, equal to or less than 5% RH.

Dry Devices are sealed in special military specificationMoisture Barrier Bags (MBB). Enough desiccant pouchesare enclosed in the MBB to maintain contents at less than20% RH for up to 12 months from the date of seal. A revers-ible Humidity Indicator Card (HIC) is enclosed to monitorthe internal humidity level. The loaded bag is then sealedshut under a partial vacuum with an impulse heat sealer.

Artwork on the bags provides storage, handling and useinformation. There are areas to mark the seal date, quan-tity, and moisture sensitivity level and other information.The following paragraphs contain additional information onhandling PSMCs.

Handling Parts in Sealed Bags

Inspection

Note the seal date and all other printed or hand enterednotations. Review the content information against what wasordered. Thoroughly inspect for holes, tears, or puncturesthat may expose contents. Xilinx strongly recommends thatthe MBB remain closed until it reaches the actual work sta-

tion where the parts will be removed from the factory ship-ping form.

Storage

The sealed MBB should be stored, unopened, in an envi-ronment of not more than 90% RH and 40°C. The enclosedHIC is the only verification to show if the parts have beenexposed to moisture. Nothing in part appearance can verifymoisture levels.

Expiration Date

The seal date is indicated on the MBB. The expiration dateis 12 months from the seal date. If the expiration date hasbeen exceeded or HIC shows exposure beyond 20% uponopening the bag bake the devices per the earlier statedbake schedules. The three following options apply afterbaking:

Use the devices within time limits stated on the MBB.

Reseal the parts completely under a partial vacuum with an impulse sealer (hot bar sealer) in an approved MBB within 12 hours, using fresh desiccant and HIC, and label accordingly. Partial closures using staples, plastic tape, or cloth tape are unacceptable.

Store the out-of-bag devices in a controlled atmosphere at less than 20% RH. A desiccator cabinet with con-trolled dry air or dry nitrogen is ideal.

Other Conditions

Open the MBB when parts are to be used. Open the bag bycutting across the top as close to the seal as possible. Thisprovides room for possible resealing and adhering to thereseal conditions outlined above. After opening, strictlyadhere to factory floor life conditions to ensure that devicesare maintained below critical moisture levels.

Bags opened for less than one hour (strongly dependent onenvironment) may be resealed with the original desiccant. Ifthe bag is not resealed immediately, new desiccant or theold one that has been dried out may be used to reseal, ifthe factory floor life has not been exceeded. Note thatfactory floor life is cumulative. Any period of time whenMBB is opened must be added to all other opened periods.

Both the desiccant pouches and the HIC are reversible.Restoration to dry condition is accomplished by baking at125°C for 10-16 hours, depending on oven loading condi-tions.


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Tape and ReelXilinx offers a tape & reel packing for PLCC, BGA, QFP, andSO packages. The packing material is made of black con-ductive Polystyrene and protects the packages frommechanical and electrical damage. The reel material pro-vides a suitable medium for pick and place equipment.

The tape & reel packaging consists of a pocketed carriertape, sealed with a protective cover. The device sits on ped-estals (for PLCC, QFP packages) to protect the leads frommechanical damage. All devices loaded into the tape carri-ers are baked, lead scanned before the cover tape isattached and sealed to the carrier. In-line mark inspectionfor mark quality and package orientation is used to ensureshipping quality.

Benefits• Increased quantity of devices per reel versus tubes

improves cycle time and reduces the amount of time to index spent tubes.

• Tape & reel packaging enables automated pick and place board assembly.

• Reels are uniform in size enabling equipment flexibility.• Transparent cover tape allows device verification and

orientation.• Anti-static reel materials provides ESD protection.• Carrier design include a pedestal to protect package

leads during shipment.• Bar code labels on each reel facilitate automated

inventory control and component traceability.• All tape & reel shipments include desiccant pouches

and humidity indicators to insure products are safe from moisture.

• Compliant to Electronic Industries Association (EIA) 481.

Material and Construction

Carrier Tape• The pocketed carrier Tape is made of conductive

polystyrene material, or equivalent, with a surface resistivity level of less than 106 ohms per square inch.

• Devices are loaded ‘live bug’ or leads down, into a device pocket.

• Each carrier pocket has a hole in the center for automated sensing of whether a unit is in the pocket or not.

• Sprocket holes along the edge of the carrier tape enable direct feeding into an automated board assembly equipment.

Cover Tape• An anti-static, transparent, polyester cover tape, with

heat activated adhesive coating, sealed to the carrier edges to hold the devices in the carrier pockets.

• Surface resistivity on both sides is less than 1011 ohms per square inch.

Reel• The reel is made of anti-static Polystyrene material. The

loaded carrier tape is wound onto this conductive plastic reel.

• A protective strip made of conductive Polystyrene material is placed on the outer part of the reel to protect the devices from external pressure in shipment.

• Surface resistivity is less than 1011 ohms per square inch.

• Device loading orientation is in compliance with EIA Standard 481.

Bar Code Label• The bar code label on each reel provides customer

identification, device part number, date code of the product and quantity in the reel.

• Print quality are in accordance with ANSI X3.182-1990 Bar Code Print Quality Guidelines. Presentation of Data on labels are EIA-556-A compliant.

• The label is an alphanumeric, medium density Code 39 labels.

• This machine-readable label enhances inventory management and data input accuracy.

Shipping Box• The shipping container for the reels are in a 13” x 13” x

3” C-flute, corrugated, # 3 white ‘pizza’ box, rated to 200 lb test.

l

Table 6: Tape & Reel Packaging

Package Type Pin CountCarrierWidth

Cover Width Pitch Reel Size

Qty per Reel

PLCC (Plastic Leaded Chip Carrier) 20 16 mm 13.3 mm 12 mm 7 inch 250

20 16 mm 13.3 mm 12 mm 13 inch 750

44 32 mm 25.5 mm 24 mm 13 inch 500

68 44 mm 37.5 mm 32 mm 13 inch 250

84 44 mm 37.5 mm 36 mm 13 inch 250

SO (Plastic Small Outline) 8 12 mm 9.2 mm 8 mm 7 inch 750


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Notes: 1.A minimum of 230mm of empty pockets are provided at the beginning (leader) of each reel.2.A minimum of 160mm of empty pockets are provided at the end (trailer) of each reel.3.Tape Leader/Trailer requirements are in compliance to EIA Standards 481.4.Peel Strength between 20 and 120 grams ensures consistency during de-reeling operations and is compliant to EIA Standard 481.5.Each reel is subject to peel back strength tests.6.For packages not listed above, please contact your Xilinx sales representative for updated information.

Standard Bar Code Label Locations

QFP (Plastic Quad Flat Pack) PQ, VQ, TQ, HQ

100 44 mm 37.5 mm 32 mm 13 inch 250

160 44 mm 37.5 mm 40 mm 13 inch 200

BGA (Plastic Ball Grid Array) 225/256 44 mm 37.5 mm 32 mm 13 inch 500

SBGA 352/432/560 56 mm 49.5 mm 40,48,48 mm 13 inch 200

Table 6: Tape & Reel Packaging

Package Type Pin CountCarrierWidth

Cover Width Pitch Reel Size

Qty per Reel


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Reflow Soldering Process GuidelinesTo implement and control the production of surface mountassemblies, the dynamics of the solder reflow process andhow each element of the process is related to the end resultmust be thoroughly understood.

The primary phases of the reflow process are as follows:

1. Melting the particles in the solder paste

2. Wetting the surfaces to be joined

3. Solidifying the solder into a strong metallurgical bond

The sequence of five actions that occur during this processis shown in Figure 4.

Each phase of a surface mount reflow profile has min/maxlimits that should be viewed as a process window. The pro-cess requires a careful selection and control of the materi-als, geometries of the mating surfaces (package footprintvs. PCB land pattern geometries) and the time temperatureof the profile. If all of the factors of the process are suffi-ciently optimized, there will be good solder wetting and filletformation (between component leads and the land patternson the substrate). If factors are not matched and optimizedthere can be potential problems as summarized in Figure 5.

200

150

100

50

Tem

pera

ture

( C

)

Time

Sol

vent

Eva

pora

tion

Flu

x R

educ

esM

etal

Oxi

des

Sol

der B

alls

Mel

t,W

ettin

g an

d W

icki

ng B

egin

Sol

der M

eltin

g C

ompl

etes

,S

urfa

ce T

ensi

on T

akes

Ove

r

Coo

l Dow

n P

hase

Reflow Soldering Phases

X5975

Figure 4: Soldering Sequence

Time

Tem

pera

ture

Potential Reflow Soldering Issues

X5976

1. Insufficient Temperature to Evaporate Solvent2. Component Shock and Solder Splatter3. Insufficient Flux Activation4. Excessive Flux Activity and Oxidation5. Trapping of Solvent and Flux, Void Formation6. Component and/or Board Damage

2

1

4

3

5

6

Figure 5: Soldering Problems Summary


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Figure 6 and Figure 7 show typical conditions for solderreflow processing using IR/Convection or Vapor Phase.Both IR and Convection furnaces are used for BGA assem-bly. The moisture sensitivity of Plastic Surface Mount Com-ponents (PSMCs) must be verified prior to surface mountflow. See the preceding sections for a more complete dis-cussion on PSMC moisture sensitivity.

The peak reflow temperature of the PSMC body should notbe more than 220° C in order to avoid internal packagedelamination. For multiple BGAs in a single board, it is rec-ommended to check all BGA sites for varying temperaturesbecause of differences in surrounding components.

Figure 6: Typical Conditions for IR Reflow Soldering

Notes:1. Max temperature range = 220°C-235°C (leads)

Time at temp 30-60 seconds2. Preheat drying transition rate 2-4°C/s3. Preheat dwell 95-180°C for 120-180 seconds4. IR reflow shall be performed on dry packages

The IR process is strongly dependent on equipment and loading differences. Components may overheat due to lack of thermal constraints. Unbalanced loading may lead to significant temperature variation on the board. This guideline is intended to assist users in avoiding damage to the components; the actual profile should be determined by the users using these guidelines.

Time (s)

Tem

pera

ture

C

Preheat & drying dwell120 - 180 sbetween 95 - 180 C (Note 3)

Temp = 183 C

2 - 4 C/s

t183

Ramp down2 - 4 C/s

T-Max (body) = 220˚ CT-Max (leads) = 235˚ C

60s < t183 < 120sapplies to lead area

X5973

(Note 2)

Figure 7: Typical Conditions for Vapor Phase Reflow Soldering

Notes:1. Solvent - FC5312 or equivalent - ensures temperature

range of leads @ 215-219°C2. Transition rate 4-5°C/s3. Dwell is intended for partial dryout and reduces the

difference in temperature between leads and PCB land patterns.

4. These guidelines are for reference. They are based on laboratory runs using dry packages. It is recommended that actual packages with known loads be checked with the commercial equipment prior to mass production.

Time (s)

Tem

pera

ture

C

Preheat & drying dwell120 s min between 95˚ - 180˚ C (Note 3)

Ramp down

2˚ - 4˚ C/st183Dwell = 30 - 60 s

215˚ - 219˚ C≅ 45 s max

X5974

(Note 2)

(Note 2)


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1

2

3

4

5

6

7

8

9

10

11

12

13

SocketsTable 7 lists manufacturers known to offer sockets for XilinxPackage types. This summary does not imply an endorse-

ment by Xilinx. Each user has the responsibility to evaluateand approve a particular socket manufacturer.

Table 7: Socket Manufacturers

Manufacturer

Packages

DIPSOVO

PCWC

PQHQTQVQ

PGPP CB

BGCG

AMP Inc.470 Friendship RoadHarrisburg, PA 17105-3608(800) 522-6752

X X X

Augat Inc.452 John Dietsch Blvd.P.O. Box 2510Attleboro Falls, MA 02763-2510(508) 699-7646

X X X

McKenzie Socket Division910 Page AvenueFremont, CA 94538(510) 651-2700

X X X

3M Textool6801 River Place Blvd.Austin, TX 78726-9000(800) 328-0411(612) 736-7167

X X X

Wells Electronics1701 South Main StreetSouth Bend, IN 46613-2299(219) 287-5941

X

Yamaichi Electronics Inc.2235 Zanker RoadSan Jose, CA 95131(408) 456-0797

X X X X


Package DrawingsCeramic DIP Package - DD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMPlastic DIP Package - PD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMSOIC and TSOP Packages - SO8, VO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMSOIC Package - SO20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMSOIC Package - SO24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMPLCC Packages - PC20, PC28, PC44, PC68, PC84 . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic Leaded Chip Carrier Package - CC44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Chip Scale Package - CS48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Chip Scale Package - CS144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Chip Scale Package - CS280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Chip Scale (0.5 mm pitch) Package - CP56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMVQFP Packages - VQ44, VQ64, VQ100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMTQFP/HTQFP Packages - TQ100, TQ144, TQ176, HT100, HT144, HT176 . . . . . . . CD-ROMTQFP Package - TQ128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMTQFP Package - TQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMPQ/HQFP Packages - PQ100, HQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMPQ/HQFP Packages - PQ44, PQ160, PQ208, PQ240, HQ160, HQ208, HQ240. . . . CD-ROMPQ/HQFP Packages - PQ304, HQ304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBGA Package - BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBGA Package - BG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBGA Packages - BG352, BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBGA Package - BG492 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBGA Package - BG560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Packages - PG68, PG84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Packages - PG120, PG132, PG156 . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Package - PG175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Package - PG191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Packages - PG223, PG299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Package - PG411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Package - PG475. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic PGA Package - PG559. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic Brazed QFP Package - CB100 (XC3000 Version) . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic Brazed QFP Package - CB164 (XC3000 Version) . . . . . . . . . . . . . . . . . . . . CD-ROMCeramic Brazed QFP Packages - CB100, CB164, CB196 (XC4000 Version) . . . . . . CD-ROMCeramic Brazed QFP Package - CB228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG456 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROMBall Fine Pitch Package - FG1156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD-ROM

0

Package Drawings

February 15, 2000 (Version 2.1) 0 8*

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