8/7/2019 Modes Registers
1/18
4/7/2011 1
Processor ModesProcessor Modes ARM has 7 operating modesARM has 7 operating modes
--UserUser(unprivileged mode under which most tasks run)(unprivileged mode under which most tasks run)
--Fast Interrupt Request Mode FIQFast Interrupt Request Mode FIQ
(to handle high priority interrupt )(to handle high priority interrupt )
--Interrupt Mode IRQInterrupt Mode IRQ(entered when a low priority interrupt is raised )(entered when a low priority interrupt is raised )
--Supervisor Mode SVCSupervisor Mode SVC
(entered on reset or a software interrupt )(entered on reset or a software interrupt )
--Abort Mode ABTAbort Mode ABT
(used to handle memory access violation)(used to handle memory access violation)
--Undefined Mode UNDUndefined Mode UND
(used to handle undefined instruction)(used to handle undefined instruction)
--System Mode SYSSystem Mode SYS
(uses same registers as user mode)(uses same registers as user mode)
8/7/2019 Modes Registers
2/18
4/7/2011 2
MODESMODES Most application program run in User ModeMost application program run in User Mode
A program in user mode is unable to access someA program in user mode is unable to access someprotected system resources or to change mode , otherprotected system resources or to change mode , other
than by causing exceptionthan by causing exception
Mode change can be byMode change can be by
--Software controlSoftware control
--External interruptsExternal interrupts
--Exception processingException processing
8/7/2019 Modes Registers
3/18
4/7/2011 3
MODESMODES Modes other than user mode are calledModes other than user mode are called privileged modesprivileged modes
Privileged modes has full access to the systemPrivileged modes has full access to the system
resourcesresources
Five of them are called exception modesFive of them are called exception modes--FIQFIQ
--IRQIRQ
--SVCSVC--ABTABT
--UNDUND
8/7/2019 Modes Registers
4/18
4/7/2011 4
MODESMODES
Processor enters into Privileged modes underProcessor enters into Privileged modes under
specific exception conditionspecific exception condition
All the exception Modes uses some additionalAll the exception Modes uses some additionalregisters ,to avoid corrupting the user stateregisters ,to avoid corrupting the user state
when exception occurswhen exception occurs
SYS uses the same no: of registers as the UserSYS uses the same no: of registers as the User
ModeMode
8/7/2019 Modes Registers
5/18
Register BankRegister BankARM 7 uses load and store Architecture.ARM 7 uses load and store Architecture.
Data has to be moved from memory location to aData has to be moved from memory location to a
central set of registers.central set of registers.
Data processing is done and is stored back intoData processing is done and is stored back into
memory.memory.
Register bank contains, general purpose registers toRegister bank contains, general purpose registers to
hold either data or address.hold either data or address.
It is a bank of 16 user registers R0It is a bank of 16 user registers R0--R15 and 2 statusR15 and 2 statusregisters.registers.
Each of these registers is 32 bit wide.Each of these registers is 32 bit wide.
4/7/2011 5
8/7/2019 Modes Registers
6/18
4/7/2011 6
REGISTERSREGISTERS
ARM hasARM has 3737 32 bit long registers32 bit long registers
30 general purpose registers30 general purpose registers 5 dedicated5 dedicated SSavedaved PProgramrogram SStatustatus RRegistersegisters
1 dedicated1 dedicated CCurrenturrent PProgramrogram SStatustatus RRegisteregister
1 dedicated program counter1 dedicated program counter
8/7/2019 Modes Registers
7/18
4/7/2011 7
General Purpose RegistersGeneral Purpose Registers
Can be divided into three groupsCan be divided into three groups
UnUn--banked r0banked r0--r7r7
Banked r8Banked r8--r14r14 PC r15PC r15
8/7/2019 Modes Registers
8/18
4/7/2011 8
UnUn--banked Registersbanked Registers
RegistersRegisters r0r0 toto r7r7
Each of these registers address the same physicalEach of these registers address the same physicalregisters for all the modesregisters for all the modes
Completely general purpose registers , with noCompletely general purpose registers , with nouses implied by the architectureuses implied by the architecture
8/7/2019 Modes Registers
9/18
4/7/2011 9
Banked RegistersBanked Registers
RegistersRegisters r8r8toto r14r14
physical registers referred to by each of themphysical registers referred to by each of them
depends on the mode of operationdepends on the mode of operation
Banked register contents are preserved acrossBanked register contents are preserved across
operating mode changesoperating mode changes
8/7/2019 Modes Registers
10/18
4/7/2011 10
Banked RegistersBanked Registers
r8 to r12r8 to r12
* two banked physical registers each* two banked physical registers each
*one for FIQ and other for all other modes*one for FIQ and other for all other modes
*referred to as r8_usr to r12_usr & r8_fiq to r12_fiq*referred to as r8_usr to r12_usr & r8_fiq to r12_fiq
r13 & r14r13 & r14
*has six banked registers each*has six banked registers each
*one in USER & SYS and rest five in each exception modes*one in USER & SYS and rest five in each exception modes*referred to as r13_/r14_*referred to as r13_/r14_(for exception modes)(for exception modes)
8/7/2019 Modes Registers
11/18
4/7/2011 11
General Purpose RegistersGeneral Purpose Registers
3030 32 bit registers32 bit registers
15 general purpose registers are visible at one15 general purpose registers are visible at one
time , depending on the current processor modetime , depending on the current processor mode
,as,as r0,r1,r2 r13,r14r0,r1,r2 r13,r14
r13r13--conventionallyused as stack pointerconventionallyused as stack pointer
r14r14 conventionallyused as link register to storeconventionallyused as link register to store
the return address for exception/ subthe return address for exception/ sub--routineroutine
callcall
8/7/2019 Modes Registers
12/18
4/7/2011 12
Program CounterProgram Counter
PC is accessed as r15PC is accessed as r15
Incremented by 4 bytes for ARM state and 2Incremented by 4 bytes for ARM state and 2
bytes for THUMB statebytes for THUMB state Branch instruction loads destination address intoBranch instruction loads destination address into
the PCthe PC
Can also be loaded using data operationCan also be loaded using data operationinstructioninstruction
8/7/2019 Modes Registers
13/18
8/7/2019 Modes Registers
14/18
4/7/2011 14
CPSRCPSR-- CCurrenturrent PProgramrogram SStatustatus RRegisteregister CPSR holdsCPSR holds
Copies of ALU status flagsCopies of ALU status flags
The current processor modeThe current processor mode
Interrupt disable flagInterrupt disable flag
ALU status flags are used to determine whetherALU status flags are used to determine whetherconditional instructions are executed or notconditional instructions are executed or not
On THUMB capable processors ,the CPSROn THUMB capable processors ,the CPSRholds the current processor stateholds the current processor state
8/7/2019 Modes Registers
15/18
4/7/2011 15
FLAGSFLAGS Condition code flagsCondition code flags
N(31)N(31) *set to bit 31 of the result of the instruction*set to bit 31 of the result of the instruction*N=0 if positive*N=0 if positive
*N=1 if negative*N=1 if negative
Z(30)Z(30)*Z=1 if result is zero*Z=1 if result is zero
*Z=0 if not zero*Z=0 if not zero
C(29)C(29) *for addition ,set to 1 if carry occurs & 0 otherwise*for addition ,set to 1 if carry occurs & 0 otherwise
*for subtraction ,set to 0 if borrow occurs & 1*for subtraction ,set to 0 if borrow occurs & 1otherwiseotherwise
*for shift operations , C contains the last bit shifted*for shift operations , C contains the last bit shifted
VV (28)(28)*for addition and subtraction V set to 1 if signed overflow*for addition and subtraction V set to 1 if signed overflowoccursoccurs
8/7/2019 Modes Registers
16/18
4/7/2011 16
FLAGSFLAGS
ControlbitsControlbits
I(7)I(7) *when set disables IRQ interrupt*when set disables IRQ interrupt
F(6)F(6) *when set disables FIQ interrupt*when set disables FIQ interrupt
T(5)T(5) *on T variants*on T variants
T=0 ,indicates ARM executionT=0 ,indicates ARM executionT=1 ,indicates THUMB executionT=1 ,indicates THUMB execution
8/7/2019 Modes Registers
17/18
4/7/2011 17
FLAGSFLAGS
MODE BITS (4:0)MODE BITS (4:0)
M(4:0)M(4:0) ModeMode
1000010000 UserUser1000110001 FIQFIQ
1001010010 IRQIRQ
1001110011 SupervisorSupervisor1011110111 AbortAbort
1101111011 UNDUND
1111111111 SYSSYS
8/7/2019 Modes Registers
18/18
4/7/2011 18
SPSRSPSR--SSavedaved PProgramrogram SStatustatus RRegisteregister
Used to store CPSR when an exception is takenUsed to store CPSR when an exception is taken
One SPSR is accessible in each of the exceptionOne SPSR is accessible in each of the exceptionhandling modehandling mode
User Mode and System Mode doesnt haveUser Mode and System Mode doesnt haveSPSR as they dont handle exceptionsSPSR as they dont handle exceptions
Top Related