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MiniBoone Detector: Digitization at Feed ThroughStudent: John Odeghe ;SC State , Fermi Lab Intern
Supervisor: JinYuan Wu;Fermi Lab
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Outline
•Mini Boone Detector•The need for changing digitization design•Digitization at Feed through•The TDC FPGA Design•Performance Tests and Results•Conclusions
General Description
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Demonstrate photon – electron identification Develop cold electronics
Implementation of cold electronics in Gaseous Argon (GAr)
Purity: Test of GAr purge in large, fully instrumented vessel
Refine sensitivity estimates for next generation detectors
Test ability to run on surface Develop tools for analysis Develop cost scaling model for larger
detectors
MicroBooNE LAr TPC Development Goals
MicroBooNE detector: 150 tons total Liquid Argon 89 tons active volume TPC: ~2.5 x 2.3 x 10.4m long Ionization electrons drift to beam right 30 PMTs peek through the wire chambers on beam right Will use BNB and NuMI beams at FNAL for physics program
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LArTPC around US
General Description: LArTPCs
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Passing charged particles ionize Argon Electric fields drift electrons meter to wire chamber planes Induction/Collection planes image charge, record dE/dx
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Readout channel information flow
Short Falls of current Design• Poor Noise Handing• Limited cable Run
Source: MicroBooNE ConceptualDesign Report , Feb 2010
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Digitization at Feed Through• The goal is to digitize the analog signals before
they are contaminated by noise.• However, digitization processes create noise that
may contaminate signals.• Therefore, it is a natural to minimize digital
activities in the digitization processes.• Q: How many bit transitions are considered to be
minimal?A: 1 bit transition/data sample.
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Single Slope TDC
AMP &ShaperAMP &ShaperAMP &ShaperAMP &Shaper
ADCADCADCADC
FPGA AMP &Shaper
AMP &Shaper
AMP &Shaper
AMP &Shaper
FPGATDC
TDC
TDC
TDC
R1 R1C
R2
VREF
T1
V1
T2
V2
T3
V3
T4
V4
The current design consist of ADC feeding digitized data to the FPGA for analysis. But we can Implement a TDC on an FPGA. This allows us to directly feed analog signals to the FPGA, eliminating extra ADC hardware. This scheme proves even more efficient in digitization.
Quick Facts on our TDC FPGA• Implemented on Altera Cyclone FPGA• Primary firmware employs delay chains to determine transition time•Wave Union launcher is implemented to ameliorate ultra wide bins effect• TDC can run to a precision of 70 ps (LSB)
RC circuit creates Ramping reference voltage, which is compared with analog signals in FPGA. Hit time is measured to a high precision. Signals can be reconstructed using the hit times.
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Fast TDC Card
TDC FPGA
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Performance Tests
•Oscilloscope pictures•Optimized range common mode signals•Calibration •Test Signals •Histograms
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Oscilloscope Pictures
Pic. 1 Ramping signals (1MHz)
Pic. 2 Ramping signals generated from clock.
Pic. 3 Sampling using the ramping Signals
• Tests Start with analyzing critical signals
• Using a scope we can check the differential ramping signals.
• The ramping RC signals are derived from clocking signals in the board
• The ramping signal serves as a sampling signal (in pic. 3 a slower ramp is sampled)
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Common mode Signals
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
120
125
130
135
140
145
150
155
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5340
350
360
370
380
390
400
410
Voltage Offset (V) Voltage Offset (V)
Tim
e (n
s)
Tim
e (n
s)
• Device is designed for differential Input Signals• Performance can be compromised owing to offset of input signal.• We can investigate this behavior by feeding common mode signals• Observe that optimization is attained within the described range
optimized
optimized
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Calibration
0 250 500 750 1000-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
CalculatedMeasured Ramping UpMeasured Ramping Dwn
Time (ns)
Volta
ge (v
)
• Check for accuracy of device by matching measured samples with calculated curve
• Generate a lookup table for time conversions
• Understand slight aberrations
• Moving forward in data interpretation
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Test Signal
40000 80000-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Ramping up signal
Ramping dwn signal
Time (ns)
• With the calibration formula obtained we can regenerate input signals
• Ramping up and ramping down samples are converted and plotted in the same graph
• Notice that both signal samples match
• A pulse signal is fed to an input channel
• Controlling the TDC through a serial port, the signal is sampled
• Raw data from the sampling is saved to a remote computer
• The goal is to recreate the signal using the array of hit time sampled
Am
plit
ude
(v)
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Histograms
0 5 10 15 20 25 30 350
4000000
8000000
12000000
Histograms of Hits on channel 7 (Ramping Down)
Bins
Hits
0 5 10 15 20 25 30 350
2500000
5000000
7500000
Histogram of hits on channel 7 (Ramp-ing up)
Bins
Hits
• Histograms plot bins on the LSB of Hit Time• It’s a pictorial evaluation of precision of the TDC.• With a constant amplitude signal, we expect a sharp pic and
little variance• Channel 7 is supplied with a constant amplitude signal.• Histograms of both ramping up and ramping down samples
confirms our prediction
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Histograms
0 5 10 15 20 25 30 350
4000000
8000000
12000000
Histogram of Hits from Ramping Down Signal
Bins
Hits
0 5 10 15 20 25 30 350
2000000
4000000
6000000
histogram of hits from Ramping up Signal
bin
hits
• A varying amplitude like the pulse signal will be interesting to analyze on a histogram.
• Observe the noticeable peak and the smaller bumps. 40000 80000
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Ramping up signal
Ramping dwn sig-nal
Time (ns)
Am
plit
ude
(v)
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Acknowledgment
•Fellow SIST Interns•SIST Committee•14th floor WH PPD crew
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Questions
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