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1NTUEE C.M. LiLogic Design
Switching Circuits & Logic Design 電路與邏輯設計
Professor Chien-Mo James Li 李建模Graduate Insti tute of Electronics Engineering
National Taiwan University
Circuits for Arithmetic Operations
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Objective of this Chapter
• Learn how to design a sequential circuit for arithmetic calculation
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3NTUEE C.M. LiLogic Design
Outline
• Serial Adder with Accumulator
• Multiplier
• Divider
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Review: Serial Adder
• What is serial adder?
♦ Add two numbers one bit by one bit
♦ Fig 13-12
Fig. 13-12
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5NTUEE C.M. LiLogic Design
Review: State Table of SA
• Fig 13-12 (b)x i y i c i c i+1 s i
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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Review: Timing Chart of SA
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7NTUEE C.M. LiLogic Design
Review: State Graph of SA
• x i y i / si
No carry in with carry in
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Review Question 2
• What is accumulator?
♦ Hint Fig 12-5
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9NTUEE C.M. LiLogic Design
Accumulator
• Accumulator is a special register that
♦ Stores one number
♦ a second number can be added to it, leaving the result stored in
the same register • Fig 12-5: N-bit Parallel Adder with Accumulator
♦ X(t+1) = X(t) + Y Fig. 12-5
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New: Serial Adder with Acc.
• Fig 18-1: block diagram for a serial adder wi th Acc.
♦ Add 4-bit X and 4-bit Y, one bit at a clock
♦ Result stored in X (accumulator)
Y
X
Fig. 18-1
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11NTUEE C.M. LiLogic Design
Four Blocks
• X is serial accumulator
• Y is cyclic shifter (Q: what is cycl ic shif ter?)
• serial adder
• Control Circuit
Serial adder
Cyclic Shifter
Accumulator
control
12NTUEE C.M. LiLogic Design
Serial Accumulator
• Control signal
♦ Sh: Shift signal
• Data input
♦ SI: serial input
• Data output
♦ SO: serial output
• Function
♦ Store X
♦ Store Sum
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13NTUEE C.M. LiLogic Design
Cyclic Shifter
• Control signal
♦ Sh: Shift signal
• Data input
♦ SI: serial input• Data output
♦ SO: serial output
• Function
♦ Store Y
• Why cyclic?
♦ Y is not lost after adding
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Operation of Serial Adder
Fig. 18-2
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Operation of Serial Adder (cont’d)
• Final result
♦ Accumulator : X = Sum
♦ Shifter : Y = Y
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Operation of SA (cont’d)
• TABLE 18-1
X Y Ci Si Ci+
t0 0101 0111 0 0 1
t1 0010 1011 1 0 1
t2 0001 1101 1 1 1
t3 1000 1110 1 1 0
t4 1100 0111 0 (1) (0)
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17NTUEE C.M. LiLogic Design
Control Circuit
• Function
♦ Control the adder and shifter and accumulator
• State graph
♦ S0 is initial state♦ If st = 0, stay in S0
♦ if st=1, start
∗ Sh=1 for four clocks
∗ then return to S0
• Fig 18-3 Next State Sh
St=0 1 0 1
S0 S0 S1 0 1S1 S2 S2 1 1
S2 S3 S3 1 1
S3 S0 S0 1 1
18NTUEE C.M. LiLogic Design
Design of Control Circuit
• State graph
• State table (Fig 18-4)
AB A+B+
0 1
S0 00 00 01
S1 01 10 10
S2 10 11 11
S3 11 00 00
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19NTUEE C.M. LiLogic Design
Design of Control Circuit
• K map
Fig. 18-4
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FFT: Which is better?
• Serial
• parallel
Fig. 18-1
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Typical Serial Processing Unit
• Fig 18-5
Fig. 18-5
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State Graph of Control
• Left: Start signal = 1 for only one clock
• Right : start signal = 1 1 1 1 … 1 ->0
♦ An extra stop state is added
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23NTUEE C.M. LiLogic Design
Outline
• Serial Adder with Accumulator
• Multiplier
• Divider
24NTUEE C.M. LiLogic Design
Binary Multiplication
• How do you perform binary multiplication?
♦ p. 542
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25NTUEE C.M. LiLogic Design
Block Diagram for Parallel Mult ipl ier
• Fig 18-7
Fig. 18-7
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How is Multiplication done?
• P. 600
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27NTUEE C.M. LiLogic Design
Controller State Graph
• Fig 18-8
• Problems:
♦ Too many states
♦ not flexible
Fig. 18-8
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Solution: Use Counter
• Fig 18-9
• Only 4 state needed, even for very many bits
♦ K=1 means the last bit
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29NTUEE C.M. LiLogic Design
Operation of Multipl ier Using Counter
• Table 18-2
Time State Cou
nter
Product
Register
St M K Load Ad Sh Done
t0 S0 00 000000000 0 0 0 0 0 0 0
t1 S0 00 000000000 1 0 0 1 0 0 0
t2 S1 00 000001011 0 1 0 0 1 0 0
t3 S2 00 011011011 0 1 0 0 0 1 0
t4 S1 01 001101101 0 1 0 0 1 0 0
t5 S2 01 100111101 0 1 0 0 0 1 0
t6
S1
10 010011110 0 0 0 0 0 1 0
t7 S1 11 001001111 0 1 1 0 1 0 0
t8 S2 11 100011111 0 1 1 0 0 1 0
t9 S3 00 010001111 0 1 0 0 0 0 1
Tab 18.2
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FFT
• Why output ‘Done’ is needed for multiplier?
♦ But no ‘Done’ for adder / accumulator?
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31NTUEE C.M. LiLogic Design
Outline
• Serial Adder with Accumulator
• Multiplier
• Divider
32NTUEE C.M. LiLogic Design
Parallel Binary Divider
• Fig 18-10
♦ 9-bit dividend
♦ 4-bit divisor
♦ 4-bit quotient
♦ 4-bit remainder Fig. 18-10
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33NTUEE C.M. LiLogic Design
Operation of Divider
• P. 603
34NTUEE C.M. LiLogic Design
Overflow
• If quotient is larger than 15
♦ More than 5 bits needed overflow occurs
• How to detect overflow before division?
♦ If first 5 bits of X is larger than Y, overflow wi ll occur
♦ WHY?
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35NTUEE C.M. LiLogic Design
Design of Controller
• Fig 18-11
♦ C=1 means subtract
♦ C=0 means no subtraction
♦ C=1 in MSB indicates overflow V=1
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Design of Subtracter
• Using full subtracers
Fig. 18-12
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37NTUEE C.M. LiLogic Design
Bus Notation
• Fig 18-3
Fig. 18-3
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Bus Splitter and Bus Merger
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39NTUEE C.M. LiLogic Design
FFT
• Compare Fig 18-3 with 18-10. Should we tie Load and Su together?
40NTUEE C.M. LiLogic Design
What’s Next After Logic Design?
• NTU undergrad.
♦ Digital circuit Lab
♦ Introduct ion to VLSI
♦ Algorithm
♦ Data structure
♦ Introduct ion to EDA
♦ Computer Architecture
• GIEE
♦ Advanced VLSI Design
♦ Computer Aided VLSI System Design
♦ VLSI Testing
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