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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 18: March 28, 2019 Energy Optimization & Design Space
Exploration, Sequential Logic
Penn ESE 570 Spring 2019 – Khanna
Lecture Outline
! Energy Optimization ! Design Space Exploration
" Example
! Sequential Logic
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Energy and Power Optimization
Penn ESE 570 Spring 2019 – Khanna
Power Sources
Review: Ptot = Pstatic + Pdyn + Psc
Penn ESE 570 Spring 2019 – Khanna
Worksheet Problem 1
Vin Istatic Idynamic Isc
0V 180pA 126uA
140mV 6nA 100uA
400mV 36uA 18uA
500mV 36uA
600mV 36uA 18uA
860mV 6nA 100uA
1V 180pA 126uA
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Reduce Vdd (Worksheet #2)
! Vdd=520mV, Vthn=|Vthp|=300mV
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Vin Istatic Idynamic Isc
0V 180pA 39.6uA
140mV 6nA 14.4uA
260mV 111nA
360mV 9nA 10.8uA
500mV 270pA 36uA
Penn ESE 570 Spring 2019 – Khanna
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Reduce Vdd (Worksheet #3)
! Vthn=|Vthp|=300mV, Vin=Vdd, estimate Eτ
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Vdd Ids τ/(τ@Vdd=1) Eswitch/
(Eswitch@Vdd=1)
Eτ2
1V
700mV
500mV
350mV
260mV
Penn ESE 570 Spring 2019 – Khanna
Reduce Vdd (Worksheet #3)
! Vthn=|Vthp|=300mV, Vin=Vdd, estimate Eτ
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Vdd Ids τ/(τ@Vdd=1) Eswitch/
(Eswitch@Vdd=1)
Eτ2
1V 126uA 1 1 1
700mV 72uA 1.225 0.49 .735
500mV 36uA 1.75 0.25 .766
350mV 9uA 4.9 0.12 2.88
260mV 111nA 295 0.07 6k
Penn ESE 570 Spring 2019 – Khanna
Increase Vth(Worksheet #4)
! What is impact of increasing threshold on " Delay? " Leakage?
! Vdd=1V, Vin=Vdd
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Vthn= -Vthp Ids τ/(τ@Vth=300mV) Istatic
Istat/(Istat@Vth=300mV)
300mV
460mV
600mV
Penn ESE 570 Spring 2019 – Khanna
Increase Vth(Worksheet #4)
! What is impact of increasing threshold on " Delay? " Leakage?
! Vdd=1V, Vin=Vdd
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Vthn= -Vthp Ids τ/(τ@Vth=300mV) Istatic
Istat/(Istat@Vth=300mV)
300mV 126uA 1 180pA 1
460mV 97uA 1.3 3.6pA 0.02
600mV 72uA 1.75 108fA 0.0006
Penn ESE 570 Spring 2019 – Khanna
Idea
! Tradeoff " Speed " Switching energy " Leakage energy
! Energy-Delay tradeoff: Eτ2
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Design Space Exploration
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Design Problem
! Function: Identify equivalence of two 32bit inputs ! Optimize: Minimize total energy ! Assumptions: Match case uncommon
" Ie. Most of the time, the inputs won’t be matched
! Deliberately focus on Energy to complement project " …but will still talk about delay
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Idea: Design Space Explore
! Identify options " All the knobs you can turn
! Explore space systematically ! Formulate continuum where possible
" i.e. formulate trends and tradeoffs quantitatively
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Problem Solvable
! Is it feasible? " First, make sure we have a solution so we know our main
goal is optimization
! How do we decompose the problem?
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Problem Solvable
! Is it feasible? " First, make sure we have a solution so we know our main
goal is optimization
! How do we decompose the problem?
! What does this look like built out of nand2 gates and inverters?
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Single Gate Match Condition
! Design a single gate for match comparison
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Total Power
! Static CMOS: " Ptot ≈ a(Cload+2Csc)V2f+VI’
s(W/L)e-Vt/(nkT/q)
! Ratioed Logic: " Ptot ≈ a(Cload+2Csc)V2f
+p(Vout=low)V2/Rpon
+(1-p(Vout=low))VI’s(W/L)e-Vt/(nkT/q)
! What can we do to reduce power?
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Knobs
! What are the options and knobs we can turn?
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Design Space Dimensions
! Topology " (A) Gate choice, logical optimization " (B) Fanin, fanout, (C) Serial vs. parallel
! Gate style / logic family " (D) CMOS, Ratioed (N load, P load), Pass Logic
! (E) Transistor Sizing ! (F) Vdd ! (G) Vth
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Gate
! (A) What gates might we build?
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Gate
! (B) High fanin?
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Gate
! (C) Serial-Parallel?
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(D) Logic Family
! Considerations for each logic family?
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(D) Logic Family
! Considerations for each logic family? " CMOS " Ratioed with PMOS load " Ratioed with NMOS load
! Ratioed Logic " Reduced Cloads result in lower switching power (Pdyn #) " Increased steady-state power
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(E) Sizing
! How do we want to size gates?
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(E) Sizing
! How do we want to size gates? " Sizing transistors up will reduce delay $
" Reduces short circuit power
" Increases dynamic power
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€
E =Vdd × Ipeak × tsc ×12#
$ % &
' (
#
$ %
&
' (
(F) Reduce Vdd
! What happens as reduce V? " Energy?
" Dynamic # " Static #
" Switching Delay? %
& τgd=Q/I=(CV)/I & Id=(µCOX/2)(W/L)(Vgs-VTH)2
& τgd impact?& τgd α 1/V
& Limit on Vdd?
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(G) Increase Vth?
! What is impact of increasing threshold on " Dynamic Energy? # " Leakage Energy? # " Delay? %
& τgd=Q/I=(CV)/I & Ids=(νsatCOX)(W)(Vgs-VTH-VDSAT/2)
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Ideas
! Three components of power " Ptot = Pstatic + Pdyn+ Psc
! We know many things we can do to our circuits ! Design space is large ! Systematically identify dimensions ! Identify continuum (trends) tuning when possible ! Watch tradeoffs
" …don’t over-tune
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Sequential MOS Logic
Penn ESE 570 Spring 2019 – Khanna
Classes of Logic Circuits
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two stable op. pts. Latch – level triggered.
Flip-Flop – edge triggered.
one stable op. pt. One-shot – single
pulse output
no stable op. pt. Ring Oscillator
Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs. b. Suited to problems that can be solved using truth tables.
Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s). b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner.
Penn ESE 570 Spring 2019 – Khanna
Sequential Circuit (or State Machine) Construct
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-> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit – clock, outputs change with clock event -> Asynchronous Sequential Circuit – no clock, outputs change after inputs change
Vo1 Vo2
.
.
.
.
.
.
.
.
Vo3
Present State
Next State
Inputs Outputs
Clock
REGISTER
Penn ESE 570 Spring 2019 – Khanna
Synchronous Discipline
! Add state elements (registers, latches) ! Compute
" From state elements " Through combinational logic " To new values for state elements
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Static Bistable Sequential Circuits
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Basic Cross-coupled Inverter
pair
Q
Q
Penn ESE 570 Spring 2019 – Khanna
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Basic Cross-coupled Inverter
pair
Q
Q
Static Bistable Sequential Circuits
Penn ESE 570 Spring 2019 – Khanna
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Basic Cross-coupled Inverter
pair
Static Bistable Sequential Circuits
Q
Q
Penn ESE 570 Spring 2019 – Khanna
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Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State.
Basic Cross-coupled Inverter
pair Q
Q
VOH = VDD
VOL = 0
maintain stable state. STATIC: VDD and GND are required to maintain a stable state.
Static Bistable Sequential Circuits
Penn ESE 570 Spring 2019 – Khanna
Basic Sequential Circuits (Cells)
! Latches ! Registers
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Latch
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Q =CLK ⋅Q+CLK ⋅ In
! Level-sensitive device ! Positive Latch
" Output follows input if CLK high
! Negative Latch " Output follows input if
CLK low
Penn ESE 570 Spring 2019 – Khanna
Register
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! Edge-triggered storage element
! Positive edge-triggered " Input sampled on
rising CLK edge
! Negative edge-triggered " Input sampled on
falling CLK edge
Penn ESE 570 Spring 2019 – Khanna
Shift Register
! How do you make a shift register out of latches?
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Positive-Edge Triggered Register
! Build register from pair of latches ! What happens when φ0 is high? ! What happens when φ1 is high?
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QM
Positive-Edge Triggered Register
! Build register from pair of latches
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QM
Positive-Edge Triggered Register
! Build register from pair of latches ! What could go wrong if clocks overlap?
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QM
Positive-Edge Triggered Register
! Build register from pair of latches ! Control with non-overlapping clocks
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Two Phase Non-Overlapping Clocks
! What timing constraints do we have?
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Latch Timing Issues
! What timing constraints do latches impose? " When can φ change? " How long must φ be high? " Delay when φ is high?
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Timing Hazards
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Clocking Discipline
! Follow discipline of combinational logic broken by registers
! Compute " From state elements " Through combinational logic " To new values for state elements
! As long as clock cycle long enough, " Will get correct behavior
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Latch Timing Issues
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Latch Timing Issues
Penn ESE 570 Spring 2019 - Khanna 52
! tsu=time data (D) must be valid before CLK edge ! tplogic=worst case propogation delay of logic ! tc-p=worst case propogation delay of latch
Latch Timing Issues
Penn ESE 570 Spring 2019 - Khanna 53
! tcdregister=minimum propogation delay of latch ! tcdlogic=minimum propogation delay of logic ! thold=time data (D) must stay valid after CLK edge
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CMOS SR Latch – NOR2
* *
Penn ESE 570 Spring 2019 – Khanna
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CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
Penn ESE 570 Spring 2019 – Khanna
CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
Penn ESE 570 Spring 2019 – Khanna
CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
HOLD OP: S = 0, R = 0
Penn ESE 570 Spring 2019 – Khanna
CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
HOLD OP: S = 0, R = 0
Penn ESE 570 Spring 2019 – Khanna
CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
SET OP: S = 1, R = 0
CMOS SR Latch – NOR2
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basic cross-coupled inverter
pair
RESET OP: R = 1, S = 0
Penn ESE 570 Spring 2019 – Khanna
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CMOS SR Latch – NOR2
* *
“ACTIVE HIGH”
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CMOS SR Latch – NAND2
* *
“ACTIVE LOW” * *
Penn ESE 570 Spring 2019 – Khanna
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CMOS SR Latch – NAND2
basic cross-coupled inverter pair
Penn ESE 570 Spring 2019 – Khanna
Synchronous Latches
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NAND SR Latch NOTE: S and R are asynchronous.
CK
S’/R'
NAND SR LATCH
S/R
Penn ESE 570 Spring 2019 – Khanna
Latch
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Q =CLK ⋅Q+CLK ⋅ In
! Level-sensitive device ! Positive Latch
" Output follows input if CLK high
! Negative Latch " Output follows input if
CLK low
Penn ESE 570 Spring 2019 – Khanna
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D
CKCK
CK
CK
Static CMOS TG D-LATCH
Penn ESE 570 Spring 2019 – Khanna
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Static CMOS TG D-LATCH – 8 Transistors
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8 Transistors
Penn ESE 570 Spring 2019 – Khanna
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Static CMOS TG D-LATCH
When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered.
When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.
Penn ESE 570 Spring 2019 – Khanna
D-LATCH Timing Requirements
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CMOS D Edge Triggered Flip-Flop
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Positive Edge Triggered D Flip-Flop = Negative D-Latch + Positive D-Latch Negative Edge Triggered D Flip-Flop = Positive D-Latch + Negative D-Latch
Positive D-Latch
Negative D-Latch
NMOS PMOS
Penn ESE 570 Spring 2019 – Khanna
Impact of Non-ideal Clock on D-Latch Operation
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CLK
CLK
CLK ideal non-ideal
CLK & CLK
CLK + τD
CLK & CLK + τD
t t
NMOS PMOS
Penn ESE 570 Spring 2019 – Khanna
t
t
ϕ1
ϕ2
Two-Phase Clocked D-Latch (non-overlapping)
72 ϕ2
ϕ1
ϕ1
ϕ2
ϕ1
ϕ2
NMOS PMOS
Penn ESE 570 Spring 2019 – Khanna
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Ideas
! Synchronize circuits " to external events (eg. Clk) " disciplined reuse of circuitry
! Leads to clocked circuit discipline " Uses state holding element (eg. Latches and registers) " Prevents
" Timing assumptions " (More) complex reasoning about all possible timings
! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation " Domino Logic allows for cascading
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Admin
! HW 7 due 4/5 " Only choose the multiplier if you have designed an adder
before… " …but you don’t have to
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