EC402 Digital Electronic Circuits
Combinational Circuit Design
Dr. Sushanta K. Mandal
1st Floor, Faculty Block -5
KIIT
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Decoder• A decoder is a multiple-input, multiple output
combinational circuit that converts binary information from n input lines to an 2n unique output lines.
• Applications:
– Microprocessor memory system: selecting different banks of memory.
– Microprocessor I/O: Selecting different devices (printer)
– Microprocessor instruction decoding: Enabling different functional units.
– Memory: Decoding memory addresses (e.g. in ROM).
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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General Structure of a Decoder Circuit
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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1-2-line Decoder
AD
AD
1
0
AA D1D1 D0D0
0 0 1
1 1 0D0
D1A
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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2-to-4-Line Decoder
A1 A0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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2-to-4-Line Decoder
A1 A0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
013
012
011
010
AAD
AAD
AAD
AAD
A1
A0D0
D1
D2
D3
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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2-to-4-Line Decoder w/ Enable
En
A1
A0
D3
D2
D1
D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
013
012
011
010
AEnAD
AEnAD
AAEnD
AAEnD
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
En
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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2-to-4-Line Decoder w/ Enable
En A1 A0 D3 D2 D1 D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
013
012
011
010
AEnAD
AEnAD
AAEnD
AAEnD
A1
A0D0
D1
D2
D3
En
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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2-to-4-Line Decoder w/ Enable
013
012
011
010
AEnAD
AEnAD
AAEnD
AAEnD
Complemented outputs
The decoder is enabled when E = 0. The output whose value = 0 represents the minterm is selected by inputs A and B.
The decoder is disabled when E = 1 D0 … D3 = 1
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3-to-8-Line Decoder
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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3-to-8-Line Decoder
D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
Binary Inputs
Outputs
If the input corresponds to minterm mi then the decoder ouputi
will be the single asserted output.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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3-to-8-Line Decoder using 2-to4-line Decoder
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Truth Table
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
En
D0
D1
D2
D3
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
En
D4
D5
D6
D7
A0
A1
A2
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-16-Line Decoder
• When w = 0, the top
decoder is enabled and the
bottom is disabled. Top
decoder generates 8
minterms 0000 to 0111,
while the bottom decoder
outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled.
Bottom decoder generates 8 minterms 1000 to 1111, while the top
decoder outputs are 0’s.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Implementing Logic w/ Decoder
D0
D1
D2
D3
3-to-83-to-8-line-line
decoderdecoder
A0
A1
A2
D4
D5
D6
D7
6,4mZ)Y,F2(X,
7) 6, 2, m(1,Z)Y,F1(X,
XX
YY
ZZF1F1
F2F2
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Combinational Logic (Full-Adder) using Decoder
Ci A B S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x138
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x138
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x138
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x138 Logic Diagram
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Position encoding for a 3-bit Position encoding for a 3-bit mechanical encoding diskmechanical encoding disk
Using a 3-to-8 decoder to decode a Gray code.
Sushanta K. Mandal 21EC402 Digital Electronic Circuits Spring 2011
4-to-16 decoder using 74X1384-to-16 decoder using 74X138
N3
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5-to-32 decoder from 74X138 chips5-to-32 decoder from 74X138 chips
Global enable goes to inputs G1 and G2A
Chip select goes to input G2B
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Complete 74x139 Decoder
All Inputs buffered to minimise loading
Sushanta K. Mandal 24EC402 Digital Electronic Circuits Spring 2011
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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M-to-N-Line Encoder (M2N)
D0
D1
D2
D3
2-to-42-to-4-line-line
DecoderDecoder
A0
A1
En
D0
D1
D2
D3
4-to-24-to-2-line-line
EncoderEncoder
A0
A1
Ac
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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M-to-N-Line Encoder
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-2 Encoder
D3 D2 D1 D0 A1 A0
0 0 0 1 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3A1 = D2 + D3
00 01 11 10
00 X 0 X 1
01 0 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D2or D3D1A0
For A0
00 01 11 10
00 X 0 X 0
01 1 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D1or D3D2A1
For A1
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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8-to-3 Encoder (Octal-to-binary)
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Example 1 of an Encoder
Only point to one single reading at a time.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Priority Encoder
• The encoder defined in the last slide has the limitation that only one input can be active at any given time.
• If two inputs are active simultaneously, the output produces an undefined combination.
• Example: if D3 and D6 are 1, the output of the encoder will be 111.
z = D1+ D3+ D5+ D7y = D2+ D3+ D6+ D7x = D4+ D5+D6+ D7
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Priority Encoder
• This does not represent either binary 3 or binary 6.
• To resolve this ambiguity, encoder circuit must establish an input priority to ensure that only one input is encoded.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Priority Encoder
• A priority encoder is an encoder circuit that includes the priority function.
• The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Priority Encoder
• Valid bit indicator (V) is set to 1 when one or more inputs are equal to 1.
• If all inputs are 0, there is no valid inputs and V is equal to 0. Timing analysis
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Priority Encoder
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Map for a Priority Encoder
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Implementation of Priority Encoder
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Design Problem
• Design a 4-input priority encoder in which D0 having the highest priority and input D3 the lowest priority.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Problem
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Problem
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Multiplexers (Mux)
• A multiplexer is a combinational circuit that
selects binary information from one of 2n
input lines and directs it to a single line. There are n selection lines.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Multiplexers (Mux)
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-1-line Mux w/o Enable
S1S1 S0S0 FF
0 0 A0
0 1 A1
1 0 A2
1 1 A3
F
A0
A1
A2
A3S1 S0
4-to-14-to-1MuxMux
S1S1 S0S0 A3A3 A2A2 A1A1 A0A0 FF
0 0 X X X 0 0
0 1 X X 0 X 0
1 0 X 0 X X 0
1 1 0 X X X 0
0 0 X X X 1 1
0 1 X X 1 X 1
1 0 X 1 X X 1
1 1 1 X X X 1
30121101 001 ASSAS0SASSASSF
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-1-line Mux using 2X1 mux
I0 0
1I1
Y0
S0
2-to-12-to-1MuxMux
I2 0
1I3
Y1
S0
2-to-12-to-1MuxMux
I0 0
1I1
F
S1
2-to-12-to-1MuxMux
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-1-line Mux
S1
S0
A0
A1
A2
A3
F
30121101 001 ASSAS0SASSASSF
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-1-line Mux with Enable
EnEn S1S1 S0S0 FF
0 X X 0
1 0 0 A0
1 0 1 A1
1 1 0 A2
1 1 1 A3
• Functionality: Selection of a particular input• Route 1 of N inputs (A) to the output F• Require Selection bits (S)• En(able) bit can disable the route and set F to 0
F
A0
A1
A2
A3S1 S0
En
4-to-14-to-1MuxMux
N2log
30121101 001
30121101 001
ASEnSAS0EnSASSEnASSEn
)ASSAS0SASSASS(EnF
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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4-to-1-line Mux with Enable
)ASSAS0SASSASS(EnF 30121101 001 S1
S0
A0
A1
A2
A3
F
En
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Quadruple 2-to-1-Line Multiplexer
F[3:0]
SEL
2-to-12-to-1MuxMux
(4-bit bus)(4-bit bus)
A3-0
B3-0
A[3:0]
B[3:0]
EnEn SELSEL F[3:0]F[3:0]
0 X 0000
1 0 A[3:0]
1 1 B[3:0]
En
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Quadruple 2-to-1-Line Multiplexer
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Quadruple 2-to-1-Line Multiplexer with Enable
EnEn SESELL
F[3:0]F[3:0]
0 X 0000
1 0 A[3:0]
1 1 B[3:0]
SEL
B0
A0 F0
B3
A3
F3
B1
A1
F1
B2
A2
F2
En
Fx=Ax·En·SEL+Bx·En·SEL
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Canonical Form w/ MUX
7) 6, 2, m(1,C)B,F(A,
ABCCABCBACBAC)B,F(A,
F
A0
A1
A2
A3
S1 S0
8-to-18-to-1MuxMux
S2
A4
A5
A6
A7
00
00
00
00
11
11
11
11
Each input in a MUX is a minterm
OR gates are included
AA BB CC
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Canonical Form w/ MUX
7) 6, 2, m(1,F
ABCCABCBACBAF
A B F
0 0 C
0 1 C
1 0 0
1 1 1
F
A0
A1
A2
A3S1 S0
En
4-to-14-to-1MuxMux
AA BB
CC
CC
00
11
Vdd
Each input in a MUX is a minterm
OR gates are included
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Canonical Form w/ MUX
7) 6, 2, m(1,F
ABCCABCBACBAF
B C F
0 0 0
0 1 A
1 0 1
1 1 A
F
A0
A1
A2
A3S1 S0
En
4-to-14-to-1MuxMux
BB CC
AA
AA
Vdd
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Full Adder using MUX
A B Ci S
0 0 0 0 Ci
0 0 1 1 Ci
0 1 0 1 Ci’
0 1 1 0 Ci’
1 0 0 1 Ci’
1 0 1 0 Ci’
1 1 0 0 Ci
1 1 1 1 Ci
Sum
A0
A1
A2
A3S1 S0
4-to-14-to-1MuxMux
AA BB
CiCi
CiCi
BAC ABC BAC B AC S inininin
CiCi
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Full Adder using MUX
A B Ci Co
0 0 0 0 0
0 0 1 0 0
0 1 0 0 Ci
0 1 1 1 Ci
1 0 0 0 Ci
1 0 1 1 Ci
1 1 0 1 1
1 1 1 1 1
Carry
A0
A1
A2
A3S1 S0
4-to-14-to-1MuxMux
AA BB
CiCi
Vdd
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Function Implementation using 8x1Multiplexer
)15,14,13,12,11,4,3,1(),,,( DCBAF
1. Complete the truth table from the SOP.
2. The first n – 1 variables in the table are applied to the
selection inputs of the multiplexer.
3. For each combination of the selection variables, we
evaluate the output as a function of the last variable.
4. Apply these values to the data input in proper order.
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Function Implementation using 8x1MUX)15,14,13,12,11,4,3,1(),,,( DCBAF
note the order of input lines
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x157
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x157
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x157
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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MSI 74x151
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Demultiplexers (DeMux)
F
A0
A1
A2
A3S1 S0
4-to-14-to-1MuxMux
A
D0
D1
D2
D3S1 S0
1-to-41-to-4DeMuxDeMux
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Demultiplexer Operation
S1 S0 D3 D2 D1 D0
0 0 0 0 0 A
0 1 0 0 A 0
1 0 0 A 0 0
1 1 A 0 0 0A
D0
D1
D2
D3S1 S0
1-to-41-to-4DeMuxDeMux
ASSD
ASSD
ASSD
ASSD
013
012
011
010
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Demultiplexer Operation
S1 S0 D3 D2 D1 D0
0 0 0 0 0 A
0 1 0 0 A 0
1 0 0 A 0 0
1 1 A 0 0 0
ASSD
ASSD
ASSD
ASSD
013
012
011
010
D0
D1
D2
D3
A
S1
S0
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Demultiplexer with Enable
En S1 S0 D3 D2 D1 D0
0 X X 0 0 0 0
1 0 0 0 0 0 A
1 0 1 0 0 A 0
1 1 0 0 A 0 0
1 1 1 A 0 0 0
D0
D1
D2
D3
A
S1
S0
En
BCD-to-Decimal Decoder (74LS42)
65
• Does not have an enable input
• Can be used as a 3-to-8 decoder with the D input used as an enable input
(a) Logic diagram for the 7442 BCD-to-decimal decoder
(b) logic symbol (c) truth table
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
BCD-to-7-SegmentDecoder
• Another kind of decoder
a
b
c
d
e
f
g
aa
bb
cc
dd
ee
ff
gg
AA
BB
CC
DD
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
• Another kind of decoder
BCD-to-7-SegmentDecoder
a
b
c
d
e
f
g
aa
bb
cc
dd
ee
ff
gg
AA
BB
CC
DD
a
b
c
d
e
g
f
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
BCD-to-7-SegmentDecoder
• Decode “2” and show
a
b
c
d
e
f
g
aa
bb
cc
dd
ee
ff
gg
AA
BB
CC
DD
a
b
c
d
e
g
f
0
0
1
0
1
1
0
1
1
1
0
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
BCD-to-7-SegmentDecoder
• Decode “4” and show
a
b
c
d
e
f
g
aa
bb
cc
dd
ee
ff
gg
AA
BB
CC
DD
a
b
c
d
e
g
f
0
1
0
0
0
1
1
0
0
1
1
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
• BCD-to-7-segment decoder/driver driving a common-anode 7-segment LED display
• Segment patterns for all possible input codes
Notice the current limiting resistors, required to prevent overdriving the LED display
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder• Common-anode: All the anode connections of the LED’s are
joined together to Vcc, LED ON when input signal (Output) is LOW
• Common-cathode : All the cathode connections of the LED’s are joined together to GND. NO VCC , LED ON when input (Output) is HIGH
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder
• TTL and CMOS devices are normally not used to drive the common-cathode display directly because of current (mA) requirement.
• A buffer circuit is used between the decoder chips and common-cathode display
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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BCD-to-7-Segment Decoder Truth Table
A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
>10 All other inputs 0 0 0 0 0 0 0
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Each Output Individually “a”A B C D a
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
>10 All other inputs 0
00 01 11 10
00 1 0 1 1
01 0 1 1 0
11 0 0 0 0
10 1 1 0 0
ABCD
CBABDACDADBAa
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011
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Design Each Output Individually “b”A B C D b
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
>10 All other inputs 0
00 01 11 10
00 1 1 1 1
01 1 0 1 0
11 0 0 0 0
10 1 1 0 0
ABCD
CDADCABACBb
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