Laurent VUILLEMIN
Platform Compile Software Manager
Emulation Division
The Veloce Emulator and its Use for Verification and System Integration of Complex
Multi-node SOC Computing System
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com2
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com3
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com4
Verification Challenges
Systems
Debug
Software
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com5
Hardware Development
Typical Development Cycle
System Verification
Block-level Verification
Design Cycle
System Integration
Software Development
Fab
Chip-level Verification
Time toMarket
Hardware Development
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com6
Hardware Development
Typical System Development
System Verification
Block-level Verification
Design Cycle
System Integration
Software Development
Fab
Chip-level Verification
Time toMarket
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com7
Software Simulation
Model is represented in Data Structures
Compute and propagate signal values
module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout;
always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; endendmodule
RTL Model
module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout;
always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; endendmodule
Test bench
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Clock Speed Scaling Stalls
Emulation Required to Extend
Performance
Source: Recording Microprocessor History 4/6/2012 Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz http://queue.acm.org/detail.cfm?id=2181798
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com9
Emulation
• Multiples FPGA reproduce Model behavior from high level description
Map RTL model in Programmable
Logic
module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout;
always @ (posedge ck) begin if ( en ==1 ) dout = dout+step; endendmodule
RTL ModelProgrammable
Logic
Control execution and
get results
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Start Early – Continue for Entire SoC Life
Architecture Phase
Block-level Verification
Fullchip/SoC Verification
Software, Firmware & Device Drivers
Systems Validation
Post Silicon Bringup and Validation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com11
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com12
Modern SOC environment
CPU
Arbiter
Fabric
UART
Slave IF
GPIO
Slave IF
PCIExpress
PHY
FabricSoftwareMemory
Master IF
DisplayProcessor
PHY
Slave IF
SATA
PHY
Slave IF
Ethernet
PHY
Slave IF
USB
PHY
SlaveIFMaster IF
CPU
Master IF
SoC
Embedded SW Debugger
RS
P
JTAG
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com13
ICE use Model
The emulator is connected to actual Hardware
Veloce
External Hardware
DUT
Cables
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com14
Ethernet Verification With ICE
iSolve EthernetiSolve Ethernet
Ethernet Network
Live Traffic
Stimulus Generation / Analysis Tools
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com15
Co EmulationTestbench Xpress (TBX)
Transactions
High-speed Interface
Testbench divided in 2 parts one in emulator the other in Station
Communication via transactor
Software sends commands that are interpreted by transactor to generate DUT stimulus
PCI E 1/2 X-actor
PCI E 1/2 X-actor
AGP 1/2 X-actor
AGP 1/2 X-actor
USB 1/2 X-actor
USB 1/2 X-actor
1/2 X-actor
1/2 X-actor
Testbench DUTDUT
Software
Hardware
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com16
Veloce Use Models
USBPCIePhysical I/O
Accelerated Transactors
OVM/UVM SystemVerilog C/SystemC
Simulation Acceleration
Testb
ench
Xpre
ss
....iSolve Solutions
VirtuaLAB Solutions
USB
Virtual Protocol SolutionsSATA Video
Ethernet
Software Debug
Codelink
SW Debug VProbe Fast ISS QEMU
VideoSATA
Co-M
od
el
Ch
an
nels
Physical Protocol SolutionsEthern
et
PCIe
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com17
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Veloce 2 Architecture
18
Crystal2 Chip
Maximus2
X 16
AVB2
X 64
+ 40 SXB (Switch boards)
+ 4 CXB (clock board)
Quattro2
+ 6 SXB (Switch boards)16 AVB2
+ 1 CXB (clock board)
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Crystal 2 IC
19
Programmable Logic Array
Control
Memories
Debug Resources
Virtual Wire Logic
Programmable Logic Array Set of LUT an Sequential elements
Interconnect Network
Memories : User Memories model
Virtual Wire Logic Transport signals between chips
Debug Resources Trace every Sequential element and
memories
Triggers
Control Load configuration
Control emulation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com20
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
— Compile Software
— Runtime Software
Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com21
Software Overview
Emulator host
Network
Compile SW
Configuration bitstream
Runtime SW
User design
Compile Servers
PC Farm
Low Level SW
Transform design in bistream
User InterfaceControl Emulator
Collect debug data
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com22
Compile software
TBX
RTLC
Platform Compile
Design +Testbench
Bitstream
Gate netlist
RTL
Partition Testbench between SW and Emulator
Perform RTL Synthesis
Partitioning in CrystalSytem RoutingCrystal Place and RouteRessource Allocation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com23
Runtime Software
Veloce DAC 2014
Emulator Message Bus
Emulator Host Server
LLSW
Ressource
Server
Maintenance Server
Runtime
Server
User Message Bus
UIVisibilit
y Server
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com24
Agenda
What is Emulation
Use models
Veloce Architecture Overview
Veloce Software
Practical : Use Veloce to verify Veloce— Challenges— The verification infrastructure— Verifying ASIC— Verifying the Compilation software— Low level software integration — Firmware validation debug— Runtime software integration
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com25
Challenges
Complex system— ASIC— FPGAs Firmware— Mutliple software components
Verifying all component of the system and their interactions
Time to get a bug Size :
— Detailed model of a full Emulator of next generatio will not fit in current generation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com26
Addressing the challenges
Use a comodel approach for more abstraction level and connection with the software
Divide verification in steps based on functionality
Simplify the model by using different abstraction level depending on what functionality is tested
Veloce DAC 2014
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification Infrastructure
Veloce27
More details on Veloce
Crystal
Control
Crystal
Control
Control Chip
LLSW on host
Control Commands
Veloce Control Bus
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification Infrastructure
Veloce28
Emulation model
Emulator
Crystal
Control
Crystal
ControlSoftware
Control Chip
Veloce Control Bus
Transactor
Nature of the Software, Transactor and Model in emulator depend on abstraction level
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
ASIC verification : example of Trace
Veloce29
Data
SW translator
Veloce Comand
s
Comodel SW
Emulation Model
Crystal
Control
Macro Block
Design
Trace Capture Trace control
DDRControler
DDRTransa
ctor
Trace Capture, Trace Control and DDR Controler are Accurate modelsDesign is a gate level netlist generating random dataData are either manually generated or come from actual compileRun million cycles on multiple designs
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification of compile SW
Veloce30
Bitstream
LLSW Bitstream
reader
Veloce Comand
s
Comodel SW
Emulation Model
Crystal
Control
Macro Block
Configuration Block
Transactor
Macro and Configuration blocks are Accurate modelsBitstream is the output of actual compile flowVerify behavior of design
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification of Low Level Software 1/2
Veloce31
Crystal
Control
Virtual Wire Logic
Virtual Wire need a training/Calibration sequenceThis sequence is controled by Low Level Software
Crystal
Control
Virtual Wire Logic
Data multiplexed on
serial link
Example : Virtual Wire Synchronisation
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification of Low Level Software 2/2
Veloce32
Actual LLSW Comodel SW
Emulation Model
Transactor
Control block in Crystal and VW block are accurate modelActual LLSW communicate with the model through comodel SW and transactor
Crystal
Control
VW Block
Control Chip
Crystal
Control
VW Block
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
AVB
Crystal
Trigger Logic
Macro Block
Crystal
Trigger Logic
Macro Block
FPGA
AVB Level reduction
Verification of Firmware 1/2
Veloce33
A trigger express a condition on values coming from the designAt AVB and System level it is implemented in FPGAA binary is genrerated by runtime SW to express condition
Example : Trigger Reduction
AVB
Crystal
Trigger Logic
Macro Block
Crystal
Trigger Logic
Macro Block
FPGA
AVB Level reduction
CXB
FPGA
System Level reduction
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Verification of Firmware
Veloce34
Trigger
binary
SW translator
Veloce Comand
s
Comodel SW
Emulation Model
Control
Transactor
Design is modeled as gate level netlistTrigger binary is generated by actual runtime SWVerify behavior of trigger in multiple design sequences
AVB
Crystal
Trigger Logi
c
Macro Block
Crystal
Trigger Logi
c
Macro Block
FPGA
AVB Level
reduction
AVB
Crystal
Trigger Logi
c
Macro Block
Crystal
Trigger Logi
c
Macro Block
FPGA
AVB Level
reduction
CXB
FPGA
System Level
reduction
© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com
Runtime SW Verification
Veloce35
Emulation Model
Transactor
CrystalContro
l
Macro Block
Design
Memories
Emulator Message Bus
Emulator Host Server
LLSW
Ressource Server
Runtime
Server
User Message Bus
UI
Comodel SW
Actual Runtime Server is usedHigh level model for the HW
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