Lab2: I/O Handling
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Goal of the lab
• Learn how to access different I/O devices
• Write programs that interact with I/O devices
• Write driver routines
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Computer system
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Simplification
• In the lab we will use – Switches/Buttons – LED – 7-Segment display
Computer System
CONTROL BUS
DATA BUS
ADDRESS BUS
MicroBlaze microprocessor
Memory
SWITCHES LEDS 7SEGMENT DISPLAYS
PUSH BUTTONS TIMER1 TIMER2 INTERRUPT
CONTROLLER
FPGA
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Memory mapped vs. Isolated I/O
• Memory mapped – Same address space shared among memory and I/O – Same instructions used to access memory and I/O
• Isolated I/O – Different address space for memory and I/O – Different instructions – More control signals
MicroBlaze
Memory mapped I/O
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Minnesmappad och isolerad I/O
Memory mapped: I/Os are addressed by reading or writing to specific memory addresses Cost: reduced address space
Isolated: I/Os are addressed by specific functions, more memory for the processor Cost: more instructions, increased complexity
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I/O devices
• Contain a set of registers • Status/Control registers • Data registers
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SWITCHES
16 switches are interfacing the microprocessor through an I/O module • one control and one data register • both registers are 32bit wide • control register gives a bit level control for the data flow
direction of each of the bits of the data registers • data register stores the state of the switches
• Input only
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SWITCHES
shuffle
Data register
Control register
ADDRESS BUS
DATA BUS
I/O module
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LEDs
16 LEDs are interfacing the microprocessor through an I/O module • one control and one data register • both registers are 32bit wide • control register gives a bit level control for the data
flow direction of each of the bits of the data registers
• data register stores the state of the switches
• Output only
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LEDS
shuffle
Data register
Control register
ADDRESS BUS
DATA BUS
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7-SEGMENT DISPLAYS
• Output device • Contains 8 data registers • Each data register is 32bit wide • One data register keeps the data to be displayed on one of
the 8 seven segment displays
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7-segment display
• 7 input signals • One signal controls the state of one segment
Data register
shuffle
a b c d e f g
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7- SEGMENT DISPLAYS
Data Register
8
Data Register
7
Data Register
6
Data Register
5
Data Register
4
Data Register
3
Data Register
2
Data Register
1
7SEGMENT DISPLAYS
ADDRESS BUS
DATA BUS
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Driver routines
• Software interface to hardware devices • Operating system can invoke driver routines • Programmers can invoke driver routines without needing to
know precise details of the hardware being used
Write driver routines for the 7-SEGMENT DISPLAYS device
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Pushbutton
• Produces a logic ‘1’ when pressed • Produces a logic ’0’ when released
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PUSH BUTTONS
5 pushbuttons are interfacing the microprocessor through an I/O module • one control and one data register • both registers are 32bit wide • control register gives a bit level control for the data flow
direction of each of the bits of the data registers • data register stores the state of the pushbuttons • Input only
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PUSH BUTTONS
Data register
Control register
ADDRESS BUS
DATA BUS
shuffle
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PUSH BUTTONS
Data register
Control register
ADDRESS BUS
DATA BUS
shuffle
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CPU - I/O communication
• Programmed I/O – CPU has to wait for completion of each I/O operation
• Interrupt-driven I/O – CPU can execute other code during I/O operation
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Programmed I/O
• Polling – CPU repeatedly checks if the device I/O is ready – Many clock cycles are wasted
Check if any of the push buttons is pressed or released
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Bouncing
• Problem with the push buttons • Tendency of any two metal contacts in an electronic device
to generate multiple signals as the contacts close or open
Pressing a button
expected
bouncing
time
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Debouncing
• Delays • If the state has changed, read the state after some delay • The delay is of order of milliseconds
Pressing a button
20ms no samples
Without delays
With delays
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