K Band Downconverter with Integrated Fractional-N PLL and VCO
Data Sheet ADMV4420
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES RF front end with integrated RF balun and LNA Double balanced, active mixer with high dynamic range IF
amplifier Fractional-N synthesizer with low phase noise, multicore VCO 5 V supply operation with integrated LDO regulators Output P1dB: 7 dBm Output IP3: 16 dBm Conversion gain: 36 dB Noise figure: 7 dB RF input frequency range: 16.95 GHz to 22.05 GHz Internal LO frequency range: 16.35 GHz to 21.15 GHz IF frequency range: 900 MHz to 2500 MHz Single-ended 50 Ω input impedance and 75 Ω IF output
impedance Programmable via 4-wire SPI 32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS Satellite communication Point to point microwave communication
GENERAL DESCRIPTION The ADMV4420 is a highly integrated, double balanced, active mixer with an integrated fractional-N synthesizer, ideally suited for next generation K band satellite communications.
The RF front end consists of an integrated RF balun and low noise amplifier (LNA) for an optimal, 7 dB, single-sideband noise figure while minimizing external components. Additionally, the high dynamic range IF output amplifier provides a nominal conversion gain of 36 dB.
An integrated low phase noise, fractional-N, phase-locked loop (PLL) with a multicore voltage controlled oscillator (VCO) and internal 2× multiplier generate the necessary on-chip LO signal for the double balanced mixer, eliminating the need for external frequency synthesis. The multicore VCO uses an internal autocalibration routine that allows the PLL to select the necessary settings and lock in approximately 400 µs.
The reference input to the PLL employs a differentially excited 50 MHz crystal oscillator. Alternatively, the reference input can be driven by an external, singled-ended, 50 MHz source. The phase frequency detector (PFD) comparison frequency of the PLL operates up to 50 MHz.
The ADMV4420 is fabricated on a silicon germanium (SiGe), bipolar complementary metal-oxide semiconductor (BiCMOS) process, and is available in a 32-lead, RoHS compliant, 5 mm × 5 mm LFCSP package with an exposed pad. The device is specified over the −40°C to +85°C temperature range on a 5 V power supply.
ADMV4420 Data Sheet
Rev. A | Page 2 of 61
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8 Interface Schematics..................................................................... 9
Typical Performance Characteristics ........................................... 10 IF = 900 MHz, Low-Side Injection LO Performance ............ 10 IF = 900 MHz, High-Side Injection LO Performance ........... 12 IF = 1700 MHz, Low-Side Injection LO Performance .......... 14 IF = 1700 MHz, High-Side Injection LO Performance ......... 16 IF = 2500 MHz, Low-Side Injection LO Performance .......... 18 IF = 2500 MHz, High-Side Injection LO Performance ......... 20 LO = 16.75 GHz, Low-Side Injection Performance ............... 22 LO = 16.75 GHz, High-Side Injection Performance ............. 24 LO = 18.95 GHz, Low-Side Injection Performance ............... 26 LO = 18.95 GHz, High-Side Injection Performance ............. 28 LO = 21.15 GHz, Low-Side Injection Performance ............... 30 LO = 21.15 GHz, High-Side Injection Performance ............. 32 Phase Noise Performance .......................................................... 34 Return Loss and Isolation .......................................................... 35 Spurious and Harmonics Performance ................................... 36
Theory of Operation ...................................................................... 37 Reference Input Stage ................................................................. 37 Reference Doubler, R Counter, and RDIV2 ............................ 37 N Counter .................................................................................... 38 INT, FRAC, MOD, and Reference Path Relationship ............ 38 Integer-N Mode .......................................................................... 38 Phase Frequency Detector and Charge Pump ........................ 38 Loop Filter ................................................................................... 39 CP Current Setup ....................................................................... 39 Bleed Current (CP_BLEED) Setup .......................................... 39 MUXOUT .................................................................................... 39 Digital Lock Detect .................................................................... 40 Enables ......................................................................................... 40
IF Output—External Inductor/Biasing ................................... 40 SPI Configuration ...................................................................... 40 VCO Autocalibration and Automatic Level Control ............. 40 Programming Sequence ............................................................ 40
Control Registers ............................................................................ 41 Register Details ............................................................................... 42
Address 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG_1 .. 42 Address 0x001, Reset: 0x00, Name: ADI_SPI_CONFIG_2 .. 43 Address 0x003, Reset: 0x01, Name: CHIPTYPE .................... 44 Address 0x004, Reset: 0x03, Name: PRODUCT_ID_L ........ 44 Address 0x005, Reset: 0x00, Name: PRODUCT_ID_H ....... 44 Address 0x00A, Reset: 0x00, Name: SCRATCHPAD ............ 44 Address 0x00B, Reset: 0x00, Name: SPI_REV ........................ 44 Address 0x103, Reset: 0x6F, Name: ENABLES ....................... 45 Address 0x108, Reset: 0x05, Name: SDO_LEVEL ................. 45 Address 0x200, Reset: 0xA7, Name: INT_L ........................... 46 Address 0x201, Reset: 0x00, Name: INT_H ........................... 46 Address 0x202, Reset: 0x02, Name: FRAC_L ......................... 46 Address 0x203, Reset: 0x00, Name: FRAC_M ....................... 46 Address 0x204, Reset: 0x00, Name: FRAC_H ........................ 46 Address 0x208, Reset: 0x04, Name: MOD_L ......................... 47 Address 0x209, Reset: 0x00, Name: MOD_M ........................ 47 Address 0x20A, Reset: 0x00, Name: MOD_H ........................ 47 Address 0x20C, Reset: 0x01, Name: R_DIV_L ...................... 48 Address 0x20D, Reset: 0x00, Name: R_DIV_H ..................... 48 Address 0x20E, Reset: 0x00, Name: REFERENCE ................ 48 Address 0x211, Reset: 0x00, Name: VCO_DATA_READBACK1 ..................................................... 49 Address 0x212, Reset: 0x00, Name: VCO_DATA_READBACK2 ..................................................... 49 Address 0x213, Reset: 0x01, Name: PLL_MUX_SEL ............ 50 Address 0x214, Reset: 0x98, Name: LOCK_DETECT .......... 50 Address 0x215, Reset: 0x00, Name: VCO_BAND_SELECT 51 Address 0x216, Reset: 0x00, Name: VCO_ALC_TIMEOUT 51 Address 0x217, Reset: 0x01, Name: VCO_MANUAL ........... 51 Address 0x219, Reset: 0x13, Name: ALC ................................ 51 Address 0x21C, Reset: 0x90, Name: VCO_TIMEOUT1 ...... 52 Address 0x21D, Reset: 0x01, Name: VCO_TIMEOUT2 ...... 52 Address 0x21E, Reset: 0x4B, Name: VCO_BAND_DIV ...... 52 Address 0x21F, Reset: 0x18, Name: VCO_READBACK_SEL....................................................................................................... 52
Data Sheet ADMV4420
Rev. A | Page 3 of 61
Address 0x226, Reset: 0x02, Name: AUTOCAL ..................... 53 Address 0x22C, Reset: 0x07, Name: CP_STATE .................... 54 Address 0x22D, Reset: 0x01, Name: CP_BLEED_EN ............ 54 Address 0x22E, Reset: 0x03, Name: CP_CURRENT ............. 54 Address 0x22F, Reset: 0x0C, Name: CP_BLEED .................... 54
Applications Information ............................................................... 55
Evaluation Board ......................................................................... 55 Outline Dimensions ........................................................................ 60
Ordering Guide ........................................................................... 60
REVISION HISTORY 4/2019—Rev. 0 to Rev. A Change to Features Section .............................................................. 1 Changes to Local Oscillator (LO) Internal Frequency Range Parameter, VCO Frequency Range Parameter, and Conversion Gain Parameter, Table 1 .................................................................... 5 Changes to IF = 900 MHz, Low-Side Injection LO Performance Section .............................................................................................. 10 Changes to IF = 1700 MHz, Low-Side Injection LO Performance Section ....................................................................... 14 Changes to IF = 2500 MHz, Low-Side Injection LO Performance Section ....................................................................... 18 10/2018—Revision 0: Initial Version
ADMV4420 Data Sheet
Rev. A | Page 4 of 61
FUNCTIONAL BLOCK DIAGRAM
1699
5-00
1
THIRD-ORDERFRACTIONAL
INTERPOLATOR
×2
N COUNTER
3.3VPLLLDO
3.3VVCOLDO 1.8V
SDMLDO
13 14 1615109
8
7
5
6
2
1
3
4
11 12
17
22
21
28303132 29 27 2526
23
24
20
19
18
MODULUS
16.75GHz TO 21.15GHz
8.375GHz TO 10.575GHz
FRACTIONREGISTER
SPI/LOGIC
PLL LOOP FILTER
CPOUT
GND
VPOS3_CP
ENBL1
ENBL0
GND
GND
SDO
GND
GND
GND
RFIN
GND
GND
DECL1_VCO1
DECL2_VCO2
VPO
S1_V
CO
DECL
3_PL
L
DECL
4_SD
M
VPO
S2_P
LL
REF/
XTAL
1
XTAL
2/NC
MUX
OUT
GND
SCLK
SDI
VTUN
E
VPO
S4_I
F
IFO
UT
GND
DECL
5_RF
PHASEFREQUENCYDETECTOR
CHARGEPUMP
BLEEDCURRENT
CALIBRATIONSWITCH
INTEGERREGISTER
VCO
VCO
ADMV4420
÷1 OR ÷2REFERENCE
DIVIDER
÷1REFERENCEDIVIDE-BY-2
×1 OR ×2REFERENCE
DOUBLER
CS
Figure 1.
Data Sheet ADMV4420
Rev. A | Page 5 of 61
SPECIFICATIONS The measurements are performed at TA = 25°C with 0 dBm external reference at 50 MHz when VVPOS1_VCO = VVPOS2_PLL = VVPOS3_CP = VVPOS4_IF = 5 V, RF input power = −40 dBm, and PLL loop filter bandwidth = 60 kHz with 45° of phase margin, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments RF INPUT
Frequency Range 16.95 22.05 GHz Input Return Loss −8.5 dB Input Impedance 50 Ω Single-ended
LOCAL OSCILLATOR (LO) INTERNAL FREQUENCY RANGE
16.35 21.15 GHz
VCO Frequency Range 8.175 10.575 GHz Tuning Sensitivity (kVCO) 50 MHz/V Calculated with fVCO/VTUNE VTUNE 0 3 V
IF OUTPUT IF Frequency Range 900 2500 MHz Conversion Gain
IF = 900 MHz Low-Side Injection
LO = 16.75 GHz 31 35 dB RF = 17.65 GHz LO = 18.95 GHz 33 39 dB RF = 19.85GHz LO = 21.15 GHz 32 dB RF = 22.05 GHz
High-Side Injection LO = 17.85 GHz 28.5 33 dB RF = 16.95 GHz LO = 18.95 GHz 32.5 37 dB RF = 18.05 GHz LO = 21.15 GHz 29 40 dB RF = 20.25 GHz
IF = 950 MHz Low-Side Injection
LO = 16.35 GHz 29 32 dB RF = 17.30 GHz IF = 2500 MHz
Low-Side Injection LO = 16.75 GHz 28.5 36 dB RF = 19.25 GHz LO = 17.95 GHz 38 dB RF = 20.45 GHz LO = 19.55 GHz 30 dB RF = 22.05 GHz
High-Side Injection LO = 19.45 GHz 27 31 dB RF = 16.95 GHz LO = 20.45 GHz 35 dB RF = 17.95 GHz LO = 21.15 GHz 37 dB RF = 18.65 GHz
Output 1 dB Compression Point (Output P1dB)
7 dBm
Output Third-Order Intercept (Output IP3)
16 dBm
Noise Figure 7 dB Single sideband with appropriate filtering Gain Flatness
±1 dB Across any 250 MHz bandwidth for an IF of 900 MHz to 2000 MHz
±2 dB Across any 250 MHz bandwidth for an IF of 2000 MHz to 2500 MHz
Output Impedance 75 Ω Single-ended Output Return Loss −6.5 dB
ADMV4420 Data Sheet
Rev. A | Page 6 of 61
Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE
VVPOS1_VCO, VVPOS2_PLL, VVPOS3_CP, VVPOS4_IF 4.75 5.00 5.25 V
TOTAL POWER CONSUMPTION Active Mode 1900 mW Sleep Mode 80 mW All blocks powered down
EXTERNAL PLL REFERENCE Frequency 50 MHz Amplitude 0.3 2.5 V p-p Single-ended input, high impedance
CRYSTAL REFERENCE Crystal Frequency 50 MHz Fundamental mode Capacitance 10 pF
PHASE FREQUENCY DETECTOR (PFD) FREQUENCY
50 MHz Compare frequency
REFERENCE SPURS −70 dBm
FREQUENCY SETTLING 400 μs After frequency change programmed; within 50 kHz resolution
CLOSED-LOOP PHASE NOISE LO frequency = 16.75 GHz to 21.15 GHz −80 dBc/Hz 10 kHz offset −85 dBc/Hz 100 kHz offset −116 dBc/Hz 1 MHz offset −125 dBc/Hz 10 MHz offset
LOGIC
(ENBL0, ENBL1, SDO, SDI, SCLK, CS)
Logic Low −0.3 0 +0.5 V Logic High 1.2 3.3 3.6 V
Data Sheet ADMV4420
Rev. A | Page 7 of 61
ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage (VVPOS1_VCO, VVPOS2_PLL,
VVPOS3_CP, and VVPOS4_IF 5.5 V
Digital Input/Output Signal (SCLK, SDI, SDO, CS, ENBL1, and ENBL0)
3.6 V
RFIN 0 dBm Source and Sink Current (MUXOUT) 300 µA Maximum Junction Temperature 125°C Peak Reflow Temperature 260°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) 500 V1 2000 V2 1500 V3 Field Induced Charged Device Model
(FICDM)1 500 V
1 Applies to all pins of the ADMV4420. 2 Applies to all pins except the MUXOUT, ENBL0, ENBL1, SDO, SDI, SCLK, and
CS pins. 3 Applies to the MUXOUT, ENBL0, ENBL1, SDO, SDI, SCLK, and CS pins.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
60 SECONDSTO 180 SECONDS 20 SECONDS
TO 40 SECONDS480 SECONDS MAX
TEM
PER
ATU
RE
(°C
)
TIME (Seconds)
260°C –5°C/+0°C
150°C TO 200°C
RAMP DOWN6°C/SEC MAX
217°C
RAMP UP3°C/SEC MAX
60 SECONDSTO
150 SECONDS
1699
5-12
4
Figure 2. Pb-Free Reflow Solder Profile
THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.
θJA is the natural convection junction to ambient measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance Package Type θJC
1 θJA1 Unit
CP-32-12 7.25 39.6 °C/W 1 The θJA and θJC values are determined by measuring the thermally
designed PCB with a heat sink.
ESD CAUTION
ADMV4420 Data Sheet
Rev. A | Page 8 of 61
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
24 SDO23 GND22 CPOUT21 VPOS3_CP20 ENBL119 ENBL018 GND17 GND
12345678
GNDGNDGNDRFINGNDGND
DECL1_VCO1DECL2_VCO2
PIN 1INDICATOR
9 10 11 12 13 14 15 16
VPO
S1_V
CODE
CL3_
PLL
DECL
4_SD
MVP
OS2
_PLL
XTAL
2/NC
REF/
XTAL
1M
UXO
UTG
ND
32 31 30 29 28 27 26 25
DECL
5_RF
GND
IFO
UTVP
OS4
_IF
VTUN
E
SCLK
SDI
ADMV4420TOP VIEW
(Not to Scale)
1699
5-00
2
CS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 3, 5, 6,
16, 17, 18, 23, 31
GND Ground. Connect these pins and package bottom to RF and dc ground. See Figure 4 for the GND interface schematic.
4 RFIN RF Input Pin. This pin has a 50 Ω input impedance. 7, 8 DECL1_VCO1,
DECL2_VCO2 LDO Regulator Decoupling Pin. Place a 10 µF capacitor close to this pin.
9 VPOS1_VCO 5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to this pin. 10, 11, 32 DECL3_PLL,
DECL4_SDM, DECL5_RF
LDO Decoupling Pin. Place a 10 µF capacitor close to this pin.
12 VPOS2_PLL 5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin. 13 XTAL2/NC Crystal Input or No Connect. When using an external crystal, place the crystal between the REF/XTAL1 and
XTAL2/DNC pins. When an external reference input signal is applied through the REF/XTAL1 pin, this pin is used as a No Connect pin. Connect this pin to ground with a 1 nF capacitor (ac ground) when an external reference input signal is applied through the REF/XTAL1 pin.
14 REF/XTAL1 External Reference Input or Crystal Input. When using an external crystal, place the crystal between the XTAL1 and XTAL2 pins. When using as external reference input, apply an external reference signal to this pin with a 0.01 µF, dc blocking capacitor. Refer to Figure 121 for the external reference input configuration. This pin is internally biased to 1.65 V.
15 MUXOUT PLL Multiplexer Output. 19 ENBL0 Device Enable 0. For nominal operation, keep this pin tied to 3.3 V. 20 ENBL1 Device Enable 1. For nominal operation, keep this pin tied to 3.3 V 21 VPOS3_CP 5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin. 22 CPOUT Synthesizer Charge Pump Output. Connect this pin to VTUNE (Pin 28) through the loop filter 24 SDO Serial Peripheral Interface (SPI) Data Output. 3.3 V logic. 25 SDI SPI Data Input. 3.3 V logic. 26 SCLK SPI Clock. 3.3 V logic. 27 CS SPI Chip Select. 3.3 V logic. Active low.
28 VTUNE VCO Tuning Voltage. This pin is driven by the output of the loop filter. 29 VPOS4_IF 5 V Power Supply. Place 0.1 µF and 100 pF decoupling capacitors close to this pin. 30 IFOUT IF Output. This pin has a 75 Ω output impedance. The output stage of the IF amplifier is an open-collector
configuration and requires a dc bias of 5 V. Use a bias choke inductor. See the IF Output—External Inductor/Biasing section for more details.
EPAD Exposed Pad. The exposed pad must be connected to GND.
Data Sheet ADMV4420
Rev. A | Page 9 of 61
INTERFACE SCHEMATICS GND
1699
5-00
3
Figure 4. GND Interface Schematic
ESDCLAMP
DECL1_VCO1,DECL2_VCO2,
DECL3_PLL,DECL4_SDM,
DECL5_RF
1699
5-00
4
Figure 5. DECL1_VCO1, DECL2_VCO2, DECL3_PLL, DECL4_SDM, and DECL5_RF Interface Schematic
1699
5-20
5ESD
RFIN
Figure 6. RFIN Interface Schematic
ESDCLAMP
VPOS1_VCO,VPOS2_PLL,VPOS3_CP,VPOS4_IF
1699
5-00
5
Figure 7. VPOS1_VCO, VPOS2_PLL, VPOS3_CP, and VPOS4_IF Interface Schematic
ESDCLAMP
XTAL2/NCREF/XTAL1
1699
5-00
6
Figure 8. XTAL2/NC and REF/XTAL1 Interface Schematic
ESDCLAMP
MUXOUT
VPOS2_PLL
1699
5-00
7
Figure 9. MUXOUT Interface Schematic
500Ω
ESDCLAMP
ENBL0ENBL1
VPOS4_IF
1699
5-00
8
Figure 10. ENBL0 and ENBL1 Interface Schematic
CPOUT
VPOS3_CP
1699
5-00
9
Figure 11. CPOUT Interface Schematic
ESDSDO
VPOS4_IF
1699
5-01
0
Figure 12. SDO Interface Schematic
500Ω
ESDCLAMP
SDI,SCLK,
CS
VPOS4_IF
1699
5-01
1
Figure 13. SDI, SCLK, and CS Interface Schematic
ESDCLAMP
VTUNE
1699
5-01
2
Figure 14. VTUNE Interface Schematic
IFOUT
VPOS4_IF
ESD
1699
5-01
3
Figure 15. IFOUT Interface Schematic
ADMV4420 Data Sheet
Rev. A | Page 10 of 61
TYPICAL PERFORMANCE CHARACTERISTICS A 0 dBm external reference at 50 MHz is used with VVPOS1_VCO = VVPOS2_PLL = VVPOS3_CP = VVPOS4_IF = 5 V, RF input power = −40 dBm, and the PLL loop filter bandwidth = 60 kHz with 45° of phase margin, unless otherwise noted.
IF = 900 MHz, LOW-SIDE INJECTION LO PERFORMANCE RF minimum and maximum frequencies are limited by the LO frequency = 16.75 GHz to 21.15 GHz.
50
45
40
35
30
25
20
15
10
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-01
4
Figure 16. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-01
5
NO FILTERING APPLIED
Figure 17. Noise Figure vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
CONV
ERSI
ON
GAI
N (d
B)RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-01
7
Figure 18. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-01
8
NO FILTERING APPLIED
Figure 19. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 11 of 61
30
28
26
24
22
20
18
14
10
16
12
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-02
0
Figure 20. Output IP3 vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-01
6
Figure 21. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
30
28
26
24
22
20
18
14
10
16
12
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-02
1
Figure 22. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
17.6
5
18.0
5
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-01
9
Figure 23. Output P1dB vs. RF Frequency at Various Temperatures
ADMV4420 Data Sheet
Rev. A | Page 12 of 61
IF = 900 MHz, HIGH-SIDE INJECTION LO PERFORMANCE The RF minimum frequency is limited at 16.95 GHz for optimal performance and the RF maximum frequency is limited at the maximum LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-02
2
Figure 24. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
1699
5-02
3
NO FILTERING APPLIED
Figure 25. Noise Figure vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
1699
5-02
4
Figure 26. Output P1dB vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-02
5
Figure 27. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
5.25V5.00V4.75V
1699
5-02
6
NO FILTERING APPLIED
Figure 28. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
5.25V5.00V4.75V
1699
5-02
7
Figure 29. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 13 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
1699
5-02
8
Figure 30. Output IP3 vs. RF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
16.9
5
17.2
5
17.5
5
18.1
5
17.8
5
18.4
5
18.7
5
19.0
5
19.3
5
19.6
5
19.9
5
20.2
5
5.25V5.00V4.75V
1699
5-02
9
Figure 31. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 14 of 61
IF = 1700 MHz, LOW-SIDE INJECTION LO PERFORMANCE The RF minimum frequency is limited at the LO frequency of 16.75 GHz and the RF maximum frequency is limited at 22.05 GHz for optimal performance.
50
45
40
35
30
25
20
15
10
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-03
0
Figure 32. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
1699
5-03
1
NO FILTERING APPLIED
Figure 33. Noise Figure vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
1699
5-03
2
Figure 34. Output P1dB vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-03
3
Figure 35. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
5.25V5.00V4.75V
1699
5-03
4
NO FILTERING APPLIED
Figure 36. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
5.25V5.00V4.75V
1699
5-03
5
Figure 37. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 15 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
1699
5-03
6
Figure 38. Output IP3 vs. RF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
18.4
5
19.2
5
18.8
5
19.6
5
20.0
5
20.4
5
20.8
5
21.2
5
21.6
5
22.0
5
1699
5-03
7
Figure 39. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 16 of 61
IF = 1700 MHz, HIGH-SIDE INJECTION LO PERFORMANCE The RF minimum frequency is limited at 16.95 GHz for optimum performance and the RF maximum frequency is limited at the maximum LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-03
8
Figure 40. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
1699
5-03
9
NO FILTERING APPLIED
Figure 41. Noise Figure vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
1699
5-04
0
Figure 42. Output P1dB vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-04
1
Figure 43. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (GHz)
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
5.25V5.00V4.75V
1699
5-04
2
NO FILTERING APPLIED
Figure 44. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
RF FREQUENCY (GHz)
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
5.25V5.00V4.75V
1699
5-04
3
Figure 45. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 17 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
+85°C+25°C–40°C
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
1699
5-04
4
Figure 46. Output IP3 vs. RF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
RF FREQUENCY (GHz)
16.9
5
17.2
0
17.4
5
17.9
5
17.7
0
18.2
0
18.4
5
18.7
0
18.9
5
19.2
0
19.4
5
5.25V5.00V4.75V
1699
5-04
5
Figure 47. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 18 of 61
IF = 2500 MHz, LOW-SIDE INJECTION LO PERFORMANCE In this configuration, the RF minimum frequency is limited at the LO frequency of 16.75 GHz and the RF maximum frequency is limited at 22.05 GHz for optimal performance.
50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
+85°C+25°C–40°C
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz) 16
995-
046
Figure 48. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
+85°C+25°C–40°C
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz) 16
995-
047
NO FILTERING APPLIED
Figure 49. Noise Figure vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OUT
PUT
P1dB
(dB)
+85°C+25°C–40°C
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz) 16
995-
048
Figure 50. Output P1dB vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-04
9
Figure 51. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
0
NO FILTERING APPLIED
Figure 52. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TPU
T P1
dB (d
B)
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
1
Figure 53. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 19 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz) 16
995-
052
Figure 54. Output IP3 vs. RF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
19.25 22.0521.6521.2520.8520.4520.0519.65RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
3
Figure 55. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 20 of 61
IF = 2500 MHz, HIGH-SIDE INJECTION LO PERFORMANCE The RF minimum frequency is limited at 16.95 GHz for optimal performance and the RF maximum frequency is limited at the maximum LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
+85°C+25°C–40°C
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz) 16
995-
054
Figure 56. Conversion Gain vs. RF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
+85°C+25°C–40°C
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz) 16
995-
055
NO FILTERING APPLIED
Figure 57. Noise Figure vs. RF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TPU
T P1
dB (d
B)
+85°C+25°C–40°C
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz) 16
995-
056
Figure 58. Output P1dB vs. RF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
7
Figure 59. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NOIS
E FI
GUR
E (d
B)
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
8
NO FILTERING APPLIED
Figure 60. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TPU
T P1
dB (d
B)
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-05
9
Figure 61. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 21 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz) 16
995-
060
Figure 62. Output IP3 vs. RF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
16.95 18.6518.3117.9717.6317.29RF FREQUENCY (GHz)
5.25V5.00V4.75V
1699
5-06
1
Figure 63. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 22 of 61
LO = 16.75 GHz, LOW-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-062
Figure 64. Conversion Gain vs. IF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-063
NO FILTERING APPLIED
Figure 65. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-064
Figure 66. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-065
Figure 67. Conversion Gain vs. IF Frequency at Various Supply Voltages, TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-066
NO FILTERING APPLIED
Figure 68. Noise Figure vs. IF Frequency at Various Supply Voltages, TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-067
Figure 69. Output P1dB vs. IF Frequency at Various Supply Voltages, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 23 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
068
Figure 70. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-06
9
Figure 71. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 24 of 61
LO = 16.75 GHz, HIGH-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-070
Figure 72. Conversion Gain vs. IF Frequency at Various Temperatures
30
25
20
15
10
5
0
NO
ISE
FIG
UR
E (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-071
NO FILTERING APPLIED
Figure 73. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-072
Figure 74. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-073
Figure 75. Conversion Gain vs. IF Frequency at Various Supply Voltages, TA = 25°C
30
25
20
15
10
5
0
NO
ISE
FIG
UR
E (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-074
NO FILTERING APPLIED
Figure 76. Noise Figure vs. IF Frequency at Various Supply Voltages, TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-075
Figure 77. Output P1dB vs. IF Frequency at Various Supply Voltages, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 25 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
076
Figure 78. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-07
7
Figure 79. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 26 of 61
LO = 18.95 GHz, LOW-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-078
Figure 80. Conversion Gain vs. IF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-079
NO FILTERING APPLIED
Figure 81. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-080
Figure 82. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-081
Figure 83. Conversion Gain vs. IF Frequency at Various Supply Voltages, TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-082
NO FILTERING APPLIED
Figure 84. Noise Figure vs. IF Frequency at Various Supply Voltages, TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-083
Figure 85. Output P1dB vs. IF Frequency at Various Supply Voltages, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 27 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
084
Figure 86. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-08
5
Figure 87. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 28 of 61
LO = 18.95 GHz, HIGH-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-086
Figure 88. Conversion Gain vs. IF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-087
NO FILTERING APPLIED
Figure 89. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-088
Figure 90. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-089
Figure 91. Conversion Gain vs. IF Frequency at Various Supply Voltages, TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-090
NO FILTERING APPLIED
Figure 92. Noise Figure vs. IF Frequency at Various Supply Voltages, TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-091
Figure 93. Output P1dB vs. IF Frequency at Various Supply Voltages, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 29 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
092
Figure 94. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-09
3
Figure 95. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 30 of 61
LO = 21.15 GHz, LOW-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-094
Figure 96. Conversion Gain vs. IF Frequency at Various Temperatures
30
25
20
15
10
5
0
NO
ISE
FIG
UR
E (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-095
NO FILTERING APPLIED
Figure 97. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz) 16995-096
Figure 98. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CO
NV
ER
SIO
N G
AIN
(d
B)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-097
Figure 99. Conversion Gain vs. IF Frequency at Various Supply Voltages, TA = 25°C
30
25
20
15
10
5
0
NO
ISE
FIG
UR
E (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-098
NO FILTERING APPLIED
Figure 100. Noise Figure vs. IF Frequency at Various Supply Voltages, TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TP
UT
P1d
B (
dB
)
900 2500230019001500 2100170013001100
IF FREQUENCY (MHz)
5.25V5.00V4.75V
16995-099
Figure 101. Output P1dB vs. IF Frequency at Various Supply Voltages, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 31 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
100
Figure 102. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-10
1
Figure 103. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 32 of 61
LO = 21.15 GHz, HIGH-SIDE INJECTION PERFORMANCE 50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
102
Figure 104. Conversion Gain vs. IF Frequency at Various Temperatures
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
103
NO FILTERING APPLIED
Figure 105. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
6
4
2
0
OU
TPU
T P1
dB (d
B)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
104
Figure 106. Output P1dB vs. IF Frequency at Various Temperatures
50
45
40
35
30
25
20
15
10
CONV
ERSI
ON
GAI
N (d
B)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-10
5
Figure 107. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
20
18
16
14
12
10
8
4
0
6
2
NO
ISE
FIG
UR
E (d
B)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-10
6
NO FILTERING APPLIED
Figure 108. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
6
4
2
0
OU
TPU
T P1
dB (d
B)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-10
7
Figure 109. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 33 of 61
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
+85°C+25°C–40°C
900 2500230019001500 2100170013001100IF FREQUENCY (MHz) 16
995-
108
Figure 110. Output IP3 vs. IF Frequency at Various Temperatures
30
28
26
24
22
20
18
14
10
16
12
OUT
PUT
IP3
(dBm
)
900 2500230019001500 2100170013001100IF FREQUENCY (MHz)
5.25V5.00V4.75V
1699
5-10
9
Figure 111. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
ADMV4420 Data Sheet
Rev. A | Page 34 of 61
PHASE NOISE PERFORMANCE –40
–50
–60
–70
–80
–90
–100
–120
–110
–130
–140
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
+85°C+25°C–40°C
10 100 10M100k 1M10k1kOFFSET FREQUENCY (Hz) 16
995-
1 10
Figure 112. Closed-Loop Phase Noise vs. Offset Frequency at Various
Temperatures, IF = 900 MHz, Low-Side Injection LO = 18.95 GHz
10 100 10M100k 1M10k1k
–40
–50
–60
–70
–80
–90
–100
–120
–110
–130
–140
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
+85°C+25°C–40°C
OFFSET FREQUENCY (Hz) 1699
5-11
1
Figure 113. Closed-Loop Phase Noise vs. Offset Frequency at Various
Temperatures, IF = 900 MHz, High-Side Injection LO = 18.95 GHz
10 100 10M100k 1M10k1k
–40
–50
–60
–70
–80
–90
–100
–120
–110
–130
–140
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
LO = 16.75GHz LOW-SIDE INJECTIONLO = 18.95GHz HIGH-SIDE INJECTIONLO = 18.95GHz LOW-SIDE INJECTIONLO = 21.15GHz HIGH-SIDE INJECTION
OFFSET FREQUENCY (Hz) 1699
5-11
2
Figure 114. Closed-Loop Phase Noise vs. Offset Frequency at Various LO
Frequencies, TA = 25°C GHz
0
–40
–60
–20
–80
–100
–120
–140
FREE
RUN
NING
PHA
SE N
OIS
E (d
Bc/H
z)
8375MHz8805MHz9270MHz9720MHz10570MHz10740MHz
100 10M100k 1M10k1kOFFSET FREQUENCY (Hz) 16
995-
113
Figure 115. Free Running Phase Noise vs. Offset Frequency at Various
VCO Frequencies, TA = 25°C
Data Sheet ADMV4420
Rev. A | Page 35 of 61
RETURN LOSS AND ISOLATION 0
–5
–10
–15
–20
–25
–30
–35
16.9
5
17.5
9
18.2
3
19.5
0
18.8
6
20.1
4
21.4
1
20.7
8
22.0
5
RF R
ETUR
N LO
SS (d
B)
FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-1 1
4
Figure 116. RF Return Loss vs. Frequency at Various Temperatures,
LO = 18.95 GHz
0
–2
–4
–6
–8
–10
–12
IF R
ETUR
N LO
SS (d
B)
+85°C+25°C–40°C
0.50 3.002.751.751.25 2.25 2.502.001.501.000.75FREQUENCY (GHz) 16
995-
115
Figure 117. IF Return Loss vs. Frequency at Various Temperatures,
LO = 18.95 GHz, Based on 75 Ω Output System
0
–10
–30
–50
–20
–40
–60
–70
–80
–90
–100
16.7
5
17.1
5
17.5
5
18.7
5
17.9
5
19.5
5
20.7
5
20.3
5
18.3
5
19.1
5
19.9
5
21.1
5
LO T
O R
F LE
AKAG
E (d
Bm)
LO FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-11
6
Figure 118. LO to RF Leakage vs. LO Frequency at Various Temperatures for
Low-Side Injection LO, IF = 900 MHz
0
–10
–30
–50
–20
–40
–60
–70
–80
–90
–100
16.7
5
17.1
5
17.5
5
18.7
5
17.9
5
19.5
5
20.7
5
20.3
5
18.3
5
19.1
5
19.9
5
21.1
5
LO T
O IF
LEA
KAG
E (d
Bm)
LO FREQUENCY (GHz)
+85°C+25°C–40°C
1699
5-11
7
Figure 119. LO to IF Leakage vs. LO Frequency at Various Temperatures for
Low-Side Injection LO, IF = 900 MHz
0
–10
–30
–50
–20
–40
–60
–70
–80
–90
–100
RF T
O IF
ISO
LATI
ON
(dB)
+85°C+25°C–40°C
16.95 22.0520.1418.86 21.4120.7819.5018.2317.59RF FREQUENCY (GHz) 16
995-
118
Figure 120. RF to IF Leakage vs. RF Frequency at Various Temperatures for
LO = 21.15 GHz
ADMV4420 Data Sheet
Rev. A | Page 36 of 61
SPURIOUS AND HARMONICS PERFORMANCE LO Harmonics
All values are in dBm and are measured at the IF output. Trace and connector losses are de-embedded.
Table 5. LO Harmonics at IF Output LO Harmonics (dBm)
LO Frequency (GHz) 0.25 0.5 1 1.5 2 16.75 −110 −49 −58 −71 −66 18.95 −113 −41 −45 −63 −62 21.15 −111 −34 −58 −85 −69
Reference Input (REFIN) Harmonics
All values are in dBm and measured at the IF output. Trace and connector losses are de-embedded. Reference frequency is at 50 MHz.
Table 6. REFIN Harmonics at the IF Output REFIN Frequency (MHz)
REFIN Harmonics (dBm)
1 2 3 4 5 6 7 8 50 −78 −46 −60 −47 −57 −56 −61 −59
IF Harmonics
All values are in dBm and are measured at the IF output. Trace and connector losses are de-embedded. The downconverted IF frequency is at 900 MHz.
Table 7. IF Harmonics at the IF Output IF Harmonics (dBm) IF Frequency (MHz) 1 2 3 4 5 900 −7 −42 −58 −89 −90
Downconverter Spurious Outputs
Mixer spurious products are measured in dBc from the IF output power level, unless otherwise specified. Trace and connector losses are de-embedded. N/A means not applicable.
RF = 19.85 GHz, LO = 18.95 GHz, IF = 0.9 GHz, RF power = −40 dBm. Spur frequencies are the absolute value of (M × RF) + (N × LO/2)
N × LO 0 1 2 3 4
M × RF
−2 −95 −99 −101 −91 −37
−1 −78 −77 0 −81 −90
0 N/A −46 −50 −65 −56
+1 −78 −98 −80 −88 N/A
+2 −95 −88 N/A N/A N/A
RF = 18.05 GHz, LO = 18.95 GHz, IF = 0.9 GHz, RF power = −40 dBm. Spur frequencies are the absolute value of (M × RF) + (N × LO/2).
N × LO 0 1 2 3 4
M × RF
−2 −77 −70 0 −82 −87
−1 −95 −98 −103 −96 −41
0 N/A −45 −49 −64 −55
+1 −77 −98 −93 −89 N/A
+2 −95 −89 N/A N/A N/A
Data Sheet ADMV4420
Rev. A | Page 37 of 61
THEORY OF OPERATION REFERENCE INPUT STAGE The reference input stage is shown in Figure 121 and employs a differentially excited, 50 MHz crystal oscillator. Alternatively, the reference input can be driven by an external singled-ended 50 MHz source. Use the REF_IN_MODE bit (Register 0x20E, Bit 1) to select the input configuration. To select crystal oscillator mode, set this bit to 0 to close the SW1 switch and open the SW2 switch. To select single-ended mode, set this bit to 1 to close the SW2 switch and open the SW1 switch.
The selection of a crystal oscillator must be such that the electrical series resistance (ESR) and the load capacitance are well defined. For worst case demonstration purposes, the crystal oscillator selected for the evaluation board uses a maximum ESR of 100 Ω. To ensure the crystal oscillation startup over all temperature and process variations, a maximum ESR of 40 Ω is recommended. The nominal crystal load capacitance (CLOAD) = 10 pF, which is computed from series combination of the C5 and C6 capacitors. It is recommended to keep CLOAD between 8 pF and 12 pF. Additionally, ensure that C21 is not installed for crystal oscillator mode, as this can impact capacitive loading on the crystal, which can in turn prevent the oscillation from starting up.
REFERENCE DOUBLER, R COUNTER, AND RDIV2 Following the reference input stage as shown in Figure 121, there is an internal reference multiply by 2 block (×2 doubler) that allows generation of higher phase frequency detector frequencies (fPFD). A higher fPFD is useful for improving overall system phase noise performance. Typically, doubling the fPFD improves the inband phase noise performance by up to 3 dBc/Hz. Use the EN_REF_X2 bit (Register 0x20E, Bit 2) to enable the reference doubler, which toggles the SW3 switch, as shown in Figure 121.
Following the reference doubler block, there are two frequency dividers: a 10-bit R counter (1 to 1023 allowed) and a divide by 2 block. These dividers allow the input reference frequency (fREF) to be divided down to produce lower fPFD, which helps to minimize fractional-N integer boundary spurs at the output.
The R counter is set using the R_DIV bits in Register 0x20C and Register 0x20D. If the R_DIV = 1, the SW4 switch is in the position shown in Figure 121. Otherwise, the SW4 switch toggles to use the R counter.
The reference divide by 2 block is enabled by using the RDIV2_ SEL bit (Register 0x20E, Bit 0), which toggles the SW5 switch, as shown in Figure 121.
×2DOUBLER
SW3
10-BITR COUNTER
SW4
÷2
SW5
TOPFD
SW1
SW2
C21Y1
C6 C5 R1
XTAL2/NC REF/XTAL1
EXTERNALREFERENCE
1699
5-22
0
Figure 121. Reference Input Path Block Diagram
ADMV4420 Data Sheet
Rev. A | Page 38 of 61
N COUNTER The N counter allows a division ratio in the PLL feedback path from the VCO. Note that the VCO signal is multiplied by 2 to achieve the LO frequency at the double balanced mixer. The division ratio is determined using the integer-N (INT), fractional-N (FRAC), and modulus (MOD) values that this counter comprises. The applicable registers for setting the INT, FRAC, and MOD values are Register 0x200 to Register 0x20A.
1699
5-22
1FRACVALUE
MODVALUE
INTVALUE
N = INT + FRAC/MODTO PFD
N COUNTERFROM VCO
THIRD-ORDERFRACTIONAL
INTERPOLATOR
Figure 122. N Counter Functional Diagram
INT, FRAC, MOD, AND REFERENCE PATH RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the reference path, make it possible to generate VCO frequencies spaced by fractions of the fPFD.
The fPFD can be calculated from the reference frequency (fREF) and the reference path configuration parameters,
1(1 )PFD REF
Df f
R T+
= ×× +
(1)
where: D is the reference doubler bit (0 or 1). R is the reference divide ratio of the binary, 10-bit programmable counter (1 to 1023). T is the reference divide by 2 bit (0 or 1).
The VCO frequency (fVCO) is calculated with the following equation:
2LO
VCO PFDff f N= = × (2)
where: fLO is the frequency of the LO driving the mixer. N is the desired value of the N counter.
The N counter value is defined as:
= + = =2
LO VCO
PFD PFD
FRAC f fN INTMOD f f
(3)
where: INT is the 16-bit integer value (75 to 65,535). FRAC is the numerator of the 24-bit primary modulus value (0 to 16,777,215). MOD is the denominator of the 24-bit primary modulus value (1 to 16,777,215).
To obtain the INT portion of the N counter value, round down using the mathematical floor function,
INT = FLOOR(N) (4)
where FLOOR is the mathematical floor function.
To determine the value of the MOD parameter, a channel spacing step size (fCHSP) and the fPFD must be selected first.
The MOD parameter is then computed with the fPFD and the greatest common denominator (GCD),
=( , )
PFD
CHSP PFD
fMODGCD f f
(5)
The FRAC value can be computed for a given an N counter value, INT value, and MOD value,
FRAC = FLOOR(MOD × (N –INT)) (6)
INTEGER-N MODE When the FRAC value is equal to zero, the synthesizer operates in integer-N mode.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP The PFD takes inputs from the R counter and N counter to produce an output that is proportional to the phase and frequency differences between them. This proportional information is then output to a charge pump (CP) circuit that generates current to drive an external loop filter, which is then used to appropriately increase or decrease the VTUNE tuning voltage.
Figure 123 shows a simplified schematic of the PFD and CP. Note that the PFD includes a fixed delay element, which is used to ensure there is no dead zone in the PFD transfer function for consistent reference spur levels.
Data Sheet ADMV4420
Rev. A | Page 39 of 61
U3
CLR2Q2D2
U2
DOWN
UPHIGH
HIGH
CPOUT
–IN
+IN
CHARGEPUMPDELAY
CLR1
Q1D1
U1
1699
5-22
2
Figure 123. PFD and CP Simplified Schematic
LOOP FILTER Defining a loop filter for a PLL is dependent on several dynamics, such as the PFD frequency, the N counter value, the tuning sensitivity characteristics (kVCO) of the VCO, and the selected CP current. A higher fPFD has the advantage of lowering inband phase noise performance at the expense of integer boundary spur levels when operating in fractional-N mode. Consequently, a lower fPFD can allow the PLL to operate in integer-N mode, which can eliminate integer boundary spurs at the expense of higher inband phase noise performance. Given the trade-offs, care must be taken with frequency planning and fPFD selection to ensure the appropriate inband phase noise performance is met with acceptable spur levels for the end application.
The loop filter, as implemented in the ADMV4420-EVALZ evaluation board, is a third-order passive filter, as shown in Figure 124. The filter is designed with the following simulation input parameters: fPFD = 50 MHz, kVCO = 80 MHz/V, fVCO = 9.4 GHz and ICP = 1.25 mA. The resulting loop filter bandwidth and phase margin are 60 kHz and 45°, respectively.
For additional guidance with loop filter simulations on the ADMV4420, contact Analog Devices, Inc., for technical support.
1699
5-22
3
CPOUT VTUNE
C1470pF
C26.8nF
R1680Ω
R21.5kΩ
C3220pF
C2DNI
R30Ω
Figure 124. Recommended Loop Filter Schematic
CP CURRENT SETUP For a specifically designed loop filter, the CP current (ICP) must be set by adjusting the CP_CURRENT value in Register 0x22E.
The CP current follows the equation,
ICP = (CP_CURRENT + 1) × 312.5 μA (7)
where CP_CURRENT is an integer value (0 to 15).
Note that the default value of CP_CURRENT is 3, which yields a current of 1.25 mA. The applicable range is 312.5 µA to 5 mA, with 312.5 µA steps.
To change the fPFD, if no change has been made to the existing loop filter components, it is recommended to scale the ICP using the following equation:
( ) ( )( )
( ) ( )
1.25 mA 50 MHz× ×= =CP DEFAULT PFD DEFAULT
CP NEWPFD NEW PFD NEW
I fI
f f (8)
where: ICP(NEW) is the new desired ICP. ICP(DEFAULT) is the default ICP. fPFD(DEFAULT) is the default fPFD. fPFD(NEW) is the new desired fPFD.
When ICP(NEW) is obtained, the CP_CURRENT value in Register 0x22E can be updated using the round function,
( )_ ROUND 1312.5 μA
CP NEWICP CURRENT
= −
(9)
where ROUND is the mathematical round function.
BLEED CURRENT (CP_BLEED) SETUP The charge pump includes a binary scaled bleed current (IBLEED), which is set by using the CP_BLEED value in Register 0x22F. The bleed current introduces a slight phase offset in the PFD to improve integer boundary spurs when operating in fractional-N mode.
Generally, the bleed current follows Equation 10 and provides a value that can be applicable for most applications, but there can be additional spur level improvement by empirically determining the appropriate bleed current value from actual measurements for the intended application. The applicable range is 0 µA to 956.25 µA, with 3.75 µA steps.
4_ 3.75 μA CP
BLEEDI
I CP BLEEDN×
= × = (10)
where CP_BLEED is an integer value (0 to 255).
When IBLEED is obtained, the CP_BLEED value in Register 0x22F can be updated using the round function,
_ ROUND3.75 μA
BLEEDICP BLEED
=
(11)
where IBLEED is the desired charge pump bleed current.
MUXOUT The on-chip multiplexer output (MUXOUT) allows access to various internal signals, in addition to providing a digital lock detect function. A representative diagram is shown in Figure 125. The state of the MUXOUT pin is determined from the PLL_MUX_SEL value in Register 0x213. See Table 31 for full details.
ADMV4420 Data Sheet
Rev. A | Page 40 of 61
1699
5-22
4
MUX MUXOUT
OUTPUT LOWDIGITAL LOCK DETECT
R COUNTER/2N COUNTER/2OUTPUT HIGH
Figure 125. Multiplexer Output Diagram
DIGITAL LOCK DETECT The digital lock detect function that is output on the MUXOUT pin has two adjustable settings in Register 0x214. LD_BIAS adjusts an internal precision window and LD_COUNT adjusts the consecutive cycle count to declare PLL lock. It is recom-mended to keep the 20 µA and 8192 PFD cycle count factory settings. For special applications, contact Analog Devices technical support for guidance on adjusting these settings.
ENABLES Register 0x103 has individual circuit block enables. Setting this register to 0 disables all circuit blocks, resulting in approximately 80 mW of power dissipation. For nominal operation, keep all enables in this register set to 1 (register value of 0x6F). Note that Bit 4 and Bit 7 are reserved and must be set to 0.
IF OUTPUT—EXTERNAL INDUCTOR/BIASING The IF amplifier output is an open-collector configuration and requires an external biasing inductor pulled up to the VPOS4_IF supply. The recommended value of the inductor is approximately 50 nH, which requires a current carrying capability of at least 150 mA. Because this configuration is dc-coupled, it is necessary to place a series capacitor between the IF output and the next stage in the end application. A recommended minimum value for the series capacitor is 1 nF.
SPI CONFIGURATION The SPI of the ADMV4420 allows configuration of the device for specific functions or operations via the 4-pin SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDI, SDO, and CS. The ADMV4420 protocol consists of a write/read bit followed by 15 register address bits and 8 data bits. The address field and data field are organized MSB first and end with the LSB.
For a write operation, set the MSB to 0, and for a read operation, set the MSB to 1. The write cycle sampling must be done on the rising edge of SCLK. The 24 bits of the serial write address and data are shifted in on the SDI control line, MSB to LSB. The ADMV4420 input logic level for the write cycle supports a 3.3 V interface.
For a read cycle, the R/W bit and the 15 bits of address shift in on the rising edge of SCLK on the SDI control line. Then, 8 bits of serial read data shift out on the SDO control line, MSB first,
on the falling edge of SCLK. The output logic level for a read cycle is 3.3 V. The output drivers of the SDO are enabled after the last rising edge of SCLK of the instruction cycle and remain active until the end of the read cycle. In a read operation, when CS is deasserted, SDO returns to high impedance until the next read transaction. The CS is active low and must be deasserted at the end of the write or read sequence.
An active low input on CS starts and gates a communication cycle. The CS pin allows more than one device to be used on the same serial communications lines. The SDO pin goes to a high impedance state when the CS input is high. During the communication cycle, the chip select must stay low.
The SPI communications protocol follows the Analog Devices SPI standard. For more information, see the ADI-SPI Serial Control Interface Standard (Rev 1.0).
VCO AUTOCALIBRATION AND AUTOMATIC LEVEL CONTROL The multicore VCO uses an internal autocalibration (AUTOCAL) and automatic level control (ALC) routine that optimizes the VCO settings for a particular frequency and allows the PLL to lock in approximately 400 µs after the lower portion of the N counter integer value (INT_L) has been programmed. For nominal applications, maintain the AUTOCAL and ALC default values in the register map (see Table 8).
PROGRAMMING SEQUENCE A number of double buffered registers that take effect only after a write to the lower portion of the N counter integer value (INT_L). The INT_L register applies any changes to these double registers and initiate the autocalibration routine. Additionally, it is recommended to allow 16 SPI clock cycles after writing to the INT_L register.
The following describes the recommended programming sequence:
1. Program the CP_CURRENT register (Register 0x22E). 2. Program the FRAC_H register (Register 0x204). 3. Program the FRAC_M register (Register 0x203). 4. Program the FRAC_L register (Register 0x202). 5. Program the MOD_H register (Register 0x20A). 6. Program the MOD_M register (Register 0x209). 7. Program the MOD_L register (Register 0x208). 8. Program the INT_H register (Register 0x201). 9. Program the INT_L register (Register 0x200). 10. Program 16 SPI clock cycles.
Data Sheet ADMV4420
Rev. A | Page 41 of 61
CONTROL REGISTERS Table 8. Control Register Map Register Address Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x000 ADI_SPI_ CONFIG_1
[7:0] SOFTRESET_ LSB_ FIRST_
ENDIAN_ SDOACTIVE_ SDOACTIVE ENDIAN LSB_FIRST SOFTRESET 0x00 R/W
0x001 ADI_SPI_ CONFIG_2
[7:0] SINGLE_ INSTRUCTION
CSB_ STALL
MASTER_ SLAVE_RB
RESERVED MASTER_SLAVE_ TRANSFER
0x00 R/W
0x003 CHIPTYPE [7:0] CHIPTYPE 0x01 R
0x004 PRODUCT_ ID_L
[7:0] PRODUCT_ID_L 0x03 R
0x005 PRODUCT_ ID_H
[7:0] PRODUCT_ID_H 0x00 R
0x00A SCRATCHPAD [7:0] SCRATCHPAD 0x00 R/W
0x00B SPI_REV [7:0] SPI_REV 0x00 R
0x103 ENABLES [7:0] RESERVED EN_PLL EN_LO RESERVED EN_VCO EN_IFAMP EN_MIXER EN_LNA 0x6F R/W
0x108 SDO_LEVEL [7:0] RESERVED SDO_LEVEL RESERVED 0x05 R/W
0x200 INT_L [7:0] INT[7:0] 0xA7 R/W
0x201 INT_H [7:0] INT[15:8] 0x00 R/W
0x202 FRAC_L [7:0] FRAC[7:0] 0x02 R/W
0x203 FRAC_M [7:0] FRAC[15:8] 0x00 R/W
0x204 FRAC_H [7:0] FRAC[23:16] 0x00 R/W
0x208 MOD_L [7:0] MOD[7:0] 0x04 R/W
0x209 MOD_M [7:0] MOD[15:8] 0x00 R/W
0x20A MOD_H [7:0] MOD[23:16] 0x00 R/W
0x20C R_DIV_L [7:0] R_DIV[7:0] 0x01 R/W
0x20D R_DIV_H [7:0] RESERVED R_DIV[9:8] 0x00 R/W
0x20E REFERENCE [7:0] RESERVED END_REF_ X2
REF_IN_ MODE
RDIV2_SEL 0x00 R/W
0x211 VCO_DATA_ READBACK1
[7:0] VCO_DATA_READBACK[7:0] 0x00 R
0x212 VCO_DATA_ READBACK2
[7:0] RESERVED VCO_DATA_READBACK[10:8] 0x00 R
0x213 PLL_ MUX_SEL
[7:0] PLL_MUX_SEL 0x01 R/W
0x214 LOCK_ DETECT
[7:0] LD_BIAS LD_COUNT RESERVED 0x98 R/W
0x215 VCO_BAND_ SELECT
[7:0] VCO_BAND_SELECT 0x00 R/W
0x216 VCO_ALC_ TIMEOUT
[7:0] RESERVED VCO_ALC_TIMEOUT 0x00 R/W
0x217 VCO_ MANUAL
[7:0] RESERVED VCO_CORE_SELECT VCO_BIAS_ADJUST 0x01 R/W
0x219 ALC [7:0] RESERVED EN_ALC RESERVED 0x13 R/W
0x21C VCO_ TIMEOUT1
[7:0] VCO_TIMEOUT[7:0] 0x90 R/W
0x21D VCO_ TIMEOUT2
[7:0] RESERVED VCO_TIMEOUT[9:8] 0x01 R/W
0x21E VCO_BAND_ DIV
[7:0] VCO_BAND_DIV 0x4B R/W
0x21F VCO_ READBACK_SEL
[7:0] RESERVED VCO_READBACK_SEL 0x18 R/W
0x226 AUTOCAL [7:0] RESERVED EN_ AUTOCAL
RESERVED 0x02 R/W
0x22C CP_STATE [7:0] RESERVED CP_STATE 0x07 R/W
2x22D CP_BLEED_EN [7:0] RESERVED EN_BLEED 0x01 R/W
0x22E CP_CURRENT [7:0] RESERVED CP_CURRENT 0x03 R/W
0x22F CP_BLEED [7:0] BICP 0x0C R/W
ADMV4420 Data Sheet
Rev. A | Page 42 of 61
REGISTER DETAILS ADDRESS 0x000, RESET: 0x00, NAME: ADI_SPI_CONFIG_1
SoftReset
1: Reset not Asserted.0: Reset Asserted.
SoftReset
1: Reset not Asserted.0: Reset Asserted.
LSB_First
1: MSB Firs t.0: LSB Firs t.
LSB_First
1: MSB Firs t.0: LSB Firs t.
Endian
1: Big Endian.0: Little Endian.
Endian
1: Big Endian.0: Little Endian.
SDOActive
1: SDO Active.0: SDO Inactive.
SDOActive
1: SDO Active.0: SDO Inactive.
0
01
02
03
04
05
06
07
0
[7] SOFTRESET_ (R/W) [0] SOFTRESET (R/W)
[6] LSB_FIRST_ (R/W) [1] LSB_FIRST (R/W)
[5] ENDIAN_ (R/W) [2] ENDIAN (R/W)
[4] SDOACTIVE_ (R/W) [3] SDOACTIVE (R/W)
Table 9. ADI_SPI_CONFIG1 Bit Descriptions Bit Bit Name Description Reset Access 7 SOFTRESET_ Soft reset bit 0x0 R/W 0: Reset asserted 1: Reset not asserted 6 LSB_FIRST_ LSB first bit 0x0 R/W 0: LSB first 1: MSB first 5 ENDIAN_ Endian bit 0x0 R/W 0: Little endian 1: Big endian 4 SDOACTIVE_ SDO active bit 0x0 R/W 0: SDO inactive 1: SDO active 3 SDOACTIVE SDO active bit 0x0 R/W 0: SDO inactive 1: SDO active 2 ENDIAN Endian bit 0x0 R/W 0: Little endian 1: Big endian 1 LSB_FIRST LSB first bit 0x0 R/W 0: LSB first 1: MSB first 0 SOFTRESET Soft reset 0x0 R/W 0: Reset asserted 1: Reset not asserted
Data Sheet ADMV4420
Rev. A | Page 43 of 61
ADDRESS 0x001, RESET: 0x00, NAME: ADI_SPI_CONFIG_2
Single Instruction
1:CSB.Disable Streaming Regardless of
0: Enable Streaming.Master Slave Transfer
CSB Stall
Master Slave RB
0
01
02
03
04
05
06
07
0
[7] SINGLE_INSTRUCTION (R/W) [0] MASTER_SLAVE_TRANSFER (R/W)
[6] CSB_STALL (R/W)
[4:1] RESERVED
[5] MASTER_SLAVE_RB (R/W)
Table 10. ADI_SPI_CONFIG_2 Bit Descriptions Bit Bit Name Description1 Reset Access 7 SINGLE_INSTRUCTION Single instruction bit 0x0 R/W 0: Enable streaming 1: Disable streaming regardless of CSB 6 CSB_STALL CSB stall bit 0x0 R/W 5 MASTER_SLAVE_RB Master slave readback bit 0x0 R/W [4:1] RESERVED Reserved 0x0 R 0 MASTER_SLAVE_TRANSFER Master slave transfer bit 0x0 R/W 1 Note that CS corresponds to CSB.
ADMV4420 Data Sheet
Rev. A | Page 44 of 61
ADDRESS 0x003, RESET: 0x01, NAME: CHIPTYPE
Chip Type (Read Only)
0
11
02
03
04
05
06
07
0
[7:0] CHIPTYPE (R)
Table 11. CHIPTYPE Bit Descriptions Bits Bit Name Description Reset Access [7:0] CHIPTYPE Chip type bits, read only. 0x01 R
ADDRESS 0x004, RESET: 0x03, NAME: PRODUCT_ID_L
Product_ID_L, Lower 8 Bits
0
11
12
03
04
05
06
07
0
[7:0] PRODUCT_ID_L (R)
Table 12. PRODUCT_ID_L Bit Descriptions Bits Bit Name Description Reset Access [7:0] PRODUCT_ID_L PRODUCT_ID_L bits, lower 8 bits. 0x03 R
ADDRESS 0x005, RESET: 0x00, NAME: PRODUCT_ID_H
Product_ID_H, Higher 8 Bits
0
01
02
03
04
05
06
07
0
[7:0] PRODUCT_ID_H (R)
Table 13. PRODUCT_ID_H Bit Descriptions Bits Bit Name Description Reset Access [7:0] PRODUCT_ID_H PRODUCT_ID_H bits, higher 8 bits. 0x00 R
ADDRESS 0x00A, RESET: 0x00, NAME: SCRATCHPAD
ScratchPad
0
01
02
03
04
05
06
07
0
[7:0] SCRATCHPAD (R/W)
Table 14. SCRATCHPAD Bit Descriptions Bits Bit Name Description Reset Access [7:0] SCRATCHPAD Scratch pad bits 0x00 R/W
ADDRESS 0x00B, RESET: 0x00, NAME: SPI_REV
SPI Register Map Revis ion
0
01
02
03
04
05
06
07
0
[7:0] SPI_REV (R)
Table 15. SPI_REV Bit Descriptions Bits Bit Name Description Reset Access [7:0] SPI_REV SPI register map revision bits 0x00 R
Data Sheet ADMV4420
Rev. A | Page 45 of 61
ADDRESS 0x103, RESET: 0x6F, NAME: ENABLES
LNA Enable
1: Power Up LNA.0: Power Down LNA.PLL Enable
1: Power Up PLL.0: Power Down PLL.
Mixer Enable
1: Power Up Mixer.0: Power Down Mixer.LO Enable
1: Power Up LO.0: Power Down LO.
IF Amp Enable
1: Power Up IF Amplifier.0: Power Down IF Amplifier.
VCO Enable
1: Power Up VCO.0: Power Down VCO.
0
11
12
13
14
05
16
17
0
[7] RESERVED [0] EN_LNA (R/W)
[6] EN_PLL (R/W)
[1] EN_MIXER (R/W)
[5] EN_LO (R/W)
[2] EN_IFAMP (R/W)
[4] RESERVED
[3] EN_VCO (R/W)
Table 16. ENABLES Bit Descriptions Bits Bit Name Description Reset Access 7 RESERVED Reserved 0x0 R 6 EN_PLL PLL enable bit 0x1 R/W 0: Power down PLL 1: Power up PLL 5 EN_LO LO enable bit 0x1 R/W 0: Power down LO 1: Power up LO 4 RESERVED Reserved 0x0 R 3 EN_VCO VCO enable bit 0x1 R/W 0: Power down VCO 1: Power up VCO 2 EN_IFAMP IF amplifier enable bit 0x1 R/W 0: Power down IF amplifier 1: Power up IF amplifier 1 EN_MIXER Mixer enable bit 0x1 R/W 0: Power down mixer 1: Power up mixer 0 EN_LNA LNA enable bit 0x1 R/W 0: Power down LNA 1: Power up LNA
ADDRESS 0x108, RESET: 0x05, NAME: SDO_LEVEL
SPI Supply Control
1: 3.3V Read Back.0: 1.8V Read Back.
0
11
02
13
04
05
06
07
0
[7:3] RESERVED [1:0] RESERVED
[2] SDO_LEVEL (R/W)
Table 17. SDO_LEVEL Bit Descriptions Bits Bit Name Description Reset Access [7:3] RESERVED Reserved 0x0 R 2 SDO_LEVEL SPI supply control bit 0x1 R/W 0: 1.8 V readback 1: 3.3 V readback [1:0] RESERVED Reserved 0x1 R/W
ADMV4420 Data Sheet
Rev. A | Page 46 of 61
ADDRESS 0x200, RESET: 0xA7, NAME: INT_L
Integer-N Word (16-Bit)
0
1
1
1
2
1
3
0
4
0
5
1
6
0
7
1
[7:0] INT[7:0] (R/W)
Table 18. INT_L Bit Descriptions Bits Bit Name Description Reset Access [7:0] INT[7:0] Integer-N word (16-bit) 0xA7 R/W
ADDRESS 0x201, RESET: 0x00, NAME: INT_H
Integer-N Word (16-Bit)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] INT[15:8] (R/W)
Table 19. INT_H Bit Descriptions Bits Bit Name Description Reset Access [7:0] INT[15:8] Integer-N word (16-bit) 0x0 R/W
ADDRESS 0x202, RESET: 0x02, NAME: FRAC_L
Fractional-N Word (24-Bit)
0
0
1
1
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] FRAC[7:0] (R/W)
Table 20. FRAC_L Bit Descriptions Bits Bit Name Description Reset Access [7:0] FRAC[7:0] Fractional-N word (24-bit) 0x2 R/W
ADDRESS 0x203, RESET: 0x00, NAME: FRAC_M
Fractional-N Word (24-Bit)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] FRAC[15:8] (R/W)
Table 21. FRAC_M Bit Descriptions Bits Bit Name Description Reset Access [7:0] FRAC[15:8] Fractional-N word (24-bit) 0x0 R/W
ADDRESS 0x204, RESET: 0x00, NAME: FRAC_H
Fractional-N Word (24-Bit)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] FRAC[23:16] (R/W)
Table 22. FRAC_H Bit Descriptions Bits Bit Name Description Reset Access [7:0] FRAC[23:16] Fractional-N word (24-bit) 0x0 R/W
Data Sheet ADMV4420
Rev. A | Page 47 of 61
ADDRESS 0x208, RESET: 0x04, NAME: MOD_L
Fractional-N Modulus (24-Bit)
0
01
02
13
04
05
06
07
0
[7:0] MOD[7:0] (R/W)
Table 23. MOD_L Bit Descriptions Bits Bit Name Description Reset Access [7:0] MOD[7:0] Fractional-N modulus (24-bit) 0x4 R/W
ADDRESS 0x209, RESET: 0x00, NAME: MOD_M
Fractional-N Modulus (24-Bit)
0
01
02
03
04
05
06
07
0
[7:0] MOD[15:8] (R/W)
Table 24. MOD_M Bit Descriptions Bits Bit Name Description Reset Access [7:0] MOD[15:8] Fractional-N modulus (24-bit) 0x0 R/W
ADDRESS 0x20A, RESET: 0x00, NAME: MOD_H
Fractional-N Modulus (24-Bit)
0
01
02
03
04
05
06
07
0
[7:0] MOD[23:16] (R/W)
Table 25. MOD_H Bit Descriptions Bits Bit Name Description Reset Access [7:0] MOD[23:16] Fractional-N modulus (24-bit) 0x0 R/W
ADMV4420 Data Sheet
Rev. A | Page 48 of 61
ADDRESS 0x20C, RESET: 0x01, NAME: R_DIV_L
R-Divider Word (10-Bit)
0
11
02
03
04
05
06
07
0
[7:0] R_DIV[7:0] (R/W)
Table 26. R_DIV_L Bit Descriptions Bits Bit Name Description Reset Access [7:0] R_DIV[7:0] R divider word (10-bit) 0x1 R/W
ADDRESS 0x20D, RESET: 0x00, NAME: R_DIV_H
R-Divider Word (10-Bit)
0
01
02
03
04
05
06
07
0
[7:2] RESERVED [1:0] R_DIV[9:8] (R/W)
Table 27. R_DIV_H Bit Descriptions Bits Bit Name Description Reset Access [7:2] RESERVED Reserved 0x0 R [1:0] R_DIV[9:8] R divider word (10-bit) 0x0 R/W
ADDRESS 0x20E, RESET: 0x00, NAME: REFERENCE
Reference Divide by 2
1: Reference Divide by 2 Enabled.0: Reference Divide by 2 Disabled.Reference Doubler Enable
1: Enable.0: Disable.
Reference Input Mode
1: Single-Ended Mode.0: XTAL Oscillator Mode.
0
01
02
03
04
05
06
07
0
[7:3] RESERVED [0] RDIV2_SEL (R/W)
[2] EN_REF_X2 (R/W)
[1] REF_IN_MODE (R/W)
Table 28. REFERENCE Bit Descriptions Bits Bit Name Description Reset Access [7:3] RESERVED Reserved 0x0 R 2 EN_REF_X2 Reference doubler enable bit 0x0 R/W 0: Disable 1: Enable 1 REF_IN_MODE Reference input mode bit 0x0 R/W 0: Crystal (XTAL) oscillator mode 1: Single-ended mode 0 RDIV2_SEL Reference divide by 2 bit 0x0 R/W 0: Reference divide by 2 disabled 1: Reference divide by 2 enabled
Data Sheet ADMV4420
Rev. A | Page 49 of 61
ADDRESS 0x211, RESET: 0x00, NAME: VCO_DATA_READBACK1
VCO Data Readback
0
01
02
03
04
05
06
07
0
[7:0] VCO_DATA_READBACK[7:0] (R)
Table 29. VCO_DATA_READBACK1 Bit Descriptions Bits Bit Name Description Reset Access [7:0] VCO_DATA_READBACK[7:0] VCO data readback 0x0 R
ADDRESS 0x212, RESET: 0x00, NAME: VCO_DATA_READBACK2
VCO Data Readback
0
01
02
03
04
05
06
07
0
[7:3] RESERVED [2:0] VCO_DATA_READBACK[10:8] (R)
Table 30. VCO_DATA_READBACK2 Bit Descriptions Bits Bit Name Description Reset Access [7:3] RESERVED Reserved 0x0 R [2:0] VCO_DATA_READBACK[10:8] VCO data readback bits 0x0 R
ADMV4420 Data Sheet
Rev. A | Page 50 of 61
ADDRESS 0x213, RESET: 0x01, NAME: PLL_MUX_SEL
PLL Mux Select
00001000: Output Logic High.
00000101:VCO/(2 x N)NDiv-by-2 to Mux Out, Frequency =
00000100:REFIN/(2 x R)RDiv-by-2 to Mux Out, Frequency =
00000001: Digital Lock Detect.00000000: Output Logic Low.
0
11
02
03
04
05
06
07
0
[7:0] PLL_MUX_SEL (R/W)
Table 31. PLL_MUX_SEL Bit Descriptions Bits Bit Name Description Reset Access [7:0] PLL_MUX_SEL PLL mux select bits 0x1 R/W 00000000: Output logic low 00000001: Digital lock detect 00000100: R divide by 2 to mux out, frequency = REFIN /2 × R) 00000101: N divide by 2 to mux out, frequency = VCO/(2 × N) 00001000: Output logic high
ADDRESS 0x214, RESET: 0x98, NAME: LOCK_DETECT
Lock Detect Bias
11: 10uA.10: 20uA.01: 30uA.00: 40uA.
Lock Detect Count
011:Declare Lock.8192 Consecutive PFD Cycles to
010:Declare Lock.4096 Consecutive PFD Cycles to
001:Declare Lock.2048 Consecutive PFD Cycles to
000:Declare Lock.1024 Consecutive PFD Cycles to
0
01
02
03
14
15
06
07
1
[7:6] LD_BIAS (R/W) [2:0] RESERVED
[5:3] LD_COUNT (R/W)
Table 32. LOCK_DETECT Bit Descriptions Bits Bit Name Description Reset Access [7:6] LD_BIAS Lock detect bias bits 0x2 R/W 00: 40 μA 01: 30 μA 10: 20 μA 11: 10 μA [5:3] LD_COUNT Lock detect count bits 0x3 R/W 000: 1024 consecutive PFD cycles to declare lock 001: 2048 consecutive PFD cycles to declare lock 010: 4096 consecutive PFD cycles to declare lock 011: 8192 consecutive PFD cycles to declare lock [2:0] RESERVED Reserved 0x0 R/W
Data Sheet ADMV4420
Rev. A | Page 51 of 61
ADDRESS 0x215, RESET: 0x00, NAME: VCO_BAND_SELECT
Manually Programmed VCO Band
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] VCO_BAND_SELECT (R/W)
Table 33. VCO_BAND_SELECT Bit Descriptions Bits Bit Name Description Reset Access [7:0] VCO_BAND_SELECT Manually programmed VCO band 0x0 R/W
ADDRESS 0x216, RESET: 0x00, NAME: VCO_ALC_TIMEOUT
VCO ALC Timeout Divide
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] RESERVED [3:0] VCO_ALC_TIMEOUT (R/W)
Table 34. VCO_ALC_TIMEOUT Bit Descriptions Bits Bit Name Description Reset Access [7:4] RESERVED Reserved 0x0 R [3:0] VCO_ALC_TIMEOUT VCO ALC timeout divide 0x0 R/W
ADDRESS 0x217, RESET: 0x01, NAME: VCO_MANUAL
Manually Control VCO Bias
Manually Control VCO Core
10: Core#2.01: Core#1.
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [3:0] VCO_BIAS_ADJUST (R/W)
[5:4] VCO_CORE_SELECT (R/W)
Table 35. VCO_MANUAL Bit Descriptions Bits Bit Name Description Reset Access [7:6] RESERVED Reserved 0x0 R [5:4] VCO_CORE_SELECT Manual control of VCO core 0x0 R/W 01: Core 1 10: Core 2 [3:0] VCO_BIAS_ADJUST Manual control of VCO bias 0x1 R/W
ADDRESS 0x219, RESET: 0x13, NAME: ALC
VCO ALC Enable
1: Enable.0: Disable.
0
1
1
1
2
0
3
0
4
1
5
0
6
0
7
0
[7:5] RESERVED [3:0] RESERVED
[4] EN_ALC (R/W)
Table 36. ALC Bit Descriptions Bits Bit Name Description Reset Access [7:5] RESERVED Reserved 0x0 R 4 EN_ACL VCO ALC enable bit 0x1 R/W 0: Disable 1: Enable [3:0] RESERVED Reserved 0x3 R/W
ADMV4420 Data Sheet
Rev. A | Page 52 of 61
ADDRESS 0x21C, RESET: 0x90, NAME: VCO_TIMEOUT1
Main VCO Calibration Timeout
0
01
02
03
04
15
06
07
1
[7:0] VCO_TIMEOUT[7:0] (R/W)
Table 37. VCO_TIMEOUT1 Bit Descriptions Bits Bit Name Description Reset Access [7:0] VCO_TIMEOUT[7:0] Main VCO calibration timeout 0x90 R/W
ADDRESS 0x21D, RESET: 0x01, NAME: VCO_TIMEOUT2
Main VCO Calibration Timeout
0
11
02
03
04
05
06
07
0
[7:2] RESERVED [1:0] VCO_TIMEOUT[9:8] (R/W)
Table 38. VCO_TIMEOUT2 Bit Descriptions Bits Bit Name Description Reset Access [7:2] RESERVED Reserved 0x0 R [1:0] VCO_TIMEOUT[9:8] Main VCO calibration timeout 0x1 R/W
ADDRESS 0x21E, RESET: 0x4B, NAME: VCO_BAND_DIV
VCO Band Select Divide
0
11
12
03
14
05
06
17
0
[7:0] VCO_BAND_DIV (R/W)
Table 39. VCO_BAND_DIV Bit Descriptions Bits Bit Name Description Reset Access [7:0] VCO_BAND_DIV VCO band select divide 0x4B R/W
ADDRESS 0x21F, RESET: 0x18, NAME: VCO_READBACK_SEL
VCO Read Back Select
101: Read Back Low (Zeros)100: Read Back Core.011: Read Back Bias Code.001: Read Back Core & Band.
000:Test)Read Back Checkered Board (Functionality
0
01
02
03
14
15
06
07
0
[7:3] RESERVED [2:0] VCO_READBACK_SEL (R/W)
Table 40. VCO_READBACK_SEL Bit Descriptions Bits Bit Name Description Reset Access [7:3] RESERVED Reserved 0x3 R [2:0] VCO_READBACK_SEL VCO read back select 0x0 R/W 000: Read back checkered board (functionality test) 001: Read back core and band 011: Read back bias code 100: Read back core 101: Read back low (zeros)
Data Sheet ADMV4420
Rev. A | Page 53 of 61
ADDRESS 0x226, RESET: 0x02, NAME: AUTOCAL
Enable VCO Auto Cal and Lock PLL
1: Enable.0: Disable.
0
01
12
03
04
05
06
07
0
[7:2] RESERVED [0] RESERVED
[1] EN_AUTOCAL (R/W)
Table 41. AUTOCAL Bit Descriptions Bits Bit Name Description Reset Access [7:2] RESERVED Reserved 0x0 R 1 EN_AUTOCAL Enable VCO autocalibration and lock PLL 0x1 R/W 0: Disable 1: Enable 0 RESERVED Reserved 0x0 R
ADMV4420 Data Sheet
Rev. A | Page 54 of 61
ADDRESS 0x22C, RESET: 0x07, NAME: CP_STATE
Charge Pump State
3: Normal Operation.2: Force Down.1: Force Up.0: Tri-State (Hi-Z)
0
11
12
13
04
05
06
07
0
[7:2] RESERVED [1:0] CP_STATE (R/W)
Table 42. CP_STATE Bit Descriptions Bits Bit Name Description Reset Access [7:2] RESERVED Reserved 0x1 R [1:0] CP_STATE Charge pump state 0x3 R/W 0: Tristate (high-Z) 1: Force up 2: Force down 3: Normal operation
ADDRESS 0x22D, RESET: 0x01, NAME: CP_BLEED_EN
Bleed CP Current Enable
1: Enable.0: Disable.
0
11
02
03
04
05
06
07
0
[7:1] RESERVED [0] EN_BLEED (R/W)
Table 43. CP_BLEED_EN Bit Descriptions Bits Bit Name Description Reset Access [7:1] RESERVED Reserved 0x0 R 0 EN_BLEED Bleed CP current enable 0x1 R/W 0: Disable 1: Enable
ADDRESS 0x22E, RESET: 0x03, NAME: CP_CURRENT
Main Charge Pump Current
0
11
12
03
04
05
06
07
0
[7:4] RESERVED [3:0] CP_CURRENT (R/W)
Table 44. CP_CURRENT Bit Descriptions Bits Bit Name Description Reset Access [7:4] RESERVED Reserved 0x0 R [3:0] CP_CURRENT Main charge pump current bit 0x3 R/W
ADDRESS 0x22F, RESET: 0x0C, NAME: CP_BLEED
Binary Scaled Bleed Current
0
01
02
13
14
05
06
07
0
[7:0] BICP (R/W)
Table 45. CP_BLEED Bit Descriptions Bits Bit Name Description Reset Access [7:0] BICP Binary scaled bleed current 0xC R/W
Data Sheet ADMV4420
Rev. A | Page 55 of 61
APPLICATIONS INFORMATION EVALUATION BOARD The ADMV4420-EVALZ evaluation board can be used to evaluate the performance of the ADMV4420. The top and cross sectional layout views of the ADMV4420-EVALZ evaluation board are shown in Figure 126 and Figure 127, respectively. The RF transmission lines were designed using a coplanar waveguide (CPWG) model with a line width (W) of 16 mil and 13 mil of ground spacing for a characteristic impedance of 50Ω for the RF input (RFIN) and the external reference input (REF/XTAL1). The line width and ground spacing for the IF output (IFOUT) are 9 mil and 15 mil, respectively. The PCB is made with Rogers 4350B dielectric material, which offers low loss performance, and isola 370HR dielectric material, which achieves the required thickness of the PCB.
The ADMV4420-EVALZ evaluation board layout consists of four layers. Layer 1 contains the charge pump, IF supplies (VPOS3_CP and VPOS4_IF), and the multiplexer output signal (MUXOUT) trace, which are routed together with the peripheral component placements. Layer 2 is arranged to provide the ground plane for the board. Layer 3 includes the VCO (VPOS1_VCO) supply, the PLL (VPOS2_PLL) supply, and digital SPI control signal (CS, SDI, SDO, and SCLK) traces, and Layer 4 includes the chip enable (ENBL0 and ENBL1) traces on the bottom side of the board. Note that on the evaluation board, CS is indicated by CSB. Figure 128 to Figure 130 show the routing details of Layer 2 to Layer 4. For optimal RF and thermal grounding place as many plated through vias as possible around the RF transmission lines, underneath the exposed pad and throughout the entire PCB (See Figure 128).
1699
5-12
3
Figure 126. ADMV4420-EVALZ Evaluation Board Layout, Top View (Layer 1)
ADMV4420 Data Sheet
Rev. A | Page 56 of 61
1oz Cu (1.4mil)
0.5oz Cu (0.7mil) LAYER 4
LAYER 3
LAYER 2
LAYER 1
1oz Cu (1.4mil) – POWER LINES0.5oz Cu (0.7mil) – SIGNAL LINES
10mil ROGERS 4350B
ISOLA 370HR
ISOLA 370HR
0.5oz Cu (0.7mil)0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil)
TOTA
L TH
ICKN
ESS
= 62
mil
W = 16mil FOR 50ΩW = 9mil FOR 75Ω
W = 13mil FOR 50ΩW = 15mil FOR 75Ω
1699
5-11
9
Figure 127. ADMV4420-EVALZ PCB, Cross Sectional View
1699
5-12
0
Figure 128. ADMV4420-EVALZ Evaluation Board, Layer 2
1699
5-12
1
Figure 129. ADMV4420-EVALZ Evaluation Board, Layer 3
Data Sheet ADMV4420
Rev. A | Page 57 of 61
1699
5-12
2
Figure 130. ADMV4420-EVALZ Evaluation Board, Layer 4 (Bottom Side)
Figure 126 shows the ADMV4420-EVALZ evaluation board with component placement. The decoupling capacitors on the LDO decoupling pin and power supply traces to minimize noise effects. The schematic and Pb-free reflow solder profile of the evaluation board are shown in and Figure 2 and Figure 132, respectively.
There are two options to power up the evaluation board. The first option is to apply a 5 V supply to the VPOS1, VPOS2, VPOS3, and VPOS4 test points for the VCO, PLL, CP, and IF blocks (VPOS1_VCO, VPOS2_PLL, VPOS3_CP, and VPOS4_IF pins) respectively, and connect a 0 V supply to one of the GND1, GND2, or GND3 ground test points. In this option, remove the R13, R14, R15, and R16 resistors from the evaluation board. This option allows the user to monitor the currents of each block separately.
The second option to power up the board requires the power supply to be applied through the VCC5P0 test point with the appropriate ground connection. Only the total current of the ADMV4420 can be monitored with this option. After powering up the evaluation board, program the required digital settings for the target configuration through the SDP-S controller board by using the Analysis, Control, Evaluation (ACE) software, which can be downloaded from the Analysis, Control, Evaluation (ACE) product page. See the ADMV4420-EVALZ user guide for details.
There are two different options to apply an external reference input to the ADMV4420, as shown in Figure 132. The required configurations for these options are described in Table 46. When using the Case 1 option, the external reference input is applied through the J2 connector with a signal generator. When using the Case 2 option, the external reference input is provided by the crystal (Y1).
A loop filter circuit generates the VCO control voltage (VTUNE) by applying the CP current output of the ADMV4420 from the charge pump output pin (CPOUT) to obtain the target LO frequency. Figure 131 shows the recommended schematic and Table 47 describes the loop filter components when the phase frequency detector frequency is 50 MHz. Table 48 describes the complete list of materials, which includes the loop filter components. For details about the evaluation board, see the ADMV4420-EVALZ user guide.
Table 46. External Reference Input Configurations Option Component Configuration Case 1 Populate C21. Replace C6 with 1 nF capacitor.
Remove C5 and Y1. Case 2 (Default) C5 = 20 pF, C6 = 20 pF. Do not populate C21.
ADMV4420 Data Sheet
Rev. A | Page 58 of 61
CPOUT VTUNE
AGND
R11
0Ω
R5
1.5kΩR4680Ω
C256800pF
C26220pF
C24470pF
1699
5-12
5
Figure 131. Recommended Integer Mode Loop Filter Schematic
Table 47. Recommended Integer Mode Loop Filter Components for Phase Frequency Detector = 50 MHz Component Value C24 470 pF (0402) C25 6800 pF (0402) C26 220 pF (0402) R4 680 Ω (0402) R5 1.5 kΩ (0402) R11 0 Ω (0402)
Table 48. Bill of Materials for ADMV4420-EVALZ Reference Designator Description C1, C3, C14, C32, C33, C35 Power supply decoupling and LDO decoupling capacitor, 10 μF, 0603
C2, C10, C16, C18, C30 Power supply decoupling and LDO decoupling capacitor, 10 pF, 0402 C5, C6 Crystal loading capacitors C7, C8, C11, C12, C13, C22, C27 Power supply decoupling and LDO decoupling capacitor, 0.1 μF, 0402 C15, C19, C20, C23, C29 Power supply decoupling and LDO decoupling capacitor, 100 pF, 0402) C4, C34 Power supply decoupling and LDO decoupling capacitor, 10 μF, 0402 C9 Power supply decoupling and LDO decoupling capacitor, 4.7 μF, 0402 C17, C21 AC coupling capacitor, 0.01 μF, 0402 C24 Loop filter capacitor, 470 pF, 0402 C25 Loop filter capacitor, 6800 pF, 0402 C26 Loop filter capacitor, 220 pF, 0402 CS, ENBL0, ENBL1, MUXOUT, SCLK, SDI, SDO Test point, yellow
DS1 LED, green GND1, GND2, GND3 Test point, black J1 RF connector, SRI, K type, female J2 RF connector, subminiature version a (SMA), female J3 System demonstration platform (SDP) connector J4 RF connector, F type, female L1 Choke inductor, 51 nH, 0402 M1 Heat sink R1 External reference input matching, 49.9 Ω, 0402 R11, R13, R14, R15, R16 Resistor, 0 Ω, 0402 R19, R29 Resistor, 1 kΩ, 0402 R25, R27 Resistor, pull-down, 100 kΩ, 0402 R4 Resistor, loop filter, 680 Ω, 0402 R5 Resistor, loop filter,1.5 kΩ, 0402 U1 K band downconverter with integrated fractional-N PLL and VCO, ADMV4420 U2 Serial EEPROM, 32-bit VCC5P0, VPOS1, VPOS2, VPOS3, VPOS4 Test point, red Y1 Crystal
Data Sheet ADMV4420
Rev. A | Page 59 of 61
PADDECL5_RF
GNDIFOUT
VPOS4_IFVTUNE
SCLKSDI
3231302928272625
SDO
GND
CPO
UTVP
OS3
_CP
ENBL
1EN
BL0
GND
GND
24 23 22
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VPO
S3
21 20 19 18 17
GNDMUXOUT
XTAL2/NCREF/XTAL1
VPOS2_PLLDECL4_SDMDECL3_PLLVPOS1_VCO
1615
1314
121110
9
DECL
2_VC
O2
DECL
1_VC
O1
GND
GND
RFIN
GND
GND
GND
8765432
43
2
11J4
L1 51nH
1J1
AGND
AGND
AGND
AGND
AGND
A0 A1 A2SD
A5
SCL
WP
1 2 3 6 7
VCC
U28
3P3V
4VSS
AC
DS1
AGND
AGND
C23
100p
FC2
20.
1µF
C18
10pF
C4 10µF
AGND
AGND
C30
10pF
C8 0.1µ
F
C19
100p
FC1
20.
1µF
C34
10µF
C16
10pF
C9 4.7µ
FAG
NDAG
ND
C2 10pF
C14
10µF
AGND
C10
10pF
AGND
C3 10µF
C35
10µF
AGND
C33
10µF
C7 0.1µ
FC1
510
0pF
R16
0Ω
R14
0Ω
AGND
VPO
S1
C32
10µF
C13
0.1µ
FC2
010
0pF
R15
0Ω
VPO
S2
ENBL
1 1
ENBL
0 1
VPO
S4
VCC5
P0
VCC5
P0
AGND
AGND
AGND
U1
54
32
1 AGND
AGND
C520
pFC6 20
pF
GND
13
24
R1 49.9Ω
R27
100kΩ
R25
100kΩ
R26
DNI
C11
0.1µ
F
R29
1kΩ
23
4
AGND
AGND
J3J3
AGND
AGND
3P3V
AGND
AGND
AGND
XTAL
2
XTAL
150
MHz
5
C17
0.01
µF
R19
1kΩ
ADM
V442
0
C21
DNI
0.01
µF
AGND
R13
0Ω
AGND
GND
1G
ND2
GND
3
CASE
1:US
ING
SMA
POPU
LATE
C21
AND
C6=
1nF.
DNIC
5AN
DY1
CASE
2:US
ING
CRYS
TAL
POPU
LATE
C5AN
DC6
DNIC
21
DEFA
ULT
CONF
IG;U
SECA
SE2
C5=
20pF
C6=
20pF
AGND
C27
0.1µ
FC2
910
0pF
C1 10µFVC
C5P0
AGND
VTUN
ECP
OUT
C25
6800
pF
C26
220p
FC2
447
0pF
C28
DNI
R11
0ΩR5 1.5kΩ
R4 680Ω
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1VC
C5P0
R28
DNI
0Ω
TWI_
A0
ENBL
0
GPI
O6_
SDP
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CS C36
DNI
AGND
SDI
C39
DNI
AGND
SDO
C37
DNI
AGND
SCLK
C38
DNI
GPI
O7_
SDP
ENBL
1SC
L_SD
PSD
A_SD
P
16995-126
TWI_
A0
SDA_
SDP
VCC5
P0
VCC5
P0
CS
Figure 132. ADMV4420-EVALZ Evaluation Board Schematic
ADMV4420 Data Sheet
Rev. A | Page 60 of 61
OUTLINE DIMENSIONS
0.500.400.30
09-1
2-20
18-C
1
0.50BSC
TOP VIEW
TOP VIEW
32
916
17
24
25
8
0.05 MAX0.02 NOM
0.20 REF
COPLANARITY0.08
0.300.250.18
5.105.00 SQ4.90
0.800.750.70
0.20 MIN
3.753.60 SQ3.55
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5PKG-
0045
70
P IN 1IN D ICATO R AR E A OP TIO N S(SEE DETAIL A)
DETAIL A(JEDEC 95)
PIN 1INDICATOR
AREA
SEATINGPLANE
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
EXPOSEDPAD
Figure 133. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12)
Dimensions shown in millimeters
07-2
3-20
18-A
NOTES:1. MEASURED FROM THE CENTERLINE OF SPROCKET HOLE TO CENTERLINE OF THE POCKET HOLE2. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE IS ± 0.203. THICKNESS IS APPLICABLE AS MEASURED AT EDGE OF TAPE4. BLACK POLYSTYRENE MATERIAL5. ALLOWABLE CAMBER TO BE 1 mm PER 100 mm IN LENGHT, NON-CUMULATIVE OVER 250 mm6. MEASUREMENT POINT TO BE 0.3 mm FROM BOTTOM POCKET7. SURFACE RESISTIVITY FROM 105 TO 1011 Ω/SQ8. KO MEASUREMENT POINT SHOULD NOT BE REFERED ON POCKET RIDGE
(NOTE 2)
(NOTE 1)
(NOTE 1)
12.3012.0011.70
5.605.505.40
A
A
DIRECTION OF FEED
Ø 1.50 MIN
TOP VIEW
1.60Ø 1.55
1.50
DETAIL A
2.052.001.95
4.104.003.90
1.851.751.65
8.00
0.500.400.30
DETAIL A
R 0.50
R 0.50
3° BSC(NOTE 6)
SECTION A-A(NOTE 8)
(NOTE 3)
0.350.300.25
5.405.305.20
1.351.251.15
Figure 134. 32-Lead Lead Frame Chip Scale Package [LFCSP] Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range
Moisture Sensitivity Level (MSL) Rating2 Package Description Package Option
ADMV4420ACPZ −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 ADMV4420ACPZ-R2 −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 ADMV4420ACPZ-RL7 −40°C to +85°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 ADMV4420-EVALZ 1 Z = RoHS Compliant Part. 2 See Table 2 and Figure 2 for the peak reflow temperature.
Data Sheet ADMV4420
Rev. A | Page 61 of 61
NOTES
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16995-0-4/19(A)
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