Jan 2015 CMOS Transistor 1
CMOS Transistor and Circuits
Instructed by Shmuel WimerEng. School, Bar-Ilan University
Credits: David HarrisHarvey Mudd College
(Some materials copied/taken/adapted from Harris’ lecture notes)
Jan 2015 CMOS Transistor 2
Outline
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
DC characteristics and transfer function
Noise margin
Latchup
Pass transistors
Tristate inverter
Jan 2015 CMOS Transistor 3
Introduction
So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current
– Depends on terminal voltages– Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance– I = C (V/t) → t = (C/I) V– Capacitance and current determine speed
Also explore what a “degraded level” really means
Jan 2015 CMOS Transistor 4
MOS Capacitor
Gate and body form MOS capacitor Operating modes
– Accumulation
– Depletion
– Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion regioninversion region
Jan 2015 CMOS Transistor 5
Terminal Voltages Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals– By convention, source is terminal at lower voltage
– Hence Vds 0
nMOS body is grounded. First assume source is 0 too. Three regions of operation
– Cutoff– Linear– Saturation
Vg
Vs Vd
VgdVgs
Vds+-
+
-
+
-
Jan 2015 CMOS Transistor 6
nMOS Cutoff No channel Ids = 0
+-
Vgs = 0
n+ n+
+-
Vgd
p-type body
b
g
s d
Jan 2015 CMOS Transistor 7
nMOS Linear
Channel forms
Current flows from d to s – e- from s to d
Ids increases with Vds
Similar to linear resistor
+-
Vgs > Vt
n+ n+
+-
Vgd = Vgs
+-
Vgs > Vt
n+ n+
+-
Vgs > Vgd > Vt
Vds = 0
0 < Vds < Vgs-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
Jan 2015 CMOS Transistor 8
nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
+-
Vgs > Vt
n+ n+
+-
Vgd < Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
Jan 2015 CMOS Transistor 9
I-V Characteristics
In Linear region, Ids depends on:
– How much charge is in the channel
– How fast is the charge moving
Jan 2015 CMOS Transistor 10
Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt (Vgc – Vt is the amount of voltage
attracting charge to channel beyond the voltage required for inversion)
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.9)
polysilicongate
Jan 2015 CMOS Transistor 11
Carrier velocity Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = E called mobility
E = Vds/L
Time for carrier to cross channel:– t = L / v
Jan 2015 CMOS Transistor 12
nMOS Linear I-V Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
ox = W
CL
Jan 2015 CMOS Transistor 13
nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
Jan 2015 CMOS Transistor 14
nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
Shockley 1st order transistor models
Jan 2015 CMOS Transistor 15
Example We will be using a 0.18 m process for your project
– tox = 40 Å
– = 180 cm2/V*s
– Vt = 0.4 V
Plot Ids vs. Vds
– Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5 and 1.8V.
– Use W/L = 4/2
14
28
3.9 8.85 10350 155 /
100 10ox
W W WC A V
L L L
Jan 2015 CMOS Transistor 16
Jan 2015 CMOS Transistor 17
pMOS I-V
All doping and voltages are inverted for pMOS
Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
Thus pMOS must be wider to provide same current
– In this class, assume n / p = 2
Jan 2015 CMOS Transistor 18
Jan 2015 CMOS Transistor 19
DC Transfer Characteristics
Vtp – Threshold voltage of p-device
Vtn – Threshold voltage of n-device
Objective: Find the variation of
output voltage Vout for changes in
input voltage Vin.
Jan 2015 CMOS Transistor 20
Jan 2015 CMOS Transistor 21
Recall CMOS device
CMOS inverter characteristics is
derived by solving for Vinn=Vinp and
Idsn=-Idsp
Jan 2015 CMOS Transistor 22
CMOS inverter is divided into five regions of operation
Jan 2015 CMOS Transistor 23
Jan 2015 CMOS Transistor 24
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Jan 2015 CMOS Transistor 26
Jan 2015 CMOS Transistor 27
I-V Characteristics
Make pMOS is wider than nMOS such that n = p
Vgsn5
Vgsn4
Vgsn3
Vgsn2Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
Jan 2015 CMOS Transistor 28
Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Jan 2015 CMOS Transistor 29
Load Line Analysis
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn
Idsp Vout
VDD
Vin
Jan 2015 CMOS Transistor 30
Load Line Summary
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Jan 2015 CMOS Transistor 31
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Jan 2015 CMOS Transistor 32
Operating Regions
Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Jan 2015 CMOS Transistor 33
Beta Ratio
If p / n 1, switching point will move from VDD/2
Called skewed gate Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.51
2
10p
n
0.1p
n
Jan 2015 CMOS Transistor 34
DC Transfer function is symmetric for βn=βp
Jan 2015 CMOS Transistor 35
Jan 2015 CMOS Transistor 36
Noise MarginIt determines the allowable noise at the input gate (0/1)
so the output (1/0) is not affected
Noise margin is closely related to input-output transfer
function
It is derived by driving two inverters connected in series
Jan 2015 CMOS Transistor 37
Jan 2015 CMOS Transistor 38
Jan 2015 CMOS Transistor 39
Impact of skewing transistor size on noise margin
Increasing (decreasing) P / N ratio increases (decreases) the low
noise margin and decreases (increases) the high noise margin
Jan 2015 CMOS Transistor 40
Latchup in CMOS Circuits
Jan 2015 CMOS Transistor 41
Parasitic bipolar transistors are formed by substrate and
source / drain devices
Latchup occurs by establishing a low-resistance paths
connecting VDD to VSS
Latchup may be induced by power supply glitches or
incident radiation
If sufficiently large substrate current flows, VBE of NPN
device increases, and its collector current grows.
This increases the current through RWELL. VBE of PNP
device increases, further increasing substrate current.
Jan 2015 CMOS Transistor 42
Jan 2015 CMOS Transistor 43
If bipolar transistors satisfy βPNP x βNPN > 1, latchup
may occur.
Operation voltage of CMOS circuits should be below
Vlatchup.
Remedies of latchup problem:
1. Reduce Rsubstrate by increasing P doping of substrate by process control.
2. Reducing RWELL and resistance of WELL contacts by process control.
3. Layout techniques: separation of P and N devices, guard rings, many WELL contacts (at design).
Jan 2015 CMOS Transistor 44
Pass Transistors
We have assumed source is grounded What if source > 0?
– e.g. pass transistor passing VDD
Vg = VDD
– If Vs > VDD-Vt => Vgs < Vt
– Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
VDDVDD
Jan 2015 CMOS Transistor 45
Pass Transistor CKTs
As the source can rise to within a threshold voltage of the gate, the
output of several transistors in series is no more degraded than that
of a single transistor.
Jan 2015 CMOS Transistor 46
Transmission Gates
Single pass transistors produce degraded outputs Complementary Transmission gates pass both 0 and
1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
Jan 2015 CMOS Transistor 47
Transmission gate ON resistance as input voltage
sweeps from 0 to 1(VSS to VDD), assuming that output
follows closely.
Jan 2015 CMOS Transistor 48
Tristates
Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN
Jan 2015 CMOS Transistor 49
Nonrestoring Tristate
Transmission gate acts as tristate buffer– Only two transistors– But nonrestoring
• Noise on A is passed on to Y
A Y
EN
EN
Jan 2015 CMOS Transistor 50
Tristate Inverter
Tristate inverter produces restored output– Violates conduction complement rule– Because we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
Jan 2015 CMOS Transistor 51
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1Y
Jan 2015 CMOS Transistor 52
Gate-Level Mux Design
How many transistors are needed? 20
1 0 (too many transistors)Y SD SD
44
D1
D0S Y
4
2
2
2 Y2
D1
D0S
Jan 2015 CMOS Transistor 53
Transmission Gate Mux
Nonrestoring mux uses two transmission gates– Only 4 transistors
S
S
D0
D1
YS
Jan 2015 CMOS Transistor 54
Inverting Mux
Inverting multiplexer– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
Jan 2015 CMOS Transistor 55
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects– Two levels of 2:1 muxes– Or four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
Sizing for Performance
Jan 2015 CMOS Transistor 56
L int extC C C Capacitive load of an inverter.
NMOS and PMOS diffusion + diffusion-gate overlap.intC
extC Fan-out (input gates) + interconnects.
eqR Equivalent gate resistance.
0
extp eq int ext p
int
0.69 1C
t R C C tSC
Propagation delay:
0p eq int0.69t R C Inverter delay loaded only by intrinsic.
int irefC SC eq refR R S S sizing factor.
Jan 2015 CMOS Transistor 57
Intrinsic cap to gate cap ratio ≈1.int gC C
ext gf C C Effective fan-out.
0 0
extp p p
g
1 1C f
t t tC
The delay of an inverter is only a function of the ratio between its external load cap to its input cap
1gC LC1 2 N
In Out
1
0 1
gp p p g L1 1
g
1 , j
j N
j
N N
j j
Ct t t C C
C
Jan 2015 CMOS Transistor 58
p
g
0, 1 1j
tj N
C
imply 1
1
g g
g g
, 2 1j j
j j
C Cf j N
C C
The optimal size of an inverter is the geometric mean of its neighbor drives 1 1g g gj j j
C C C
It implies that same sizing factor f is used for all stages.
Nf FGiven and , and the optimal sizing factor is
1gC LC
The minimum delay through the chain is 0p p 1
N Ft Nt
1L gF C C
Jan 2015 CMOS Transistor 59
What should be the optimal N ?
The derivative by N of yieldsptln
0N
N F FF
N
1 ff e or equivalently having a closed form solution
only for γ=0, a case where the intrinsic self load is ignored and only the fan-out is considered. f e
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