Page 1ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Herve Jaouen1, Bert Huizing2, Jürgen Lorenz3 , Wladek Grabinski4 (presenter)1STMicroelectronics, Crolles, France2NXP, Eindhoven, The Netherlands3Fraunhofer IISB, Erlangen, Germany 4GMC, Commugny, Suisse
ITRS Perspective on the Compact Model Developments
Page 2ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
OUTLINE: ITRS Overview
Objective of the ITRS
Organization of the ITRS
TCAD Challenges
Short Term (until 2019)
Long-Term (until 2026)
ITRS for Compact Modeling
Page 3ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
About the ITRS
The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are:
European Semiconductor Industry Association (ESIA)
Japan Electronics and Information Technology Industries Association (JEITA)
Korean Semiconductor Industry Association (KSIA)
Taiwan Semiconductor Industry Association (TSIA)
United States Semiconductor Industry Association (SIA)
Page 4ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
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The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of the semiconductor industry
Set benchmark/guidelines for R&D: SRA, Work Programs of subsidy frameworks
• US event originally (NTRS), since 1998 world wide effort
Sponsored by 5 Semiconductor Industry Associations (Korea, Taiwan, Japan, Europe, US)
• Pre-competitive; 15 year scope
• Output: biyearly update text; yearly update tables
• Participants: Manufacturers, Suppliers, Academia, Consortia, Gov Labs
Page 5ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB5
Organization of the ITRS
International Roadmap Committee (Executive Committee)
Public Voice of the ITRS
Representatives from 5 regional SIA’s (US, Europe, Japan, Korea, Taiwan)
Provides direction: content, scope, timing, etc
TWGs (Technology Working Groups)
16 (->17) teams of experts in major technology disciplines
3 live meetings a year: US, Asia, Europe
Page 6ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
TWGs (Technology Working Groups)
InterconnectFactory IntegrationAssembly & PackagingEnvironment, Safety, & HealthYield EnhancementMetrologyModeling & SimulationMEMS
System DriversDesignTest & Test EquipmentProcess Integration, Devices, & StructuresRF & A/MS Technologies Emerging Research DevicesEmerging Research MaterialsFront End ProcessesLithography
The working groups, known as TWGs, focus on technologies that are crucial to the design, materials, and manufacture of semiconductors, as well as the factory sciences, process control, metrology, and environmental aspects. The working group members include subject matter experts that represent all sectors of the industry-chip manufacturers, equipment suppliers, and R&D experts.
Page 7ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Technology Modeling and Simulation
Technology Modeling and Simulation covers the region of the semiconductor modeling world called extended TCAD, and it is one of the few enabling methodologies that can reduce development cycle times and costs. Extended TCAD, within the scope of this document, covers the following topical areas:
1.Front end process modeling, simulation of the physical effects of manufacturing steps used to build transistors up to metallization, but excluding lithography
2.Lithography modeling-modeling of the imaging of the mask by the lithography equipment, the photoresist characteristics and processing
3.Device modeling-hierarchy of physically based models for the operational description of active devices
4.Interconnect and integrated passives modeling-the operational response (mechanical, electromagnetic, and thermal properties) of back-end architectures;
5.Circuit element modeling-compact models for active, passive, and parasitic circuit components, and new circuit elements based on new device structures;
6.Package simulation-electrical, mechanical, and thermal modeling of chip packages
7.Materials modeling-simulation tools that predict the physical properties of materials and, in some cases, the subsequent electrical properties
8.Equipment/feature scale modeling-hierarchy of models that allows the simulation of the local influence of the equipment (except lithography) on each point of the wafer, starting from the equipment geometry and settings
9.TCAD for design, manufacturing and yield-the development of additional models and software to enable the use of TCAD to study the impact of inevitable process variations and dopant fluctuations on IC performance and in turn design parameters, manufacturability and the percentage of ICs that are within specifications
10.Numerical methods-all algorithms needed to implement the models developed in any of the other sections, including grid generators, surface-advancement techniques, (parallel) solvers for systems of (partial) differential equations, and optimization routines
Page 8ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
ITRS Overview International Technology Roadmap for Semiconductors ITRS Modeling and Simulation Chapter
Also relevant: Modeling section of „Emerging Research Materials“ Chapter
Page 9ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB9
ITRS: International Technology Roadmap for SemiconductorsTWG: Technology Working Group
Overview of ITRS Process
TWGsIdentifies/Updates
KeyChallenges
TWGsQuantify
Technology Requirement
s
TWGsIdentify
Innovation Areas
Revises & Distributes to Industry Community
CommunityImplementsRoadmap
CommunityInputs to
Contributors
Determine Roadmap Objective
Steering CommitteeIdentifies
TechnologyDrivers
Reach Consensus
(peer review)
Manufacturers, Suppliers, Academia, Consortia, Government Labs
Page 10ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Some essentials on ITRS process Industrial perspective: ITRS governed by semiconductor industry;
contributions from suppliers and research Top-level specifications by IRC and ORTC – e.g. on scaling speed 17 ITWGs derive challenges and requirements for focus and cross-cut
areas – Modeling and Simulation on crosscut ITWG New roadmap each odd year – even years only update of tables Limited publication in July, full publication in December
(Winter meeting and internet)
Modeling and Simulation ITWG Currently 35 members – 17 industry, 8 suppliers, 10 research Discussion starts from analysis of requirements of other ITWGs w.r.t
M&S cross-cut texts Challenges, requiremens and chapter texts derived State-of-the-art vs. requirements labelled in colour codes
ITRS Process Essentials
Page 11ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB11
ITRS Documentation Output
Outline ITRS Executive Summary Overall Roadmap Technology Characteristics 16 Chapters (from 2011: 17)
Each Chapter also contains tables Difficult challenges Near term and long term requirements Accuracy tables for most relevenant FOMs Color coding system to indicate issues
Page 12ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
TCAD ChallengesITRS Short Term (until 2019)
Lithography simulation including EUV• EMF simulation• Resist simulation• Double patterning, EUV, ebeam,
Direct Self-Assembly• Metrology/Characterization• OPC and defects
2011 ITRS draft, Jul/Aug 2011
Front-end process modeling for nanometer structures• Implantation; diffusion/(de-)activation,
segregation; epitaxy• New materials and processes• Defects, damage, stress• 3D meshing
Page 13ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
TCAD Challenges
ITRS Short Term (until 2019)
Integrated modeling of equipment, materials, feature scale processes and influences on device and circuit performance and reliability, including random and systematic variability• Deposition, etching, CMP, ECP, wafer
polishing/thinning
Nanoscale device simulation capability: Methods, models and algorithms• Models and software• Novel device architectures, channel and
gate stack materials• Fluctuations/variations; reliability• Efficient and robust QM-based simulation
2011 ITRS draft, Jul/Aug 2011
Page 14ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
TCAD Challenges
ITRS Short Term (until 2019)
Electro-thermal-mechanical modeling for interconnects and packaging• Co-simulation electro-thermal-mechanical• Feature scale to 3D ICs and packages• Novel materials• Interfaces and thin layers• Variability, reliability
Circuit element and system modeling for high frequency (up to 300 GHz) applications• From device/interconnect to dies and
packages• Novel device architectures• More-than-Moore• Noise, variations, aging, reliability
2011 ITRS draft, Jul/Aug 2011
Page 15ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
ITRS Long-Term (until 2026)
TCAD Challenges
Modeling of chemical, thermomechanical and electrical properties of new materials
Nano-scale modeling for Emerging Research Devices and interconnects including Emerging Research Materials
Optoelectronics modeling
NGL simulation
2011 ITRS draft, Jul/Aug 2011
Page 16ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
ITRS for Compact Modeling
Historically analog simulation drove development of circuit element models. Today and for future needs faster models and improved convergence required
Device models will include many more detailed effects
Parasitic effects, like series resistance, inductance and capacitance
Quantum effects
Leakage (gate, junction, off-state)
Noise, distortion and non-quasi-static effects
Variability at local level or at global level resulting from layout configuration and process variability
Page 17ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
ITRS for Compact Modeling
Compact models for future CMOS generations should model new effects correct, i.e.
mobility-enhanced channels and high-k gate leakage
fully depleted channels, like FD SOI-CMOS, FinFET, multy gate FET
non-classical, new architecture CMOS devices
ultra short channels (L <10nm)
ballistic effects
quantum mechanical interactions
RF models extend to the 100 GHz range
process compact models (PCM) based on pre-calibrated TCAD simulations
local process variability and statistics via SPICE parameters
Page 18ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Non-CMOS Compact Modeling
For non-CMOS devices the number of options in ITRS chapters is still very large, requiring huge efforts in the modeling domain
• For bipolar devices, models will be extended towards extreme HBTs, either in SiGe(C) or in III-V materials
• RF power devices
• For memories models are needed for new memory concepts
• FRAM
• MRAM
• Phase-change memories
Page 19ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Compact Modeling at Circuit Level
Support heterogeneous integration
• handle multiple interactions between circuit models, building block models, interconnect, chip, dies and packages
• importance of interconnect modeling increases with the stronger contribution to circuit delays and cross talk
• interactions between neighboring devices modeled on the basis of the layout including substrate coupling
• predictive DC and RF reliability based on device level compact models
• device level ESD reliability modeling for future processes
• SPICE and behavioral modeling of the failure mechanisms and elementary devices degradation
Page 20ITRS Perspective on the Compact Model Developments
MOS-AK Workshop, Helsinki, Sept. 16, 2011
© NXP / STM / Fraunhofer IISB
Summary:
ITRS Overview
Objective of the ITRS
Organization of the ITRS
TCAD Challenges
ITRS for Compact Modeling
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