Introduction to Digital Design using Verilog
EE370Ashish Bhatia
What is Verilog?
models digital hardwareto what extent?
models digital hardwarecombinatoricsequential
use for synthesizing digital hardwarefpgaasic
modeling digital hardware
to what extent?
A CMOS inverter has nMOS transistor with L = 10 units, W = 20 units, Kn = 400 and pMOS transistor with L = 10 units, W=40 units, Kp = 400
Can Verilog model this?
A CS amplifier has gain = -10 and cut-off freq = 20 MHz
Can Verilog model this?
A spice generated netlist of resistors and capacitors
Can Verilog model this?
An inverter with Tr = 1 ns, Tf = 500 ps and Tp = 800 ps
Can Verilog model this?
Can Verilog model this?
A B F
0 0 0
0 1 1
1 0 1
1 1 0
Can Verilog model this?
Q(n) X Q(n+1)
0 0 0
0 1 1
1 0 1
1 1 0
modeling digital hardware
combinatoricsequential
consider combinatoric first
NOT Gate
module Not ( input wire x, output wire y);
assign y = ~x;
endmodule
NOT Gate
module Not ( input wire x, output wire y);
assign y = ~x;
endmodule
NOT Gate
module Not ( input wire x, output wire y);
assign y = ~x;
endmodule
NOT Gate
module Not ( input wire x, output wire y);
assign y = ~x;
endmodule
NOT Gate (of parallel bus)
module Not ( input wire [7:0] x, output wire [7:0] y);
assign y = ~x;
endmodule
AND Gate
module And ( input wire x, input wire y output wire z);
assign z = x&y;
endmodule
do Nand, Nor, Xor, Or gate yourself
Hardware Abstraction
behavioralhighest level of abstractionfarthest from hardwareclosest to ideas (thinking)
dataflowhardware described in boolean (logic)
combinatoricsequential
structuralhardware described in terms of fundamental gates
Let us analyze 1-bit adder for all three cases
Behavioral design (adder)
module adder_b(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
assign {carry, sum} = in1 + in2; endmodule
Behavioral design (adder)
module adder_b(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
assign {carry, sum} = in1 + in2; endmodule
Addition is a high level construct Verilog compiler will generate the code for addition
DataFlow Design (adder)
module adder_d(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
assign sum = in1 ^ in2;assign carry = in1 & in2; endmodule
DataFlow Design (adder)
module adder_d(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
assign sum = in1 ^ in2;assign carry = in1 & in2; endmodule
Boolean logic - more fundamental construct than addition
Structural Design (adder)
module adder_s(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
and g0(carry,in1,in2);
xor g1(sum,in1,in2);
endmodule
Structural Design (adder)
module adder_s(in1, in2, sum, carry);
input wire in1, in2;output wire sum, carry;
and g0(carry,in1,in2);
xor g1(sum,in1,in2);
endmoduleAssuming and and xor gates are available
Structural Design (adder)
module adder_s(in1, in2, sum, carry);//Assume only NAND gates are available
input wire in1, in2;output wire sum, carry;wire signal1, signal2, signal3;//intermediate wires
nand n0 (signal1, in1, in2);nand n1 (carry, signal1, signal1);
nand n2 (signal2, in1, signal1);nand n3 (signal3, in2, signal1);nand n4 (sum, signal2, signal3);endmodule
Assuming only nand gates are available
what about sequential elements?
let us consider D F/F
D F/F
module D_FF ( input wire clk, input wire d, output reg q ); always @(posedge clk) begin q <= #2 d; endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q ); always @(posedge clk) begin q <= #2 d; endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q //output need to be a register to hold the value ); always @(posedge clk) begin q <= #2 d;
endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q //output need to be a register to hold the value ); always @(posedge clk) begin //posedge triggered q <= #2 d;
endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q //output need to be a register to hold the value ); always @(posedge clk) begin //posedge triggered q <= #2 d; //2 units (propagation delay)
endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q //output need to be a register to hold the value ); always @(posedge clk) begin //posedge triggered q <= #2 d; //2 units (propagation delay) //non-blocking assignment
endendmodule
D F/F
module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, output reg q //output need to be a register to hold the value ); always @(posedge clk) begin //posedge triggered q <= #2 d; //2 units (propagation delay) //non-blocking assignment //assuming setup and hold are not //violated endendmodule
D F/F (with reset)module D_FF ( input wire clk, //every sequential circuit element has a trigger input wire d, input wire rst, output reg q ); always @(posedge clk or posedge rst) begin //posedge triggered if(rst == 1) q <= #2 1'b0; else q <= #2 d; //2 units (propagation delay) //non-blocking assignment //assuming setup and hold are not //violated endendmodule
Will "reg" always correspond to reg in hardware?
Consider 2x1 MUX
2x1 MUX
module MUX_2_1 ( input wire a, input wire b, input wire sel output reg op);
always @(sel or a or b) begin if(sel) op = b; else op = a;end endmodule
2x1 MUX
module MUX_2_1 ( input wire a, input wire b, input wire sel output reg op);
always @(sel or a or b) begin if(sel) op = b; else op = a;end endmodule
op will be implemented as wire only if 1) a and b both are in sensitivity list of always block 2) all possible cases are covered in if-else or switch
2x1 MUX
module MUX_2_1 ( input wire a, input wire b, input wire sel output reg op);
always @(sel or a or b) begin if(sel) op = b; else op = a;end endmodule
op will be implemented as wire only if 1) a and b both are in sensitivity list of always block 2) all possible cases are covered in if-else or switch
This is behavioral model of 2-1 MUXwhat will be dataflow model?
2x1 MUX (data flow model)
module MUX_2_1 ( input wire a, input wire b, input wire sel output wire op);
assign op = sel?b:a; endmodule
4x1 MUX (data flow model)
module MUX_2_1 ( input wire a, input wire b, input wire c, input wire d, input wire sel[1:0], output wire op);
assign op = (sel[1]==1)?(sel[0]==1?d:c):(sel[0]==1?b:a); endmodule
A 32 operation ALU is like 32-1 MUX, try writing ternary operations for that :)
4x1 MUX - behavioral model
module MUX_2_1 ( input wire a, input wire b, input wire c, input wire d, input wire sel[1:0], output reg op);
always @(sel or a or b or c or d) begin case(sel) 2'b00: op = a; 2'b01: op = b; 2'b10: op = c; 2'b11: op = d; endendmodule
is wire (in verilog) always synthesized as wire?
yes
is reg (in verilog) always synthesized as reg?
most of the times yes, but in some case if design permits,
optimization occurs
Designing Test Benches
why?
Consider XOR Gate
module XOR(input wire A, input wire B, output wire X); assign X = A^B; endmodule
XOR Test Bench
module TB_XOR(); reg A, B; reg clk; wire X; XOR xor1(.A(A), .B(B), .X(X)); initial begin clk = 0; end initial begin forever clk = #5 ~clk; //clk with period = 10 end
always @(posedge clk) begin A<=0; B<=0; #5; A<=0; B<=1; #5; A<=1; B<=0; #5; A<=1; B<=1; end
endmodule
Unsynthesizable Constructs
reg clk;
intial begin clk <= 0; forever clk = #10 ~clk; end
Unsynthesizable Constructs
reg a = 1'bx;reg b = 1'bz;
x or X (uninitialized state)z or Z (high impedance state) - can be synthesized using tri-state buffers but not directly
If they cannot be synthesizd why do we need them?
Remember verilog is for1) Simulation2) FPGA based design3) ASIC based design
Simulationunsynthesizable constructs are needed for simulation
FPGA vs ASIC
Some constructs are synthesizable on FPGA but not ASIClike initial block requires explicit hardware implementation on ASIC
Timing failures In case of FPGA, compiler ensures proper floorplan to minimize such failuresIn ASIC, floorplan is manual, timing faliures are more probable
Preprocessors
`define DELAY 2 //macro definition just like in C`include mylib.v //include just like in C`ifdef ENABLE_MY_CODE//my code goes here`endif
b <= `DELAY a;
Misc
Open Drain Configall inputs low => output is highotherwise output is lowwor is use to model not of open drain config similarly wand models not of open collector config
Good Reference Book: Verilog HDL by Palnitkar
Top Related