Introduction to Computing Systems and Programming
Digital Logic Structures
Introduction to Computing Systems and Programming Fall 1384, 2
Logical Operations
0, 1 in a binary value can represent logical TRUE = 1, or FALSE = 0.
We can perform logical operations on binary bits or a set of binary bits, also known as Boolean algebra.
The basic operations are AND, OR, NOT
Introduction to Computing Systems and Programming Fall 1384, 3
Basic Logic OperationsTruth Tables of Basic Operations
Equivalent Notations Not A = A’ = A A and B = A.B = AB = A intersection B A or B = A+B = AB = A union B
ANDA B A.B0 0 00 1 01 0 01 1 1
ORA B A+B0 0 00 1 11 0 11 1 1
NOTA A'0 11 0
Introduction to Computing Systems and Programming Fall 1384, 4
More Logic Operations
XOR and XNORXOR
A B AB0 0 00 1 11 0 11 1 0
XNORA B (AB)’0 0 10 1 01 0 01 1 1
Introduction to Computing Systems and Programming Fall 1384, 5
Logical Operations Example AND
useful for clearing bits AND with zero = 0 AND with one = no change
OR useful for setting bits
OR with zero = no change OR with one = 1
NOT unary operation -- one argument flips every bit
11000101AND 00001111
00000101
11000101OR 00001111
11001111
NOT 1100010100111010
Introduction to Computing Systems and Programming Fall 1384, 6
Simple Switch Circuit Switch Switch openopen::
– No current through circuitNo current through circuit– Light is Light is offoff– VVoutout is is +2.9V+2.9V
Switch Switch closedclosed::– Short circuit across switchShort circuit across switch– Current flowsCurrent flows– Light is Light is onon– VVoutout is is 0V0VSwitch-based circuits can easily represent two states:
on/off, open/closed, voltage/no voltage.
Introduction to Computing Systems and Programming Fall 1384, 7
Transistor
Microprocessors contain millions of transistors Intel Pentium II: 7 million Intel Pentium III: 28 million Intel Pentium 4: 54 million
Logically, each transistor acts as a switch
Introduction to Computing Systems and Programming Fall 1384, 8
N-type MOS Transistor
Gate = 1
Gate = 0Terminal #2 must beconnected to GND (0V).
MOS = Metal Oxide SemiconductorMOS = Metal Oxide Semiconductor– two types: N-type and P-typetwo types: N-type and P-type
N-typeN-type– when Gate has when Gate has positivepositive voltage, voltage,
short circuit between #1 and #2short circuit between #1 and #2(switch (switch closedclosed))
– when Gate has when Gate has zerozero voltage, voltage,open circuit between #1 and #2open circuit between #1 and #2(switch (switch openopen))
Introduction to Computing Systems and Programming Fall 1384, 9
P-type MOS Transistor
P-type is complementary to N-type when Gate has positive voltage,
open circuit between #1 and #2(switch open)
when Gate has zero voltage,short circuit between #1 and #2(switch closed)
Gate = 1
Gate = 0Terminal #1 must beconnected to +2.9V.
Introduction to Computing Systems and Programming Fall 1384, 10
CMOS Circuit
Complementary MOS Uses both N-type and P-type MOS transistors
P-type Attached to + voltage Pulls output voltage UP when input is zero
N-type Attached to GND Pulls output voltage DOWN when input is one
For all inputs, make sure that output is either connected to GND or to +, but not both!
Introduction to Computing Systems and Programming Fall 1384, 11
Inverter (NOT Gate)
In Out0 V 2.9 V
2.9 V 0 V
In Out0 11 0
Truth table
Introduction to Computing Systems and Programming Fall 1384, 12
NOR Gate
A B C0 0 10 1 01 0 01 1 0
C
A
B
2.9 v
0 v0 v
P
N
P
N
Introduction to Computing Systems and Programming Fall 1384, 13
NOR Gate Operation2.9 v
0 v0 v
P
N
P
0 v
0 v2.9 v
2.9 v
0 v0 v
N
P
N
2.9 v
2.9 v
0 v
N
0 v0 v
P
N
P
N
2.9 v
2.9 v
0 v
0 v
P
Introduction to Computing Systems and Programming Fall 1384, 14
OR Gate
Add inverter to NOR.
A B C0 0 00 1 11 0 11 1 1
Introduction to Computing Systems and Programming Fall 1384, 15
NAND Gate (AND-NOT)
A B C0 0 10 1 11 0 11 1 0
Introduction to Computing Systems and Programming Fall 1384, 16
AND Gate
Add inverter to NAND.
A B C0 0 00 1 01 0 01 1 1
Introduction to Computing Systems and Programming Fall 1384, 17
Basic Logic Gates
Introduction to Computing Systems and Programming Fall 1384, 18
More Inputs AND/OR can take any number of inputs.
AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR.
Can implement with multiple two-input gates,or with single CMOS circuit.
Introduction to Computing Systems and Programming Fall 1384, 19
Logical Completeness
Can implement ANY truth table with AND, OR, NOT.A B C D0 0 0 00 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1. AND combinations that yield a "1" in the truth table.
2. OR the resultsof the AND gates.
Introduction to Computing Systems and Programming Fall 1384, 20
Practice
Implement the following truth table.
A B C0 0 00 1 11 0 11 1 0
A B C0 0 10 1 01 0 01 1 1
Introduction to Computing Systems and Programming Fall 1384, 21
Summary MOS transistors are used as switches to implement
logic functions. N-type: connect to GND, turn on (with 1) to pull down to 0 P-type: connect to +2.9V, turn on (with 0) to pull up to 1
Basic gates: NOT, NOR, NAND Logic functions are usually expressed with AND, OR, and NOT
Properties of logic gates Completeness
can implement any truth table with AND, OR, NOT DeMorgan's Law
convert AND to OR by inverting inputs and output
Introduction to Computing Systems and Programming Fall 1384, 22
Logic Structures
We've already seen how to implement truth tablesusing AND, OR, and NOT -- an example of combinational logic.
Combinational Logic Circuit output depends only on the current inputs stateless
Sequential Logic Circuit output depends on the sequence of inputs (past and
present) stores information (state) from past inputs
Introduction to Computing Systems and Programming Fall 1384, 23
Decoder
n inputs, 2n outputs exactly one output is
1 for each possible input pattern
1, iff A,B is 00AB
1, iff A,B is 01
1, iff A,B is 10
1, iff A,B is 11
i = 0
i = 1
i = 2
i = 3
Introduction to Computing Systems and Programming Fall 1384, 24
Multiplexer
n-bit selector and 2n inputs, one output output equals one of the inputs, depending on
selector
4-to-1 MUX
Introduction to Computing Systems and Programming Fall 1384, 25
Half Adder
Half Adder 2 inputs 2 outputs: sum and carry
A B C S0 0 0 00 1 0 11 0 0 11 1 1 0
Introduction to Computing Systems and Programming Fall 1384, 26
Full Adder
Add two bits and carry-in,produce one-bit sum and carry-out.
A B Cin S Cout
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Introduction to Computing Systems and Programming Fall 1384, 27
Four-bit Adder
Introduction to Computing Systems and Programming Fall 1384, 28
Combinational vs. Sequential Combinational Circuit
always gives the same output for a given set of inputs ex: adder always generates sum and carry,
regardless of previous inputs Sequential Circuit
stores information output depends on stored information (state) plus input
so a given input might produce different outputs,depending on the stored information
example: ticket counter advances when you push the button output depends on previous state
useful for building “memory” elements and “state machines”
Introduction to Computing Systems and Programming Fall 1384, 29
R-S Latch
If both R and S are one, out could be either zero or one. “quiescent” state -- holds its previous value note: if a is 1, b is 0, and vice versa
1
0
1
1
1
1
0
0
1
1
0
0
1
1
Introduction to Computing Systems and Programming Fall 1384, 30
Clearing the R-S latch
Suppose we start with output = 1, then change R to zero.
Output changes to zero.1
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1
Introduction to Computing Systems and Programming Fall 1384, 31
Setting the R-S Latch
Suppose we start with output = 0, then change S to zero.
Output changes to one.
1
1
0
0
1
10
1
1
1
0
0
Introduction to Computing Systems and Programming Fall 1384, 32
R-S Latch R = S = 1
hold current value in latch S = 0, R=1
set value to 1 R = 0, S = 1
set value to 0
R = S = 0 both outputs equal one final state determined by electrical properties of gates Don’t do it!
Introduction to Computing Systems and Programming Fall 1384, 33
Gated D-Latch
Two inputs: D (data) and WE (write enable) when WE = 1, latch is set to value of D
S = NOT(D), R = D when WE = 0, latch holds previous value
S = R = 1
Introduction to Computing Systems and Programming Fall 1384, 34
Register
A register stores a multi-bit value. We use a collection of D-latches, all controlled by a
common WE. When WE=1, n-bit value D is written to register.
Introduction to Computing Systems and Programming Fall 1384, 35
Memory
Now that we know how to store bits, we can build a memory – a logical k × m array of stored bits.
•••
k = 2n
locations
m bits
Address Space:number of locations(usually a power of 2)
Addressability:number of bits per location(e.g., byte-addressable)
Introduction to Computing Systems and Programming Fall 1384, 36
Address Space
n bits allow the addressing of 2n memory locations. Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations). If each location holds 1 byte then the memory is 16MB. If each location holds one word (32 bits = 4 bytes) then it
is 64 MB.
Introduction to Computing Systems and Programming Fall 1384, 37
Addressability Computers are either byte or word addressable - i.e. each memory
location holds either 8 bits (1 byte), or a full standard word for that computer (typically 32 bits, though now many machines use 64 bit words).
Normally, a whole word is written and read at a time: If the computer is word addressable, this is simply a single address location. If the computer is byte addressable, and uses a multi-byte word, then the
word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines).
Introduction to Computing Systems and Programming Fall 1384, 38
Memory Structure
Each bit is a gated D-latch
Each location consists of w bits (here w = 1) w = 8 if the memory is byte
addressable
Addressing n locations means log2n address
bits (here 2 bits => 4 locations) decoder circuit translates
address into 1 of n addresses
WE
A[1:0] D
Introduction to Computing Systems and Programming Fall 1384, 39
A 2222 by 3 bits memory: by 3 bits memory:•two address lines: A[1:0]two address lines: A[1:0]•three data lines: D[2:0]three data lines: D[2:0]•one control line: WEone control line: WE
One gated One gated D-latchD-latch
Memory example
Introduction to Computing Systems and Programming Fall 1384, 40
22 x 3 Memory
addressdecoder
word select word WEaddress
writeenable
input bits
output bits
Introduction to Computing Systems and Programming Fall 1384, 41
Memory details
This is a not the way actual memory is implemented. fewer transistors, much more dense, relies on electrical properties
But the logical structure is very similar. address decoder word select line word write enable
Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM)
fast, maintains data without power Dynamic RAM (DRAM)
slower but denser, bit storage must be periodically refreshed
Introduction to Computing Systems and Programming Fall 1384, 42
Memory building blocks
–Building an 8K byte memory using chips that are 2K by 4 bits.Building an 8K byte memory using chips that are 2K by 4 bits.
CS = chip select:when set, it enables the addressing, reading and writing of that chip.
This is an 8KBbyte addressable
memory
decoder
CS CS
CS CS
CS CS
CS CS
A10-A0
A12-A11
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits
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