ABSTRACT
CHAPTER-1
The relentless growth of Internet and communication technologies has made the extensive use of
images unavoidable. The specific characteristics of image like high transmission rate with
limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard
algorithms not suitable for image encryption. In order to overcome these limitations for real time
applications, design of new algorithms that require less computational power while preserving a
sufficient level of security has always been a subject of interest.
This project proposes an algorithm based on AES Key Expansion in which the encryption
process is a bit wise exclusive or operation of a set of image pixels along with the a 128 bit key
which changes for every set of pixels . The keys to be used are generated independently at the
sender and receiver side based on AES Key Expansion process hence the initial key is alone
shared rather than sharing the whole set of keys. The algorithm has been experimented with
standard bench mark images proposed in USC-SIPI database. Experimental results and security
analysis of the proposed algorithm shows that the proposed algorithm offers good resistance
against brute force attack, key sensitivity tests and statistical crypt analysis.
INTRODUCTION
A digital image is defined as a two dimensional rectangle array. The elements of this array are
denoted as pixels. Each pixel has an intensity value (digital number) and a location address (row,
column). Many applications like military image databases, confidential video conferencing,
personal online photograph albums, medical imaging system, Cable TV requires a fast and
efficient way of encrypting images for storage as well as in transmission. Many encryption
methods have been proposed in literature, and the most common way to protect large multimedia
files is by using conventional encryption techniques. Private Key bulk encryption algorithms,
such as Triple DES or Blowfish, are not suitable for transmission of large amounts of data. Due
to the complexity of their internal structure, they are not particularly fast in terms of execution
speed and cannot be applied for images in the real time scenario. Also traditional cryptographic
techniques such as DES, AES, etc cannot be applied to images due to the intrinsic properties of
images such as bulk data capacity, redundancy and high correlation among pixels. Image
encryption algorithms can become an integral part of the image delivery process if they aim
towards efficiency and at the same time preserve the highest security level.
SOLUTIONS FOR THE PROBLEM:
A wide variety of cryptographic algorithms for images have been proposed in the literature.
Kuo proposed an image encryption method known as image distortion which obtains the
encrypted image by adding the phase spectra of the plain image with those of the key
image. This method is safe but no image compression is considered.
N.G.Bourbakis have presented a new methodology which performs both lossless
compression and encryption of binary and gray-scale images. The compression and
encryption schemes are based on SCAN patterns generated by the SCAN methodology.
The SCAN is a formal language-based two-dimensional spatial- accessing methodology
which can efficiently specify and generate a wide range of scanning paths or space filling
curves.
Chin – Chen Chang have used the popular image compression technique, vector
quantization to design an efficient cryptosystem. The images are first decomposed into
vectors and the sequentially encoded vector by vector.
Fridrich demonstrated the construction of a symmetric block encryption technique based
on two dimensional standard chaotic map.
Scharinger designed a kolmogorov flow based image encryption technique in which the
whole image is taken as a block and permuted through a key controlled chaotic system. A
shift register pseudo random generator is also used to provide confusion in data.
Mitra have used a random combinational of bit, pixel, and block permutations. The
permutation of bits decreases the perceptual information, whereas the permutation of
pixels and blocks produce high level security.
PROPOSED ALGORITHM
The algorithm is based on AES Key Expansion technique. Now let us see the AES Key
Expansion in detail.
A. AES Key Expansion
Pseudo code for AES Key Expansion: The key-expansion routine creates round keys word by
word, where a word is an array of four bytes. The routine creates 4x(Nr+1) words.
Where Nr is the number of rounds. The process is as follows
The first four words are made from the cipher key (initial key). The key is considered as
an array of 16 bytes (k0 to k15). The first four bytes (k0 to k3) become w0, the four bytes
(k4 to k7) become w1, and so on.
The rest of the words (wi for i=4 to 43) are made as follows
• If (i mod 4)!=0, wi=wi-1 XOR wi-4.
• If (i mod 4)=0, wi=t XOR wi-4.
Here t is a temporary word result of applying SubByte transformation and rotate word on wi-1
and XORing the result with a round constant.
B. Modifications in AES KeyExpansion
Certain changes made in the above key expansion process improves the encryption quality, and
also increases the avalanche effect in the resulting cipher image. The changes are
The initial key is not only expanded for 10 rounds as in AES process, but it is expanded
based on the number of pixels in the image.
The Rcon value is not constant instead it is being formed from the initial key itself, this
improves the avalanche effect.
Both the s-box and Inverse s-box are used for the Key Expansion process which improves
non-linearity in the expanded key and also improves the encryption quality.
We do not use the S-box and Inverse S-box as such for this algorithm; instead we
perform
some circular shift on the boxes based on the initial key this improves the key sensitivity.
The above changes in the algorithm can be represented as
1) Key Expansion for the image:
Let P be the plain gray-level image of size mxn. So we have m*n pixels in the image. We
encrypt a set of 16 pixels (128 bits) using 2 round keys. So the number of keys to Encrypt the
whole image N=2*{(m*n)/16}.
2) Formation of Rcon values:
Rcon [0]=key[12:15]; Rcon [1]=key[4:7];
Rcon [2]=key[0:3]; Rcon [3]=key[8:11];
3) Using Inverse S-Box for key expansion:
The ‘temp’ value used in the algorithm is formed as
temp = SubWord(RotWord(temp)) InvSubWord(Rcon[i/4]);
Where InvSubWord: InverseSubByte transformation table
value
4) Shifting of S-box and Inverse S-box:
Sbox_offset = sum(key[0:15])mod256;
Inv_Sbox_offset = (sum(key[0:15])*mean(key[0:15]))mod256;
The initial key is represented as blocks key[0],key[1],..,key[15]. Where each block is 8bitslong
(8*16=128 bits).
C. Steps Involved
1. Key selection:
The sender and receiver agree upon a 128 bit key. This key is used for encryption and decryption
of images. It is a symmetric key encryption technique, so they must share this key in a secure
manner. The key is represented as blocks k[0],k[1]...k[15]. Where each block is 8bits long
(8*16=128 bits).
2. Generation of Multiple keys:
The sender and receiver can now independently generate the keys required for the process using
the above explained Modified AES Key Expansion technique. This is a one time process; these
expanded keys can be used for future communications any number of times till they change their
initial key value.
3. Encryption:
Encryption is done in spans, where we process 16 pixels in each span. We perform two XOR
operations and a SubBytes Transformation for each set of pixels. Since we perform two XOR
operations using our expanded key for every set of pixels it is impossible to get the key from
plain image and cipher image, and to improve the non linearity we also use the s-box values used
in AES.
4. Decryption:
The decryption process is similar as encryption, but we use Inverse SubByte Transformation and
lso the order of XOR operation using the expanded key is reversed .
Block diagram for encryption and decryption process
Chapter-2
IMAGE ENCRYPTION
An image can be encrypted by combining MATLAB with the encoder. Each pixel in an image is
represented by 8 bits,ie 1 byte.Using MATLAB convert the pixel values into bytes.These byte
values are then used as input to the encoder. The 128 bit encoder then convert this byte into
corresponding encoded byte. The encoded bit values are then converted into decimal values for
pixels. Repeat this operation for each pixels (Figure 10).
ENCRYPTION is a common technique to uphold image security. Image and
video encryption have applications in various fields including internet communication,
multimedia systems, medical imaging, Tele-medicine and military communication. Many image-
protection techniques are using vector quantization (VQ) as encryption technique (Chang et al.,
2001; Chen and Chang, 2001). In Chang et al. (2001), VQ decomposes an image into vectors,
which are then encoded and decoded vector-by-vector.
Alternatively, Chen and Chang (2001) use VQ to divide desired images for
encryption into a large number of shadows that are guaranteed undetectable to illegal users.
Image and text cryptography has been achieved using chaotic algorithms (Fridrich, 1997; Sobhy
and Shehata, equations. Both image and text data are encrypted 2001, Haojiang, Yisheng,
Shuyun and Dequn Li 2005). A symmetric block encryption algorithm creates a chaotic map
(Fridrich, 1997) for permuting and diffusing image data. For thorough encryption, the chaotic
map is applied to the image, iteratively, multiple times.
The chaotic algorithm of Sobhy and Shehata (2001) is based on the Lorenz
system of successfully, but knowledge of the system allows devising an optimization routine that
discovers the key by output minimization. Phase encoding techniques exist for encrypting image
data (Zhang and Karim, 1999; Park et al., 2001). Color image data is regarded in Zhang and
Karim (1999), where a double-phase technique is utilized. Color images are encrypted from an
indexed image and thereby decrypted back to its color format. The work of Wu and Kuo (2001)
describes selective encryption based on a digital coefficients table. It was shown its limitation
due to a less intelligible recovered image.
Color and gray-scale images were considered in Koga and Yamamoto (1998),
where a lattice-based extension to Visual Secret Sharing Scheme (VSSS) (Naor and Shamir,
1994) was developed. A hashing approach to image cryptography is taken in Venkatesan et al.
(2000); wavelet representations of images are obtained, and a new randomized strategy for
hashing is introduced. Several cryptosystems exist like as data encryption [3], steganography
[14], digital signature (Aloka Sinha, Kehar Singh, 2003) and SCAN (S.S. Maniccama, N.G.
Bourbakis 2004) have been proposed to increase the security of secret images. However, one
common defect of these techniques is their policy of centralized storage, in that an entire
protected image is usually maintained in a single information carrier.
If a cracker detects an abnormality in the information carrier in which the
protected image resides, he or she may intercept it, attempt to decipher the secret inside or
simply ruin the entire information carrier (and once the information carrier is destroyed, the
secret image is also lost forever). Another method is to encrypt image data, e.g., using DES
(Data Encryption Standard). DES, however, is very complicated and involves large
computations. A software DES implementation is not fast enough to process the vast amount of
data generated by multimedia applications and a hardware DES implementation (a set-top box)
adds extra costs both to broadcasters and to receivers.
In order to tackle these problems systems based on advanced encryption standard
(AES) where proposed. AES is very fast symmetric block algorithm especially by hardware
implementation [7, 11, 12, 15]. The AES algorithm is used in some applications that require fast
processing such as smart cards, cellular phones and image-video encryption. However, a central
consideration for any cryptographic system is its susceptibility to possible attacks against the
encryption algorithm such as statistical attack, differential attack, and various brute attacks.
Block cipher symmetric algorithms; allow different ciphering mode [17].
Electronic CodeBook (ECB) is the most obvious mode; ciphered blocks is a
function of the corresponding plaintext block, the algorithm and the secret key. Consequently a
same data will be ciphered to the same value; which is the main security weakness of that mode
[1, 15, 19, 20]. CBC mode provides improved security since each encrypted block depends also
on the previous plaintext block. Its use proves limited in an encryption image due to the
processing time. There are two levels of security for digital image encryption: low-level security
encryption and highlevel security encryption.
In low-level security encryption, the encrypted image has degraded visual quality
compared to that of the original one, but the content of the image is still visible and
understandable to the viewers. In the high-level security case, the content is completely
scrambled and the image just looks like random noise. In this case, the image is not
understandable at all to the viewers. This paper proposes new encryption schemes as a
modification of AES algorithm.
The modification is done by adding a key stream generator, such as (A5/1, W7),
to the AES image encryption algorithm in order to increase the image security and in turn the
encryption performance. This paper is organized as follows. Section 2, gives a brief survey of
AES techniques. Section 3 evaluates the performance of AES algorithm with respect to the
security in image encryption. Section 4 announces the proposed encryption algorithm and
describes its hardware implementation. Experimental results are shown in section 5, and discuss
the efficiency of the proposed algorithm scheme.
Advance Encryption Standard
The Advance Encryption Standard (AES) was announced by the Nation Institute of Standard and
Technology (NIST) in 2001.It is a symmetric block cipher that is intended to replace DES as the
approved standard for a wide range of applications, such as highspeed web-server, wireless
communication, low-power smart card and RFID. In the same year, the cipher block modes of
operation were also published to fit AES more easily for such a wide range of applications.
Basically, AES includes three main processes, KeyExpansion (key expansion), Encryption, and
Decryption. The 128-bit plaintext and key are added (xored) to be encrypted to become a
ciphertext which looks just like a random number and hides the plaintext. However, by using the
same key, the ciphertext can be decrypted back to plaintext as shown in Figure .
Figure 1. Encryption and Decryption of AES.
Accordingly, a cipher image, obtained from image encryption included many random numbers
expressed in a two-dimensional array, becomes a kind of random noise shown in Figure
However, sometimes a pattern is appeared in cipher image if plain image has the identical color
at the related area, or the shape of a picture is not hided if it contains many identical colors as
shown in Figure. Those cipher images having patterns apparently are not random enough.
Figure 2. The plain image and ECB cipher image.
However, sometimes a pattern is appeared in cipher image if plain image has an identical color at
the related area, or the shape of a picture is not hided if it contains many identical colors as
shown in Figure. Those cipher images having patterns apparently are not random enough
In case of text message encryption, the same random number repeated if the plaintext is identical
in encryption as shown in Fig. Yet, the repeated cipher text is rather uneasy to be found if it is
not displayed with the multiple of 128-bit widths. Besides, identical texts in a message are
always the rare case.
2.1 The AES Algorithm
The AES Algorithm is a symmetric-key cipher, in which both the sender and the receiver use a
single key for encryption and decryption. The data block length is fixed to be 128 bits, while the
length can be 128,192,or 256 bits. In addition, the AES algorithm is an iterative algorithm. Each
iteration can be called a round, and the total number of rounds is 10,12, or 14, when key length is
128,192, or 256, respectively. The 128 bit data block is divided into 16 bytes. These bytes are
mapped to a 4x4 array called the State, and all the internal operations of the AES algorithm are
performed on the State.
Table 1: AES parameters
3. DESIGN OF 128BIT ENCODER
3.1 Methodology
The encryption process is iterative in nature.Each iterations are known as rounds.For each round
128 bit input data and 128 bit key is required.That is,need 4 words of key in one round.So the
input key must be expanded to the required number of words,which depends upon the number of
rounds.The output of each round serves as input of next stage.In AES system,same secret key is
used for both encryption and decryption.So it provides simplicity in design.
Figure:2 Detailed Block diagram of encryption part
In the encryption of the AES algorithm(Figure), each round except the final round consists of our
transformations:
i. SubBytes: Operates in each byte of the State independently. Each byte is substituted by
corresponding byte in the S-box.
ii. ShiftRow: Cyclically shifts the rows of the State over different offsets.
iii. MixColumn: In this operation the column of the State are considered as polynomials over
GF(2⁸) and are multiplied with a fixed polynomial. The MixColumn component doesnot operate
in the last round of the algorithm.
iv. AddRoundKey: Involves bit-wise XOR operation.
3.2 Design steps
3.2.1 State array
The input to the encryption algorithm is a single 128-bit block .This block is copied into the State
array, which is a square matrix of bytes. State array is modified at each stage of encryption.
Similarly, the 128 bit key is depicted as a square matrix of bytes. The ordering of bytes within a
matrix is by column. 3.2.2 Key expansion Key expansion is an important for both encryption and
decryption.
Figure:3 Key Expansion algorithm
The AES key expansion algorithm takes as input a 4-word (16 bytes) key and produces a linear
array of 44 words (176 bytes).This is sufficient to provide a 4-word round key for the initial Add
Round Key stage and each of the 10 rounds of the cipher.
The following pseudocode describes the expansion:
Table 2: Pseudocode for KeyExpansio
KeyExpansion(byte key[16],word[44]){
word tempfor (i=0; i<4; i++)
w[i]=(key[4*i],key[4*i+1],key[4*i+2],key[4*i+3]);for
(i=4; i<44; i++){
temp =w[i-1];if(i mod 4 = 0)
temp=SubWord(RotWord(temp)) xor Rcon[i/4];w[i] = w[i-4] xor temp
}}
The key is copied into the first 4 words of the expanded key.The reminder of the expanded key is
filled in 4 words at a time.Each added word w[i] depends on the immediately preceding word,
w[i-1] and the word four positions back, w[i-4]. In three out of four cases, a simple XOR is used.
For a word whose position in the w array is a multiple of 4, a more complex function g is used.
1. RotWord performs a one-byte circular left shift on a word.This means that an input word
[b0,b1,b2,b3] is transformed into [b1,b2,b3,b0].
2. SubWord performs a byte substitution on each byte of its input word,using the S-box.
3. The result of step 1 and step2 is XORed with a round constant Rcon[j].
The round constant is a word in which the three rightmost bytes are always 0.Thus the effect of
XOR of a word with Rcon is to only perform an XOR on the left byte of the word. The round
constant is for each round and is defined as Rcon[j] = ( RC[j],0,0,0), with RC[1]=1;
C[j]=2*RC[j-1] and with multiplication over the field GF(2^8).
The values of RC[j] in hexadecimal are :
Table 3: Round constant values
3.2.3 AddRound Key
The 128 bits of State array are bitwise XORed with the 128 bits of the round key(4 words of the
expanded key).The operation is viewed as a columnwise operation between the 4 bytes of the
State array column and one word of the round key (Figure 4).
Figure 4: XOR operation between State and key word
3.2.4 Substitute Bytes
AES defines a 16 x 16 matrix of byte values, called an S-box, that contains a permutation of all
possible 256 8-bit values. Each byte of State array is mapped into a new byte in the following
way: The leftmost 4 bits of the byte are used as a row value and the leftmost 4 bits are used as a
column value. These row and column values serve as indexes into the S-box to select a unique
8-bit output value (Figure 5).
Figure 5: Sub-byte Operation
3.2.5 Shift Rows
The first row of State array is not altered. For the second row , a 1-byte circular left shift is
performed. For the third row,a 2- byte circular left shift is performed. For the third row, a 3-
byte circular left shift is performed
Figure 6: Shifting operation
3.2.6 Mix Column
It operates on each column individually.Each byte of a column is mapped into a new value that is
a function of all four bytes in the column.The transformation can be defined by following matrix
multiplication on State array.
[02 03 01 01 [ S(0,0) S(0,1) S(0,2) S(0,3)
01 02 03 01 S(1,0) S(1,1) S(1,2) S(1,3)
01 01 02 03 S(2,0) S(2,1) S(2,2) S(2,3)
03 01 01 02 ] S(3,0) S(3,1) S(3,2) S(3,3)]
[S’(0,0) S’(0,1) S’(0,2) S’(0,3)
S’(1,0) S’(1,1) S’(1,2) S’(1,3)
S’(2,0) S’(2,1) S’(2,2) S’(2,3)
S’(3,0) S’(3,1) S’(3,2) S’(3,3)] -- (1)
Each element in the product matrix is the sum of products of elements of one row and one
column.In this case,individual additions and multiplications are performed in GF(2^8).The Mix
Column transformation on a single column j(0 <= j <= 3) of State
array can be expressed as
S’(0,j) = (2.s(0,j)) xor (3.s(1,j)) xor (s(2,j)) xor (s(3,j))
S’(1,j) = ( s(0,j)) xor (2.s(1,j)) xor (3.s(2,j)) xor (s(3,j))
S’(2,j) = (s(0,j)) xor (s(1,j)) xor (2.s(2,j)) xor (3.s(3,j))
S’(3,j) = (3.s(0,j)) xor (s(1,j)) xor (s(2,j)) xor (2.s(3,j)) -- (2)
IV. MODIFIED AES ALGORITHM
The new image encryption scheme is a modified AES algorithm. It is formed by the AES
algorithm and a key stream generator as shown in Fig. 6.The latter has two different forms;
(i) A5/1 key stream generator and (ii) W7 key stream generator.
Fig. 6 New AES image encryption scheme
1) A5/1 Key Stream Generator
The A5/1 cipher is composed by three Linear Feedback Shift Registers (LFSRs); R1, R2, and R3
of length 19, 22, and 23 bits, respectively. Each LFSR is shifted, using clock cycles that are
determined by a majority function. The majority function uses three bits; C1, C2, and C3. The 64
bits of the key map to the LFSR’s initial state as: R1(19 bits): x19 + x5 + x2 + x + 1 , R2(22 bits):
x22 + x +1,R3(23 bits): x23 + x15 + x2 + x + 1. At each clock cycle, after the initialization phase,
the last bits of each LFSR are XORed to produce one output bit [2, 8]. 2) W7 Key Stream
Generator The W7 algorithm is a byte-wide, synchronous stream cipher optimized for efficient
hardware implementation at very high data rates. It is a symmetric key algorithm supporting key
lengths of 128 bits. W7 cipher contains eight similar models; C1, C2,…., C8. Each model
consists of three LFSR’s and one majority function. W7 architecture is composed by a control
unit and a function unit [8]. The function unit is responsible of the key stream generation. The
proposed architecture for the hardware implementation of one cell is presented in Fig. 7. Each
cell has two inputs and one output. The one input is the key and it is the same for all the cells.
The other input consists of control signals. Finally, the output is of 1-bit long. The outputs of
each cell form the key stream byte.
Fig. 7 W7 key stream generator proposed architecture
CHAPTER-3
INTRODUCTION OF VLSI
Very-large-scale integration (VLSI) is the process of creating integrated circuits by
combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s
when complex semiconductor and communication technologies were being developed. The
microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have
increased in complexity into the hundreds of millions of transistors.
Overview
The first semiconductor chips held one transistor each. Subsequent advances added more
and more transistors, and, as a consequence, more individual functions or systems were
integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten
diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic
gates on a single device. Now known retrospectively as "small-scale integration" (SSI),
improvements in technique led to devices with hundreds of logic gates, known as large-scale
integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved
far past this mark and today's microprocessors have many millions of gates and hundreds of
millions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale
integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge
number of gates and transistors available on common devices has rendered such fine distinctions
moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.
Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are
VLSI or better.
As of early 2008, billion-transistor processors are commercially available, an
example of which is Intel's Montecito Itanium chip. This is expected to become more
commonplace as semiconductor fabrication moves from the current generation of 65 nm
processes to the next 45 nm generations (while experiencing new challenges such as increased
variation across process corners). Another notable example is NVIDIA’s 280 series GPU.
This microprocessor is unique in the fact that its 1.4 Billion transistor count,
capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor
count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices,
use extensive design automation and automated logic synthesis to lay out the transistors,
enabling higher levels of complexity in the resulting logic functionality. Certain high-
performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the
highest efficiency (sometimes by bending or breaking established design rules to obtain the last
bit of performance by trading stability).
What is VLSI?
VLSI stands for "Very Large Scale Integration". This is the field
which involves packing more and more logic devices into smaller and smaller areas.
VLSI
1. Simply we say Integrated circuit is many transistors on one chip.
2. Design/manufacturing of extremely small, complex circuitry using modified
semiconductor material
3. Integrated circuit (IC) may contain millions of transistors, each a few mm in size
4. Applications wide ranging: most electronic logic devices
History of Scale Integration
late 40s Transistor invented at Bell Labs
late 50s First IC (JK-FF by Jack Kilby at TI)
early 60s Small Scale Integration (SSI)
10s of transistors on a chip
late 60s Medium Scale Integration (MSI)
100s of transistors on a chip
early 70s Large Scale Integration (LSI)
1000s of transistor on a chip
early 80s VLSI 10,000s of transistors on a
chip (later 100,000s & now 1,000,000s)
Ultra LSI is sometimes used for 1,000,000s
SSI - Small-Scale Integration (0-102)
MSI - Medium-Scale Integration (102-103)
LSI - Large-Scale Integration (103-105)
VLSI - Very Large-Scale Integration (105-107)
ULSI - Ultra Large-Scale Integration (>=107)
Advantages of ICs over discrete components
While we will concentrate on integrated circuits , the properties of
integrated circuits-what we can and cannot efficiently put in an integrated circuit-largely
determine the architecture of the entire system. Integrated circuits improve system characteristics
in several critical ways. ICs have three key advantages over digital circuits built from discrete
components:
Size. Integrated circuits are much smaller-both transistors and wires are shrunk to
micrometer sizes, compared to the millimeter or centimeter scales of discrete
components. Small size leads to advantages in speed and power consumption,
since smaller components have smaller parasitic resistances, capacitances, and
inductances.
Speed. Signals can be switched between logic 0 and logic 1 much quicker within
a chip than they can between chips. Communication within a chip can occur
hundreds of times faster than communication between chips on a printed circuit
board. The high speed of circuits on-chip is due to their small size-smaller
components and wires have smaller parasitic capacitances to slow down the
signal.
Power consumption. Logic operations within a chip also take much less power.
Once again, lower power consumption is largely due to the small size of circuits
on the chip-smaller parasitic capacitances and resistances require less power to
drive them.
VLSI and systems
These advantages of integrated circuits translate into advantages at the system level:
Smaller physical size. Smallness is often an advantage in itself-consider
portable televisions or handheld cellular telephones.
Lower power consumption. Replacing a handful of standard parts with a
single chip reduces total power consumption. Reducing power consumption
has a ripple effect on the rest of the system: a smaller, cheaper power supply
can be used; since less power consumption means less heat, a fan may no
longer be necessary; a simpler cabinet with less shielding for electromagnetic
shielding may be feasible, too.
Reduced cost. Reducing the number of components, the power supply
requirements, cabinet costs, and so on, will inevitably reduce system cost. The
ripple effect of integration is such that the cost of a system built from custom
ICs can be less, even though the individual ICs cost more than the standard
parts they replace.
Understanding why integrated circuit technology has such profound influence on the design of
digital systems requires understanding both the technology of IC manufacturing and the
economics of ICs and digital systems.
Applications
Electronic system in cars.
Digital electronics control VCRs
Transaction processing system, ATM
Personal computers and Workstations
Medical electronic systems.
Etc….
Applications of VLSI
Electronic systems now perform a wide variety of tasks in daily life. Electronic
systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or
by other means; electronics are usually smaller, more flexible, and easier to service. In other
cases electronic systems have created totally new applications. Electronic systems perform a
variety of tasks, some of them visible, some more hidden:
Personal entertainment systems such as portable MP3 players and DVD
players perform sophisticated algorithms with remarkably little energy.
Electronic systems in cars operate stereo systems and displays; they also
control fuel injection systems, adjust suspensions to varying terrain, and
perform the control functions required for anti-lock braking (ABS) systems.
Digital electronics compress and decompress video, even at high-definition
data rates, on-the-fly in consumer electronics.
Low-cost terminals for Web browsing still require sophisticated electronics,
despite their dedicated function.
Personal computers and workstations provide word-processing, financial
analysis, and games. Computers include both central processing units (CPUs)
and special-purpose hardware for disk access, faster screen display, etc.
Medical electronic systems measure bodily functions and perform complex
processing algorithms to warn about unusual conditions. The availability of
these complex systems, far from overwhelming consumers, only creates
demand for even more complex systems.
The growing sophistication of applications continually pushes the design and manufacturing of
integrated circuits and electronic systems to new levels of complexity. And perhaps the most
amazing characteristic of this collection of systems is its variety-as systems become more
complex, we build not a few general-purpose computers but an ever wider range of special-
purpose systems. Our ability to do so is a testament to our growing mastery of both integrated
circuit manufacturing and design, but the increasing demands of customers continue to test the
limits of design and manufacturing
ASIC
An Application-Specific Integrated Circuit (ASIC) is an integrated circuit
(IC) customized for a particular use, rather than intended for general-purpose use. For example, a
chip designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry
standard integrated circuits, like the 7400 or the 4000 series, are application specific standard
products (ASSPs).
As feature sizes have shrunk and design tools improved over the years, the
maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates
to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks
including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often
termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description
language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.
Field-programmable gate arrays (FPGA) are the modern-day technology for building a
breadboard or prototype from standard parts; programmable logic blocks and programmable
interconnects allow the same FPGA to be used in many different applications. For smaller
designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC
design even in production.
1. An application-specific integrated circuit (ASIC) is an integrated circuit (IC)
customized for a particular use, rather than intended for general-purpose use.
2. A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC
3. Structured ASIC’s are used mainly for mid-volume level designs
4. The design task for structured ASIC’s is to map the circuit into a fixed arrangement
of known cells
CHAPTER-4
XILINX
Migrating Projects from Previous ISE Software Releases
When you open a project file from a previous release, the ISE® software prompts you to migrate
your project. If you click Backup and Migrate or Migrate Only, the software automatically
converts your project file to the current release. If you click Cancel, the software does not
convert your project and, instead, opens Project Navigator with no project loaded.
Note: After you convert your project, you cannot open it in previous versions of the ISE
software, such as the ISE 11 software. However, you can optionally create a backup of the
original project as part of project migration, as described below.
To Migrate a Project
1. In the ISE 12 Project Navigator, select File > Open Project.
2. In the Open Project dialog box, select the .xise file to migrate.
Note You may need to change the extension in the Files of type field to display .npl
(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.
3. In the dialog box that appears, select Backup and Migrate or Migrate Only.
4. The ISE software automatically converts your project to an ISE 12 project.
Note If you chose to Backup and Migrate, a backup of the original project is created at
project_name_ise12migration.zip.
5. Implement the design using the new version of the software.
Note Implementation status is not maintained after migration.
Properties
For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12
Properties Conversion.
IP Modules
If your design includes IP modules that were created using CORE Generator™ software or
Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required to
update the core. However, if the core netlist is present and you do not need to modify the core,
updates are not required and the existing netlist is used during implementation.
Obsolete Source File Types
The ISE 12 software supports all of the source types that were supported in the ISE 11
software.
If you are working with projects from previous releases, state diagram source files (.dia), ABEL
source files (.abl), and test bench waveform source files (.tbw) are no longer supported. For state
diagram and ABEL source files, the software finds an associated HDL file and adds it to the
project, if possible. For test bench waveform files, the software automatically converts the TBW
file to an HDL test bench and adds it to the project. To convert a TBW file after project
migration, see Converting a TBW File to an HDL Test Bench.
Migrating Projects from Previous ISE Software Releases
When you open a project file from a previous release, the ISE® software prompts you to migrate
your project. If you click Backup and Migrate or Migrate Only, the software automatically
converts your project file to the current release. If you click Cancel, the software does not
convert your project and, instead, opens Project Navigator with no project loaded.
Note After you convert your project, you cannot open it in previous versions of the ISE
software, such as the ISE 11 software. However, you can optionally create a backup of the
original project as part of project migration, as described below.
To Migrate a Project
1. In the ISE 12 Project Navigator, select File > Open Project.
2. In the Open Project dialog box, select the .xise file to migrate.
Note You may need to change the extension in the Files of type field to display .npl
(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.
3. In the dialog box that appears, select Backup and Migrate or Migrate Only.
4. The ISE software automatically converts your project to an ISE 12 project.
Note If you chose to Backup and Migrate, a backup of the original project is created at
project_name_ise12migration.zip.
5. Implement the design using the new version of the software.
Note Implementation status is not maintained after migration.
Properties
For information on properties that have changed in the ISE 12 software, see ISE 11 to ISE 12
Properties Conversion.
IP Modules
If your design includes IP modules that were created using CORE Generator™ software or
Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required to
update the core. However, if the core netlist is present and you do not need to modify the core,
updates are not required and the existing netlist is used during implementation.
Obsolete Source File Types
The ISE 12 software supports all of the source types that were supported in the ISE 11
software.
If you are working with projects from previous releases, state diagram source files (.dia), ABEL
source files (.abl), and test bench waveform source files (.tbw) are no longer supported. For state
diagram and ABEL source files, the software finds an associated HDL file and adds it to the
project, if possible. For test bench waveform files, the software automatically converts the TBW
file to an HDL test bench and adds it to the project. To convert a TBW file after project
migration, see Converting a TBW File to an HDL Test Bench.
Using ISE Example Projects
To help familiarize you with the ISE® software and with FPGA and CPLD designs, a set of
example designs is provided with Project Navigator. The examples show different design
techniques and source types, such as VHDL, Verilog, schematic, or EDIF, and include different
constraints and IP.
To Open an Example
1. Select File > Open Example.
2. In the Open Example dialog box, select the Sample Project Name.
Note To help you choose an example project, the Project Description field describes
each project. In addition, you can scroll to the right to see additional fields, which
provide details about the project.
3. In the Destination Directory field, enter a directory name or browse to the
directory.
4. Click OK.
The example project is extracted to the directory you specified in the Destination Directory
field and is automatically opened in Project Navigator. You can then run processes on the
example project and save any changes.
Note If you modified an example project and want to overwrite it with the original example
project, select File > Open Example, select the Sample Project Name, and specify the same
Destination Directory you originally used. In the dialog box that appears, select Overwrite the
existing project and click OK.
Creating a Project
Project Navigator allows you to manage your FPGA and CPLD designs using an ISE® project,
which contains all the source files and settings specific to your design. First, you must create a
project and then, add source files, and set process properties. After you create a project, you can
run processes to implement, constrain, and analyze your design. Project Navigator provides a
wizard to help you create a project as follows.
Note If you prefer, you can create a project using the New Project dialog box instead of the
New Project Wizard. To use the New Project dialog box, deselect the Use New Project wizard
option in the ISE General page of the Preferences dialog box.
To Create a Project
1. Select File > New Project to launch the New Project Wizard.
2. In the Create New Project page, set the name, location, and project type, and
click Next.
3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page,
select the input and constraint file for the project, and click Next.
4. In the Project Settings page, set the device and project properties, and click
Next.
5. In the Project Summary page, review the information, and click Finish to
create the project.
Project Navigator creates the project file (project_name.xise) in the directory you specified.
After you add source files to the project, the files appear in the Hierarchy pane of the Design
panel. Project Navigator manages your project based on the design properties (top-level
module type, device type, synthesis tool, and language) you selected when you created the
project. It organizes all the parts of your design and keeps track of the processes necessary to
move the design from design entry through implementation to programming the targeted
Xilinx® device.
Note For information on changing design properties, see Changing Design Properties.
You can now perform any of the following:
Create new source files for your project.
Add existing source files to your project.
Run processes on your source files.
Modify process properties.
Creating a Copy of a Project
You can create a copy of a project to experiment with different source options and
implementations. Depending on your needs, the design source files for the copied project and
their location can vary as follows:
Design source files are left in their existing location, and the copied project
points to these files.
Design source files, including generated files, are copied and placed in a
specified directory.
Design source files, excluding generated files, are copied and placed in a
specified directory.
Copied projects are the same as other projects in both form and function. For example, you can
do the following with copied projects:
Open the copied project using the File > Open Project menu command.
View, modify, and implement the copied project.
Use the Project Browser to view key summary data for the copied project and then,
open the copied project for further analysis and implementation, as described in Using
the Project Browser.
Note Alternatively, you can create an archive of your project, which puts all of the project
contents into a ZIP file. Archived projects must be unzipped before being opened in Project
Navigator. For information on archiving, see Creating a Project Archive.
To Create a Copy of a Project
1. Select File > Copy Project.
2. In the Copy Project dialog box, enter the Name for the copy.
Note The name for the copy can be the same as the name for the project, as long as you
specify a different location.
3. Enter a directory Location to store the copied project.
4. Optionally, enter a Working directory.
By default, this is blank, and the working directory is the same as the project directory.
However, you can specify a working directory if you want to keep your ISE® project
file (.xise extension) separate from your working area.
5. Optionally, enter a Description for the copy.
The description can be useful in identifying key traits of the project for reference later.
6. In the Source options area, do the following:
o Select one of the following options:
o Keep sources in their current locations - to leave the design source files
in their existing location.
If you select this option, the copied project points to the files in their
existing location. If you edit the files in the copied project, the changes
also appear in the original project, because the source files are shared
between the two projects.
o Copy sources to the new location - to make a copy of all the design
source files and place them in the specified Location directory.
If you select this option, the copied project points to the files in the specified
directory. If you edit the files in the copied project, the changes do not appear in
the original project, because the source files are not shared between the two
projects.
o Optionally, select Copy files from Macro Search Path directories to copy files
from the directories you specify in the Macro Search Path property in the Translate Properties
dialog box. All files from the specified directories are copied, not just the files used by the
design.
Note If you added a netlist source file directly to the project as described in
Working with Netlist-Based IP, the file is automatically copied as part of Copy
Project because it is a project source file. Adding netlist source files to the project
is the preferred method for incorporating netlist modules into your design,
because the files are managed automatically by Project Navigator.
o Optionally, click Copy Additional Files to copy files that were not included in
the original project. In the Copy Additional Files dialog box, use the Add Files and Remove
Files buttons to update the list of additional files to copy. Additional files are copied to the
copied project location after all other files are copied.
7. To exclude generated files from the copy, such as implementation results and
reports, select Exclude generated files from the copy.
When you select this option, the copied project opens in a state in which processes have
not yet been run.
8. To automatically open the copy after creating it, select Open the copied project.
Note By default, this option is disabled. If you leave this option disabled, the original
project remains open after the copy is made.
Click OK.
Creating a Project Archive
A project archive is a single, compressed ZIP file with a .zip extension. By default, it contains all
project files, source files, and generated files, including the following:
User-added sources and associated files
Remote sources
Verilog `include files
Files in the macro search path
Generated files
Non-project files
To Archive a Project
1. Select Project > Archive.
2. In the Project Archive dialog box, specify a file name and directory for the ZIP
file.
3. Optionally, select Exclude generated files from the archive to exclude
generated files and non-project files from the archive.
4. Click OK.
A ZIP file is created in the specified directory. To open the archived project, you must first
unzip the ZIP file, and then, you can open the project.
Note Sources that reside outside of the project directory are copied into a remote_sources
subdirectory in the project archive. When the archive is unzipped and opened, you must either
specify the location of these files in the remote_sources subdirectory for the unzipped project, or
manually copy the sources into their original location.
CHAPTER-4
INTRODUCTION TO VERILOG HDL
What is HDL
A typical Hardware Description Language (HDL) supports a mixed-level description in
which gate and netlist constructs are used with functional descriptions. This mixed-level
capability enables you to describe system architectures at a high level of abstraction, then
incrementally refine a design’s detailed gate-level implementation.
HDL descriptions offer the following advantages:
• We can verify design functionality early in the design process. A design written as an HDL
description can be simulated immediately. Design simulation at this high level — at the
gate-level before implementation — allows you to evaluate architectural and design decisions.
• An HDL description is more easily read and understood than a netlist or schematic description.
HDL descriptions provide technology-independent documentation of a design and its
functionality. Because the initial HDL design description is technology independent, you
can use it again to generate the design in a different technology, without having to
translate it from the original technology.
• Large designs are easier to handle with HDL tools than schematic tools.
Verilog Overview :
Introduction
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description
Language is a language used to describe a digital system, for example, a microprocessor or
a memory or a simple flip-flop. This just means that, by using a HDL one can describe any
hardware (digital ) at any level.
Verilog provides both behavioral and structural language structures. These structures allow
expressing design objects at high and low levels of abstraction. Designing hardware with a
language such as Verilog allows using software concepts such as parallel processing and
object-oriented programming. Verilog has a syntax similar to C and Pascal.
Design Styles
Verilog like any other hardware description language permits the designers to create a design in
either Bottom-up or Top-down methodology.
Bottom-Up Design
The traditional method of electronic design is bottom-up. Each design is performed at the
gate-level using the standard gates. With increasing complexity of new designs this
approach is nearly impossible to maintain. New systems consist of ASIC or
microprocessors with a complexity of thousands of transistors. These traditional bottom-up
designs have to give way to new structural, hierarchical design methods. Without these new
design practices it would be impossible to handle the new complexity.
Top-Down Design
The desired design-style of all designers is the top-down design. A real top-down design
allows early testing, easy change of different technologies, a structured system design and
offers many other advantages. But it is very difficult to follow a pure top-down design. Due
to this fact most designs are mix of both the methods, implementing some key elements of
both design styles.
Complex circuits are commonly designed using the top down methodology. Various
specification levels are required at each stage of the design process.
Abstraction Levels of Verilog
Verilog supports a design at many different levels of abstraction. Three of them are very
important:
Behavioral level
Register-Transfer Level
Gate Level
Behavioral level
This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is
sequential, that means it consists of a set of instructions that are executed one after the other.
Functions, Tasks and Always blocks are the main elements. There is no regard to the structural
realization of the design.
Register-Transfer Level
Designs using the Register-Transfer Level specify the characteristics of a circuit by operations
and the transfer of data between the registers. An explicit clock is used. RTL design contains
exact timing possibility; operations are scheduled to occur at certain times. Modern definition
of a RTL code is "Any code that is synthesizable is called RTL code".
Gate Level
Within the logic level the characteristics of a system are described by logical links and
their timing properties. All signals are discrete signals. They can only have definite logical
values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR,
NOT etc gates). Using gate level modeling might not be a good idea for any level of logic
design. Gate level code is generated by tools like synthesis tools and this Netlist is used for gate
level simulation and for backend.
vlsi design flow
Introduction
Design is the most significant human endeavor: It is the channel through which creativity is
realized. Design determines our every activity as well as the results of those activities; thus it
includes planning, problem solving, and producing. Typically, the term "design" is applied
to the planning and production of artifacts such as jewelry, houses, cars, and cities. Design is
also found in problem-solving tasks such as mathematical proofs and games. Finally,
design is found in pure planning activities such as making a law or throwing a party.
More specific to the matter at hand is the design of manufacturable artifacts. This
activity uses all facets of design because, in addition to the specification of a producible
object, it requires the planning of that object's manufacture, and much problem solving
along the way. Design of objects usually begins with a rough sketch that is refined by
adding precise dimensions. The final plan must not only specify exact sizes, but also include a
scheme for ordering the steps of production. Additional considerations depend on the
production environment; for example, whether one or ten million will be made, and how
precisely the manufacturing environment can be controlled.
A semiconductor process technology is a method by which working circuits can be
manufactured from designed specifications. There are many such technologies, each of
which creates a different environment or style of design.
FUTURESCOPE AND CONCLUSIONS
FUTURESCOPE:
CONCLUSIONS:
The work proposed in this paper makes use of AES Key Expansion which is used to generate
multiple non-linear keys for the encryption process. Based on the experimental results it can be
observed that the proposed algorithm offers high encryption quality with minimal memory
requirement and computational time. The key sensitivity and key space of the algorithm is very
high which makes it resistant towards Brute force attack and statistical cryptanalysis of original
and encrypted images. The time taken for encryption is relatively less in comparison with the
algorithms proposed in the literature. The above mentioned features make the algorithm suitable
for image encryption in real time applications.
REFERENCES
[1] C.J.Kuo, Novel image Encryption Technique and its application in progressive transmission.
Journal of Electron imaging 24 1993 pp 345-351.
[2] N.J.Bourbakis , C.Alexopoulos, Picture data encryption using SCAN patterns. Pattern
Recognition 256 1992 pp567 -581.
[3] Chin-Chen Chang, Min-Shian Hwang, Tung-Shou Chen, “A new encryption algorithm for
image cryptosystems”, The Journal of Systems and Software 58 (2001), 83-91.
[4] Fridrich Jiri, Symmetric ciphers based on two dimensional chaotic maps, Int. J. Bifurcat
Chaos 8 (1998) (6), pp. 1259–1284.
[5] J. Scharinger, Fast encryption of image data using chaotic Kolmogrov flow, J. Electronic Eng
7 (1998) (2), pp. 318–325.
[6] Socek, S. Li, S. S. Magliveras, and B. Furht, Enhanced 1-D chaotic key-based algorithm for
image encryption, IEEE/CreateNet SecureComm, pp. 406-408, September 5-9,2005
[7] Mitra, Y. V. Subba Rao, and S. R. M. Prasanna, A new image encryption approach using
combinational permutation techniques, International Journal of Computer Science, vol. 1,
no. 2 , pp. 1306- 4428, 2006.
[8] R. Ramasamy, et al., A new algorithm for encryption/decryption for field applications,
Computer Standards & Interfaces doi:10.1016/j.csi.2008.09.037,2008.
[9] J.C Yen, J.I Guo, A new image encryption algorithm and its VLSI architecture in
proceedings of IEEE workshop signal processing ystems, 1999 pp 430-437.
[10] N.K.Pareek, Vinod Patidar, K.K.Sud Image Encryption using chaotic logistic map image
and Vision Computing ,24 pp 926-934 2006
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