III V ili h t i t tiIII-V silicon heterogeneous integrationDries Van Thourhout – IPRM ‘08, Paris
InP/InGaAsPepitaxial layer stack
Si WG
DVS-BCB
SiO2 200nm
III V ili h t i t tiIII-V silicon heterogeneous integrationDries Van Thourhout – IPRM ‘08, Paris
InP/InGaAsPepitaxial layer stack
Si WG
DVS-BCB
SiO2 200nm
1. Silicon photonics is great !!!2. But we still need InP
3 III-V silicon integration3. III-V silicon integration4. Devices
AcknowledgementsPh t i R h GPhotonics Research Group
III-V silicon integration: G. Roelkens, J. Van Campenhout, J. Brouckaert, L. Liu
Silicon ProcessingW. Bogaerts, P. Dumon, S. Selvarajan, R. Baets
EU IST-PICMOS teamJ.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)C. Seassal, P. Rojo-Romeo, P. Regreny, P. Viktorovitch (INL) (processing, epitaxy)R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)C. Lagahe, B. Aspar (TRACIT) (planarization)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
III V ili h t i t tiIII-V silicon heterogeneous integration
InP/InGaAsPepitaxial layer stack
Si WG
DVS-BCB
SiO2 200nm
1. Silicon photonics is great !!!2. But we still need InP
3 III V silicon integration3. III-V silicon integration4. Devices
Silicon photonicsthe solution to all our problems?
Width (500nm) x Height (220nm)
… the solution to all our problems Transparent at telecom wavelengths (1.3 µm, 1.55 µm)High refractive index contrast ultra-compact circuits
?
SiO (1 2 )High refractive index contrast ultra compact circuits“Compatible” with CMOS-processing
Highest quality processesHigh yield high repeatability
SiO2 (1-2 µm)
SiliconHigh yield, high repeatability
Integration with electronicsPattern definition: DUV litho`
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Photonic wiringLow loss bends <0.3dB excess loss for splitters
0°]
0 09dB/90°
d lo
ss [d
B/9
0
0.08
0.06
0.09dB/90
Exce
ss b
end 0.04
0.02
00.004dB/90°0.01dB/90°
0.027dB/90°
E 1 2 3 4 5Radius [um]
97% transmission in crossings
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
(b)
97% transmission in crossings
Wavelength dependent devices
-5
0FSR
-15
-10
mis
sion
[dB
]
1 2 3 4 8 16 1
30
-25
-20
tran
sm
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
1520 1525 1530 1535 1540 1545 1550 1555 1560wavelength [nm]
-30
Increasing Index Contrast
Glass based devicesBend Radius ~ 5 mm
5 mm
5 cm
200 µm
InP/InGaAsP(bend radius ~ 500um)
Silicon photonic ICs
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Bend Radius < 5µm
Silicon PhotonicsIntel 40GHz Detector
Ceramic Package
Fiber cable plugs here
Luxtera Ethernet Tranceiver
IBM Modulator
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Silicon PhotonicsSilicon photonics comes in many flavorsSilicon photonics comes in many flavors …
Large rib type waveguides Small core devices
Easy coupling with fiber
Optimized for nanophotonics
Small device size
This work and many others
Large device size
e.g. www.kotura.comFull CMOS integration
Fabricated in CMOS process
Directly integrated with electronics
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
e.g. www.luxtera.com
III-V on silicon ?Sili h t i iSilicon photonics gives us:
Excellent passives
F t d l t f t h t d t tFast modulators, fast photodetectors
But: (almost) no light …
N d f i t ti ith III VNeed for integration with III-Vs
RequirementsHigh density (~10-20um device pitch)
High alignment accuracy (~100nm)
Waferscale processes
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
III V ili h t i t tiIII-V silicon heterogeneous integration
InP/InGaAsPepitaxial layer stack
Si WG
DVS-BCB
SiO2 200nm
1. Silicon photonics is great !!!2. But we still need InP
3 III V silicon integration3. III-V silicon integration4. Devices
III-V on siliconThere are several ways to integrate III V on SOIThere are several ways to integrate III-V on SOI
Flip-chip integration of opto-electronic components☺ most rugged technology☺ most rugged technology☺ testing of opto-electronic components in advance
slow sequential process (alignment accuracy)low density of integration
Hetero-epitaxial growth of III-V on silicon☺ collective process high density of integration☺ collective process, high density of integration
mismatch in lattice constant, CTE, polar/non-polarcontamination and temperature budget
See other talks at this conferenceSee other talks at this conference
Bonding of III-V epitaxial layers☺ sequential but fast integration process☺ hi h d i f i i ll i i
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
☺ high density of integration, collective processing☺ high quality epitaxial III-V layers
Proposed integration processStarting point: Processed SOI-waveguide wafer
193nm or 248nm DUV lithographyFabricated in pilot CMOS-line
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration process
Planarization
PlanarizationUsing BCB (50nm to 2um) (UGent/IMEC)Using SiO (TRACIT CEA LETI)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Using SiO2 (TRACIT - CEA-LETI)
Proposed integration process
Die-to-wafer bonding
Bonding InP-dies on top of planarized SOI-waferLow alignment accuracy requiredFast pick and place
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Fast pick-and-place
Proposed integration process
Substrate removal
Remove InP-substrate down to etch stop layerRemove etch stopThin membrane remains (200nm 2 µm)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Thin membrane remains (200nm ~ 2 µm)
Proposed integration processH d k d itiHardmask deposition
Micro-disk sources
Detectors
D t i ti d h d k d iti
DBR sources
Decontamination and hardmask depositionAlignment of waveguides and devices through lithographic methods
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Proposed integration processProcessing of InP-optoelectronic devices
Mesa etching and Metallization“Waferscale” processing !!!
on 2cm2 pieces (UGent INL)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
on 2cm2 pieces (UGent, INL)on 200mm wafers (CEA-LETI)
III-V/Silicon photonicsB di f III V it i l lBonding of III-V epitaxial layers
Molecular die-to-wafer bondingBased on van der Waals attraction between wafer surfacesased o a de aa s att act o bet ee a e su acesRequires “atomic contact” between both surfaces
- very sensitive to particlesvery sensitive to roughness- very sensitive to roughness
- very sensitive to contamination of surfacesAdhesive die-to-wafer bonding
Uses an adhesive layer as a glue to stick both surfacesRequirements are more relaxed compared to Molecular
- glue compensates for particles (some)g ( )- glue compensates for roughness (all)- glue allows (some) contamination of surfaces
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Bonding TechnologyR i t f th dh i f b diRequirements for the adhesive for bonding
Optically transparentHigh thermal stability (post-bonding thermal budget) 400C400C
<0.1dB/cm<0.1dB/cm
High thermal stability (post bonding thermal budget)Low curing temperature (low thermal stress)No outgassing upon curing (void formation)
400C400C
250C250COKOK
Resistant to all kinds of chemicals HCl,HHCl,H22SOSO44,H,H22OO22,…,…
DVS BCB satisfies these requirements
CH3 CH3
DVS-BCB satisfies these requirements
Si
CH3
Si
CH3
O
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
CH3 CH3
1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene
Bonding TechnologyCross-sectional image of III-V/Silicon substrate
InP/InGaAsP
InP-InGaAsP
InP/InGaAsP epitaxial layer stack
epitaxial layer stack
DVS-BCBSiO2
Si Si WGDVS-BCB
200nm2
Si SiO2 200nm
300nm bonding layer routinely and reliably obtained
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Bonding TechnologyCross-sectional image of III-V/Silicon substrate
InP/InGaAsP
InP-InGaAsP
InP/InGaAsP epitaxial layer stack
epitaxial layer stack
DVS-BCBSiO2
Si Si WGDVS-BCB
200nm2
Si SiO2 200nm
300nm bonding layer routinely and reliably obtained
Recently also sub 100nm layers demonstrated
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Recently also sub-100nm layers demonstrated
III V ili h t i t tiIII-V silicon heterogeneous integration
InP/InGaAsPepitaxial layer stack
Si WG
DVS-BCB
SiO2 200nm
1. Silicon photonics is great !!!2. But we still need InP
3 III V silicon integration3. III-V silicon integration4. Devices
Integrated Devices: laser diodeI t t d l di dIntegrated laser diodes
First only pulsed operation due to high thermal resistivity DVS-BCBIntegration of a heat sink to improve heat dissipationContinuous wave operation achieved this way
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Other groupsIntel / UCSB Hybrid laser CEA LETI / III V labIntel / UCSB Hybrid laser
p-type contact5 µm
CEA-LETI / III-V lab
n-type contact III-V etched facet
4
5
4
5
15°C
10°C
2
3
4
2
3
4
30°C
25°C
15 C
20°C
t pow
er (m
W)
Voltage (V
0
1
0 100 200 300 4000
140°C
35°C
Out
put
Current (mA)
V)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
( )
(IPRM ‘08, paper MoA4.2)
MSM detectorsInGaAs/ InAlAs
polyimide
•Etching of detectors in III-V•Spinning insulation layer of polyimide
polyimide
25µm long detector
R = 1.0A/W (1550nm), IQE = 80% (5V bias)
Id k = 3nA (5V bias)•Opening contact window•Metallization
40µm
contact window
Idark 3nA (5V bias)
SOI waveguides (30µm pitch)
40µm
L=30µm, d=400nm
no absorption
Ti/Au contact
contact window
IN
InGaAs absorption
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
40µm IN
Wavelength selective filter
V bias = 10VV_bias = -10V
1
)
0 01
0.1oc
urre
nt (m
A
1x4 demux, ∆λ=20nm,
280µm x 150µm 0.001
0.01
1480 1500 1520 1540 1560 1580 1600 1620
Phot
o
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
1480 1500 1520 1540 1560 1580 1600 1620
Integrated microdisk laserMi di k l d iMicrodisk laser design
Whispering-gallery modesCentral top contact
top contactbottom contact active layer
2Rdisk
Central top contactBottom contact on thin lateral contact layer (ts)
SiO2Si waveguide
tunnel junction
InP
dox
t
ts
Hole injection through a reverse-biased tunnel-junction
Si substrate
2Si waveguide
wSi
Microdisk thickness 0.5 < t < 1µm
Evanescent coupling to SOI wirep gwaveguide (500x220nm2)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
On-chip optical interconnect ?I t t h t i i t t CMOS ?
SOI waveguide microdetectormicrolaserIII-V material
Integrate photonic interconnect on CMOS ?
SOI Optical pInterconnect
layer
Electrical Interconnect
layerlayer
Silicon transistor layer
Need integrated interconnect layer on top of CMOSSilicon wiring for interconnectIII V microdevices for sources and detectors
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
III-V microdevices for sources and detectors
PICMOS 25 µm
A collaborative project …A collaborative project …
InP island
microdisk
SOI waveguide
IMEC: SOI-wafer fabricationIMEC: SOI-wafer fabrication
TU/e: detector etchingTU/e: detector etchingIMEC: metallizationIII-V processingIMEC: metallizationIII-V processing
microdisk
III V processingIII V processing
TRACIT: planarizationTRACIT: planarizationINL: substrate removalINL: substrate removal
INL: source etchingINL: source etching SiO2 Si wire
BCBInP - InGaAsP
LETI: bondingLETI: bondingLETI: hard maskLETI: hard maskSi substrate
130-nm bonding layer
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Six cleanrooms but still working devices …Six cleanrooms but still working devices …
Continuous-wave lasing1 thi k 7 5 d i hibit
30 2.5CW power
1-µm thick, 7.5-µm devices exhibitcontinuous-wave lasing
-200 9 A
20
25
wer
(µW
)
1.5
2
e (V
)
Pulsed peak power
CW Voltage
-50
-40
-30
wer
(dB
m)
0.9mA
5
10
15
Out
put p
ow
0.5
1 Volta
ge
80
-70
-60
Spec
tral
pow
0
5
0 0.5 1 1.5 2Current (mA)
0 -90
-80
1560 1580 1600 1620 1640Wavelength (nm)Current (mA)
Threshold current Ith = 0.5mA, voltage Vth = 1.5-1.7Vslope efficiency = 30µW/mA, up to 10µW
g ( )
BCB InP - InGaAsP
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
(Pulsed regime: up to 100µW peak power)J. Van Campenhout et al., "Electrically pumped inp-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit" Optics Express, May 2007Si substrate
SiO2 Si wire
InP - InGaAsP
130-nm b di
Temperature dependence“L i i t 70°C”“Laser emission up to 70°C”
(pulsed operation)
300
400
T=10T=10°°CCD = 6µm
1570
1571
1572
elen
gth
[nm
]
200
300
wer
[a.u
.]
T=20T=20°°CCT=30T=30°°CC
T=40T=40°°CC1567
1568
1569
0 10 20 30 40 50
peak
wav
e
1Kpm86 −≈dTdλ
100
pow T=40T=40 CC
T=50T=50°°CC T=60T=60°°CC
0 10 20 30 40 50Tamb [°C]
14 K012)( −−≈InPdTdn
0400 600 800 1000 1200 1400 1600 1800
T=70T=70°°CCdT
13 K017)( −−−≈BCBdTdn
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
current [uA]
Fit to experimental data30 3
20
25
30
(µW
)
2
2.5
3
)
10
15
20
cal P
ower
(
1
1.5
2
Volta
ge (V
pulsed data
0 0 5 1 1 5 2 2 5 30
5
10
Opt
ic
0
0.5
1 V
CW data
Model can be fitted to pulsed experimental data, assuming:uniform injection: injection efficiency =0.36x0.7=0.25
0 0.5 1 1.5 2 2.5 3Current (mA)
j j ycoupling loss = 3cm-1 (simulation)tunnel-junction p-doping Na = 2x1018cm-3
(design target Na = 2x1019cm-3, SIMS analysis: Na ~ 8x1018cm-3 )fitted scatter loss = 8cm-1 (passive ring resonators: 7-13cm-1)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
fitted scatter loss 8cm (passive ring resonators: 7 13cm )
Consistent fit, except for tunnel-junction p-doping and saturation effect
Ultra-low-power Wavelength conversion
-30
-20
-10
Bm
/0.1
nm)
∆λFSR=32nm
dominant lasingwavelength of MDL
injected laserwavelength
tunable
polarizationcontroller
patterngenerator
variablemodulator
60
-50
-40 w/o injectionwith injection
de in
tens
ity (d
Blaser polarizationcontroller
attentuatormodulator
EDFAband-pass
filter
high-speeddetector
detector
oscilloscope
MDL
SOIwg.
1.56 1.58 1.6 1.62-70
-60
wavelength (µm)
moddetector
1
r (a.
u.)
• No control power needed.
• Wavelength conversion with
0
0.5 2ns
pow
er Wavelength conversion with only 6.4uW control power.
• 5Gbps dynamic results.
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
0 0.5 1 1.5 2 2.5time (ns)
p y
Full LinkD t t di ( t i 256 ti l li k )Demonstrator die (contains 256 optical links)
7mm
detector III-V dielaser III-V die
120 Microdisklasers
120 DBRmicrolasers
S S laser III-V die
-poi
nts -p
oint
sCO
UPL
ERS
cast
s CO
UPL
ERS
200mm SOI wafer
9mm
Poin
t-to-
links
Poin
t-to-
links
GR
ATIN
G C
Bro
adc
links
GR
ATIN
G C
264 Micro detectors(TU Ei dh / C b )
FIB
RE
G
FIB
RE
G
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
(TU Eindhoven / Cobra)
Pulsed operation of the linkDuty cycle = 8% Period = 1 µsmonitor grating
Detector not biased (0V), negligible dark current
on-chip detector
etecto ot b ased (0 ), eg g b e da cu e t
Performance under pulsed operation:Threshold current < 700 µA & Slope efficiency ~ 1.1 µW/mAD t t ffi i f 0 23 0 29 A/W
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Detector efficiency of 0.23-0.29 A/W.
Outlook & conclusionW d t t dWe demonstrated:
Ultra-dense waveguiding< 2 µm pitch (waveguide to waveguide)< 2 µm pitch (waveguide-to-waveguide)
A powerfull III-V on Silicon integration technology
Several proof-of-principle demonstratorsSeveral proof of principle demonstratorsElectrically pumped micro-disk sources on silicon platform
500 µA threshold current500 µA threshold current
Micro-detectors on silicon platform1.0A/W
Fabrication using waferscale processes
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Outlook & conclusionW till d t
Single wavelength
We still need to:Improve source performance
Towards 50 µA threshold current 10GHz modulation
Multi-wavelength sources
Towards 50 µA threshold current – 10GHz modulation speed – 30% internal efficiencyThrough improved processing
λ λ
λ1
λ2
λ3
λN
Through improved device designImproved high temperature operation
Full fabrication in CMOS pilot line
λ1
λ2
λ3
λN
λ1,λ2 ... λN-1,λN
λ λ λ λNFull fabrication in CMOS pilot-line
Integration with CMOS electronic driving circuit
Implement WDM-functionality
1 2 3N
λ1,λ2 ... λN-1,λN
Implement WDM functionality
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Multi-wavelength Laser4 a elength laser
D1 D2 D3 D4SM fiber
4-wavelength laser
gratingcoupler
-1023nmλ =
32nmFSRλ =-10
(a) (b)
10µm diameter 7.5µm diameter
40
-30
-2023nmFSRλ =
40
-30
-20D1
D4 D3D2 D1
D4D3
D2
biased at:4mA
biased at:3mAer
(dB
)
er (d
B)
-60
-50
-40
-60
-50
-40D1
D2
D1
D2
3po
we
pow
e
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
1.56 1.57 1.58 1.59 1.6 1.61 1.62-70
1.56 1.57 1.58 1.59 1.6 1.61 1.62-70
wavelength (µm) wavelength (µm)
Outlook & conclusionW till d tWe still need to:
Improve source performance Towards 50 µA threshold current 10GHz modulationTowards 50 µA threshold current – 10GHz modulation speed – 30% internal efficiencyThrough improved processingThrough improved device designImproved high temperature operation
Full fabrication in CMOS pilot lineFull fabrication in CMOS pilot-line
Integration with CMOS electronic driving circuit
Implement WDM-functionalityImplement WDM functionality
Simplify overall processing
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Outlook & conclusionSi lif iSimplify processing
Avoid critical patterning in the III-V layer
Silicon racetrack
III-V film
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
AcknowledgementsPh t i R h GPhotonics Research Group
III-V silicon integration: G. Roelkens, J. Van Campenhout, J. Brouckaert, L. Liu
Silicon ProcessingW. Bogaerts, P. Dumon, S. Selvarajan, R. Baets
PICMOS teamJ.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing)C. Lagahe, B. Aspar (TRACIT) (planarization)C. Seassal, P. Rojo-Romeo, P. Regreny, P. Viktorovitch (INL) (processing, epitaxy)R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Fiber-chip coupling
1
Important:Low loss coupling
1µm Large bandwidth
Coupling tolerance
FabricationFabricationLimited extra processingTolerant to fabrication
SOI wire Low reflection
Polarization ?
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Single-mode fiber
Coupling to fiber – Grating couplerAlternative: Grating couplers
Waferscale testing
Waferscale packaging
High alignment tolerance
d t h
shallow fibre couplerFrom Fibre
70% efficiencymeasured
deep trench
Towards optical circuit
Single modefiber core
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Increase effieciency ?Top view Improving performance
Add bottom mirrorgrating coupler Apodize
“Other”
With mirror
BCB
Without mirror
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
FIB cross-section 1dB bandwidth > 40nm
1 Coupling of light between III V and SiliconMain Challenges
1. Coupling of light between III-V and SiliconOption 1: evanescent
Guiding in siliconRequires thin bonding layerRequires III-V thinner than <250nm
Option 2: other (adiabatic grating coupler )Option 2: other (adiabatic, grating coupler …)Guiding in III-VThicker III-V layerSometimes thicker bondingSometimes thicker bonding
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
1 Coupling of light between III V and SiliconMain Challenges
1. Coupling of light between III-V and SiliconOption 1: evanescent
Guiding in siliconRequires thin bonding layerRequires III-V thinner than <250nm
Option 2: other (adiabatic grating coupler )Loss at metal contactOption 2: other (adiabatic, grating coupler …)Guiding in III-VThicker III-V layerSometimes thicker bondingSometimes thicker bonding
2. Electrical injection Metal contact on membrane devices without inducing additional loss
3. Thermal managementOvercome thermal barrier of bonding layer and BOX
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be
Overcome thermal barrier of bonding layer and BOX
Integrated Devices: laser diodeIntegrated laser diodesIntegrated laser diodes
Fabry-Perot laser cavity by etching InP/InGaAsP laser facets
Inverted adiabatic taper coupling approach
© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be