A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Cover SheetCustom
1 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
REV:1.0
Mobile Yonah uFCPGA with IntelCalistoga_P/GM+ ICH7-M core logic
Schematics Document
2006-04-28
Compal confidential
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Block DiagramCustom
2 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Power On/Off CKT.
File Name : LA-2952P
LPC BUS
Compal confidential
PCBGA 1466
page 19
H_A#(3..31)
CardBus ControllerTI PCI6612
page 27
BANK 0, 1, 2, 3
USB conn x3
533/667MHz
DMI
DC/DC Interface CKT.
Mobile Yonah/Merom
page 34
USB2.0
FSB
Clock GeneratorICS9LP306BGLFT
Power Circuit DC/DC
Multi-bay II Connector
PCI BUS
uFCPGA-478 CPU
page 31
DDR2-SO-DIMM X2
page 33
Intel Calistoga MCH
page 4page 4,5,6
RTC CKT.
page 15
DDR2 -400/533/667
mBGA-652
page 34
page 4
page 7,8,9,10,11,12
Intel ICH7-M
Thermal SensorADM1032AR
page 13,14
page 18,19,20,21
Docking CONN.*RJ-45(LED*2)*RJ-11(Pass Through)*CRT*COMPOSITE Video Out*TVOUT*DVI*LINE IN*LINE OUT*PCI-E x2*Serial Port*Parallel Port*PS/2 x2*USB x2*DC JACK
Power OK CKT.
page 19
Slot 0/Smart Card
Fan Control
Dual Channel
SMSC Super I/OLPC47N217
TPM 1.2
COM1 LPTTouch Pad CONN. Int.KBD
SMSC KBC 1021
SD/MMC Slot
page 30
page 37page 31
page 29
Page 35,36,37,38,39,40,41,42,43
page 22/23
page 23
10/100/1000 LANBCM5753M
RJ45/11 CONN
PCI-E BUS
page 32 page 32
page 29
FingerPrinter AES2501 USBx1
BT Connpage 27
( Docking ) ( Docking )
page 29
LED
SPI
25LF080A
SPI ROM
page 29
page 25
page 26
AD1981HDAudio CKT
AMP & Audio JackMAX9710
H_D#(0..63)
Caymus
USB conn x2(Docking) page 32
AC-LINK/Azalia
page 31MDC
page 19
SATA HDD Connector
PATA Slave
page 24
Mini-Card WLAN
945GM
SATA
daughter board
Mini-Card WWANpage 24
Accelerometer
page 24
LIS3LV02DQ
DVICH7307C
page 16
page 16
CRT / TV-OUT
LCD CONNpage 17
daughter board
page 34
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Notes List
3 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
IDSEL #
VIN
SMBUS
OFF
Power Plane
N/AN/A
PATA/SATALPC I/F
ON
AC or battery power rail for power circuit
AC97 Audio
+CPU_CORE
+0.9VS
S3
D31
+1.5VS
AC97 MODEM
D29
OFF+VCCP
D8
2
N/A
1 0 1 0 0 1 0 0
Internal PCI Devices
A4
USB1.1/2.0
I2C / SMBUS ADDRESSING
D30
C D E G
ON
1 0 1 0 0 0 0 0
D2
CARD BUS
A0
CLOCK GENERATOR (EXT.)
HEX
D30
DDR SO-DIMM 1
0.9V switched power rail for DDRII Vtt
S0-S1
D6
D30
ON OFF
ON
PCI Device ID
N/AN/A
ADDRESS
DEVICE
OFF
PCI Device ID
Description
DDR SO-DIMM 0
DEVICE
1.05V power rail for Processor I/O and MCH/ICH core power
PCI to PCI (DMI to PCI)
Adapter power supply (18.5V)
1 1 0 1 0 0 1 0
External PCI Devices
LAN
N/A
REQ/GNT #
OFF
D31
OFF
DEVICE
Core voltage for CPUOFF
AD22
OFF
PIRQ
S5
D31
1.5V switched power rail for PCI-E interface
B+
Voltage Rails
OFF2.5V switched power rail for MCH video PLL
5V always on power railON
3.3V always on power rail3.3V switched power rail+3VS
ON*
RTC power ONONNote : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+1.8V
OFF
OFF
ON
ON
+3VALW
OFF
ON
5V switched power railON
+2.5VS
+RTC_VCC+5VS
ON
ON
ON OFF
+5VALW
ON
1.8V power rail for DDRII
ON*
ON+1.8VS OFF OFF1.8V switched power rail
D28PCI-EAzalia D27
IDSEL #
AD24AD11AD12AD13AD14
AD15
AD14AD14
AD15AD15
Bus
01
00000000
AD15D310CPU I/F0 D31 AD15DMA0 D31 AD15PMU
ON OFF OFF
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
SPI@ : means just build when SPI I/F BIOS function reserve.
NOXDP@ : means just build when XDP function disable.XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
FWH@ : means just build when FWH I/F BIOS function reserve.
45@ : means need be mounted when 45 level assy or rework stage.
1021@ : means just build when SMsC KBC1021 chip selected.
M52@ : means build discrete sku with ATI VGA M52 .UMA@ : means build UMA sku with Intel 945GM .
LP@ : means just build when Low power clock gen. installNOLP@ : means just build when Low power clock gen. NO install
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_A#28
H_THERMDA
H_FERR#
H_ADSTB#0
H_A#23
H_REQ#2
H_A#31
H_REQ#0
H_A#17
H_BNR#
H_A#29
H_DSTBP#0
H_A#8
H_DEFER#
H_REQ#1
H_A#3
H_RS#0
H_DSTBN#1
H_A#6
XDP_BPM#2
H_BPRI#
H_ADS#
H_A#25
XDP_BPM#3
H_RS#1
H_DSTBP#1
H_A#4
H_IERR#H_HITM#
H_DSTBN#0
H_INTR
H_DSTBN#2
H_A#22
H_A#7
H_REQ#4
XDP_DBRESET#
H_DRDY#
H_A#15H_A#14
H_A20M#
H_DINV#0
H_DSTBP#2
H_DINV#2H_DINV#3
H_DINV#1
H_DSTBN#3
H_DSTBP#3
H_NMI
H_A#30
H_A#27
H_A#18
H_A#10
H_BR0#
H_LOCK#
H_A#11
H_A#21
H_A#26
H_A#13
H_A#9
XDP_BPM#0
H_DPSLP#
H_A#20
H_A#16
H_A#12
H_HIT#
H_ADSTB#1
H_THERMTRIP#
H_DBSY#
H_A#19
H_A#24
H_A#5
H_RS#2
H_RESET#
XDP_BPM#1
H_REQ#3
H_SMI#H_STPCLK#
XDP_TCK
XDP_TRST#XDP_TMS
H_CPUSLP#
XDP_TDOXDP_TDI
H_PWRGOOD
XDP_BPM#5
H_DPRSTP#
H_TRDY#
CLK_CPU_BCLKCLK_CPU_BCLK#
ICH_SMBCLKICH_SMBDATA
H_THERMDA
H_THERMDC
THERM#
THERM_SCI#
ICH_SMBDATA
ICH_SMBCLK
THERM#
FAN
H_THERMDC
XDP_BPM#4H_DPWR#
TEST1TEST2
H_D#0H_D#1H_D#2H_D#3
H_D#7H_D#6
H_D#4H_D#5
H_D#11H_D#10
H_D#8H_D#9
H_D#15H_D#14
H_D#12H_D#13
H_D#19H_D#18
H_D#16H_D#17
H_D#23H_D#22
H_D#20H_D#21
H_D#27H_D#26
H_D#24H_D#25
H_D#31H_D#30
H_D#28H_D#29
H_D#35H_D#34
H_D#32H_D#33
H_D#39H_D#38
H_D#36H_D#37
H_D#43H_D#42
H_D#40H_D#41
H_D#47H_D#46
H_D#44H_D#45
H_D#51H_D#50
H_D#48H_D#49
H_D#55H_D#54
H_D#52H_D#53
H_D#59H_D#58
H_D#56H_D#57
H_D#63H_D#62
H_D#60H_D#61
H_INIT#H_IGNNE#
H_PROCHOT#
H_PROCHOT# OCP#
H_DPSLP#
H_DPRSTP#
XDP_BPM#3
ICH_SMBDATAICH_SMBCLK
XDP_BPM#2
XDP_DBRESET#_R
XDP_BPM#1XDP_BPM#0
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
XDP_TDO
XDP_TRST#
XDP_TMSXDP_TDI
XDP_TDO
H_RESET#H_RESET#_R
H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDPCLK_CPU_XDP#
XDP_BPM#4XDP_BPM#5
XDP_BPM#5
ICH_SMBDATA<13,14,15,20,22,24>ICH_SMBCLK<13,14,15,20,22,24>
THERM_SCI# <20>
FAN_PWM<30>
H_D#[0..63] <7>H_A#[3..31]<7>
H_REQ#[0..4]<7>
H_ADSTB#0<7>H_ADSTB#1<7>
CLK_CPU_BCLK#<15>CLK_CPU_BCLK<15>
H_ADS#<7>H_BNR#<7>
H_BR0#<7>
H_DRDY#<7>H_HIT#<7>
H_HITM#<7>
H_BPRI#<7>
H_DEFER#<7>
H_LOCK#<7>H_RESET#<7>
H_RS#[0..2]<7>
H_TRDY#<7>
H_DBSY#<7>H_DPSLP#<19>
H_DPRSTP#<19,42>H_DPWR#<7>
H_CPUSLP#<7>
H_THERMTRIP#<7,19>
H_DINV#0 <7>H_DINV#1 <7>H_DINV#2 <7>H_DINV#3 <7>
H_DSTBN#[0..3] <7>
H_DSTBP#[0..3] <7>
H_A20M# <19>H_FERR# <19>H_IGNNE# <19>H_INIT# <19>H_INTR <19>H_NMI <19>
H_STPCLK# <19>H_SMI# <19>
XDP_DBRESET#<20>
H_PROCHOT#<42>
OCP# <20,43>
CLK_CPU_XDP <15>CLK_CPU_XDP# <15>
H_PWRGOOD<19>
+VCCP
+3VS
+3VS
+5VS
+3VS
+VCCP
+VCCP
+3VS
+VCCP +VCCP
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Yonah CPU in mFCPGA479
4 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
H_THERMDA, H_THERMDC routing together.Trace width / Spacing = 10 / 10 mil
Thermal Sensor ADM1032AR-2
ITP-XDP ConnectorThis shall place near CPU
Address:1001_101
PWM Fan Control circuit
ZD1
RLZ5.1B_LL34
@
12
U24
TC7SH00FU_SSOP5
INB1
INA2 O 4
G3
P5
C273
0.1U_0402_16V4Z1
2
R12941K_0402_5%@1 2
R236 56_0402_1%1 2
R239 56_0402_5%1 2
R246 56_0402_5%1 2
R41056_0402_5% 1 2
R238 56_0402_5%1 2
C125
0.1U_0402_16V4Z
1
2
JP19
SAMTE_BSH-030-01-L-D-A
GND01OBSFN_A03OBSFN_A15GND27OBSDATA_A09OBSDATA_A111GND413OBSDATA_A215OBSDATA_A317GND619OBSFN_B021OBSFN_B123GND825OBSDATA_B027OBSDATA_B129GND1031OBSDATA_B233OBSDATA_B335GND1237PWRGOOD/HOOK039HOOK141VCC_OBS_AB43HOOK245HOOK347GND1449SDA51SCL53TCK155TCK057GND1659
GND1 2OBSFN_C0 4OBSFN_C1 6
GND3 8OBSDATA_C0 10OBSDATA_C1 12
GND5 14OBSDATA_C2 16OBSDATA_C3 18
GND7 20OBSFN_D0 22OBSFN_D1 24
GND9 26OBSDATA_D0 28OBSDATA_D1 30
GND11 32OBSDATA_D2 34OBSDATA_D3 36
GND13 38ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42VCC_OBS_CD 44
RESET#/HOOK6 46DBR#/HOOK7 48
GND15 50TD0 52
TRST# 54TDI 56
TMS 58GND17 60
R2421K_0402_1%1 2
R1266
56_0402_5%@
1 2
U16
ADM1032AR-2_MSOP8
VDD1
ALERT# 6
THERM#4 GND 5
D+2
D-3
SCLK 8
SDATA 7
R243200_0402_1%
12
R227
10K_0402_5%
12
R228
10K_0402_5%
1 2
R1265 51_0402_5%
12
R1296 0_0402_5%1 2
D11
CH751H-40_SC76 2
1
S
GD
Q33AO6402_TSOP63
624
51
ADDR GROUP
CONTROL
HOST CLK
MISC
DATA GROUP
THERMALDIODE
LEGACY CPU
YONAHJP12A
FOX_PZ47903-2741-42_YONAH
A3#J4A4#L4A5#M3A6#K5A7#M1A8#N2A9#J1A10#N3A11#P5A12#P2A13#L1A14#P4A15#P1A16#R1A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5A23#U2A24#R4A25#T5A26#T3A27#W3A28#W5A29#Y4A30#W2A31#Y1
REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L5
ADSTB0#L2ADSTB1#V4
BCLK0A22BCLK1A21
ADS#H1BNR#E2BPRI#G5BR0#F1DEFER#H5DRDY#F21HIT#G6HITM#E4IERR#D20LOCK#H4RESET#B1
RS0#F3RS1#F4RS2#G3TRDY#G2
BPM0#AD4BPM1#AD3BPM2#AD1BPM3#AC4
DBR#C20DBSY#E1DPSLP#B5
DPWR#D24PRDY#AC2PREQ#AC1PROCHOT#D21
PWRGOODD6SLP#D7TCKAC5TDIAA6TDOAB3TEST1C26TEST2D25TMSAB5TRST#AB6
THERMDAA24THERMDCA25THERMTRIP#C7
D0# E22D1# F24D2# E26D3# H22D4# F23D5# G25D6# E25D7# E23D8# K24D9# G24
D10# J24D11# J23D12# H26D13# F26D14# K22D15# H25D16# N22D17# K25D18# P26D19# R23D20# L25D21# L22D22# L23D23# M23D24# P25D25# P22D26# P23D27# T24D28# R24D29# L26D30# T25D31# N24D32# AA23D33# AB24D34# V24D35# V26D36# W25D37# U23D38# U25D39# U22D40# AB25D41# W22D42# Y23D43# AA26D44# Y26D45# Y22D46# AC26D47# AA24D48# AC22D49# AC23D50# AB22D51# AA21D52# AB21D53# AC25D54# AD20D55# AE22D56# AF23D57# AD24D58# AE21D59# AD21D60# AE25D61# AF25D62# AF22D63# AF26
DINV0# J26DINV1# M26DINV2# V23DINV3# AC20
DSTBN0# H23DSTBN1# M24DSTBN2# W24DSTBN3# AD23DSTBP0# G22DSTBP1# N25DSTBP2# Y25DSTBP3# AE24
A20M# A6FERR# A5
IGNNE# C4INIT# B3
LINT0 C6LINT1 B4
STPCLK# D5SMI# A3
DPRSTP#E5
R1255
56_0402_5%@
12
C948 0.1U_0402_16V4Z12
R237 56_0402_5%1 2
EB
C
Q85MMBT3904_SOT23@
2
3 1
R1264 1K_0402_5%@1 2
R241 56_0402_5%1 2
C122
4.7U_0805_10V4Z
1
2
C264
2200P_0402_50V7K
1 2
R17256_0402_5%
1 2
R1295
1K_0402_5%12
R1267
56_0402_5%@
1 2
JP8
ACES_85205-0200
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COMP3COMP2
H_PSI#
COMP1COMP0
CPU_VID1CPU_VID0
CPU_VID3CPU_VID4
CPU_VID2
CPU_VID5CPU_VID6
CPU_BSEL1CPU_BSEL2
CPU_BSEL0
VSSSENSEVCCSENSE
VSSSENSE
VCCSENSE
H_PSI#<42>
CPU_VID0<42>CPU_VID1<42>CPU_VID2<42>CPU_VID3<42>CPU_VID4<42>CPU_VID5<42>CPU_VID6<42>
CPU_BSEL0<15>CPU_BSEL1<15>CPU_BSEL2<15>
VCCSENSE<42>VSSSENSE<42>
+VCCP
+VCC_CORE
+VCCP
V_CPU_GTLREF
V_CPU_GTLREF
+1.5VS
+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Yonah CPU in mFCPGA479
5 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Resistor placed within0.5" of CPU pin.Traceshould be at least 25mils away from anyother toggling signal.
Close to CPU pin AD26within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
0 0
0 1
CPU_BSEL0
1
1
Length match within 25 milsThe trace width 18 mils space7 mils
Close to CPU pinwithin 500mils.
R35
527
.4_0
402_
1%
12
C53
110
U_0
805_
10V4
Z
1
2
POWER, GROUNG, RESERVED SIGNALS AND NC
YONAH
JP12B
FOX_PZ47903-2741-42_YONAH
PSI#AE6
GTLREFAD26
VCCSENSEAF7
VCCAB26
VCCAB20VCCAA20VCCAF20VCCAE20VCCAB18VCCAB17VCCAA18VCCAA17VCCAD18VCCAD17VCCAC18VCCAC17VCCAF18VCCAF17
RSVDT22
RSVDV3RSVDB2RSVDC3
VSS AB26VSS AA25VSS AD25VSS AE26VSS AB23VSS AC24VSS AF24VSS AE23VSS AA22VSS AD22VSS AC21VSS AF21VSS AB19VSS AA19VSS AD19VSS AC19VSS AF19VSS AE19VSS AB16VSS AA16VSS AD16VSS AC16VSS AF16VSS AE16VSS AB13VSS AA14VSS AD13VSS AC14VSS AF13VSS AE14VSS AB11VSS AA11VSS AD11VSS AC11VSS AF11VSS AE11VSS AB8VSS AA8VSS AD8VSS AC8VSS AF8VSS AE8VSS AA5VSS AD5VSS AC6VSS AF6VSS AB4VSS AC3VSS AF3VSS AE4VSS AB1VSS AA2VSS AD2VSS AE1VSS B6VSS C5VSS F5VSS E6VSS H6VSS J5VSS M5VSS L6VSS P6VSS R5VSS V5VSS U6VSS Y6VSS A4VSS D4VSS E3VSS H3VSS G4VSS K4VSS L3VSS P3VSS N4VSS T4VSS U3VSS Y3VSS W4VSS D1VSS C2VSS F2VSS G1RSVDB25
VSSSENSEAE7
VCCPK6VCCPJ6VCCPM6VCCPN6VCCPT6VCCPR6VCCPK21VCCPJ21VCCPM21VCCPN21VCCPT21VCCPR21VCCPV21VCCPW21VCCPV6VCCPG21
VID0AD6VID1AF5VID2AE5VID3AF4VID4AE3VID5AF2VID6AE2
BSEL0B22BSEL1B23BSEL2C21
COMP0R26COMP1U26COMP2U1COMP3V1
RSVDC23RSVDC24RSVDAA1RSVDAA4RSVDAB2RSVDAA3RSVDM4RSVDN5RSVDT2
RSVDD2RSVDF6RSVDD3RSVDC1RSVDAF1RSVDD22
VCCE7
R12
2054
.9_0
402_
1%
12
R24
427
.4_0
402_
1%
12
R12681K_0402_1%
12
R1270100_0402_1%
1 2
R1269100_0402_1%
1 2
R12712K_0402_1%
12
C52
00.
01U
_040
2_16
V7K
1
2
POWER, GROUND
YONAH
JP12C
FOX_PZ47903-2741-42_YONAH
VCCAE18VCCAE17VCCAB15VCCAA15VCCAD15VCCAC15VCCAF15VCCAE15VCCAB14VCCAA13VCCAD14VCCAC13VCCAF14VCCAE13VCCAB12VCCAA12VCCAD12VCCAC12VCCAF12VCCAE12VCCAB10VCCAB9VCCAA10VCCAA9VCCAD10VCCAD9VCCAC10VCCAC9VCCAF10VCCAF9VCCAE10VCCAE9VCCAB7VCCAA7VCCAD7VCCAC7VCCB20VCCA20VCCF20VCCE20VCCB18VCCB17VCCA18VCCA17VCCD18VCCD17VCCC18VCCC17VCCF18VCCF17VCCE18VCCE17VCCB15VCCA15VCCD15VCCC15VCCF15VCCE15
VSS K1VSS J2VSS M2VSS N1VSS T1VSS R2VSS V2VSS W1VSS A26VSS D26VSS C25VSS F25VSS B24VSS A23VSS D23VSS E24VSS B21VSS C22VSS F22VSS E21VSS B19VSS A19VSS D19VSS C19VSS F19VSS E19VSS B16VSS A16VSS D16VSS C16VSS F16VSS E16VSS B13VSS A14VSS D13VSS C14VSS F13VSS E14VSS B11VSS A11VSS D11VSS C11VSS F11VSS E11VSS B8VSS A8VSS D8VSS C8VSS F8VSS E8VSS G26VSS K26VSS J25VSS M25VSS N26VSS T26VSS R25VSS V25VSS W26VSS H24VSS G23VSS K23VSS L24VSS P24VSS N23VSS T23VSS U24VSS Y24VSS W23VSS H21VSS J22VSS M22VSS L21VSS P21VSS R22VSS V22VSS U21VSS Y21
VCCB14VCCA13VCCD14VCCC13VCCF14VCCE13VCCB12VCCA12VCCD12VCCC12VCCF12VCCE12VCCB10VCCB9VCCA10VCCA9VCCD10VCCD9VCCC10VCCC9VCCF10VCCF9VCCE10VCCE9VCCB7
VCCF7 VCCA7
R24
554
.9_0
402_
1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCP
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
CPU Bypass capacitors
6 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Mid Frequence Decoupling
ESR <= 1.5m ohmCapacitor > 1980uF
Place these capacitors on L8(North side,Secondary Layer)
Place these capacitors on L8(Sorth side,Secondary Layer)
Place these capacitors on L8(Sorth side,Secondary Layer)
Place these capacitors on L8(North side,Secondary Layer)
C919
10U_0805_6.3V6M
1
2
+C934820U_E9_2_5V_M_R745@
1
2
C926
10U_0805_6.3V6M
1
2
C943
0.1U_0402_10V6K
1
2
C911
10U_0805_6.3V6M
1
2
C925
10U_0805_6.3V6M
1
2
C916
10U_0805_6.3V6M
1
2
C918
10U_0805_6.3V6M
1
2
C902
10U_0805_6.3V6M
1
2
C901
10U_0805_6.3V6M
1
2
C930
10U_0805_6.3V6M
1
2
C906
10U_0805_6.3V6M
1
2
C903
10U_0805_6.3V6M
1
2
C923
10U_0805_6.3V6M
1
2
+C931
330U_D2E_2.5VM_R7@
1
2
C909
10U_0805_6.3V6M
1
2
C905
10U_0805_6.3V6M
1
2
+C932
330U_D2E_2.5VM_R7@
1
2
+C935
330U_D2E_2.5VM_R7
1
2
C910
10U_0805_6.3V6M
1
2
C917
10U_0805_6.3V6M
1
2
C900
10U_0805_6.3V6M
1
2
C908
10U_0805_6.3V6M
1
2
+C937
330U_D2E_2.5VM_R7
1
2
C904
10U_0805_6.3V6M
1
2
C912
10U_0805_6.3V6M
1
2
C899
10U_0805_6.3V6M
1
2
C941
0.1U_0402_10V6K
1
2
C921
10U_0805_6.3V6M
1
2
C924
10U_0805_6.3V6M
1
2
C929
10U_0805_6.3V6M
1
2
C928
10U_0805_6.3V6M
1
2
C915
10U_0805_6.3V6M
1
2
C944
0.1U_0402_10V6K
1
2
C945
0.1U_0402_10V6K
1
2
C927
10U_0805_6.3V6M
1
2
C920
10U_0805_6.3V6M
1
2
C922
10U_0805_6.3V6M
1
2
+C933
330U_D2E_2.5VM_R7@
1
2
C907
10U_0805_6.3V6M
1
2
+C983
330U_D2E_2.5VM_R9
1
2
C914
10U_0805_6.3V6M
1
2
C942
0.1U_0402_10V6K
1
2
+C936
330U_D2E_2.5VM_R7
1
2
C940
0.1U_0402_10V6K
1
2
C913
10U_0805_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AH_SWNG0
H_VREF
DDR_THERM#
V_DDR_MCH_REF
M_OCDOCMP1
PM_EXTTS#1
H_RS#0
H_ADSTB#1
H_SWNG1
H_XRCOMP
CFG3
DMI_TXP1
H_REQ#0
CFG7
CFG5
DDR_CKE0_DIMMA
M_CLK_DDR3
DMI_RXN2
H_HIT#
H_DSTBP#0
H_REQ#4
H_SWNG0
CFG15
DDR_CKE1_DIMMA
M_OCDOCMP0
DMI_TXN1DMI_TXN0
H_BNR#
H_REQ#2
M_ODT1
DMI_TXP2
H_DSTBP#2
CLK_MCH_3GPLL
CFG13
M_CLK_DDR#0
DMI_RXP2
H_REQ#3
CFG9
H_DINV#2
CLK_MCH_BCLK#
H_REQ#1
H_YSCOMP
MCH_CLKSEL0
DDR_CKE3_DIMMB
H_BPRI#
H_DINV#0
CFG18
CFG4
M_CLK_DDR#1
DMI_RXP1DMI_RXP0
DMI_TXP0
H_CPUSLP#
H_DPWR#
H_ADS#
H_DSTBP#3
H_DSTBN#3
CFG16
DMI_RXN1
M_OCDOCMP0
CLK_MCH_BCLK
PLTRST_R#
CFG19
CFG12
DDR_CS1_DIMMA#
SMRCOMPN
H_DSTBP#1
H_DINV#3
H_RS#2
H_ADSTB#0
CFG17
CFG8
CFG6
DDR_CKE2_DIMMB
DMI_RXN0
H_LOCK#
H_RESET#
M_ODT3
M_OCDOCMP1
M_CLK_DDR#2
DMI_TXP3
DMI_TXN3
H_DBSY#
H_BR0#
H_DSTBN#1H_DSTBN#0
CLK_MCH_3GPLL#
CFG20
V_DDR_MCH_REF
H_DSTBN#2
H_RS#1
H_XSCOMP
CFG10
MCH_CLKSEL2
DDR_CS0_DIMMA#
SMRCOMPP
M_CLK_DDR#3
CFG11
DDR_CS3_DIMMB#
DMI_RXN3
H_HITM#
H_DRDY#
DDR_CS2_DIMMB#
M_ODT2
M_ODT0
H_DEFER#
H_TRDY#
H_DINV#1
H_THERMTRIP#
CFG14
M_CLK_DDR2M_CLK_DDR1M_CLK_DDR0
H_VREF
H_YRCOMP
DMI_TXN2
DMI_RXP3
PM_EXTTS#1
MCH_CLKSEL1
H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7
H_D#11
H_D#13
H_D#9
H_D#14
H_D#8
H_D#15
H_D#12
H_D#10
H_D#19
H_D#21
H_D#17
H_D#22
H_D#16
H_D#23
H_D#20
H_D#18
H_D#27
H_D#29
H_D#25
H_D#30
H_D#24
H_D#31
H_D#28
H_D#26
H_D#35
H_D#37
H_D#33
H_D#38
H_D#32
H_D#39
H_D#36
H_D#34
H_D#43
H_D#45
H_D#41
H_D#46
H_D#40
H_D#47
H_D#44
H_D#42
H_D#51
H_D#53
H_D#49
H_D#54
H_D#48
H_D#52
H_D#50
H_D#55
H_D#59
H_D#61
H_D#57
H_D#62
H_D#56
H_D#63
H_D#60
H_D#58
H_A#3H_A#4H_A#5H_A#6H_A#7
H_A#11
H_A#8
H_A#10
H_A#12
H_A#9
H_A#13
H_A#15
H_A#17
H_A#14
H_A#21
H_A#18
H_A#20
H_A#22
H_A#19
H_A#26
H_A#23
H_A#25
H_A#27
H_A#24
H_A#31
H_A#28
H_A#30H_A#29
H_A#16
CLK_MCH_REF#CLK_MCH_REF
CLK_MCH_SS#CLK_MCH_SS
GMCH_H32
PWROK
PWROK
CLKREQC#GMCH_H32
PM_BMBUSY#DDR_THERM#
H_SWNG1
H_D#[0..63]<4> H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_ADSTB#1 <4>H_ADSTB#0 <4>
CLK_MCH_BCLK# <15>CLK_MCH_BCLK <15>H_DSTBN#[0..3] <4>
H_DSTBP#[0..3] <4>
H_DINV#0 <4>H_DINV#1 <4>H_DINV#2 <4>H_DINV#3 <4>
H_RESET# <4>H_ADS# <4>H_TRDY# <4>H_DPWR# <4>H_DRDY# <4>H_DEFER# <4>
H_BR0# <4>H_BNR# <4>H_BPRI# <4>H_DBSY# <4>H_CPUSLP# <4>
H_HITM# <4>H_HIT# <4>H_LOCK# <4>
H_RS#[0..2] <4>
DMI_TXN0<20>DMI_TXN1<20>DMI_TXN2<20>DMI_TXN3<20>
DMI_TXP0<20>DMI_TXP1<20>DMI_TXP2<20>DMI_TXP3<20>
DMI_RXN0<20>DMI_RXN1<20>DMI_RXN2<20>DMI_RXN3<20>
DMI_RXP0<20>DMI_RXP1<20>DMI_RXP2<20>DMI_RXP3<20>
M_CLK_DDR0<13>M_CLK_DDR1<13>M_CLK_DDR2<14>M_CLK_DDR3<14>
M_CLK_DDR#0<13>M_CLK_DDR#1<13>M_CLK_DDR#2<14>M_CLK_DDR#3<14>
DDR_CS0_DIMMA#<13>DDR_CS1_DIMMA#<13>DDR_CS2_DIMMB#<14>DDR_CS3_DIMMB#<14>
DDR_CKE0_DIMMA<13>DDR_CKE1_DIMMA<13>DDR_CKE2_DIMMB<14>DDR_CKE3_DIMMB<14>
M_ODT0<13>M_ODT1<13>M_ODT2<14>M_ODT3<14>
PM_BMBUSY#<20>
H_THERMTRIP#<4,19>
PLT_RST#<16,18,19,20,22,24,30>
MCH_ICH_SYNC#<18>
V_DDR_MCH_REF<13,14,41>
MCH_CLKSEL0 <15>
CFG5 <11>
CFG7 <11>
CFG9 <11>
CFG11 <11>CFG12 <11>CFG13 <11>
MCH_CLKSEL2 <15>MCH_CLKSEL1 <15>
CFG16 <11>
CFG18 <11>CFG19 <11>CFG20 <11>
CLK_MCH_3GPLL <15>CLK_MCH_3GPLL# <15>
VGATE_INTEL<20,42>PM_POK<20,30>
DPRSLPVR<20,42>
CLKREQC# <15>
CLK_MCH_REF# <15>CLK_MCH_REF <15>
CLK_MCH_SS# <15>CLK_MCH_SS <15>
DDR_THERM#<13,14>
+VCCP
+VCCP+VCCP
+VCCP
+3VS
+1.8V
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (1/6)
7 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Layout Note:H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /H_SWNG1 trace width and spacing is 18/20.
Layout Note:Route as shortas possible
Description at page11.
Stuff R1202 & R1203 for A1 Calistoga
Layout Note: V_DDR_MCH_REFtrace width andspacing is 20/20.
LH_XSCOMP/H_YSCOMP tracewidth and spacing is 5/20.
R1205
10K_0402_5%
12
DM
ID
DR
MU
CFG
PM
CLK
NC
RES
ERVE
D
U15B
CALISTOGA_FCBGA1466~D
DMIRXN0AE35DMIRXN1AF39DMIRXN2AG35DMIRXN3AH39
DMIRXP0AC35DMIRXP1AE39DMIRXP2AF35DMIRXP3AG39
DMITXN0AE37DMITXN1AF41DMITXN2AG37DMITXN3AH41
DMITXP0AC37DMITXP1AE41DMITXP2AF37DMITXP3AG41
SM_CK0AY35SM_CK1AR1SM_CK2AW7SM_CK3AW40
SM_CK0#AW35SM_CK1#AT1SM_CK2#AY7SM_CK3#AY40
SM_OCDCOMP0AL20SM_OCDCOMP1AF10
SM_ODT0BA13SM_ODT1BA12SM_ODT2AY20SM_ODT3AU21
SM_RCOMPNAV9SM_RCOMPPAT9
SM_VREF0AK1SM_VREF1AK41
SM_CKE0AU20SM_CKE1AT20SM_CKE2BA29SM_CKE3AY29
SM_CS0#AW13SM_CS1#AW12SM_CS2#AY21SM_CS3#AW21
CFG16 G18
CFG1 K18CFG2 J18CFG3 F18CFG4 E15CFG5 F15CFG6 E18CFG7 D19CFG8 D16CFG9 G16
CFG10 E16CFG11 D15CFG12 G15CFG13 K15CFG14 C15CFG15 H16
CFG0 K16
CFG17 H15CFG18 J25CFG19 K27CFG20 J26
G_CLKP AG33G_CLKN AF33
D_REF_CLKN A27D_REF_CLKP A26
D_REF_SSCLKN C40D_REF_SSCLKP D41
NC0 A3NC1 A39NC2 A4NC3 A40NC4 AW1NC5 AW41NC6 AY1NC7 BA1NC8 BA2NC9 BA3
NC10 BA39NC11 BA40NC12 BA41NC13 C1NC14 AY41NC15 B2NC16 B41NC17 C41NC18 D1
PM_BMBUSY#G28PM_EXTTS0#F25PM_EXTTS1#H26PM_THERMTRIP#G6PWROKAH33RSTIN#AH34
RESERVED1 T32RESERVED2 R32RESERVED3 F3RESERVED4 F7RESERVED5 AG11RESERVED6 AF11RESERVED7 H7RESERVED8 J19RESERVED9 A41
RESERVED10 A34RESERVED11 D28RESERVED12 D27RESERVED13 A35
ICH_SYNC#K28
CLK_REQ# H32
T74PAD
R1204
100_0402_1%@
12
R1194 80.6_0402_1%
1 2
R1344
0_0402_5%1 2
R12
08
100_
0402
_1%
12
HOST
U15A
CALISTOGA_FCBGA1466~D
HD0#F1HD1#J1HD2#H1HD3#J6HD4#H3HD5#K2HD6#G1HD7#G2HD8#K9HD9#K1HD10#K7HD11#J8HD12#H4HD13#J3HD14#K11HD15#G4HD16#T10HD17#W11HD18#T3HD19#U7HD20#U9HD21#U11HD22#T11HD23#W9HD24#T1HD25#T8HD26#T4HD27#W7HD28#U5HD29#T9HD30#W6HD31#T5HD32#AB7HD33#AA9HD34#W4HD35#W3HD36#Y3HD37#Y7HD38#W5HD39#Y10HD40#AB8HD41#W2HD42#AA4HD43#AA7HD44#AA2HD45#AA6HD46#AA10HD47#Y8HD48#AA1HD49#AB4HD50#AC9HD51#AB11HD52#AC11HD53#AB3HD54#AC2HD55#AD1HD56#AD9HD57#AC1HD58#AD7HD59#AC6HD60#AB5HD61#AD10HD62#AD4HD63#AC8
HVREF1K13HXRCOMPE1HXSCOMPE2HYRCOMPY1HYSCOMPU1HXSWINGE4HYSWINGW1
HA3# H9HA4# C9HA5# E11HA6# G11HA7# F11HA8# G12HA9# F9
HA10# H11HA11# J12HA12# G14HA13# D9HA14# J14HA15# H13HA16# J15HA17# F14HA18# D12HA19# A11HA20# C11HA21# A12HA22# A13HA23# E13HA24# G13HA25# F12HA26# B12HA27# B14HA28# C12HA29# A14HA30# C14HA31# D14
HREQ#0 D8HREQ#1 G8HREQ#2 B8HREQ#3 F8HREQ#4 A8
HADSTB#0 B9HADSTB#1 C13
HRS0# B4HRS1# E6HRS2# D6
HCLKN AG1HCLKP AG2
HDINV#0 J7HDINV#1 W8HDINV#2 U3HDINV#3 AB10
HDSTBN#0 K4HDSTBN#1 T7HDSTBN#2 Y5HDSTBN#3 AC4HDSTBP#0 K3HDSTBP#1 T6HDSTBP#2 AA5HDSTBP#3 AC5
HCPURST# B7HADS# E8
HTRDY# E7HDPWR# J9HDRDY# H8
HDEFER# C3HHITM# D4
HHIT# D3HLOCK# B3
HBREQ0# C7HBNR# C6HBPRI# F6
HDBSY# A7HCPUSLP# E3
HVREF0J13
R12
0240
.2_0
402_
1%
@
12
C89
60.
1U_0
402_
16V4
Z
1
2
R12
10
100_
0402
_1%
12
C89
70.
1U_0
402_
16V4
Z
1
2
R1304 0_0402_5%@1 2
T76PAD
R1201
100_0402_1%@
12
R1209
10K_0402_5%@ 12
R1305 0_0402_5%1 2
R12
0340
.2_0
402_
1%
@
12
T73PAD
T77PAD
C89
50.
1U_0
402_
16V4
Z
1
2
R11
9654
.9_0
402_
1%
12
R12
11
100_
0402
_1%
12
T78PAD
R12
0024
.9_0
402_
1%
12
R1309 0_0402_5%1 2
R12
12
200_
0402
_1%
12
R11
9924
.9_0
402_
1%
12
R12
06
221_
0603
_1%
12
T72PAD
R12
07
221_
0603
_1%
12
R11
9754
.9_0
402_
1%
12
R1198 100_0402_1%
12
T75PAD
C89
8
0.1U
_040
2_16
V4Z
1
2
R1195 80.6_0402_1%
1 2
T79PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D11
DDR_B_D57
DDR_B_D46
DDR_B_D7
DDR_B_D0
DDR_B_D44
DDR_B_D40
DDR_B_D30
DDR_B_D27
DDR_B_D15
DDR_B_D3
DDR_B_D35
DDR_B_D25
DDR_B_D23
DDR_B_D49
DDR_B_D37
DDR_B_D19
DDR_B_D48DDR_B_D47
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D62
DDR_B_D60
DDR_B_D9
DDR_B_D2
DDR_B_D52
DDR_B_D50
DDR_B_D22
DDR_B_D56
DDR_B_D51
DDR_B_D39
DDR_B_D28
DDR_B_D17
DDR_B_D45
DDR_B_D6
DDR_B_D61
DDR_B_D58
DDR_B_D1
DDR_B_D54
DDR_B_D41
DDR_B_D31
DDR_B_D12
DDR_B_D5
DDR_B_D38
DDR_B_D32
DDR_B_D20
DDR_B_D16
DDR_B_D14
DDR_B_D33
DDR_B_D63
DDR_B_D59
DDR_B_D42
DDR_B_D55
DDR_B_D53
DDR_B_D43
DDR_B_D29
DDR_B_D26
DDR_B_D13
DDR_B_D4
DDR_B_BS#2
DDR_B_D34
DDR_B_D24
DDR_B_D21
DDR_B_D10
DDR_B_WE#DDR_B_RAS#
DDR_A_D35
DDR_A_D15DDR_A_D14
DDR_A_D21
DDR_A_BS#2
DDR_A_D28
DDR_A_D11
DDR_A_D7
DDR_A_WE#
DDR_A_D31
DDR_A_D16
DDR_A_D59
DDR_A_D56
DDR_A_D42
DDR_A_D25
DDR_A_D9
DDR_A_D60
DDR_A_D55
DDR_A_D13
DDR_A_D0
DDR_A_D62
DDR_A_D3
DDR_A_D1
DDR_A_D41
DDR_A_D20
DDR_A_D43
DDR_A_D24
DDR_A_CAS#
DDR_A_D54
DDR_A_D52
DDR_A_D33
DDR_A_D12
DDR_A_D19
DDR_A_D46
DDR_A_D23
DDR_A_D18
DDR_A_D63
DDR_A_D34
DDR_A_D26
DDR_A_D22
SA_RCVENIN#SA_RCVENOUT#
SB_RCVENIN#SB_RCVENOUT#
DDR_A_D27
DDR_A_D2
DDR_A_D32
DDR_A_D6
DDR_A_D49
DDR_A_D47
DDR_A_D58
DDR_A_D40
DDR_A_D36
DDR_A_D5
DDR_A_D48
DDR_A_D10
DDR_A_D8
DDR_A_D57
DDR_A_D39
DDR_A_D37
DDR_A_D30
DDR_A_D4
DDR_A_D45
DDR_A_D53
DDR_A_D51
DDR_A_D17
DDR_A_D38
DDR_A_D29
DDR_A_D44
DDR_A_D50
DDR_A_D61
DDR_A_DQS6DDR_B_DQS7
DDR_B_MA9
DDR_A_MA13
DDR_A_MA7
DDR_A_DM1
DDR_A_MA5
DDR_A_DM7
DDR_B_MA0
DDR_A_DQS7
DDR_A_DM5
DDR_B_MA7
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DM3
DDR_B_DQS1
DDR_B_DM1
DDR_A_BS#0
DDR_A_DQS#6
DDR_B_DQS5
DDR_B_DM0
DDR_A_MA4
DDR_A_MA8
DDR_A_DQS#7
DDR_A_MA10
DDR_A_DQS5
DDR_A_DM2
DDR_A_DQS0
DDR_B_MA2
DDR_B_MA13
DDR_B_DM5
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_BS#1
DDR_A_DQS#1
DDR_A_MA2
DDR_B_MA4
DDR_A_DQS#5
DDR_B_DM6
DDR_B_DQS4
DDR_A_DQS1
DDR_A_MA9
DDR_A_DQS4
DDR_A_DM0
DDR_A_MA0
DDR_B_MA5
DDR_A_DM4
DDR_A_DQS#2
DDR_A_DQS3
DDR_B_MA3
DDR_A_MA11 DDR_B_MA11
DDR_B_BS#0
DDR_A_DM6
DDR_B_MA6DDR_A_MA6
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_DQS#0
DDR_A_DM3
DDR_A_MA3
DDR_A_MA12
DDR_B_MA8
DDR_A_DQS2
DDR_B_DQS#0
DDR_B_MA10
DDR_B_DM7
DDR_A_MA1
DDR_B_MA12
DDR_B_DQS#2
DDR_B_DM4
DDR_B_DQS#6
DDR_B_MA1
DDR_B_DQS2
DDR_B_DQS6
DDR_B_DM2
DDR_A_DQS#3DDR_A_DQS#4
DDR_A_RAS#DDR_B_CAS#
DDR_A_BS#1DDR_A_BS#0<13>DDR_A_BS#1<13>DDR_A_BS#2<13>
DDR_A_DM[0..7]<13>
DDR_A_DQS[0..7]<13>
DDR_A_DQS#[0..7]<13>
DDR_A_MA[0..13]<13>
DDR_A_CAS#<13>DDR_A_RAS#<13>DDR_A_WE#<13>
DDR_B_BS#0<14>DDR_B_BS#1<14>DDR_B_BS#2<14>
DDR_B_DM[0..7]<14>
DDR_B_DQS[0..7]<14>
DDR_B_DQS#[0..7]<14>
DDR_B_MA[0..13]<14>
DDR_B_CAS#<14>DDR_B_RAS#<14>DDR_B_WE#<14>
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (2/6)
8 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
T71 PADT68 PAD
DDR SYS MEMORY B
U15E
CALISTOGA_FCBGA1466~D
SB_DQ0 AK39SB_DQ1 AJ37SB_DQ2 AP39SB_DQ3 AR41SB_DQ4 AJ38SB_DQ5 AK38SB_DQ6 AN41SB_DQ7 AP41SB_DQ8 AT40SB_DQ9 AV41
SB_DQ10 AU38SB_DQ11 AV38SB_DQ12 AP38SB_DQ13 AR40SB_DQ14 AW38SB_DQ15 AY38SB_DQ16 BA38SB_DQ17 AV36SB_DQ18 AR36SB_DQ19 AP36SB_DQ20 BA36SB_DQ21 AU36SB_DQ22 AP35SB_DQ23 AP34SB_DQ24 AY33SB_DQ25 BA33SB_DQ26 AT31SB_DQ27 AU29SB_DQ28 AU31SB_DQ29 AW31SB_DQ30 AV29SB_DQ31 AW29SB_DQ32 AM19SB_DQ33 AL19SB_DQ34 AP14SB_DQ35 AN14SB_DQ36 AN17SB_DQ37 AM16SB_DQ38 AP15SB_DQ39 AL15SB_DQ40 AJ11SB_DQ41 AH10SB_DQ42 AJ9SB_DQ43 AN10SB_DQ44 AK13SB_DQ45 AH11SB_DQ46 AK10SB_DQ47 AJ8SB_DQ48 BA10SB_DQ49 AW10SB_DQ50 BA4SB_DQ51 AW4SB_DQ52 AY10SB_DQ53 AY9SB_DQ54 AW5SB_DQ55 AY5SB_DQ56 AV4SB_DQ57 AR5SB_DQ58 AK4SB_DQ59 AK3SB_DQ60 AT4SB_DQ61 AK5SB_DQ62 AJ5SB_DQ63 AJ3
SB_BS0AT24SB_BS1AV23SB_BS2AY28
SB_CAS#AR24SB_RAS#AU23SB_WE#AR27SB_RCVENIN#AK16SB_RCVENOUT#AK18
SB_DM0AK36SB_DM1AR38SB_DM2AT36SB_DM3BA31SB_DM4AL17SB_DM5AH8SB_DM6BA5SB_DM7AN4
SB_DQS0AM39SB_DQS1AT39SB_DQS2AU35SB_DQS3AR29SB_DQS4AR16SB_DQS5AR10SB_DQS6AR7SB_DQS7AN5
SB_DQS0#AM40SB_DQS1#AU39SB_DQS2#AT35SB_DQS3#AP29SB_DQS4#AP16SB_DQS5#AT10SB_DQS6#AT7SB_DQS7#AP5
SB_MA0AY23SB_MA1AW24SB_MA2AY24SB_MA3AR28SB_MA4AT27SB_MA5AT28SB_MA6AU27SB_MA7AV28SB_MA8AV27SB_MA9AW27SB_MA10AV24SB_MA11BA27SB_MA12AY27SB_MA13AR23
DDR SYS MEMORY A
U15D
CALISTOGA_FCBGA1466~D
SA_DQ0 AJ35SA_DQ1 AJ34SA_DQ2 AM31SA_DQ3 AM33SA_DQ4 AJ36SA_DQ5 AK35SA_DQ6 AJ32SA_DQ7 AH31SA_DQ8 AN35SA_DQ9 AP33
SA_DQ10 AR31SA_DQ11 AP31SA_DQ12 AN38SA_DQ13 AM36SA_DQ14 AM34SA_DQ15 AN33SA_DQ16 AK26SA_DQ17 AL27SA_DQ18 AM26SA_DQ19 AN24SA_DQ20 AK28SA_DQ21 AL28SA_DQ22 AM24SA_DQ23 AP26SA_DQ24 AP23SA_DQ25 AL22SA_DQ26 AP21SA_DQ27 AN20SA_DQ28 AL23SA_DQ29 AP24SA_DQ30 AP20SA_DQ31 AT21SA_DQ32 AR12SA_DQ33 AR14SA_DQ34 AP13SA_DQ35 AP12SA_DQ36 AT13SA_DQ37 AT12SA_DQ38 AL14SA_DQ39 AL12SA_DQ40 AK9SA_DQ41 AN7SA_DQ42 AK8SA_DQ43 AK7SA_DQ44 AP9SA_DQ45 AN9SA_DQ46 AT5SA_DQ47 AL5SA_DQ48 AY2SA_DQ49 AW2SA_DQ50 AP1SA_DQ51 AN2SA_DQ52 AV2SA_DQ53 AT3SA_DQ54 AN1SA_DQ55 AL2SA_DQ56 AG7SA_DQ57 AF9SA_DQ58 AG4SA_DQ59 AF6SA_DQ60 AG9SA_DQ61 AH6SA_DQ62 AF4SA_DQ63 AF8
SA_BS0AU12SA_BS1AV14SA_BS2BA20
SA_CAS#AY13SA_RAS#AW14SA_WE#AY14SA_RCVENIN#AK23SA_RCVENOUT#AK24
SA_DM0AJ33SA_DM1AM35SA_DM2AL26SA_DM3AN22SA_DM4AM14SA_DM5AL9SA_DM6AR3SA_DM7AH4
SA_DQS0AK33SA_DQS1AT33SA_DQS2AN28SA_DQS3AM22SA_DQS4AN12SA_DQS5AN8SA_DQS6AP3SA_DQS7AG5
SA_DQS0#AK32SA_DQS1#AU33SA_DQS2#AN27SA_DQS3#AM21SA_DQS4#AM12SA_DQS5#AL8SA_DQS6#AN3SA_DQS7#AH5
SA_MA0AY16SA_MA1AU14SA_MA2AW16SA_MA3BA16SA_MA4BA17SA_MA5AU16SA_MA6AV17SA_MA7AU17SA_MA8AW17SA_MA9AT16SA_MA10AU13SA_MA11AT17SA_MA12AV20SA_MA13AV12
T69 PADT70 PAD
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEGCOMP
C_VSYNCC_HSYNC
C_LUMAC_COMP
C_CRMA
C_GRN
C_RED
C_BLU
CRT_IREF
LIBGENAVDD
LCD_CLKLCD_DAT
BKLT_CTLENABLT
LCD_CLKLCD_DAT
PEG_RXP1
PEG_TXP0PEG_TXP1PEG_TXP2PEG_TXP3
PEG_TXN0PEG_TXN1PEG_TXN2PEG_TXN3
C_GRN_LC_GRN
C_RED_L
C_BLU_LC_BLU
C_CRMA
C_COMP
C_LUMA
PEG_RXN1
C_VSYNCC_HSYNC
C_RED
TXCLK_U-<17>TXCLK_U+<17>
TXCLK_L+<17>TXCLK_L-<17>
C_DDCCLK<16>C_DDCDATA<16>
C_VSYNC<16>C_HSYNC<16>
LCD_CLK<17>LCD_DAT<17>
BKLT_CTL<17>ENABLT<17>
INTEL_BLUE <32>
INTEL_RED <32>
INTEL_GREEN <32>
LUMA <16,32>
CRMA <16,32>
COMP <16,32>
SDVOB_R- <16>SDVOB_G- <16>SDVOB_B- <16>SDVOB_CLK- <16>
SDVOB_R+ <16>SDVOB_G+ <16>
SDVOB_CLK+ <16>SDVOB_B+ <16>
SDVO_SCLK<16>SDVO_SDAT<16>
TXOUT_U2+<17>
TXOUT_U2-<17>TXOUT_U1-<17>
TXOUT_U1+<17>TXOUT_U0+<17>
TXOUT_U0-<17>
TXOUT_L2-<17>
TXOUT_L2+<17>TXOUT_L1+<17>
TXOUT_L1-<17>TXOUT_L0-<17>
TXOUT_L0+<17>
ENAVDD<17>
PEG_RXP1 <16>
PEG_RXN1 <16>
+1.5VS_PCIE
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (3/6)
9 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
PEGCOMP trace widthand spacing is 18/25 mils.
TV-Out Termination/EMI FilterCRT Termination/EMI Filter
C7
82P_0402_50V8J
1
2
C1065 0.1U_0402_16V4Z1 2
C232
12P_0402_50V8J
1
2R174
75_0402_1%
12
R390255_0402_1%
12
C333
82P_0402_50V8J
1
2
C193
12P_0402_50V8J
1
2
R351 1.5K_0402_1%12
C237
12P_0402_50V8J
1
2
LVDS
TVC
RT
PCI-EXPRESS GRAPHICS
U15C
CALISTOGA_FCBGA1466~D<BOM Structure>
SDVOCTRL_CLKH28 SDVOCTRL_DATAH27
LA_DATA0B37LA_DATA1B34LA_DATA2A36
LVREFHC33LVREFLC32
TVDAC_AA16TVDAC_BC18TVDAC_CA19
TV_IREFJ20
TV_IRTNAB16TV_IRTNBB18TV_IRTNCB19
DDCCLKC26DDCDATAC25
LA_DATA#0C37LA_DATA#1B35LA_DATA#2A37
LB_DATA0F30LB_DATA1D29LB_DATA2F28
LB_DATA#0G30LB_DATA#1D30LB_DATA#2F29
LA_CLKA32LA_CLK#A33LB_CLKE26LB_CLK#E27
LBKLT_CTLD32LBKLT_ENJ30LCTLA_CLKH30LCTLB_DATAH29LDDC_CLKG26LDDC_DATAG25LVDD_ENF32LIBGB38LVBGC35
VSYNCH23HSYNCG23BLUEE23BLUE#D23GREENC22GREEN#B22REDA21RED#B21
CRT_IREFJ22
EXP_COMPI D40EXP_COMPO D38
EXP_RXN0 F34EXP_RXN1 G38EXP_RXN2 H34EXP_RXN3 J38EXP_RXN4 L34EXP_RXN5 M38EXP_RXN6 N34EXP_RXN7 P38EXP_RXN8 R34EXP_RXN9 T38
EXP_RXN10 V34EXP_RXN11 W38EXP_RXN12 Y34EXP_RXN13 AA38EXP_RXN14 AB34EXP_RXN15 AC38
EXP_RXP0 D34EXP_RXP1 F38EXP_RXP2 G34EXP_RXP3 H38EXP_RXP4 J34EXP_RXP5 L38EXP_RXP6 M34EXP_RXP7 N38EXP_RXP8 P34EXP_RXP9 R38
EXP_RXP10 T34EXP_RXP11 V38EXP_RXP12 W34EXP_RXP13 Y38EXP_RXP14 AA34EXP_RXP15 AB38
EXP_TXN0 F36EXP_TXN1 G40EXP_TXN2 H36EXP_TXN3 J40EXP_TXN4 L36EXP_TXN5 M40EXP_TXN6 N36EXP_TXN7 P40EXP_TXN8 R36EXP_TXN9 T40
EXP_TXN10 V36EXP_TXN11 W40EXP_TXN12 Y36EXP_TXN13 AA40EXP_TXN14 AB36EXP_TXN15 AC40
EXP_TXP0 D36EXP_TXP1 F40EXP_TXP2 G36EXP_TXP3 H40EXP_TXP4 J36EXP_TXP5 L40EXP_TXP6 M36EXP_TXP7 N40EXP_TXP8 P36EXP_TXP9 R40
EXP_TXP10 T36EXP_TXP11 V40EXP_TXP12 W36EXP_TXP13 Y40EXP_TXP14 AA36EXP_TXP15 AB40
TV_DCONSEL1J29TV_DCONSEL0K30
L37CHB1608U301_0603
1 2
R173
75_0402_1%
12
R910K_0402_5%
12
R39
34.
99K_
0603
_1% 1
2
C1049 0.1U_0402_16V4Z1 2
L26
MCI1608HQ39NJA_06031 2
C1046 0.1U_0402_16V4Z1 2
C251
82P_0402_50V8J
1
2
L34
MCI1608HQ39NJA_06031 2
L28
0_0603_5%1 2
R117624.9_0402_1%
1 2
C354
82P_0402_50V8J
1
2
C1045 0.1U_0402_16V4Z1 2
C1050 0.1U_0402_16V4Z1 2
C355
82P_0402_50V8J
1
2
C1047 0.1U_0402_16V4Z1 2
L17CHB1608U301_0603
1 2
R177
75_0402_1%
12
L35
0_0603_5%1 2
L31
MCI1608HQ39NJA_06031 2
L38CHB1608U301_0603
1 2
C1051 0.1U_0402_16V4Z1 2
R171
75_0402_1%
12
R175
75_0402_1%
12
C238
82P_0402_50V8J
1
2
R1010K_0402_5%
12
D67
PACDN042_SOT23~D@
231
L27
0_0603_5%1 2
R176
75_0402_1%
12
C1048 0.1U_0402_16V4Z1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MCH_D2
MCH_A6
MC
H_A
B1
3GPLL
MCH_CRTDAC
+1.5VS
+1.5VS_PCIE
+1.5VS
+1.5VS+1.5VS_3GPLL
+3VS
+1.5VS_MPLL
+1.5VS
+1.5VS_3GPLL
+1.5VS
+VCCP
+1.5VS_MPLL +1.5VS_HPLL
+1.5VS+1.5VS
+2.5VS
+2.5VS
+2.5VS
+1.5VS_TVDAC
+2.5VS
+2.5VS
+1.5VS_DPLLB+1.5VS_DPLLA
+1.5VS_HPLL
+3VS_TVBG
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC
+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC
+1.5VS_DPLLA +1.5VS_DPLLB
+1.5VS+1.5VS
+1.5VS_DPLLA +1.5VS_DPLLB
+3VS+3VS_TVBG
+1.5VS_TVDAC +1.5VS
+VCCP
+2.5VS +3VS
+1.5VS
+2.5VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (4/6)
10 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
W=40 mils
45mA Max. 45mA Max.
PCI-E/MEM/PSB PLL decoupling
Place close to Pin G41
L40CHB1608U301_0603@
12
C839
10U_0805_6.3V6M
1
2
C15
10.
1U_0
402_
16V
4Z
1
2
C14
522
00P
_040
2_50
V7K
1
2
R1339
0.5_0805_1%1 2
+ C666
330U_D
2E_2.5V
M
@
1
2
C83
64.
7U_0
805_
10V
4Z
1
2
P O W E R
U15H
CALISTOGA_FCBGA1466~D
VCC_SYNC H22
VCCTX_LVDS0 B30VCCTX_LVDS1 C30
VCC3G0 AB41VCC3G1 AJ41VCC3G2 L41VCC3G3 N41VCC3G4 R41VCC3G5 V41VCC3G6 Y41
VCCA_3GBG G41VSSA_3GBG H41
VCCA_3GPLL AC33
VCCTX_LVDS2 A30
VCCA_LVDS A38VSSA_LVDS B39
VCCA_MPLL AF2
VCCA_TVBG H20VSSA_TVBG G20
VCCA_TVDACA0 E19VCCA_TVDACA1 F19VCCA_TVDACB0 C20VCCA_TVDACB1 D20VCCA_TVDACC0 E20VCCA_TVDACC1 F20
VCCAUX1 AF31VCCAUX2 AE31VCCAUX3 AC31VCCAUX4 AL30VCCAUX5 AK30VCCAUX6 AJ30VCCAUX7 AH30VCCAUX8 AG30VCCAUX9 AF30
VCCAUX10 AE30VCCAUX11 AD30VCCAUX12 AC30VCCAUX13 AG29VCCAUX14 AF29VCCAUX15 AE29VCCAUX16 AD29VCCAUX17 AC29VCCAUX18 AG28VCCAUX19 AF28VCCAUX20 AE28
VTT0AC14VTT1AB14VTT2W14VTT3V14VTT4T14VTT5R14VTT6P14VTT7N14VTT8M14VTT9L14VTT10AD13VTT11AC13VTT12AB13VTT13AA13VTT14Y13VTT15W13VTT16V13VTT17U13VTT18T13VTT19R13VTT20N13VTT21M13VTT22L13VTT23AB12VTT24AA12VTT25Y12VTT26W12VTT27V12VTT28U12VTT29T12VTT30R12VTT31P12VTT32N12VTT33M12VTT34L12VTT35R11VTT36P11VTT37N11VTT38M11VTT39R10VTT40P10VTT41N10VTT42M10VTT43P9VTT44N9VTT45M9VTT46R8VTT47P8VTT48N8VTT49M8VTT50P7VTT51N7VTT52M7VTT53R6VTT54P6VTT55M6VTT56A6VTT57R5
VTT59N5VTT60M5VTT61P4VTT62N4VTT63M4VTT64R3VTT65P3VTT66N3VTT67M3VTT68R2VTT69P2VTT70M2VTT71D2VTT72AB1VTT73R1VTT74P1VTT75N1VTT76M1
VCCA_CRTDAC0 E21VCCA_CRTDAC1 F21VSSA_CRTDAC2 G21
VCCA_DPLLA B26VCCA_DPLLB C39
VCCA_HPLL AF1
VCCD_HMPLL0 AH1VCCD_HMPLL1 AH2
VCCD_LVDS0 A28VCCD_LVDS1 B28VCCD_LVDS2 C28
VCCD_TVDAC D21VCCDQ_TVDAC H19
VCCHV0 A23VCCHV1 B23 VCCHV2 B25
VCCAUX21 AH22VCCAUX22 AJ21VCCAUX23 AH21VCCAUX24 AJ20VCCAUX25 AH20VCCAUX26 AH19VCCAUX27 P19VCCAUX28 P16VCCAUX29 AH15VCCAUX30 P15VCCAUX31 AH14
VCCAUX32AG14VCCAUX33AF14VCCAUX34AE14VCCAUX35Y14VCCAUX36AF13VCCAUX37AE13VCCAUX38AF12VCCAUX39AE12VCCAUX40AD12
VCCAUX0 AK31
VTT58P5
C15
222
00P
_040
2_50
V7K
1
2
C14
60.
1U_0
402_
16V
4Z
1
2
R1168
0_0805_5%12
L41CHB1608U301_0603
12
C14
30.
1U_0
402_
16V
4Z
1
2
R61
0_0805_5%12
C14
90.
1U_0
402_
16V
4Z
1
2
C84
40.
47U
_060
3_10
V7K
1
2
C83
80.
1U_0
402_
16V
4Z
1
2
D12CH751H-40_SOD323@
12
C84
50.
1U_0
402_
16V
4Z
1
2
C15
422
00P
_040
2_50
V7K
1
2
C14
422
00P
_040
2_50
V7K
1
2
+
C83
022
0U_D
2_2V
M_R
9
1
2
C846
10U_0805_6.3V6M
1
2
C86
1
0.1U
_040
2_16
V4Z
1
2
R1173
0_0805_5%12
R11630_0805_5%
12
C84
10.
1U_0
402_
16V
4Z
@
1
2
C85
00.
1U_0
402_
16V
4Z 1
2
R2600_1206_5%
1 2
R115
0_0805_5%12
+
C981220U_D2_2VM_R9
1
2
R1180_0603_5%
12
D21CH751H-40_SOD323@
12
C84
90.
22U
_060
3_10
V7K
1
2
L39BLM11A601S_0603
1 2
+
C616
330U_D
2E_2.5V
M
1
2
C83
10.
1U_0
402_
16V
4Z
1
2
C825
10U_0805_6.3V6M
1
2
C15
522
00P
_040
2_50
V7K
1
2
C85
30.
22U
_060
3_10
V7K
1
2
C15
30.
1U_0
402_
16V
4Z
1
2
C860
10U_0805_6.3V6M
1
2
C158
0.1U_0402_16V
4Z
1
2
R127
10_0402_5%@
12
C85
9
0.1U
_040
2_16
V4Z
1
2
C862
10U_0805_6.3V6M
1
2
R179
0_0805_5% 12
C17
20.
1U_0
402_
16V
4Z
@
1
2
C85
60.
47U
_060
3_10
V7K
1
2
C824
10U_0805_6.3V6M
1
2
R1174
0_0805_5%12
C253
0.1U_0402_16V
4Z
1
2
R520
10_0402_5%@
12
R97
0_0805_5%12
C1620.1U_0402_16V4Z
1 2
C15
70.
1U_0
402_
16V
4Z
1
2
C83
72.
2U_0
805_
16V
4Z
1
2
C61
422
00P
_040
2_50
V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSM_LF1VCCSM_LF2
VCCSM_LF5VCCSM_LF4
CFG18<7>
CFG13<7>
CFG19<7>
CFG16<7>
CFG9<7>
CFG20<7>
CFG11<7>
CFG12<7>
CFG5<7>
CFG7<7>
+VCCP+1.5VS+VCCP
+1.8V+VCCP
+1.8V
+3VS
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (5/6)
11 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place near pin BA15
Place near pin BA23
Place near pin AT41 & AM41
Place near pin AV1 & AJ1
CFG[13:12]
1 = PCIE/SDVO are operatingsimu.
CFG7
CFG19
(Default)
CFG20
0 = DMI x 2
CFG18
CFG[19:18] have internal pull down
*
Strap Pin Table
*
10 = All Z Mode Enabled
0 = Reserved
(Default)
1 = Normal Operation
CFG5
SDVO_CTRLDATA
*
1 = DMI Lane Reversal Enable
(Default)
*
1 = Dynamic ODT Enabled (Default)
*
(Default)
00 = Reserved
1 = 1.5V
**
1 = DMI x 4
CFG[3:17] have internal pull up
0 = No SDVO Device Present
(Default)
*
*
(Default)
(Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO isoperational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
001 = 533MT/s FSB
CFG16
0 = 1.05V
011 = 667MT/s FSB
0 = Lane Reversal Enable CFG9
1 = SDVO Device Present
CFG[2:0]
1 = Mobile Yonah CPU
11 = Normal Operation
CFG11
0 = Calistoga
1 = Reserved
*(According to Intel Napa Schematic Checklist & CRB Rev1.301 document 2.2Kohm pull-down resistor request)
C80
70.
47U
_060
3_10
V7K
1
2
P O W E R
U15G
CALISTOGA_FCBGA1466~D
VCC0AA33VCC1W33VCC2P33VCC3N33VCC4L33VCC5J33VCC6AA32VCC7Y32VCC8W32VCC9V32VCC10P32VCC11N32VCC12M32VCC13L32VCC14J32VCC15AA31VCC16W31VCC17V31VCC18T31VCC19R31VCC20P31VCC21N31VCC22M31VCC23AA30VCC24Y30VCC25W30VCC26V30VCC27U30VCC28T30VCC29R30VCC30P30VCC31N30VCC32M30VCC33L30VCC34AA29VCC35Y29VCC36W29VCC37V29VCC38U29VCC39R29VCC40P29VCC41M29VCC42L29VCC43AB28VCC44AA28VCC45Y28
VCC_SM5 AY34VCC_SM6 AW34VCC_SM7 AV34VCC_SM8 AU34VCC_SM9 AT34
VCC_SM10 AR34VCC_SM11 BA30VCC_SM12 AY30VCC_SM13 AW30VCC_SM14 AV30VCC_SM15 AU30VCC_SM16 AT30VCC_SM17 AR30VCC_SM18 AP30VCC_SM19 AN30VCC_SM20 AM30VCC_SM21 AM29VCC_SM22 AL29VCC_SM23 AK29VCC_SM24 AJ29VCC_SM25 AH29VCC_SM26 AJ28VCC_SM27 AH28VCC_SM28 AJ27VCC_SM29 AH27VCC_SM30 BA26VCC_SM31 AY26VCC_SM32 AW26VCC_SM33 AV26VCC_SM34 AU26VCC_SM35 AT26VCC_SM36 AR26VCC_SM37 AJ26VCC_SM38 AH26VCC_SM39 AJ25VCC_SM40 AH25VCC_SM41 AJ24VCC_SM42 AH24VCC_SM43 BA23VCC_SM44 AJ23VCC_SM45 BA22VCC_SM46 AY22VCC_SM47 AW22VCC_SM48 AV22VCC_SM49 AU22VCC_SM50 AT22VCC_SM51 AR22VCC_SM52 AP22VCC_SM53 AK22VCC_SM54 AJ22VCC_SM55 AK21VCC_SM56 AK20VCC_SM57 BA19VCC_SM58 AY19VCC_SM59 AW19VCC_SM60 AV19VCC_SM61 AU19VCC_SM62 AT19VCC_SM63 AR19VCC_SM64 AP19VCC_SM65 AK19VCC_SM66 AJ19VCC_SM67 AJ18VCC_SM68 AJ17VCC_SM69 AH17VCC_SM70 AJ16VCC_SM71 AH16VCC_SM72 BA15
VCC_SM3 AU40VCC_SM4 BA34
VCC_SM73 AY15VCC_SM74 AW15VCC_SM75 AV15VCC_SM76 AU15VCC_SM77 AT15VCC_SM78 AR15VCC_SM79 AJ15VCC_SM80 AJ14VCC_SM81 AJ13VCC_SM82 AH13VCC_SM83 AK12VCC_SM84 AJ12VCC_SM85 AH12VCC_SM86 AG12VCC_SM87 AK11VCC_SM88 BA8VCC_SM89 AY8VCC_SM90 AW8VCC_SM91 AV8VCC_SM92 AT8VCC_SM93 AR8VCC_SM94 AP8VCC_SM95 BA6VCC_SM96 AY6VCC_SM97 AW6VCC_SM98 AV6VCC_SM99 AT6
VCC_SM1 AT41VCC_SM0 AU41
VCC_SM2 AM41
VCC46V28VCC47U28VCC48T28VCC49R28VCC50P28VCC51N28VCC52M28VCC53L28VCC54P27VCC55N27VCC56M27VCC57L27VCC58P26VCC59N26VCC60L26VCC61N25VCC62M25VCC63L25VCC64P24VCC65N24VCC66M24VCC67AB23VCC68AA23VCC69Y23VCC70P23VCC71N23VCC72M23VCC73L23VCC74AC22VCC75AB22VCC76Y22VCC77W22VCC78P22VCC79N22VCC80M22VCC81L22VCC82AC21VCC83AA21VCC84W21VCC85N21VCC86M21VCC87L21VCC88AC20VCC89AB20VCC90Y20VCC91W20VCC92P20VCC93N20VCC94M20VCC95L20VCC96AB19VCC97AA19VCC98Y19VCC99N19
C79
9
0.1U
_040
2_16
V4Z
1
2
R1158 1K_0402_5%@ 1 2
P O
W E
R
U15F
CALISTOGA_FCBGA1466~D
VCC_NCTF1AC27VCC_NCTF2AB27VCC_NCTF3AA27VCC_NCTF4Y27VCC_NCTF5W27VCC_NCTF6V27VCC_NCTF7U27
VCCAUX_NCTF52 Y15
VCC_NCTF9R27VCC_NCTF10AD26VCC_NCTF11AC26VCC_NCTF12AB26VCC_NCTF13AA26VCC_NCTF14Y26VCC_NCTF15W26VCC_NCTF16V26VCC_NCTF17U26VCC_NCTF18T26VCC_NCTF19R26VCC_NCTF20AD25VCC_NCTF21AC25VCC_NCTF22AB25VCC_NCTF23AA25VCC_NCTF24Y25VCC_NCTF25W25
VCCAUX_NCTF53 W15
VCC_NCTF27U25VCC_NCTF28T25VCC_NCTF29R25VCC_NCTF30AD24VCC_NCTF31AC24VCC_NCTF32AB24VCC_NCTF33AA24VCC_NCTF34Y24VCC_NCTF35W24VCC_NCTF36V24
VCCAUX_NCTF54 V15
VCC_NCTF38T24VCC_NCTF39R24VCC_NCTF40AD23VCC_NCTF41V23VCC_NCTF42U23VCC_NCTF43T23VCC_NCTF44R23VCC_NCTF45AD22VCC_NCTF46V22VCC_NCTF47U22VCC_NCTF48T22VCC_NCTF49R22VCC_NCTF50AD21VCC_NCTF51V21VCC_NCTF52U21VCC_NCTF53T21VCC_NCTF54R21VCC_NCTF55AD20VCC_NCTF56V20VCC_NCTF57U20VCC_NCTF58T20
VCCAUX_NCTF55 U15
VCC_NCTF60AD19VCC_NCTF61V19VCC_NCTF62U19VCC_NCTF63T19VCC_NCTF64AD18VCC_NCTF65AC18VCC_NCTF66AB18VCC_NCTF67AA18VCC_NCTF68Y18VCC_NCTF69W18VCC_NCTF70V18VCC_NCTF71U18VCC_NCTF72T18
VCC_NCTF0AD27 VCCAUX_NCTF0 AG27VCCAUX_NCTF1 AF27VCCAUX_NCTF2 AG26VCCAUX_NCTF3 AF26VCCAUX_NCTF4 AG25VCCAUX_NCTF5 AF25VCCAUX_NCTF6 AG24VCCAUX_NCTF7 AF24VCCAUX_NCTF8 AG23VCCAUX_NCTF9 AF23
VCCAUX_NCTF10 AG22VCCAUX_NCTF11 AF22VCCAUX_NCTF12 AG21VCCAUX_NCTF13 AF21VCCAUX_NCTF14 AG20VCCAUX_NCTF15 AF20VCCAUX_NCTF16 AG19VCCAUX_NCTF17 AF19VCCAUX_NCTF18 R19VCCAUX_NCTF19 AG18VCCAUX_NCTF20 AF18VCCAUX_NCTF21 R18VCCAUX_NCTF22 AG17VCCAUX_NCTF23 AF17VCCAUX_NCTF24 AE17VCCAUX_NCTF25 AD17VCCAUX_NCTF26 AB17VCCAUX_NCTF27 AA17VCCAUX_NCTF28 W17VCCAUX_NCTF29 V17VCCAUX_NCTF30 T17VCCAUX_NCTF31 R17VCCAUX_NCTF32 AG16VCCAUX_NCTF33 AF16VCCAUX_NCTF34 AE16VCCAUX_NCTF35 AD16VCCAUX_NCTF36 AC16VCCAUX_NCTF37 AB16VCCAUX_NCTF38 AA16VCCAUX_NCTF39 Y16VCCAUX_NCTF40 W16VCCAUX_NCTF41 V16VCCAUX_NCTF42 U16VCCAUX_NCTF43 T16VCCAUX_NCTF44 R16VCCAUX_NCTF45 AG15VCCAUX_NCTF46 AF15VCCAUX_NCTF47 AE15VCCAUX_NCTF48 AD15VCCAUX_NCTF49 AC15VCCAUX_NCTF50 AB15
VSS_NCTF0 AE27
VCCAUX_NCTF51 AA15
VSS_NCTF1 AE26
VCC_NCTF59R20
VCCAUX_NCTF56 T15
VSS_NCTF2 AE25VSS_NCTF3 AE24VSS_NCTF4 AE23VSS_NCTF5 AE22VSS_NCTF6 AE21VSS_NCTF7 AE20VSS_NCTF8 AE19VSS_NCTF9 AE18
VSS_NCTF10 AC17VSS_NCTF11 Y17VSS_NCTF12 U17
VCC_NCTF26V25
VCCAUX_NCTF57 R15
VCC_NCTF37U24
VCC_NCTF8T27
VCC100M19VCC101L19VCC102N18VCC103M18VCC104L18VCC105P17VCC106N17VCC107M17VCC108N16VCC109M16VCC110L16
VCC_SM100 AR6VCC_SM101 AP6VCC_SM102 AN6VCC_SM103 AL6VCC_SM104 AK6VCC_SM105 AJ6VCC_SM106 AV1VCC_SM107 AJ1
R1160 1K_0402_5%@1 2
C81
40.
47U
_060
3_10
V7K
1
2
C79
80.
22U
_060
3_10
V7K
1
2
C803
10U_0805_6.3V6M
1
2
R1152 2.2K_0402_5%@1 2
R1155 2.2K_0402_5%@1 2
R1157 2.2K_0402_5%@1 2
C79
40.
47U
_060
3_10
V7K
1
2
C81
30.
47U
_060
3_10
V7K
1
2
R1156 2.2K_0402_5%@ 1 2C809
10U_0805_6.3V6M
1
2
R1153 2.2K_0402_5%@1 2
C81
20.
47U
_060
3_10
V7K
1
2
C80
0
0.1U
_040
2_16
V4Z
1
2
C79
50.
47U
_060
3_10
V7K
1
2
C80
2
0.1U
_040
2_16
V4Z
1
2C804
10U_0805_6.3V6M
1
2 C80
51U
_060
3_10
V4Z
1
2
+ C808
220U_D2_4VM@
1
2
+
C80
622
0U_D
2_2V
M_R
9
1
2
+C811
330U
_D2E
_2.5
VM_R
9
@
1
2
C79
70.
22U
_060
3_10
V7K
1
2
R1151 2.2K_0402_5%@1 2
C810
10U_0805_6.3V6M
1
2
C79
60.
22U
_060
3_10
V7K
1
2
R1159 1K_0402_5%@1 2
C80
1
0.1U
_040
2_16
V4Z
1
2
R1154 2.2K_0402_5%@1 2
+C98
0
330U
_D2E
_2.5
VM_R
9
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Calistoga (6/6)
12 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
P O W E R
U15I
CALISTOGA_FCBGA1466~D
VSS0AC41VSS1AA41VSS2W41VSS3T41VSS4P41VSS5M41VSS6J41VSS7F41VSS8AV40VSS9AP40VSS10AN40VSS11AK40
VSS13AH40VSS14AG40VSS15AF40VSS16AE40VSS17B40VSS18AY39VSS19AW39
VSS21AR39VSS22AN39
VSS24AC39VSS25AB39VSS26AA39VSS27Y39VSS28W39VSS29V39VSS30T39VSS31R39VSS32P39VSS33N39VSS34M39VSS35L39VSS36J39VSS37H39
VSS20AV39
VSS23AJ39
VSS12AJ40
VSS38G39
VSS40D39VSS41AT38VSS42AM38VSS43AH38VSS44AG38VSS45AF38VSS46AE38VSS47C38VSS48AK37VSS49AH37VSS50AB37VSS51AA37VSS52Y37VSS53W37VSS54V37VSS55T37VSS56R37VSS57P37VSS58N37VSS59M37VSS60L37VSS61J37VSS62H37VSS63G37VSS64F37VSS65D37VSS66AY36VSS67AW36VSS68AN36VSS69AH36VSS70AG36VSS71AF36VSS72AE36VSS73AC36VSS74C36VSS75B36VSS76BA35VSS77AV35VSS78AR35VSS79AH35VSS80AB35VSS81AA35VSS82Y35VSS83W35VSS84V35VSS85T35VSS86R35VSS87P35VSS88N35VSS89M35VSS90L35VSS91J35VSS92H35VSS93G35VSS94F35VSS95D35VSS96AN34VSS97AK34VSS98AG34VSS99AF34
VSS39F39
VSS100 AE34VSS101 AC34VSS102 C34VSS103 AW33VSS104 AV33VSS105 AR33VSS106 AE33VSS107 AB33VSS108 Y33VSS109 V33VSS110 T33VSS111 R33VSS112 M33VSS113 H33VSS114 G33VSS115 F33VSS116 D33VSS117 B33VSS118 AH32VSS119 AG32VSS120 AF32VSS121 AE32VSS122 AC32VSS123 AB32VSS124 G32VSS125 B32VSS126 AY31VSS127 AV31VSS128 AN31VSS129 AJ31VSS130 AG31VSS131 AB31VSS132 Y31VSS133 AB30VSS134 E30VSS135 AT29VSS136 AN29VSS137 AB29VSS138 T29VSS139 N29VSS140 K29VSS141 G29VSS142 E29VSS143 C29VSS144 B29VSS145 A29VSS146 BA28VSS147 AW28VSS148 AU28VSS149 AP28VSS150 AM28VSS151 AD28VSS152 AC28VSS153 W28VSS154 J28VSS155 E28VSS156 AP27VSS157 AM27VSS158 AK27VSS159 J27VSS160 G27VSS161 F27VSS162 C27VSS163 B27VSS164 AN26VSS165 M26VSS166 K26VSS167 F26VSS168 D26VSS169 AK25VSS170 P25VSS171 K25VSS172 H25VSS173 E25VSS174 D25VSS175 A25VSS176 BA24VSS177 AU24VSS178 AL24VSS179 AW23VSS180 AT23VSS181 AN23VSS182 AM23VSS183 AH23VSS184 AC23VSS185 W23VSS186 K23VSS187 J23VSS188 F23VSS189 C23VSS190 AA22VSS191 K22VSS192 G22VSS193 F22VSS194 E22VSS195 D22VSS196 A22VSS197 BA21VSS198 AV21VSS199 AR21
P O W E R
U15J
CALISTOGA_FCBGA1466~D
VSS200AN21VSS201AL21VSS202AB21VSS203Y21VSS204P21VSS205K21VSS206J21VSS207H21VSS208C21VSS209AW20VSS210AR20VSS211AM20VSS212AA20VSS213K20VSS214B20VSS215A20VSS216AN19VSS217AC19VSS218W19VSS219K19VSS220G19VSS221C19VSS222AH18VSS223P18VSS224H18VSS225D18VSS226A18VSS227AY17VSS228AR17VSS229AP17VSS230AM17VSS231AK17VSS232AV16VSS233AN16VSS234AL16VSS235J16VSS236F16VSS237C16VSS238AN15VSS239AM15VSS240AK15VSS241N15VSS242M15VSS243L15VSS244B15VSS245A15VSS246BA14VSS247AT14VSS248AK14VSS249AD14VSS250AA14VSS251U14VSS252K14VSS253H14VSS254E14VSS255AV13VSS256AR13VSS257AN13VSS258AM13VSS259AL13VSS260AG13VSS261P13VSS262F13
VSS266AC12VSS267K12VSS268H12VSS269E12VSS270AD11VSS271AA11VSS272Y11VSS273J11VSS274D11VSS275B11VSS276AV10VSS277AP10VSS278AL10VSS279AJ10
VSS265D13VSS264B13VSS263AY12
VSS285 AW9VSS286 AR9VSS287 AH9VSS288 AB9VSS289 Y9VSS290 R9VSS292 G9VSS291 E9VSS293 A9VSS294 AG8VSS295 AD8VSS296 AA8VSS297 U8VSS298 K8VSS299 C8VSS300 BA7VSS301 AV7VSS302 AP7VSS303 AL7VSS304 AJ7VSS305 AH7VSS306 AF7VSS307 AC7VSS308 R7VSS309 G7VSS310 D7VSS311 AG6VSS312 AD6VSS313 AB6VSS314 Y6
VSS317 K6VSS318 H6VSS319 B6VSS320 AV5VSS321 AF5VSS322 AD5VSS323 AY4VSS324 AR4VSS325 AP4VSS326 AL4VSS327 AJ4VSS328 Y4VSS329 U4VSS330 R4VSS331 J4VSS332 F4VSS333 C4VSS334 AY3VSS335 AW3VSS336 AV3VSS337 AL3
VSS341 AD3
VSS345 AT2VSS346 AR2VSS347 AP2VSS348 AK2
VSS351 AB2VSS352 Y2VSS353 U2VSS354 T2VSS355 N2VSS356 J2VSS357 H2
VSS359 C2VSS360 AL1
VSS358 F2
VSS349 AJ2VSS350 AD2
VSS344 G3VSS343 AA3VSS342 AC3
VSS340 AF3
VSS338 AH3
VSS280 AG10VSS281 AC10VSS282 W10VSS283 U10VSS284 BA9
VSS315 U6VSS316 N6
VSS339 AG3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_MA11
V_DDR_MCH_REF
DDR_CKE1_DIMMA
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
ICH_SMBCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D3DDR_A_D2
DDR_A_D17DDR_A_D21
DDR_A_D30DDR_A_D27
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2
DDR_A_DM0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
ICH_SMBDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_BS#1DDR_A_RAS#
DDR_A_D15
DDR_A_D20
DDR_A_D9
DDR_A_D16
DDR_A_D28
DDR_A_D26DDR_A_D31
DDR_A_D33DDR_A_D36
DDR_A_D37
DDR_A_D29
DDR_A_D32
DDR_A_D49DDR_A_D48
DDR_A_D54
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS#0
DDR_A_BS#2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA4
DDR_A_BS#2
DDR_A_BS#1
DDR_A_MA6
DDR_A_MA9
DDR_CKE0_DIMMA
DDR_A_MA2
DDR_A_MA12
DDR_A_MA5
DDR_A_MA1
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#0
DDR_A_MA8
DDR_A_MA3
DDR_A_MA10
DDR_CS0_DIMMA#
M_ODT1DDR_CS1_DIMMA#
M_ODT1
DDR_A_WE#
M_ODT0DDR_A_MA13
DDR_A_MA7
M_ODT0
DDR_A_D59DDR_A_D58
DDR_A_D63DDR_A_D62
DDR_A_D60DDR_A_D57
DDR_A_D56DDR_A_D61
DDR_A_D50DDR_A_D51DDR_A_D55
DDR_A_D52DDR_A_D53
DDR_A_D42DDR_A_D43
DDR_A_D47DDR_A_D46
DDR_A_D41DDR_A_D45
DDR_A_D40DDR_A_D44
DDR_A_D39DDR_A_D35
DDR_A_D34DDR_A_D38
DDR_A_D25DDR_A_D24
DDR_A_D22DDR_A_D19 DDR_A_D23
DDR_A_D18
DDR_A_D13DDR_A_D12
DDR_A_D0DDR_A_D4
DDR_A_D14
DDR_A_D7DDR_A_D1
DDR_A_D5DDR_A_D6
DDR_A_D11DDR_A_D10
DDR_A_DQS#[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DM[0..7]<8>
DDR_A_MA[0..13]<8>
DDR_CKE0_DIMMA<7>
DDR_A_BS#2<8>
DDR_A_BS#0<8>DDR_A_WE#<8>
DDR_A_CAS#<8>
M_ODT1<7>
DDR_CS1_DIMMA#<7>
M_CLK_DDR0 <7>M_CLK_DDR#0 <7>
DDR_CKE1_DIMMA <7>
DDR_A_BS#1 <8>DDR_A_RAS# <8>DDR_CS0_DIMMA# <7>
M_CLK_DDR#1 <7>
M_ODT0 <7>
V_DDR_MCH_REF <7,14,41>
ICH_SMBDATA<4,14,15,20,22,24>ICH_SMBCLK<4,14,15,20,22,24>
M_CLK_DDR1 <7>
DDR_THERM# <7,14>
+1.8V
+0.9V
+3VS
+1.8V
+1.8V
+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
DDRII-SODIMM SLOT1
13 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Layout Note:Place these resistorclosely JP34,alltrace length Max=1.5"
Layout Note:Place near JP34
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
REVERSESO-DIMM A
Top side
RP30 56_0404_4P2R_5%1423
RP34 56_0404_4P2R_5%1423
C272
0.1U_0402_16V4Z
1
2 C234
0.1U_0402_16V4Z
1
2
RP22 56_0404_4P2R_5%1423
R45
310
K_04
02_5
%
12
C252
0.1U_0402_16V4Z
1
2
R45
510
K_04
02_5
%
12
RP32
56_0404_4P2R_5%
1 42 3
C498
2.2U_0805_16V4Z
1
2
C241
0.1U_0402_16V4Z
1
2
C308
0.1U_0402_16V4Z
1
2
RP29
56_0404_4P2R_5%
1 42 3
C227
0.1U_0402_16V4Z
1
2C250
0.1U_0402_16V4Z
1
2
C255
0.1U_0402_16V4Z
1
2
RP25 56_0404_4P2R_5%1423
C362
0.1U_0402_16V4Z
1
2
RP31
56_0404_4P2R_5%
1 42 3
C280
0.1U_0402_16V4Z
1
2
RP28 56_0404_4P2R_5%1423
C465
2.2U_0805_16V4Z
1
2
C235
0.1U_0402_16V4Z
1
2
C279
0.1U_0402_16V4Z
1
2 C281
0.1U_0402_16V4Z
1
2C229
0.1U_0402_16V4Z
1
2
JP34
FOX_ASOA426-M4R-TR
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
DQS5# 146DQS5 148
VSS 150DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SAO 198SA1 200
GND203 GND 204RP33
56_0404_4P2R_5%
1 42 3
RP35
56_0404_4P2R_5%
1 42 3
C239
0.1U_0402_16V4Z
1
2
C242
0.1U_0402_16V4Z
1
2
C268
0.1U_0402_16V4Z
1
2C257
0.1U_0402_16V4Z
1
2
C491
2.2U_0805_16V4Z
1
2
RP27
56_0404_4P2R_5%
1 42 3
RP26 56_0404_4P2R_5%1423
RP24 56_0404_4P2R_5%1423
C274
0.1U_0402_16V4Z
1
2
C458
2.2U_0805_16V4Z
1
2C
363
2.2U_0805_16V4Z
1
2
C473
2.2U_0805_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_MA1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_MA0
DDR_B_RAS#
DDR_B_MA3
DDR_B_MA10
DDR_B_BS#2
DDR_CS2_DIMMB#
DDR_B_BS#1
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_B_MA4
DDR_B_MA7
DDR_B_MA9
DDR_B_MA2
DDR_B_MA11
DDR_B_MA5
DDR_B_MA12
DDR_B_MA6
DDR_B_MA8
M_ODT3DDR_CS3_DIMMB# M_ODT2
DDR_B_MA13
DDR_B_WE#
DDR_B_DQS#4
DDR_B_D14
DDR_B_DQS4
DDR_B_BS#2
DDR_B_D57
DDR_B_MA2
DDR_CKE2_DIMMB
DDR_B_D8
DDR_B_D1
DDR_B_DM3
ICH_SMBDATA
DDR_B_D52
DDR_B_D45
DDR_B_MA3
DDR_B_D37
DDR_B_D59
DDR_B_D40
DDR_B_D6
DDR_B_MA7
DDR_B_D13
DDR_B_D5
DDR_B_D61
DDR_B_DQS#0
DDR_CS3_DIMMB#
M_ODT3
DDR_B_MA11
DDR_B_D46
DDR_B_WE#
DDR_B_D2
DDR_B_D11
DDR_B_MA10
DDR_B_D55
DDR_B_D35
DDR_B_D41
DDR_B_DQS5
M_ODT2
DDR_B_DQS2
DDR_B_DQS#7
DDR_B_MA6
DDR_B_D9
DDR_B_D44
DDR_B_D63
DDR_B_DM7
DDR_B_BS#0
DDR_B_MA5
DDR_B_D56
DDR_B_D4
DDR_B_DQS#3
DDR_B_D10
DDR_B_D12
DDR_B_D22
DDR_B_D48
DDR_B_D36
DDR_B_DQS7
DDR_B_D42
DDR_B_D33
DDR_CKE3_DIMMB
DDR_B_DQS0
DDR_B_D43
DDR_B_MA1
DDR_B_MA8
DDR_B_DQS#2
DDR_B_DQS#5
DDR_B_MA12
DDR_B_DQS3
DDR_B_RAS#
DDR_B_MA4
DDR_B_DM5
DDR_B_D34
ICH_SMBCLK
DDR_B_D47
DDR_B_D7
DDR_B_MA13
DDR_B_D32
DDR_B_DQS1
DDR_B_BS#1
DDR_B_D62
DDR_B_DQS#6
DDR_B_D54
DDR_B_DM4
DDR_B_DQS6
DDR_B_DQS#1
DDR_B_D49
DDR_B_MA9
DDR_B_MA0
DDR_B_D3
DDR_B_D15
DDR_B_CAS#
DDR_B_D23
DDR_CS2_DIMMB#
DDR_B_DM0
DDR_B_DM1
DDR_B_D0
V_DDR_MCH_REF
DDR_B_DM6
DDR_B_D60
DDR_B_D58
DDR_B_D53
DDR_B_DM2
DDR_B_D50DDR_B_D51
DDR_B_D39DDR_B_D38
DDR_B_D31DDR_B_D30
DDR_B_D27DDR_B_D29
DDR_B_D25DDR_B_D24
DDR_B_D28DDR_B_D26
DDR_B_D19DDR_B_D17
DDR_B_D20DDR_B_D16DDR_B_D21DDR_B_D18
M_CLK_DDR2M_CLK_DDR#2
M_CLK_DDR3M_CLK_DDR#3
DDR_B_DQS#[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_MA[0..13]<8>
DDR_B_DM[0..7]<8>
DDR_CKE3_DIMMB <7>
DDR_CS2_DIMMB# <7>
V_DDR_MCH_REF <7,13,41>
ICH_SMBCLK<4,13,15,20,22,24>ICH_SMBDATA<4,13,15,20,22,24>
DDR_B_WE#<8>
DDR_B_BS#1 <8>DDR_B_RAS# <8>
DDR_B_CAS#<8>
M_ODT3<7>
DDR_CKE2_DIMMB<7>
DDR_CS3_DIMMB#<7>
DDR_B_BS#2<8>
DDR_B_BS#0<8>
M_ODT2 <7>
M_CLK_DDR2 <7>M_CLK_DDR#2 <7>
M_CLK_DDR3 <7>M_CLK_DDR#3 <7>
DDR_THERM# <7,13>
+0.9V
+1.8V
+3VS+3VS
+1.8V
+1.8V
+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
DDRII-SODIMM SLOT2
14 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
SO-DIMM BSTANDARD
Bottom side
Layout Note:Place near JP34
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
Layout Note:Place these resistorclosely JP10,alltrace length Max=1.5"
C90
0.1U_0402_16V4Z
1
2
RP19
56_0404_4P2R_5%
1 42 3
C219
0.1U_0402_16V4Z
1
2
C166
0.1U_0402_16V4Z
1
2
C265
2.2U_0805_16V4Z
1
2
C218
0.1U_0402_16V4Z
1
2
C301
0.1U_0402_16V4Z
1
2
C164
2.2U_0805_16V4Z
1
2
RP11 56_0404_4P2R_5%1423
RP15 56_0404_4P2R_5%1423
C177
0.1U_0402_16V4Z
1
2
C159
2.2U_0805_16V4Z
1
2
RP17
56_0404_4P2R_5%
1 42 3
C220
0.1U_0402_16V4Z
1
2C213
0.1U_0402_16V4Z
1
2C197
0.1U_0402_16V4Z
1
2
C236
2.2U_0805_16V4Z
1
2
C183
0.1U_0402_16V4Z
1
2
RP10 56_0404_4P2R_5%1423
C176
0.1U_0402_16V4Z
1
2 C173
0.1U_0402_16V4Z
1
2
C161
0.1U_0402_16V4Z
1
2
RP16
56_0404_4P2R_5%
1 42 3
C179
0.1U_0402_16V4Z
1
2 C186
0.1U_0402_16V4Z
1
2
R254
10K_0402_5%
12
RP12 56_0404_4P2R_5%1423
R257
10K_0402_5%
1 2
RP13 56_0404_4P2R_5%1423
RP9
56_0404_4P2R_5%
1423
C210
0.1U_0402_16V4Z
1
2 C163
0.1U_0402_16V4Z
1
2
RP14
56_0404_4P2R_5%
1 42 3
RP23
56_0404_4P2R_5%
1 42 3
RP21 56_0404_4P2R_5%1423
C247
2.2U_0805_16V4Z
1
2
C188
0.1U_0402_16V4Z
1
2
JP10
FOX_ASOA426-M2RN-7F
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144DQS5# 146
DQS5 148VSS 150
DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SA0 198SA1 200
GND203 GND 204
RP18
56_0404_4P2R_5%
1 42 3
C199
0.1U_0402_16V4Z
1
2
C89
2.2U_0805_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_STP_CPU#
CLK_PCI_ICH PCI_ICH
H_STP_PCI#
CLKREF1
CLK_XTAL_IN
CLK_XTAL_OUT
FSB
FSA
PCIE_SATA
PCIE_SATA# CLK_PCIE_SATA#
CLK_PCIE_SATA
CLKREQC#
PCI_ICH
CLK_ENABLE#
CLK_ENABLE#
PCI_MINI
PCI_CLK3
CLKREF0CLK_14M_SIO
CLK_14M_ICH
PCI_EC
CPPE#CLKREQB#
CK_VDD_48
CK_VDD_REF
CLK_14M_KBC
CLKREF1
CK_VDD_48
CK_VDD_REF
CLKIREF
PCIE_DOCK CLK_PCIE_DOCK
CLK_PCIE_DOCK#PCIE_DOCK#
MCH_3GPLL
MCH_3GPLL#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
PCIE_MCARD
PCIE_MCARD#
PCI_PCM
ICH_SMBDATA
ICH_SMBCLK
FSB
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_CPU_BCLK
CPU_BCLK#
CPU_XDP
CLK_MCH_BCLK#
CLK_CPU_XDP#
CLK_CPU_XDP
CPU_BCLK
CPU_XDP#
CLK_MCH_BCLK
MCH_BCLK#
CLKIREF
MCH_BCLK
PCIE_ICH
CLK_CPU_BCLK#
PCIE_ICH#
PCI_CLK3
CLKREQD#
CLK_48M_ICHCLK_48M_CB
CLK_DEBUG_PORT PCI_MINI
FSA
PCI_CLK5
PCI_EC
MCH_REF#
MCH_REF
CLK_MCH_REF#
CLK_MCH_REF
CLK_MCH_SS#
CLK_MCH_SSMCH_SS
MCH_SS#
CLK_48M_CB
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_ICH
CLK_14M_SIO
CLK_14M_KBC
CLK_PCI_TCG
CLK_PCI_PCM
CLK_PCI_EC
CLK_PCI_SIO
CLK_DEBUG_PORT
CLKREQA#
CLK_PCIE_LOM#
CLK_PCIE_LOM
PCIE_LOM#
PCIE_LOM
CLKREQA#
CLKREQB#
CPU_XDP
CPU_XDP#
CPU_BSEL2<5>MCH_CLKSEL2 <7>
CPU_BSEL1<5>
MCH_CLKSEL1 <7>
CPU_BSEL0<5>
MCH_CLKSEL0 <7> CLK_48M_CB<24>CLK_48M_ICH<20>
H_STP_PCI#<20>H_STP_CPU#<20>
CLK_PCI_ICH<18>
CLK_14M_SIO<28>
ICH_SMBDATA<4,13,14,20,22,24>
ICH_SMBCLK<4,13,14,20,22,24>
CLK_CPU_BCLK# <4>
CLK_CPU_XDP <4>
CLK_CPU_BCLK <4>
CLK_CPU_XDP# <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>
CLK_DEBUG_PORT<24>
CLK_PCI_PCM<24>
CLK_PCI_EC<30>
CLK_14M_KBC<30>
CLK_14M_ICH<20>
CPPE# <18,32>
CLK_ENABLE#<34,42>
CLKREQD# <24>
CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>
CLK_PCI_SIO<28>
CLK_PCI_TCG<29>
CLK_PCIE_DOCK <32>
CLK_PCIE_DOCK# <32>
CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>
CLK_PCIE_MCARD <24>
CLK_PCIE_MCARD# <24>
CLKREQC# <7>
CLK_MCH_REF#<7>
CLK_MCH_REF<7>
CLK_MCH_SS <7>
CLK_MCH_SS# <7>
CLKREQA# <22>
CLK_PCIE_LOM <22>
CLK_PCIE_LOM# <22>
+3VS
+3VS
+3VS
+CK_VDD_DP
+CK_VDD_DP
+3VS
+VCCP
+CK_VDD_DP
+3VS
+CK_VDD_MAIN2
+CK_VDD_MAIN1
+3VS
+VCCP
+VCCP
+VCCP
+3VS
+3VS +3VS
+CK_VDD_MAIN1
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Clock generator
15 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place crystal within500 mils of CK410
Routing the trace at least 10mil
LCD(Low)/SRC(High) clock select
High:Pin18/19 = 100MHzLow:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP
High:Pin44/45 = CLKREQ
Pin44/45 function select
CLK_Ra
CLK_Rb
CLK_Rc
CLK_Rd
CLK_Re
CLK_Rf
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable.When this time, docking PCI express will not work.
CLK_Rc
Stuff
CLK_Rf
CLK_Ra
CLK_Re
CLK_Re
Stuff
CLK_Ra
FSB Frequency Selet:
No Stuff
CLK_Rb
No Stuff
533MHzCLK_Rf
CLK_Rc
CLK_Re
CLK_Rd
CLK_Rf
CLK_Ra
CLK_Rd
CLK_RcCPU Driven
No Stuff
CLK_Rb
Stuff
CLK_Rd
CLK_Rb
667MHz
*(Default)
1
1000
CLKSEL1
100
0
PCIMHz
133
0
Table : ICS954306
SRCMHz
33.3
CPUMHzCLKSEL2
33.31
FSLACLKSEL0
166
FSLC
1
FSLB
**
Place close to U25
R1143 24_0402_5%XDP@1 2
C739
0.1U_0402_16V4Z
1
2
C3535P_0402_50V8C@
12
R10692.2_0805_1%
1 2
R10791K_0402_5%
1 2
R1111 24_0402_5%1 2
R114824_0402_5% 12R1142 0_0402_5%NOXDP@
12
R1067 0_0805_5%
1 2
C1062
10U_0805_10V4Z
1
2
R114033_0402_5%
12
R1075 24_0402_5%
1 2
C734
0.1U_0402_16V4Z
1
2
R1126 24_0402_5%
1 2
R11051K_0402_5%
1 2
R1113
0_0402_5%
@
12
R1145 24_0402_5%
1 2
R1254 0_0402_5%NOXDP@12
C3744.7P_0402_50V8C
12
R1115 24_0402_5%1 2
R1080 12_0402_5%
12
R1087 33_0402_5%
12
C36118P_0402_50V8J
12
R1333 0_0402_5%LP@1 2
R1092 910_0402_1%
R1081 24_0402_5%
1 2
C3805P_0402_50V8C@
12
R10830_0402_5%
1 2
R11070_0402_5%
1 2
R1147 10K_0402_5%NOXDP@12
C3565P_0402_50V8C@
12
R1070 24_0402_5%
1 2
R1072 24_0402_5%
1 2
R1101 12_0402_5%
12
C364 18P_0402_50V8J12
Y314.31818MHZ_16P
12
C7411000P_0402_50V4Z@
1 2
C3754.7P_0402_50V8C
12
T93 PAD
R114924_0402_5% 12
C7310.01U_0402_16V7K
1
2
C735
0.1U_0402_16V4Z
1
2
R1104 12_0402_5%
12
R1144 24_0402_5%
1 2
R10788.2K_0402_5%
12
R1128
1K_0402_5%
12
R1108
10K_0402_5%
12
R1086
1K_0402_5%
12
R111733_0402_5%DEBUG@
12
R1106 10K_0402_5%12
R1389
0_0805_5%NOXDP@1 2
R1246
10K_0402_5%@
12
R1257 24_0402_5%1 2
R1120 10K_0402_5%NOXDP@12
C3764.7P_0402_50V8C
12
C7441000P_0402_50V4Z@
1 2
R1251 24_0402_5%
1 2
C730
10U_0805_10V4Z
1
2
T92 PAD
R107456_0402_5%@
12
C743
0.1U_0402_16V4Z
1
2
R1123 24_0402_5%
1 2
C1061
0.1U_0402_16V4Z@
1
2
C7320.01U_0402_16V7K
1
2
R1129 24_0402_5%1 2
R11308.2K_0402_5%
12
C7401000P_0402_50V4Z@
1 2
C738
0.1U_0402_16V4Z
1
2
R109733_0402_5%
12
C3784.7P_0402_50V8C
12
C3574.7P_0402_50V8C
12
R1095 24_0402_5%1 2
R1068
1_0805_1%1 2
R1066 0_0805_5%
1 2
R1133 24_0402_5%XDP@1 2
C7451000P_0402_50V4Z@
1 2
R1245
10K_0402_5%
12
R1259 24_0402_5%1 2
R11350_0402_5%
1 2
R1394 10K_0402_5%@12
R111433_0402_5%
12
R1351
300_0402_5%
12
R1132 24_0402_5%1 2
R1139
0_0402_5%
@
12
* Internal Pull-Up Resistor** Internal Pull-Down Resistor
U25
ICS9LP306_TSSOP64
*SEL_PCI1/PCICLK31
**SEL_SATA1/PCICLK42
**SEL_SATA2/PCICLK53
GND4
VDDPCI5
PCI/SRC_STOP#8
PCICLK66
**SEL_LCDCLK#/PCICLK_F17
FSLA/USB_48MHz11
SATACLKT 28
DOTT_96MHz13
VDD4810
Vtt_PwrGd#/PD9
SRCCLKC3 27
SRCCLKT3 26
SATACLKC 29
GND17
GND12
SRCCLKC1 21
SRCCLKT1 20
LCDCLK_SSC/SRCCLKC0 19
LCDCLK_SST/SRCCLKT0 18
SRCCLKT2 22
CPUCLKC0 51
CPU_STOP#61
REF0/PCICLK160
FSLC/TEST_SEL/REF159
VDDREF55
VDDCPU50
VDD16
FSLB/TEST_MODE15
DOTC_96MHz14
X2 56
X1 57
SCLK53
CPUCLKT0 52
*REQ_SEL/PCICLK262
*CLKREQB# 63
*CLKREQA# 64
GNDSRC40
SATA1/SRCCLKC4 31
SATA1/SRCCLKT4 30
SDATA54
CPUCLKT1 49
CPUCLKC1 48
VDDSRC24
GNDSRC25
GNDCPU47
SRCCLKC2 23
IREF46
*CPUCLKT2_ITP/CLKREQC# 45
*CPUCLKC2_ITP/CLKREQD# 44
SRCCLKT8 43
SRCCLKC8 42
GNDSATA32
VDDSRC41
GND58
SRCCLKT7 39
SRCCLKC7 38
SRCCLKT6 37
SRCCLKC6 36
SATA2/SRCCLKT5 35
SATA2/SRCCLKC5 34
VDDSATA33
R114133_0402_5% 12
R1249 24_0402_5%
1 2
R1093 24_0402_5%1 2
R111033_0402_5%
12
C3724.7P_0402_50V8C
12
R1247
10K_0402_5%@
12
R1098
1K_0402_5%
12
R13930_0402_5%@
12
J29NO SHORT PADS
12
C737
10U_0805_10V4Z
1
2
R110910K_0402_5%
12
C3794.7P_0402_50V8C
12
R1077 12_0402_5%
12
R1390
0_0805_5%XDP@1 2
R1352 0_0402_5%LP@1 2
C736
0.1U_0402_16V4Z
1
2
C7330.01U_0402_16V7K
1
2
R11311K_0402_5%
1 2
R1146
10K_0402_5%@
12
C742
0.1U_0402_16V4Z
1
2
C3734.7P_0402_50V8C
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RED_R
GREEN_R
BLUE_R
D_DDCCLK
RED_RGREEN_RBLUE_R
TV_COMP
HSYNC_G_A D_HSYNC
VSYNC_G_A D_VSYNC
AS
AS
DVI_VSWING
DVI_AVDD_2.5V
DVI_DETECT
SDVO_SDAT
PLT_RST#
SDVO_SCLKSDVO_SDAT
DVI_AVDD_3V
DVI_AVDD_3V
SDVOB_INT+SDVOB_INT-
TV_CRMA
TV_LUMA
DVI_AVDD_2.5V
SDVO_SCLK
D_DDCDATA
DVI_DVDD_2.5V
DVI_DVDD_2.5V
C_HSYNC<9>
C_VSYNC<9>
D_HSYNC <32>
D_VSYNC <32>
D_DDCCLK<32>
RED<32>
GREEN<32>
BLUE<32>
C_DDCCLK <9>
C_DDCDATA <9>
SDVOB_R-<9>SDVOB_R+<9>
SDVOB_G-<9>SDVOB_G+<9>
SDVOB_B-<9>SDVOB_B+<9>
SDVOB_CLK+<9>SDVOB_CLK-<9>
PEG_RXP1<9>PEG_RXN1<9>
DVI_DETECT <32>
SDVO_SDAT <9>SDVO_SCLK <9>
PLT_RST#<7,18,19,20,22,24,30>
DVI_CLK- <32>DVI_CLK+ <32>DVI_TX0- <32>DVI_TX0+ <32>DVI_TX1- <32>DVI_TX1+ <32>DVI_TX2- <32>DVI_TX2+ <32>
DVI_CLK <32>DVI_DAT <32>
COMP<9,32>
CRMA<9,32>
LUMA<9,32>
D_DDCDATA<32>
+CRTVDD+RCRT_VCC
+3VS
+5VS
+CRTVDD +CRTVDD
+5VS
+3VS
+CRTVDD
+5VS
+2.5VS
+2.5VS
+2.5VS
+3VS+2.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
CRT & TVout Connector
16 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
W=40milsCRT Connector
Place close to docking connector
TV-Out Connector
Place close to JP1
W=20 mils
DVI Transnitter
R543
0_0603_5%1 2
C31
418
P_04
02_5
0V8C
1
2
C141
0.1U_0402_16V4Z
R542
0_0603_5%1 2
R103
1.3K_0402_1%
12
R497
10K_0402_5%
12
R545
0_0603_5%1 2
R544
0_0603_5%1 2
C150
0.1U_0402_16V4Z
C368
0.1U_0402_16V4Z
R183
2.2K_0402_5%
12
D1DAN217_SC59@
2 31
D3DAN217_SC59@
2 31
C36910U_0805_10V4Z
1
2
U11
CH7307C_LQFP48
HPDET 29
ATPG27
SDVOB_INT+32SDVOB_INT-33
NC
35
SC_PROM 9SD_PROM 8
SPD 5SPC 4
SDVOB_R+37SDVOB_R-38
SDVOB_G+40SDVOB_G-41
SDVOB_B+43SDVOB_B-44
SDVOB_CLK+46SDVOB_CLK-47
AS3RESET#2
SCEN26
VSWING25
SC_DDC 11SD_DDC 10
NC
34
DVD
D12
DVD
D28
AVD
D_P
LL1
TVD
D15
TVD
D21
AVD
D36
AVD
D42
AVD
D48
DG
ND
7D
GN
D30
AGN
D31
AGN
D39
AGN
D45
TGN
D18
TGN
D24
AG
ND
_PLL
6
TLC# 13TLC 14
TDC0# 16TDC0 17
TDC1# 19TDC1 20
TDC2# 22TDC2 23
PAD
49
C359
0.1U_0402_16V4Z
1 2
D18
CH491D_SC59
2 1
R5470_0603_5%
1 2
R114
10K_0402_5%
12
R1367
KC FBM-L11-201209-221LMA30T_08051 2
C174
0.1U_0402_16V4Z
D5DAN217_SC59@
2 31
C31
318
P_04
02_5
0V8C
1
2
C315
0.1U_0402_16V4Z
1
2
JP1
SUYIN_33007SR-07T1-C
1234567
C352
5P_0402_50V8C@
1
2
R5480_0603_5%
1 2
JP2
SUYIN_070912FR015S207CR
611
17
1228
1339
144
1015
5
1617
R54
51K_
0402
_5%
12
C178
0.1U_0402_16V4Z
R498
10K_0402_5%
12
R1368
KC FBM-L11-201209-221LMA30T_08051 2
C142
0.1U_0402_16V4Z
R5490_0603_5%
1 2
F1
1.1A_6VDC_FUSE
21
R53
51K_
0402
_5%
12
D4
DAN
217_
SC59
@
2 31
R1369CHB1608U301_0603
12
D20
DAN
217_
SC59
@
2 31
R142 5.6K_0402_5%1 2
U54SN74AHCT1G125GW_SOT353-5
A2 Y 4OE#
1G
3P
5
C371
0.1U_0402_16V4Z
R2
2.2K
_040
2_5%
12
R162
2.2K_0402_5%
12 G
D S
Q46
RHU002N06_SOT323
2
1 3
C358
0.1U_0402_16V4Z
C370
0.1U_0402_16V4Z
1 2
C351
5P_0402_50V8C@
1
2
C31
018
P_04
02_5
0V8C
1
2
C1043
0.1U_0402_16V4Z
R4
2.2K
_040
2_5%
12
C14022U_0805_6.3V4Z
1
2
D19
DAN
217_
SC59
@
2 31
G
D S
Q52RHU002N06_SOT323
2
1 3
U33SN74AHCT1G125GW_SOT353-5
A2 Y 4OE#
1G
3P
5
R143 5.6K_0402_5%1 2
R546
0_0603_5%1 2
C10420.1U_0402_16V4Z
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LID_SW#
LCD_CLK <9>BKLT_CTL <9>
ENABLT<9>
ENAVDD<9>
LID_SW#<20,31>
ALS_EN <18>
TXCLK_U+ <9>TXCLK_U- <9>
TXOUT_U2+ <9>TXOUT_U2- <9>
TXOUT_U1+ <9>TXOUT_U1- <9>
TXOUT_U0+ <9>TXOUT_U0- <9>
TXOUT_L0- <9>TXOUT_L0+ <9>
TXOUT_L1- <9>TXOUT_L1+ <9>
TXOUT_L2- <9>TXOUT_L2+ <9>
TXCLK_L- <9>TXCLK_L+ <9>
LCD_DAT <9>
+3VALWLCDVDD
LCDVDD
+5VS_INV+5VS
+3VS
B+
B+_LCD
+5VS_INV
LCDVDD
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
LCD CONN.
17 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
LCD POWER CIRCUITLVDS CONN
JP35
ACES_88316-4000
1 12 23 34 45 56 67 78 89 910 1011 1112 1213 1314 1415 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 40
C587 68P_0402_50V8J1 2
Q6DTC124EK_SC59
2
13
R509
2.2K_0402_5%
12
L76 KC FBM-L11-201209-221LMA30T_0805 @12
C31
4.7U_0805_10V4Z
1
2
R19
100_0402_1%
12
L62 KC FBM-L11-201209-221LMA30T_080512
C28
0.047U_0402_16V7K
1 2
U43ASN74LVC08APW_TSSOP14
A1
B2 O 3
P14
G7
R501100K_0402_5%
12
G
D
S
Q5
RHU002N06_SOT323
2
13
C586 0.1U_0603_50V4Z1 2
R12
1M_0402_5%
1 2
10K47
K
Q53DTA114YKA_SC59
2
13
C29
0.1U_0402_16V4Z
1
2
G
D
S
Q36BSS138_SOT23
2
13
R474
47K_0402_5%
1 2
R360
100K_0402_5%
12
G
D S
Q8SI2301BDS_SOT23
2
1 3
C20
4.7U_0805_10V4Z@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_ICH
PCI_SERR#
PCI_DEVSEL#PCI_PCIRST#
PCI_CBE#0
PCI_PERR#
IDE_RESET#
PCI_PIRQG#PCI_PIRQB#
PCI_STOP#
PCI_CBE#1
PCI_CBE#3
PCI_PIRQF#PCI_PIRQC#
PCI_REQ2#
PCI_PIRQE#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_CBE#2
PCI_REQ1#
PCI_REQ0#
PCI_PIRQD#
PCI_PIRQA#
PCI_PAR
PCI_TRDY#
PCI_PIRQH#
PCI_RST#
PCI_PLTRST#CLK_PCI_ICHPCI_PME#
PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5
PCI_AD7PCI_AD6
PCI_AD8PCI_AD9
PCI_AD11PCI_AD10
PCI_AD14PCI_AD15
PCI_AD13PCI_AD12
PCI_AD16PCI_AD17
PCI_AD19PCI_AD18
PCI_AD22PCI_AD23
PCI_AD21PCI_AD20
PCI_AD25PCI_AD24
PCI_AD28PCI_AD29
PCI_AD31PCI_AD30
PCI_AD26PCI_AD27
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_PLOCK#
PCI_SERR#
PCI_PERR#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQH#
PCI_PIRQG#
PCI_PIRQF#
PCI_PIRQE#
PCI_REQ0#
PCI_REQ2#
CPPE#
PLT_RST#
PCI_REQ1#
ALS_EN#
PCI_GNT0#
PCI_GNT2#
PCI_REQ4#
PCI_REQ3#
PCI_PCIRST#
ALS_EN#
ALS_EN
PCI_PLTRST#
CPPE#
PCI_REQ3#
IDE_RESET#
PCI_REQ4#
ALS_EN#
PCI_AD[0..31]<24>
PCI_PIRQC#<24>PCI_PIRQD#<24>
PCI_CBE#0 <24>PCI_CBE#1 <24>PCI_CBE#2 <24>PCI_CBE#3 <24>
PCI_IRDY# <24>PCI_PAR <24>
PCI_DEVSEL# <24>PCI_PERR# <24>
PCI_STOP# <24>PCI_TRDY# <24>PCI_FRAME# <24>
CLK_PCI_ICH <15>
PCI_SERR# <24,30>
PCI_PME#
PCI_RST# <19,24>
PLT_RST# <7,16,19,20,22,24,30>
PCI_REQ0#PCI_GNT0#
PCI_GNT2# <24>PCI_REQ2# <24>
PCI_PIRQE# <24>
PCI_PIRQG# <24>
MCH_ICH_SYNC# <7>
ALS_EN <17>
CPPE# <15,32>
ACCEL_INT <24>
IDE_RESET# <19>
+3VS
+3VS
+3VS
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
ICH7-M(1/4)
18 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place closely pin A9
Boot BIOS destination
L The pad must be placed on PCB easilycontact space for BIOS team setting.
LPC@SPI@
BIOS_SEL1 Short Open
Interrupt I/F
PCI
MISC
U26B
ICH7_BGA652~D
FRAME# F16
GPIO17 / GNT5# D8
TRDY# F14STOP# F15
GPIO2 / PIRQE# G8GPIO3 / PIRQF# F7GPIO4 / PIRQG# F8GPIO5 / PIRQH# G7
C/BE0# B15C/BE1# C12C/BE2# D12C/BE3# C15
IRDY# A7PAR E10
PCIRST# B18DEVSEL# A12
PERR# C9PLOCK# E11
SERR# B10
PIRQC#C5
RSVD[4]AH4
PIRQA#A3
RSVD[5]AD9
RSVD[2]AD5RSVD[3]AG4
PIRQB#B4
PIRQD#B5
RSVD[1]AE5
REQ0# D7GNT0# E7REQ1# C16GNT1# D16REQ2# C17GNT2# D17REQ3# E13GNT3# F13
REQ4# / GPIO22 A13GNT4# / GPIO48 A14GPIO1 / REQ5# C8
AD0E18AD1C18AD2A16AD3F18AD4E16AD5A18AD6E17AD7A17AD8A15AD9C14AD10E14AD11D14AD12B12AD13C13AD14G15AD15G13AD16E12AD17C11AD18D11AD19A11AD20A10AD21F11AD22F10AD23E9AD24D9AD25B9AD26A8AD27A6AD28C7AD29B6AD30E6AD31D6
RSVD[6] AE9RSVD[7] AG8RSVD[8] AH8RSVD[9] F21
MCH_SYNC# AH20
PLTRST# C26PCICLK A9
PME# B19
R1062 8.2K_0402_5%
1 2
R1262 8.2K_0402_5%@1 2
R1052 8.2K_0402_5%
1 2
C729
8.2P_0402_50V@
1
2
R1063 8.2K_0402_5%
1 2
R1050 8.2K_0402_5%
1 2
R1055 8.2K_0402_5%
1 2
R1064 8.2K_0402_5%
1 2
R1060 8.2K_0402_5%
1 2
R1043 8.2K_0402_5%
1 2
R1045 8.2K_0402_5%
1 2
R1053 8.2K_0402_5%
1 2
R1042 8.2K_0402_5%
1 2
G
D
SQ45
RHU002N06_SOT323
2
13
R1056 8.2K_0402_5%
1 2
R1058 8.2K_0402_5%
1 2
U59
TC7SH08FU_SSOP5@
B1
A2 Y 4
P5
G3
R10570_0402_5%
12
R1059 8.2K_0402_5%
1 2
R13880_0402_5%
12
U56
TC7SH08FU_SSOP5@
B1
A2 Y 4
P5
G3
R12901K_0402_5%
12
R1061 8.2K_0402_5%
1 2
R1047 8.2K_0402_5%
1 2
R1046 8.2K_0402_5%
1 2
R1065
10_0402_5% @
12
R1044 8.2K_0402_5%
1 2
R1041 8.2K_0402_5%
1 2
R1049 8.2K_0402_5%
1 2
R10510_0402_5%
12
R1054 8.2K_0402_5%
1 2
R1048 8.2K_0402_5%
1 2
R433
330_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PD_DREQ
H_A20M#
H_INIT#
H_IGNNE#
H_INTR
H_NMI
PD_D9
PD_D2
PD_D15
PD_D0
PD_IOR#
DPRSLP#
LPC_FRAME#
PD_A1
PD_D14
PD_A2
PD_IOW#
AC97_SDIN1
PD_D6
PD_A0
AC97_SDOUT
PD_D13
PD_D10
PD_D8
PD_D1
PD_D7
PD_D4
LPC_AD3
AC97_RST#
PD_D12
PD_D3
THRMTRIP_ICH#
PD_D5
LPC_AD0
PD_D11
PD_DACK#
AC97_SDIN0
LPC_DRQ#0
PD_CS#1
SM_INTRUDER#
H_CPUSLP_R#
H_PWRGOOD
H_SMI#
LPC_AD2
PD_CS#3
LPC_AD1
ICH_INTVRMEN
PD_IRQPD_IORDY
FWH_INIT#
ICH_RTCX2
ICH_INTVRMEN
RTC_R
AC97_SYNC
H_FERR#
GATEA20
KB_RST#
ICH_RTCX1
AC97_BITCLK
CLK_PCIE_SATA#CLK_PCIE_SATA
SATA_RXN0_CSATA_RXP0_C
SATA_TXP0_CSATA_TXN0_C
SATA_TXN0SATA_TXN0_C
SATA_TXP0_C SATA_TXP0
SATA_RXP0
SATA_RXN0
SATA_RXP0_C
SATA_RXN0_C
PD_D2
PD_D4
PD_D6
PD_D7PD_D8
PD_D10
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOW#
PD_CS#1
MBAY_DET#
PLT_RST_B#
SATA_TXP0SATA_TXN0
SATA_RXN0SATA_RXP0
H_STPCLK#
DPSLP#
RTC
PLT_RST_B#ODD_RST#
ODD_RST#
PD_IORDY
PD_D5
PD_A2
PD_A1
PD_D9
PD_D0
PD_DACK#
PD_D1
PD_D3
PD_CS#3
PD_A0
PD_IRQ
PD_IOR#
PD_D11
MB2_LED#
MBAY_DET#
MB2_LED#
IDE_LED#SATA_LED#
SATA_LED#
ICH_RTCRST#
AC97_SDIN0<25>AC97_SDIN1<31>
LPC_AD[0..3] <24,28,29,30>
H_A20M# <4>
H_DPRSTP# <4,42>H_DPSLP# <4>
H_FERR# <4>
H_PWRGOOD <4>
H_IGNNE# <4>
H_INIT# <4>H_INTR <4>
H_SMI# <4>H_NMI <4>
H_STPCLK# <4>
GATEA20 <30>
KB_RST# <30>
H_THERMTRIP# <4,7>
FWH_INIT#
LPC_DRQ#0 <28>
LPC_FRAME# <24,28,29,30>
AC97_SDOUT_MDC<31>
AC97_SDOUT_CODEC<25>
AC97_SYNC_CODEC<25>
AC97_SYNC_MDC<31>
AC97_BITCLK_CODEC<25>
AC97_BITCLK_MDC<31>
AC97_RST#_CODEC<25>
AC97_RST#_MDC<31>
CLK_PCIE_SATA#<15>CLK_PCIE_SATA<15>
PLT_RST#<7,16,18,20,22,24,30>PLT_RST_B# <24,28,29>
MB_PWR<20>
MBAY_DET#<20>
IDE_RESET#<18>
PCI_RST#<18,24>
IDE_LED# <24>
+3VS
+VCCP
+RTCVCC
+RTCVCC
+VCCP
+5VS_MB
+RTCVCC
+3VS
+3VS
+RTCVCC+3VL
+3VALW
+5VS+5VS
+5VS_MB
+5VS
+5VS_MB
+3VS
+5VS_MB
+3VS
+5VS +3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
ICH7-M(2/4)
19 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place close to JP37
Multi Bay II connector
-+
W=20mils
Place close to ICH7
Near ICH7(U26) side.
Near Device(JP45) side.
SATA CONN
R93
220K_0402_5%
1 2R10334.7K_0402_5%
12
C630
0.1U_0402_16V4Z
1
2
Y4
32.768KHZ_12.5P_MC-146
14
23
C627
0.1U_0402_16V4Z
1
2
C62410U_0805_10V4Z
1
2
R40533_0402_5%
12
R1241
0_0402_5%@
12
R976 1K_0402_5%1 2
D16 CH751H-40_SC7621
ZZZ
Audio-wire
T88PAD
C516
15P_0402_50V8J1 2
R1027 56_0402_5%
12
R1263
332K_0402_1%@
12
R40233_0402_5%
1 2
R37133_0402_5% 1 2
RTC
LAN
SATA
AC-97/AZALIA
LPC
CPU
IDE
U26A
ICH7_BGA652~D
RTXC1AB1RTCX2AB2
RTCRST#AA3
INTVRMENW4INTRUDER#Y5
EE_CSW1EE_SHCLKY1EE_DOUTY2EE_DINW3
LAN_CLKV3
LAN_RSTSYNCU3
LAN_RXD0U5LAN_RXD1V4LAN_RXD2T5
LAN_TXD0U7LAN_TXD1V6LAN_TXD2V7
ACZ_BCLKU1ACZ_SYNCR6
ACZ_RST#R5
ACZ_SDIN0T2ACZ_SDIN1T3ACZ_SDIN2T1
ACZ_SDOUTT4
SATALED#AF18
SATA0RXNAF3SATA0RXPAE3SATA0TXNAG2SATA0TXPAH2
SATA2RXNAF7SATA2RXPAE7SATA2TXNAG6SATA2TXPAH6
SATA_CLKNAF1SATA_CLKPAE1
SATARBIASNAH10SATARBIASPAG10
IORDYAG16IDEIRQAH16DDACK#AF16DIOW#AH15DIOR#AF15
LAD0 AA6LAD1 AB5LAD2 AC4LAD3 Y6
LDRQ0# AC3LDRQ1# / GPIO23 AA5
LFRAME# AB3
A20GATE AE22A20M# AH28
CPUSLP# AG27
TP1 / DPRSTP# AF24TP2 / DPSLP# AH25
FERR# AG26
GPIO49 / CPUPWRGD AG24
IGNNE# AG22INIT3_3V# AG21
INIT# AF22INTR AF25
RCIN# AG23
SMI# AF23NMI AH24
STPCLK# AH22
THERMTRIP# AF26
DA0 AH17DA1 AE17DA2 AF17
DCS1# AE16DCS3# AD16
DD0 AB15DD1 AE14DD2 AG13DD3 AF13DD4 AD14DD5 AC13DD6 AD12DD7 AC12DD8 AE12DD9 AF12
DD10 AB13DD11 AC14DD12 AF14DD13 AH13DD14 AH14DD15 AC15
DDREQ AE15
U43DSN74LVC08APW_TSSOP14
A12
B13 O 11
P14
G7
C52815P_0402_50V8J
1 2
R1243 10K_0402_5% 12
R37633_0402_5% 12
U43BSN74LVC08APW_TSSOP14
A4
B5 O 6
P14
G7
R8810K_0402_5%
12
R98
100_0402_5%
12
R1408 0_0402_5% 12
R1026
1M_0402_5%
1 2
R1036 0_0402_5% 12
R133
100_0402_5%
1 2
R83470K_0402_5%
12
R432
10M_0402_5%
12
C62910U_0805_10V4Z
1
2
C958 3900P_0402_50V7K1 2
C665
1U_0603_10V4Z
1
2
R10320_0402_5%
12
C956 3900P_0402_50V7K1 2
R9010K_0402_5%
12
G
D
SQ38RHU002N06_SOT323
2
13
R724.7K_0402_5%
12
C633
0.1U_0402_16V4Z
1
2
Q92AO4407_SO8
3 65
78
2
4
1
JP45
OCTEK_SAT-22DD1G
GND S1RX+ S2RX- S3
GND S4TX- S5TX+ S6
GND S7
3.3V P13.3V P23.3V P3GND P4GND P5GND P6
5V P75V P85V P9
GND P10Rsv P11
GND P1212V P1312V P1412V P15
boss
23bo
ss24
GN
D25
GN
D26
ZZZ
PCB-MB
R1037 0_0402_5%@12
C6310.1U_0402_16V4Z
1
2
T86PAD
G
D
SQ39RHU002N06_SOT323
2
13
R1240
332K_0402_1%
12
C640
10U_0805_10V4Z
1
2
R131533_0402_5% 1 2
R1031 24.9_0402_1% 1 2
R131433_0402_5% 1 2
R301
33_0402_5%
12
R1035 0_0402_5% 12
R102933_0402_5%
12
R1244 10K_0402_5% 12
R1256
24.9_0402_1%
1 2
R23020K_0402_5%
1 2
C625
0.1U_0402_16V4Z
1
2
D14
DAN202U_SC70
2
31
C626
0.1U_0402_16V4Z
1
2
C955 3900P_0402_50V7K1 2
C641
0.1U_0402_16V4Z
1 2
C2871U_0603_10V4Z 1 2
R1030
56_0402_5%
12
JP5
JAE_WM2M054JKB
1 12 23 34 45 56 67 78 89 9
10 1011 1112 1213 1314 1415 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 4849 4950 5051 5152 5253 5354 54
GND55GND56GND57GND58
R10348.2K_0402_5%
12
R1028
10_0402_5%@1 2
R36733_0402_5% 12
C721
10P_0402_25V8K@
12
C957 3900P_0402_50V7K1 2
R1025 0_0402_5% 12
D15 CH751H-40_SC7621
CMOS_CLR1
NO SHORT PADS
1 2
C628
0.1U_0402_16V4Z
1
2
JP42ACES_85205-0200
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LINKALERT#
OCP#
THERM_SCI#
SIRQ
PM_CLKRUN#
USB_OC#1
THERM_SCI#
USB_OC#2
CLK_48M_ICH
PM_BMBUSY#
CLK_14M_ICH
PLT_RST#
H_STP_CPU#
PWROK_ICH7
SLP_S3#XDP_DBRESET#
CLK_48M_ICH
CLK_14M_ICHICH_RI#
SIRQ
SLP_S5#OCP#
PM_CLKRUN#
SB_SPKR
LINKALERT#
H_STP_PCI#
ICH_SMLINK0ICH_SMLINK1
DPRSLPVR
ON/OFFBTN#
PM_POK
ICH_SUSCLK
USB_OC#3
DPRSLPVR
DMI_TXN3
DMI_TXN0
USBRBIAS
DMI_TXP1
USB_OC#2
USB_OC#4
DMI_TXP2
USB_OC#3
DMI_TXN1
DMI_RXN1
USB_OC#1
DMI_TXP3
DMI_RXP1
DMI_RXN3
CLK_PCIE_ICH
DMI_RXN2
DMI_RXN0
DMI_TXP0
DMI_RXP3
CLK_PCIE_ICH#
DMI_TXN2
DMI_RXP0
USB_OC#4
DMI_RXP2
USB20_N7USB20_P7
USB20_N6USB20_P6
USB20_N0USB20_P0USB20_N1USB20_P1USB20_N2USB20_P2USB20_N3USB20_P3USB20_N4USB20_P4USB20_N5USB20_P5
ICH_LOW_BAT#
FWH_TBL#FWH_WP#
LID_SW#
DMI_IRCOMP
PCIE_C_TXP1
PCIE_RXN1PCIE_RXP1PCIE_C_TXN1
LPC_PD#
PM_RSMRST#
SLP_S4#
ISO_PREP#PREP#
PCIE_C_TXP2PCIE_C_TXN2PCIE_RXP2PCIE_RXN2
USB_OC#0
USB_OC#0
RUNSCI_EC#ISO_PREP#
USB_OC#5
USB_OC#5
LID_SW#LANLINK_STATUS#
CB_IN#
XMIT_OFF
NPCI_RST#
SPI_CS#
SPI_SO
SPI_CLK
ICH_SMBCLK ICH_SMB_CLK
ICH_SMB_DATAICH_SMBDATA
ICH_SMB_DATAICH_SMBCLKICH_SMBDATA
ICH_SMB_CLK
XDP_DBRESET# PWROK_ICH7
USB_OC#6USB_OC#7
USB_OC#6
USB_OC#7
SPI_SI
PCIE_C_TXP4
PCIE_RXP4PCIE_C_TXN4
PCIE_RXN4
ICH_PCIE_WAKE#
GPIO25
GPIO25
LP_EN#
SPI_CS#
SPI_SI
SPI_SO
HDD_HALTLED
HDD_HALTLED
PM_CLKRUN#<24,28,29,30>
H_STP_PCI#<15>H_STP_CPU#<15>
PM_BMBUSY#<7>
SIRQ<24,28,29,30>THERM_SCI#<4>
SLP_S3# <22,24,25,26,30,32,33,40,41>
SLP_S5# <33,41>
DPRSLPVR <7,42>
DMI_RXN0 <7>DMI_RXP0 <7>DMI_TXN0 <7>DMI_TXP0 <7>
DMI_RXN1 <7>DMI_RXP1 <7>DMI_TXN1 <7>DMI_TXP1 <7>
DMI_RXN2 <7>DMI_RXP2 <7>DMI_TXN2 <7>DMI_TXP2 <7>
DMI_RXN3 <7>DMI_RXP3 <7>DMI_TXN3 <7>DMI_TXP3 <7>
CLK_PCIE_ICH# <15>CLK_PCIE_ICH <15>
PM_RSMRST# <30>
ON/OFFBTN# <31>
PM_POK <7,30>
CLK_48M_ICH <15>CLK_14M_ICH <15>
USB20_P7 <32>USB20_N7 <32>
USB20_N6 <32>USB20_P6 <32>
USB20_N1 <24>USB20_P1 <24>USB20_N2 <29>USB20_P2 <29>USB20_N3 <27>USB20_P3 <27>USB20_N4 <27>USB20_P4 <27>USB20_N5 <27>USB20_P5 <27>
USB20_N0 <27>USB20_P0 <27>
LOW_BAT# <30>
XDP_DBRESET#<4>
OCP#<4,43>
FWH_WP#FWH_TBL#
PCIE_RXN1<22>
PCIE_TXN1<22>PCIE_TXP1<22>
PCIE_RXP1<22>
LPC_PD#<29,30>
SLP_S4# <41>
PREP#<23,25,32>
PCIE_TXN2<24>PCIE_RXP2<24>PCIE_RXN2<24>
PCIE_TXP2<24>
RUNSCI_EC#<30>
LOM_LOW_PWR <22>
CABLE_DETECT <22,23>
LID_SW# <17,31>LANLINK_STATUS# <22,23,32>
XMIT_OFF <24>
NPCI_RST# <28>
SPI_SO<29>
SPI_CS#<29>
SPI_SI<29>
SPI_CLK<29>
ISO_PREP#<32>
ICH_SMBCLK<4,13,14,15,22,24>
ICH_SMBDATA<4,13,14,15,22,24>
MBAY_DET# <19>
VGATE_INTEL<7,42>
PM_POK<7,30>
DOCK_ID <32>
MB_PWR <19>
WXMIT_OFF#<24>
PLT_RST# <7,16,18,19,22,24,30>
PCIE_TXP4<32>
PCIE_RXP4<32>PCIE_TXN4<32>
PCIE_RXN4<32>
ICH_PCIE_WAKE#<22,24>
BT_OFF <27>
LP_EN#<22>
HDD_HALTLED# <24>
SB_SPKR<25>
+3VALW
+3VALW
+3VS
+3VALW
+1.5VS
+3VALW
+3VL
+3VALW
V_3P3_LAN +3VS
+3VALW
+3VALW
+5VS
+3VS
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
ICH7-M(3/4)
20 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place closely pin B2 Place closely pin AC1
Within 500 mils
Within 500 mils
L R1292/R1293 should be placedless than 100 mils from U26.
R1015 need be removed when ICH7M ES2 samples used,but need be stuffed when ICH7M ES1 samples used.
LR1284,R1285 and R1286 shouldbe placed close to U26.
L R213,R233 change from 2.2Kohm to10Kohm when Q23,Q24,R206,R204 stuffed.
R100610K_0402_5% 1 2
G
D
S
Q43RHU002N06_SOT323
2
13
R1007
10K_0402_5%
12
R129247_0402_5%
1 2
C706
4.7P_0402_50V8C@
1
2
R1015100K_0402_5%@
12
R233
2.2K_0402_5%
1
2
R5321K_0402_5% 1 2
R1019 22.6_0402_1% 1 2
R206
2.2K_0402_5%@
12
G
DS
Q23RHU002N06_SOT323@
2
13
C9530.1U_0402_16V4Z 12
D57
CH751H-40_SC76
21
RP64
10K_1206_8P4R_5%
1 82 73 64 5
R1285 10K_0402_5%1 2
R102010K_0402_5%
1 2
T91
PAD
R1001
10K_0402_5%
12
R101010K_0402_5%
1 2
R1373 0_0402_5%@1 2
C9520.1U_0402_16V4Z 12
R10118.2K_0402_5%
12
R1395 0_0402_5%1 2
C7100.1U_0402_16V4Z 12
R997
10_0402_5%@
12
R1437100K_0402_5%
12
R126110K_0402_5%
1 2
R1016 24.9_0402_1%
1 2
T80 PAD
R101310K_0402_5%
12
R1008
10K_0402_5%
12
R1386 0_0402_5%@1 2
R998
10_0402_5%@
12
R13200_0402_5%1 2
R9998.2K_0402_5%
1 2
T89 PAD
R1374 0_0402_5%1 2
R99410K_0402_5% 1 2
R101810K_0402_5%
1 2
R1003
8.2K_0402_5%
1 2
R1284 10K_0402_5%1 2
J28
PAD-SHORT 2x2m
2 1
R1014 10K_0402_5%
1 2
R100410K_0402_5% 1 2
R13190_0402_5%1 2
T94PAD
R1002 100_0402_5%
1 2
R99310K_0402_5%@1 2
G
DS
Q24RHU002N06_SOT323@2
13
PCI-EXPRESS
DIRECT MEDIA INTERFACE
USB
SPI
U26D
ICH7_BGA652~D
SPI_CLKR2SPI_CS#P6SPI_ARBP1
SPI_MOSIP5SPI_MISOP2
DMI0RXN V26DMI0RXP V25DMI0TXN U28DMI0TXP U27
DMI1RXN Y26DMI1RXP Y25DMI1TXN W28DMI1TXP W27
DMI2RXN AB26DMI2RXP AB25DMI2TXN AA28DMI2TXP AA27
DMI3RXN AD25DMI3RXP AD24DMI3TXN AC28DMI3TXP AC27
DMI_CLKN AE28DMI_CLKP AE27
DMI_ZCOMP C25DMI_IRCOMP D25
PERn1F26PERp1F25PETn1E28PETp1E27
PERn2H26PERp2H25PETn2G28PETp2G27
PERn3K26PERp3K25PETn3J28PETp3J27
PERn4M26PERp4M25PETn4L28PETp4L27
PERn5P26PERp5P25PETn5N28PETp5N27
PERn6T25PERp6T24PETn6R28PETp6R27
OC0#D3OC1#C4OC2#D5OC3#D4OC4#E5OC5# / GPIO29C3OC6# / GPIO30A2OC7# / GPIO31B3
USBP0N F1USBP0P F2USBP1N G4USBP1P G3USBP2N H1USBP2P H2USBP3N J4USBP3P J3USBP4N K1USBP4P K2USBP5N L4USBP5P L5USBP6N M1USBP6P M2USBP7N N4USBP7P N3
USBRBIAS# D2USBRBIAS D1
D58
CH751H-40_SC76
2 1
R100510K_0402_5% 1 2
T90PAD
C707
4.7P_0402_50V8C@
1
2
R1017 0_0402_5%@12
R1000
10K_0402_5%
12
R129347_0402_5%
1 2
T67 PAD
C7090.1U_0402_16V4Z 12
R213
2.2K_0402_5%
12
R204
2.2K_0402_5%@
12
C7110.1U_0402_16V4Z 12
R100910K_0402_5% 1 2
R1286 10K_0402_5%1 2
SATA
POWER MGT
SYS
SMB
GPIO
Clocks
GPIO
GPIO
U26C
ICH7_BGA652~D
RI#A28
SPKRA19
SYS_RST#A22 SUS_STAT#A27
GPIO0 / BM_BUSY#AB18
GPIO26A21
GPIO27B21GPIO28E23
GPIO32 / CLKRUN#AG18
GPIO33 / AZ_DOCK_EN#AC19GPIO34 / AZ_DOCK_RST#U2
VRMPWRGDAD22
GPIO11 / SMBALERT#B23
SUSCLK C20
SLP_S3# B24SLP_S4# D23SLP_S5# F22
PWROK AA4
GPIO16 / DPRSLPVR AC22
TP0 / BATLOW# C21
PWRBTN# C23
LAN_RST# C19
RSMRST# Y4
GPIO21 / SATA0GP AF19GPIO19 / SATA1GP AH18GPIO36 / SATA2GP AH19GPIO37 / SATA3GP AE19
CLK14 AC1CLK48 B2
GPIO9 E20GPIO10 A20GPIO12 F19GPIO13 E19GPIO14 R4GPIO15 E22GPIO24 R3GPIO25 D20
GPIO35 / SATAREQ# AD21GPIO38 AD20GPIO39 AE20
SMBCLKC22SMBDATAB22LINKALERT#A26SMLINK0B25SMLINK1A25
GPIO18 / STPPCI#AC20GPIO20 / STPCPU#AF21
WAKE#F20SERIRQAH21THRM#AF20
GPIO6AC21GPIO7AC18GPIO8E21
C7080.1U_0402_16V4Z 12
R1322 10K_0402_5%1 2
R123710K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_V5REF_SUS
ICH_V5REF_RUN
ICH_V5REF_RUN
ICH_V5REF_SUS
ICH_AA2ICH_Y7
ICH_K7
ICH_C28ICH_G20
+1.5VS_DMIPLL+3VALW
+VCCP
+3VS
+1.5VS
+RTCVCC
+3VALW
+1.5VS
+1.5VS
+3VS+5VS
+3VALW+5VALW
+3VS
+1.5VS
+1.5VS
+3VS
+3VS
+3VS
+3VALW
+3VALW
+1.5VS
+VCCP
+1.5VS
+1.5VS_DMIPLL+1.5VS_DMIPLLR
+3VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
ICH7-M(4/4)
21 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place closely pinD28,T28,AD28.
Place closely pin AG28 within 100mlis.
Place closely pin AG5.
Place closely pin AG9.C702
0.1U_0402_16V4Z
1
2
C69
8
0.1U
_040
2_16
V4Z
1
2
C674
0.1U_0402_16V4Z
1
2
C684
0.1U_0402_16V4Z
1
2
C677
0.1U_0402_16V4Z
1
2
+
C57
015
0U_D
_6.3
VM 1
2
T82PAD
U26E
ICH7_BGA652~D
VSS[0]A4VSS[1]A23VSS[2]B1VSS[3]B8VSS[4]B11VSS[5]B14VSS[6]B17VSS[7]B20VSS[8]B26VSS[9]B28VSS[10]C2VSS[11]C6VSS[12]C27VSS[13]D10VSS[14]D13VSS[15]D18VSS[16]D21VSS[17]D24VSS[18]E1VSS[19]E2VSS[21]E4VSS[22]E8VSS[23]E15VSS[24]F3VSS[25]F4VSS[26]F5VSS[27]F12VSS[28]F27VSS[29]F28VSS[30]G1VSS[31]G2VSS[32]G5VSS[33]G6VSS[34]G9VSS[35]G14VSS[36]G18VSS[37]G21VSS[38]G24VSS[39]G25VSS[40]G26VSS[41]H3VSS[42]H4VSS[43]H5VSS[44]H24VSS[45]H27VSS[46]H28VSS[47]J1VSS[48]J2VSS[49]J5VSS[50]J24VSS[51]J25VSS[52]J26VSS[53]K24VSS[54]K27VSS[55]K28VSS[56]L13VSS[57]L15VSS[58]L24VSS[59]L25VSS[60]L26VSS[61]M3VSS[62]M4VSS[63]M5VSS[64]M12VSS[65]M13VSS[66]M14VSS[67]M15VSS[68]M16VSS[69]M17VSS[70]M24VSS[71]M27VSS[72]M28VSS[73]N1VSS[74]N2VSS[75]N5VSS[76]N6VSS[77]N11VSS[78]N12VSS[79]N13VSS[80]N14VSS[81]N15VSS[82]N16VSS[83]N17VSS[84]N18VSS[85]N24VSS[86]N25VSS[87]N26VSS[88]P3VSS[89]P4VSS[90]P12VSS[91]P13VSS[92]P14VSS[93]P15VSS[94]P16VSS[95]P17VSS[96]P24VSS[97]P27
VSS[98] P28VSS[99] R1
VSS[100] R11VSS[101] R12VSS[102] R13VSS[103] R14VSS[104] R15VSS[105] R16VSS[106] R17VSS[107] R18VSS[108] T6VSS[109] T12VSS[110] T13VSS[111] T14VSS[112] T15VSS[113] T16VSS[114] T17VSS[115] U4VSS[116] U12VSS[117] U13VSS[118] U14VSS[119] U15VSS[120] U16VSS[121] U17VSS[122] U24VSS[123] U25VSS[124] U26VSS[125] V2VSS[126] V13VSS[127] V15VSS[128] V24VSS[129] V27VSS[130] V28VSS[131] W6VSS[132] W24VSS[133] W25VSS[134] W26VSS[135] Y3VSS[136] Y24VSS[137] Y27VSS[138] Y28VSS[139] AA1VSS[140] AA24VSS[141] AA25VSS[142] AA26VSS[143] AB4VSS[144] AB6VSS[145] AB11VSS[146] AB14VSS[147] AB16VSS[148] AB19VSS[149] AB21VSS[150] AB24VSS[151] AB27VSS[152] AB28VSS[153] AC2VSS[154] AC5VSS[155] AC9VSS[156] AC11VSS[157] AD1VSS[158] AD3VSS[159] AD4VSS[160] AD7VSS[161] AD8VSS[162] AD11VSS[163] AD15VSS[164] AD19VSS[165] AD23VSS[166] AE2VSS[167] AE4VSS[168] AE8VSS[169] AE11VSS[170] AE13VSS[171] AE18VSS[172] AE21VSS[173] AE24VSS[174] AE25VSS[175] AF2VSS[176] AF4VSS[177] AF8VSS[178] AF11VSS[179] AF27VSS[180] AF28VSS[181] AG1VSS[182] AG3VSS[183] AG7VSS[184] AG11VSS[185] AG14VSS[186] AG17VSS[187] AG20VSS[188] AG25VSS[189] AH1VSS[190] AH3VSS[191] AH7VSS[192] AH12VSS[193] AH23VSS[194] AH27
C705
0.1U_0402_16V4Z
1
2
T84 PAD
C690
0.1U_0402_16V4Z
1
2
C701 0.1U_0402_16V4Z
1 2
D56
CH751H-40_SC76
21
C697
0.1U_0402_16V4Z
1
2
R989
100_0402_5%
12
C700
1U_0603_10V4Z
1
2
C69
10.
1U_0
402_
16V4
Z
1
2
C69
310
U_0
805_
10V4
Z
1
2
C975
0.1U_0402_16V4Z
1
2
T81PAD
C68
70.
1U_0
402_
16V4
Z
1
2
C696
0.1U_0402_16V4Z
1
2
C681
0.1U_0402_16V4Z
1
2
R992
0_0805_5%
1 2
C676
0.1U_0402_16V4Z
1
2
R990
10_0402_5%
12
T83PAD
+ C979
330U_D2E_2.5VM_R9@
1
2
C974
1U_0603_10V4Z
1
2
T85 PAD
D55
CH751H-40_SC76
21
U26F
ICH7_BGA652~D
V5REF[1]G10
V5REF[2]AD17
V5REF_SusF6
Vcc1_5_B[1]AA22Vcc1_5_B[2]AA23Vcc1_5_B[3]AB22Vcc1_5_B[4]AB23Vcc1_5_B[5]AC23Vcc1_5_B[6]AC24Vcc1_5_B[7]AC25Vcc1_5_B[8]AC26Vcc1_5_B[9]AD26Vcc1_5_B[10]AD27Vcc1_5_B[11]AD28Vcc1_5_B[12]D26Vcc1_5_B[13]D27Vcc1_5_B[14]D28Vcc1_5_B[15]E24Vcc1_5_B[16]E25Vcc1_5_B[17]E26Vcc1_5_B[18]F23Vcc1_5_B[19]F24Vcc1_5_B[20]G22Vcc1_5_B[21]G23Vcc1_5_B[22]H22Vcc1_5_B[23]H23Vcc1_5_B[24]J22Vcc1_5_B[25]J23Vcc1_5_B[26]K22Vcc1_5_B[27]K23Vcc1_5_B[28]L22Vcc1_5_B[29]L23Vcc1_5_B[30]M22Vcc1_5_B[31]M23Vcc1_5_B[32]N22Vcc1_5_B[33]N23Vcc1_5_B[34]P22Vcc1_5_B[35]P23Vcc1_5_B[36]R22Vcc1_5_B[37]R23Vcc1_5_B[38]R24Vcc1_5_B[39]R25
Vcc1_5_B[41]T22Vcc1_5_B[42]T23Vcc1_5_B[43]T26Vcc1_5_B[44]T27Vcc1_5_B[45]T28Vcc1_5_B[46]U22Vcc1_5_B[47]U23Vcc1_5_B[48]V22Vcc1_5_B[49]V23Vcc1_5_B[50]W22
Vcc1_5_B[52]Y22Vcc1_5_B[53]Y23
Vcc1_5_B[51]W23
Vcc1_5_B[40]R26
Vcc3_3[1]B27
VccDMIPLLAG28
VccSATAPLLAD2
Vcc3_3[2]AH11
Vcc1_05[1] L11Vcc1_05[2] L12Vcc1_05[3] L14Vcc1_05[4] L16
Vcc1_05[6] L18Vcc1_05[5] L17
Vcc1_05[7] M11Vcc1_05[8] M18Vcc1_05[9] P11
Vcc1_05[10] P18Vcc1_05[11] T11Vcc1_05[12] T18Vcc1_05[13] U11Vcc1_05[14] U18Vcc1_05[15] V11Vcc1_05[16] V12Vcc1_05[17] V14Vcc1_05[18] V16Vcc1_05[19] V17Vcc1_05[20] V18
Vcc3_3 / VccHDA U6
VccSus3_3/VccSusHDA R7
V_CPU_IO[1] AE23V_CPU_IO[2] AE26V_CPU_IO[3] AH26
Vcc3_3[3] AA7Vcc3_3[4] AB12Vcc3_3[5] AB20Vcc3_3[6] AC16Vcc3_3[7] AD13Vcc3_3[8] AD18Vcc3_3[9] AG12
Vcc3_3[10] AG15Vcc3_3[11] AG19
Vcc3_3[12] A5
Vcc3_3[14] B16Vcc3_3[15] B7Vcc3_3[16] C10
Vcc3_3[13] B13
Vcc3_3[17] D15Vcc3_3[18] F9Vcc3_3[19] G11Vcc3_3[20] G12
VccRTC W5
VccSus3_3[1] P7
VccSus3_3[2] A24
VccSus3_3[4] D19VccSus3_3[5] D22VccSus3_3[6] G19
VccSus3_3[3] C24
VccSus3_3[7] K3VccSus3_3[8] K4VccSus3_3[9] K5
VccSus3_3[10] K6VccSus3_3[11] L1
Vcc1_5_A[19] AB17Vcc1_5_A[20] AC17
Vcc1_5_A[21] T7Vcc1_5_A[22] F17Vcc1_5_A[23] G17
Vcc1_5_A[24] AB8Vcc1_5_A[25] AC8
VccSus1_05[1] K7
Vcc1_5_A[1]AB7Vcc1_5_A[2]AC6Vcc1_5_A[3]AC7Vcc1_5_A[4]AD6Vcc1_5_A[5]AE6Vcc1_5_A[6]AF5Vcc1_5_A[7]AF6Vcc1_5_A[8]AG5Vcc1_5_A[9]AH5
Vcc1_5_A[10]AB10Vcc1_5_A[11]AB9Vcc1_5_A[12]AC10Vcc1_5_A[13]AD10Vcc1_5_A[14]AE10Vcc1_5_A[15]AF10Vcc1_5_A[16]AF9Vcc1_5_A[17]AG9Vcc1_5_A[18]AH9
VccSus3_3[19]E3
VccUSBPLLC1
VccSus1_05/VccLAN1_05[1]AA2VccSus1_05/VccLAN1_05[2]Y7
VccSus3_3/VccLAN3_3[1]V5VccSus3_3/VccLAN3_3[2]V1VccSus3_3/VccLAN3_3[3]W2VccSus3_3/VccLAN3_3[4]W7
Vcc3_3[21] G16
VccSus3_3[12] L2VccSus3_3[13] L3VccSus3_3[14] L6VccSus3_3[15] L7VccSus3_3[16] M6VccSus3_3[17] M7VccSus3_3[18] N7
VccSus1_05[2] C28VccSus1_05[3] G20
Vcc1_5_A[26] A1Vcc1_5_A[27] H6Vcc1_5_A[28] H7Vcc1_5_A[29] J6Vcc1_5_A[30] J7
C69
40.
01U
_040
2_16
V7K
1
2
C688
0.1U_0402_16V4Z
1
2
C69
20.
1U_0
402_
16V4
Z
1
2
C679
0.1U_0402_16V4Z
1 2
C69
90.
1U_0
402_
16V4
Z
1
2
C695
0.1U_0402_16V4Z
1
2
C68
50.
1U_0
402_
16V4
Z
1
2
C678
0.1U_0402_16V4Z
1
2
+
C670
220U_D2_2VM_R9
1
2
C68
60.
1U_0
402_
16V4
Z
1
2
R991
0.5_0805_1%
1 2
C6824.7U_0805_10V4Z
1 2
C704
0.1U_0402_16V4Z
1
2
C672
0.1U_0402_16V4Z
1
2
C6800.1U_0402_16V4Z
1 2
C673
0.1U_0402_16V4Z
1
2
C703
0.1U_0402_16V4Z
1
2
C689
0.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LP_EN#
LP_EN#
5751_GPIO1
ICH_LAN_SMBDATA
5751_EEDAT5751_EECLK
ICH_LAN_SMBDATA
LOM_LOW_PWR
ICH_LAN_SMBCLK
LANLINK_STATUS#
XTALI
CLK_PCIE_LOM#CLK_PCIE_LOM
LOM_PCIE_WAKE#
PCIE_C_RXN1
PCIE_C_RXP1
VAUX_1.2_CTL
LAN_TX1+
LAN_TX0+
LAN_TX2-
LAN_TX0-
LAN_TX1-
LAN_TX2+
LAN_TX3+LAN_TX3-
5751_GPIO15751_EECLK5751_EEDAT
CABLE_DETECT
ICH_SMBDATAICH_SMBCLK
ICH_LAN_SMBDATA
ICH_LAN_SMBCLKICH_SMBCLK
ICH_SMBDATA
VAUX_1.2_CTL
REGSUP12
ICH_LAN_SMBCLK
LAN_ACT#
REGSUP12
XTALO
PLT_RST_LAN#
PLT_RST_LAN#
LOM_LOW_PWR
LOM_PCIE_WAKE#
NIC_PD
NIC_PD#
NIC_PD_N
NIC_PD
NIC_PD_N
SLP_S3#<20,24,25,26,30,32,33,40,41>
ADP_PRES<30,37,38,39,43>
LP_EN# <20>
LOM_LOW_PWR<20>
CABLE_DETECT<20,23>
LAN_ACT#<23,32>
LANLINK_STATUS#<20,23,32>
CLK_PCIE_LOM# <15>CLK_PCIE_LOM <15>
PCIE_TXP1 <20>
PCIE_TXN1 <20>
PCIE_RXN1 <20>
PCIE_RXP1 <20>
LAN_TX3+ <23>LAN_TX3- <23>LAN_TX2+ <23>LAN_TX2- <23>LAN_TX1+ <23>LAN_TX1- <23>LAN_TX0+ <23>LAN_TX0- <23>
ICH_SMBDATA <4,13,14,15,20,24>ICH_SMBCLK <4,13,14,15,20,24>
PLT_RST#<7,16,18,19,20,24,30>
ICH_PCIE_WAKE# <20,24>
CLKREQA# <15>
NIC_PD <23>
V_3P3_LAN
+3VALW
V_1P2_LAN V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
+3VALW
+3VS
V_2P5_LAN
V_3P3_LAN
V_2P5_LAN
V_3P3_LAN
V_1P2_LAN
V_3P3_LAN
+5VS
+3VS
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
+3VS
V_3P3_LAN +3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
BCM5751M
22 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
L Place close U6 pin M13
L Place close U6 pin N13
Layout Notice : No highspeed signal should berouted near RDAC or onadjacent layer to RDAC
Layout Notice : Place as closechip as possible.
CKT Notice : CABLE IN, CABLE_DETECT=0CABLE OUT, CABLE_DETECT=1
LMust having maximizedcopper under pin 2 & 4 of Q13
C180.1U_0402_16V4Z
1 2
C24310U_0805_10V4Z @
1
2
R10880_0402_5%
1 2
R506
10K_0402_5%
12
R16
1K_0
402_
5%
12
C83
0.1U_0402_16V4Z 1
2
Q13BCP69_SOT223
1
24
3
R1398 0_0402_5%@1 2
C16
27P_0402_50V8J
1
2
R277 10K_0402_5%12
C19
27P_0402_50V8J 1
2
G
D
SQ30RHU002N06_SOT323
2
13
R73 4.7K_0402_5%1 2
C580
0.1U_0402_16V4Z
1 2
R1089
0_0402_5%
12
C74
0.1U_0402_16V4Z 1
2
R1094 0_0402_5%12
U36
SN74LVC1G17DBVR_SOT23-5@
O4 I 2
P5
G3
NC1
G
D
S
Q104AO7407_SOT323@
2
13
C32
0.1U
_040
2_16
V4Z
1
2
C44
0.1U
_040
2_16
V4Z
1
2
C32
44.
7U_0
805_
10V4
Z
1
2R1396 0_0402_5%@1 2
G
D
S Q54RHU002N06_SOT323
2
13
G
D S
Q103AO7407_SOT323
2
1 3
C578
0.1U_0402_16V4Z
1
2
C1058
0.1U_0402_16V4Z 1
2
R1082
100K_0402_5%
1 2
R540
10K_0402_5%
12
R26847K_0402_5%
12
R1419
220K_0402_5%
1 2
R10210_0402_5%@
12
R267
4.7K_0402_5%
12
R71 4.7K_0402_5%1 2
G
D
S
Q105RHU002N06_SOT323
2
13
R14032.2K_0402_5%@
12
G
DS
Q96 RHU002N06_SOT323@
2
13
R70
1.21K_0402_1%
12
R14 200_0402_1% 12
C170.1U_0402_16V4Z
1 2
U4
AT24C64AN-10SU-2.7_SO8
A01A12NC3GND4
VCC 8WP 7
SCL 6SDA 5
R10900_0402_5%@
1 2
R36 4.7K_0402_5%12
C9
0.1U_0402_16V4Z
12
+ C976
100U_B2_6.3VM
1
2
C347
4.7U_0805_10V4Z 1
2
R1024121K_0402_1%
1 2
R1420
0_0402_5%@
12
C55
0.1U_0402_16V4Z 1
2
G
DS
Q93 RHU002N06_SOT323@
2
13
Y1
25MHZ_20P_1BG25000CK1A
1 2
R10220_0402_5%
12
G
D
SQ29RHU002N06_SOT323
2
13
C22810U_0805_10V4Z
1
2
C39
0.1U
_040
2_16
V4Z
1
2
R503
100K_0402_5%
1 2
R275 1K_0402_5%1 2
G
D
S
Q40AO7407_SOT323
2
13
C576
0.1U_0402_16V4Z
1
2
R1076
4.7K_0402_5%
1 2
C41
0.1U
_040
2_16
V4Z
1
2
C348
4.7U_0805_10V4Z 1
2
R108510K_0402_5%
12
Media
Misc
BCM5753
Power
Hot Plug
PCI-E
TEST
LED
Bias
Clock
Control
Support
Regulator
Control
U7A
BCM5753MKFBG P3_FPBGA196~D
GPIO0_TST_CLKOUTJ10GPIO1J12
SMB_CLKD9SMB_DATAD8
EECLKH10EEDATAJ11
SIF11
SCLKD10
SOE10
CS#D11
PWR_IND#H2ATTN_IND#J2ATTN_BTTN#B3
LINKLED#B10SPD100LED#C10SPD1000LED#B11TRAFFICLED#C9
XTALIM10
XTALON10
REFCLK_SEL C4
TRD3+ C12TRD3- C13TRD2+ D12TRD2- D13TRD1+ E12TRD1- E13TRD0+ F12TRD0- F13
LOW_PWR J5
REGSUP12 L13REGCTL12 K12REGSEN12 K13
REGOUT25 N13
REGSUP25 M13
PCIE_TXDN N4
PCIE_TXDP M4
PCIE_RXDN M8
PCIE_RXDP N8
WAKE# B5REFCLK- M6REFCLK+ N6
PCIE_TST D7PERST# C2
RDAC B9
TCK C6TDI G4
TDO C5TMS F4
TRST# E5
G
DS
Q31SI2301BDS_SOT23
2
13
R34
1K_0
402_
5%
12
R13922.2K_0402_5%@
12
R10910_0402_5%@1 2
R1397
0_0402_5%@
12
U55SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1R507
0_0402_5%@
1 2R1023
0_0402_5%12
R289 1K_0402_5%1 2
C68
0.1U_0402_16V4Z 1
2
J7
PAD-NO SHORT 2x2m
21
R35
1K_0
402_
5%
12
D63 1N4148_SOD80
1 2
G
D
S Q94RHU002N06_SOT323
2
13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MDO3-
MDO3+
LAN_TX3-LAN_TX3+
LAN_TX2+LAN_TX2-LAN_TX1+
LAN_TX0+LAN_TX0-
LAN_TX1-
BIASVDD_LAN
MCT1
MCT0TRM_CT
LAN_TX0+
LAN_TX0-
TRM_CT
TRM_CT
TRM_CT
LAN_TX1-
LAN_TX1+
LAN_TX2-
LAN_TX2+
LAN_TX3-
LAN_TX3+
MDO2-
MDO2+
MDO0+
MDO0-
MDO1-
MDO1+
LAN_AUXPWR
MDO1-
MDO1+
MDO2-
MDO2+
MDO0+
MDO0-
MDO3+
MDO3-
LANLINK_STATUS#
LAN_ACT#
VMAINPRSNT VMAINPRSNT_R
VMAINPRSNT
LAN_TX3+ <22>
LAN_TX0- <22>
LAN_TX1+ <22>
LAN_TX3- <22>LAN_TX2+ <22>
LAN_TX1- <22>LAN_TX0+ <22>
LAN_TX2- <22>
PREP#<20,25,32>
MDO3-<32>
MDO3+<32>
MDO1-<32>
MDO2-<32>
MDO2+<32>
MDO1+<32>
MDO0-<32>
MDO0+<32>
CABLE_DETECT <20,22>
LANLINK_STATUS#<20,22,32>
LAN_ACT#<22,32>
NIC_PD <22>
V_2P5_LAN
V_3P3_LAN V_3P3_LAN_LED
V_2P5_LAN V_1P2_LAN
AVDD1
XTALVDD
AVDD2
V_2P5_LAN
V_1P2_LAN
AVDDL
GPHY_PLLVDD
PCIE_PLLVDD
PCIE_SDS_VDD
V_2P5_LAN
V_1P2_LAN
V_3P3_LAN
V_3P3_LAN
V_3P3_LAN
AVDDL
AVDD2AVDD1
GPHY_PLLVDDPCIE_PLLVDD
V_2P5_LAN XTALVDD
PCIE_SDS_VDD
V_3P3_LAN
V_3P3_LAN_LED
V_3P3_LAN_LED
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Magnetic & RJ45/RJ11
23 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Layout Notice : Placetermination as close asBCM5751M as possible
L T59 , T60 place together
Layout Notice : Filter place as closechip as possible.
Layout Notice : 1.2V filter. Place as closechip as possible.
RJ-45 CONN.
R50 49.9_0402_1%
1 2
R10400_0402_5%1 2
T60PAD
C331
4.7U_0805_10V4Z 1
2
R27275_0402_1%
12
C579
0.1U_0402_16V4Z
1
2
G
D S
Q106 AO7407_SOT323@
2
1 3
R287 4.7K_0402_5%@ 1 2
R2761K_0402_5% 1 2
C540.1U_0402_16V4Z
1 2
R266 300_0402_5%12
C34
10.
1U_0
402_
16V4
Z
1
2
R525
100K_0402_5%
12
C34
30.
1U_0
402_
16V4
Z
1
2
C344
1000P_1808_3KV7K
1 2
C560.1U_0402_16V4Z
1 2
R44 49.9_0402_1%1 2
R41 49.9_0402_1%1 2
C46
0.1U_0402_16V4Z
1
2
C33
60.
1U_0
402_
16V4
Z
1
2
C63
0.1U_0402_16V4Z
1
2
G
D
SQ61RHU002N06_SOT323
2
13
C3300.01U_0402_16V7K
12
C66
4.7U
_080
5_10
V4Z
1
2
C323
4.7U_0805_10V4Z1
2
G
DS
Q60SI2301BDS_SOT232
13
C33
70.
1U_0
402_
16V4
Z
1
2
R63 49.9_0402_1%
1 2
C61
0.1U
_040
2_16
V4Z
1
2
R45 49.9_0402_1%
1 2
R27175_0402_1%
12C3280.01U_0402_16V7K
12
JP4
FOX_JM36113-P1122-7F
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Green LED-12
Green LED+11
Yellow LED-14
Yellow LED+13
SHLD1 15
SHLD1 16
DETECT PIN1 9
DETCET PIN2 10
L8
BLM11A601S_0603
1 2
C325
0.1U_0402_16V4Z1
2
C3270.01U_0402_16V7K
12
C15
0.1U_0402_16V4Z
1
2
R987
0_0603_5%12
C65
0.1U_0402_16V4Z
1
2
C34
00.
1U_0
402_
16V4
Z
1
2
L29
BLM11A601S_060312
R48 49.9_0402_1%
1 2
C490.1U_0402_16V4Z
1 2C35
0.1U_0402_16V4Z 1
2
C339
0.1U_0402_16V4Z 1
2C342
4.7U_0805_10V4Z1
2
1:1
1:1
1:1
1:1
T66
24HST1041-3TCT11
TD1+2
TD1-3
TCT24
TD21+5
TD2-6
TCT37
TD3+8
TD3-9
TCT410
TD4+11
TD4-12 MX4- 13
MX3- 16
MCT3 18
MX2- 19
MX2+ 20
MCT2 21
MX1- 22
MX1+ 23
MCT1 24
MX4+ 14
MCT4 15
MX3+ 17
C33
40.
1U_0
402_
16V4
Z
1
2
C326
0.1U_0402_16V4Z1
2
R985
0_0603_5%12
R986
0_0603_5%12
R40 49.9_0402_1%1 2
C33
80.
1U_0
402_
16V4
Z
1
2
C60
0.1U_0402_16V4Z1
2
C332
0.1U_0402_16V4Z 1
2
C320
1000P_1808_3KV7K
1 2
C500.1U_0402_16V4Z
1 2
C322
4.7U_0805_10V4Z
1
2
R871
10K_0402_5%
12
L32
BLM11A601S_0603
12
L30
BLM11A601S_060312
R284
4.7K_0402_5%@
12
R265 300_0402_5%12
BCM5753
Digial power
Analogpower
PLL
GND
BIAS
Don't care
Disconnected
U7B
BCM5753MKFBG P3_FPBGA196~D
VDDIO_0A2VDDIO_1A6VDDIO_2A10
VDDP_0B6VDDP_1H4VDDP_2M12
AVDDL_0G11AVDDL_1G12AVDD_0B12AVDD_1G13
PCIE_PLLVDDL7GPHY_PLLVDDH13
DC_31 P3DC_32 P4DC_33 P5DC_34 P6DC_35 P7DC_36 P8DC_37 P9DC_38 P10DC_39 P13
BIASVDD B13
VDDC_0E6VDDC_1E7VDDC_2E8VDDC_3E9VDDC_4J6VDDC_5J7VDDC_6J9VDDC_7K5
VSS_0 A3VSS_1 A8VSS_2 A12VSS_3 A14VSS_4 B1VSS_5 C1VSS_6 C3VSS_7 C11VSS_8 F1VSS_9 F5
VSS_10 F6VSS_11 F7VSS_12 F8VSS_13 F9VSS_14 F10VSS_15 G5VSS_16 G6VSS_17 G7VSS_18 G8VSS_19 G9VSS_20 G10VSS_21 H6VSS_22 H7VSS_23 H8VSS_24 H9VSS_25 J1VSS_26 M3VSS_27 M7
NC_0A1NC_1A4NC_2A5NC_3A7NC_4A9NC_5B2NC_6B7
DC_0 A11DC_1 A13DC_2 B14DC_3 C14DC_4 D6DC_5 D14DC_6 E3DC_7 E14DC_8 F14DC_9 G14
DC_10 H5DC_11 H14DC_12 J8DC_13 J14DC_14 K4DC_15 K6DC_16 K7DC_17 K8DC_18 K9DC_19 K10DC_20 K14DC_21 L6DC_22 L10DC_23 L12DC_24 L14DC_25 M11DC_26 M14DC_27 N5DC_28 N11DC_29 N12DC_30 N14
VDDIO_3B4VDDIO_4D3VDDIO_5E11VDDIO_6G2VDDIO_7H11VDDIO_8K3VDDIO_9M2VDDIO_10P12
VSS_28 N1VSS_29 N7VSS_30 P11VSS_31 P14
NC_7B8NC_8C8NC_9D1NC_10D2NC_11D4NC_12D5NC_13E1NC_14E2NC_15E4NC_16F2NC_17F3NC_18G1NC_19G3NC_20H1NC_21H3NC_22J3NC_23J4NC_24K1NC_25K2NC_26K11NC_27L1NC_28L2NC_29L3NC_30L4NC_31L8NC_32L9NC_33L11NC_34M1NC_35M5NC_36M9NC_37N2NC_38N3
XTALVDDJ13VAUXPRSNTC7VMAINPRSNTH12PCIE_SDSVDDL5
NC_39N9NC_40P1NC_41P2
R286 4.7K_0402_5%@ 1 2
C33
50.
1U_0
402_
16V4
Z
1
2
T59
PAD
L33
BLM11A601S_0603
12
R42 49.9_0402_1%1 2
R285 4.7K_0402_5%@ 1 2
R26975_0402_1%
12
R27075_0402_1%
12
C3290.01U_0402_16V7K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI_AD[0..31]
PCIE_TXN2
CH_DATA
WP_LED#
WW_LED#
CH_CLK
XMIT_OFF#
CLK_PCIE_MCARD
WL_LED#
PCIE_TXP2
CLK_PCIE_MCARD#
ICH_PCIE_WAKE#
CLKREQD#_MC
PCIE_C_RXP2PCIE_C_RXN2PCIE_RXN2
PCIE_RXP2
WW_LED#
M_WXMIT_OFF#
UIM_VPP
UIM_PWRUIM_DATAUIM_CLKUIM_RSTUIM_VPP
CLK_PCI_PCM
PCI_PIRQG#PCI_PIRQD#
PCI_PIRQC#PCI_RST#PCI_GNT2#
PCI_PIRQE#
LPC_AD0
LPC_AD3LPC_AD2
PLT_RST_B#
SC_CD#
SC_RSTSC_CLK
SC_DATA
SC_FCB
SC_RFU
PCI_AD13PCI_AD11PCI_AD9
PCI_CBE#0
PCI_AD2
PCI_AD6
PCI_AD0
PCI_AD4
PCI_STOP#PCI_TRDY#PCI_FRAME#
PCI_DEVSEL#PCI_AD15
PCI_PAR
PCI_AD16PCI_AD18
PCI_AD20PCI_AD22
PCI_AD28
PCI_AD24PCI_AD26
PCI_AD30
PCI_AD14PCI_AD12PCI_AD10
PCI_AD7PCI_AD8
PCI_AD5PCI_AD3PCI_AD1
PCI_SERR#
PCI_CBE#1PCI_PERR#
PCI_AD19
PCI_CBE#2PCI_AD17
PCI_IRDY#
PCI_REQ2#
PCI_AD29PCI_AD31
PCI_AD27PCI_AD25
PCI_AD23PCI_AD21
LPC_AD1
UIM_DATAUIM_RSTUIM_PWR
XMIT_OFF#
UIM_CLK
M_WXMIT_OFF#
CLK_48M_CB
PCI_AD[0..31] <18>
CLK_PCIE_MCARD<15>CLK_PCIE_MCARD#<15>
PLT_RST_B# <19,28,29>
ICH_SMBCLK <4,13,14,15,20,22>ICH_SMBDATA <4,13,14,15,20,22>PCIE_TXN2<20>
PCIE_TXP2<20>
WL_LED# <29>WW_LED# <29>
WP_LED# <29>
CLKREQD#<15>
PCIE_RXP2<20>PCIE_RXN2<20>
PLT_RST_B# <19,28,29>
WW_LED# <29>
USB20_N1 <20>USB20_P1 <20>
CH_CLK<27>CH_DATA<27>
XMIT_OFF<20>
ICH_SMBDATA <4,13,14,15,20,22>
ICH_SMBCLK <4,13,14,15,20,22>
ACCEL_INT <18>
CLK_PCI_PCM<15>
PCI_PIRQD#<18>PCI_PIRQG#<18>
PCI_PIRQC# <18>PCI_RST# <18,19>
PCI_PIRQE# <18>
PCI_GNT2# <18>SIRQ <20,28,29,30>
PCI_CBE#0 <18>
LPC_AD[0..3] <19,28,29,30>
LPC_FRAME# <19,28,29,30>
PLT_RST_B#<19,28,29>CLK_DEBUG_PORT<15>
STB_LED#<30,31,32>NUM_LED#<30,31>
SC_RST <27>SC_CLK <27>
SC_DATA <27>
SC_FCB <27>
SC_RFU <27>
SC_CD# <27>
IRRX <28>IRTXOUT <28>IRMODE <28>
PCI_TRDY# <18>PCI_STOP# <18>
PCI_FRAME# <18>
PCI_DEVSEL# <18>
PCI_PAR <18>
PLT_RST# <7,16,18,19,20,22,30>
PCM_SPK <25>
WL_BLUE_LED#<29,31>
PM_CLKRUN#<20,28,29,30>PCI_SERR#<18,30>PCI_PERR#<18>PCI_CBE#1<18>
PCI_CBE#2<18>PCI_IRDY#<18>
PCI_REQ2#<18>
PCI_CBE#3<18>
CLK_48M_CB <15>
HDD_HALTLED#<20>
STB_LED#<30,31,32>IDE_LED#<19>
AMBER_BATLED#<30>GREEN_BATLED#<30>
CAPS_LED#<30,31>
WXMIT_OFF#<20>
SLP_S3#<20,22,25,26,30,32,33,40,41>
ICH_PCIE_WAKE#<20,22>
+3VS +1.5VS
+1.5VS +3V_MINI
+3VALW
+3VS+1.5VS
+3VALW
+3VALW
+1.5VS +3VS
+3VALW
+3VS_UIM
+3VS +3VS_ACL
+3VS_ACL
+3VS_ACL_IO
+3VS_ACL_IO
+3VS_ACL
+3VS_ACL
+SC_PWR+5VS
+3VS
+3VL
+3VS_UIM
+3VL
+3VS
+3VS
+3VALW +3V_MINI +3VS
+3VS
+3VS +3VS
V_3P3_LAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Mini-Card/Mini-PCI/Accelerometer
24 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Mini-Express Card---WLAN
B/B connector with PCI / LED / FIR / SC interface
Mini-Express Card--WWANACCELEROMETER
Must be placed in the center of the system.
R1359 0_0402_5%12
R13640_0402_5%@
1 2
C544
4.7U_0805_10V4Z
1
2
R1360 0_0402_5%DEBUG@1 2
U64
LIS3LV02DQ_QFN28
Vdd
19
NC515 NC414
NC621
GN
D17
GN
D2
Vdd
3
Reserved14
GN
D5
NC38 NC27 NC11
PAD
DLE
29
NC722NC823NC924NC1025NC1126NC1227NC1328
Reserved218
Reserved320
RDY/INT 6
SDO 9
SDA/SDI/SDO 10
Vdd_
IO11
SCL/SPC 12
CS 13
CK 16
C533
4.7U_0805_10V4Z
1
2
JP44
MOLEX 67910-0002 52P
11 2 233 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 202121 22 222323 24 242525 26 262727 28 282929 30 303131 32 323333 34 343535 36 363737 38 383939 40 404141 42 424343 44 444545 46 464747 48 484949 50 505151 52 52
GND153 GND2 54
C538
0.1U_0402_16V4Z
1
2
R1348 0_0402_5%1 2
R10610_0402_5%@
12
JP46
MOLEX 67910-0002 52P
11 2 233 4 455 6 677 8 899 10 101111 12 121313 14 141515 16 161717 18 181919 20 202121 22 222323 24 242525 26 262727 28 282929 30 303131 32 323333 34 343535 36 363737 38 383939 40 404141 42 424343 44 444545 46 464747 48 484949 50 505151 52 52
GND153 GND2 54
C540
0.1U_0402_16V4Z
1
2
R1356
0_0603_5%1 2
R1361
0_0402_5%
12
88020-90101
JP13
40 404141
14 14
3737
8383
4545
5555
99
36 36
68 68
10 10
55 6 6
88 88
6969
6363
54 54
58 58
32 32
6565
11
66 6664 6462 62
8989
84 84
7777
2323
28 28
80 80
59596161
8787
24 24
3333
1919
48 48
6767
4949
2929
7575
82 82
20 20
76 76
1515
7373
42 42
38 38
8181
2525
16 16
86 86
5757
5353
1111
3939
7171
12 12
7979
77
90 90
8 8
3535
4343
60 60
4 4
34 34
33
74 74
30 30
56 56
72 72
78 78
2 2
8585
2121
26 26
50 50
22 22
5151
46 46
3131
1717
52 52
4747
44 44
18 18
1313
70 70
2727
GND 92GND 94GND 96
GND91GND93GND95
R1355
0_0805_5%@1 2
R1414
0_0402_5%DEBUG@
1 2
C547
0.01U_0402_16V7K
1
2
C542
4.7U_0805_10V4Z
1
2
C16518P_0402_50V8J@
1
2
R521
100K_0402_5%
12
C291
0.01U_0402_16V7K
1
2
R1422 0_0402_5%1 2
R516
10K_0402_5%@
12
R1415
0_0402_5%DEBUG@
1 2
SW11BD002-1101L_4P
2
4
1
3
U72
S DIO(BR) NUP4301MR6T1 TSOP-6
CH11
Vn2
CH23 CH3 4
Vp 5
CH4 6
R1417
0_0402_5%DEBUG@
1 2
R1413
0_0402_5%DEBUG@
1 2
R1349 0_0402_5%1 2
G
DS
Q41
SI2301BDS_SOT23@
2
13
D13
DAN217_SC59
@
2
31
R1416
0_0402_5%DEBUG@
1 2
G
D
SQ58RHU002N06_SOT323@
2
13
C996
10U_0805_10V4Z
1
2
C295
0.01U_0402_16V7K
1
2
R1357 0_0402_5%12
R1418 0_0402_5%DEBUG@1 2
C986
0.1U_0402_16V4Z
1
2
R10710_0603_5%1 2
C954
0.1U_0402_16V4Z
1
2
C960
0.1U
_040
2_16
V4Z
1
2
JP50
SUYIN_254021MA006G100ZL
VCC 1RST 2CLK 3
GND4VPP5I/O6
D64CH751H-40_SC76
2 1
G
D
SQ42RHU002N06_SOT323@
2
13
L78
FBMA-L11-201209-102LMA10T
1 2
R1365 0_0402_5%@1 2
R517
100K_0402_5%@
12
R1425
0_0402_5%@1 2
R1391
0_0402_5%
1 2
R1362
10K_0402_5%1 2R1073
0_0603_5%
1 2
R1336 0_0402_5%1 2
R1353 0_0402_5%DEBUG@1 2
C554
4.7U_0805_10V4Z
1
2
R1366 0_0402_5%1 2
R1412 0_0402_5%DEBUG@1 2
C994
0.01U_0402_16V7K@
1
2
C294
0.1U_0402_16V4Z
1
2
R519
100K_0402_5%@1 2
C995
0.1U_0402_16V4Z
1
2
R13630_0402_5%
1 2
R1426
0_0402_5%1 2
C293
0.01U_0402_16V7K
1
2
C959
0.1U_0402_16V4Z
1
2
U43CSN74LVC08APW_TSSOP14
A9
B10 O 8
P14
G7
R1358 0_0402_5%DEBUG@1 2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
MONO_IN
+3VS_CODEC
MIC1_CMIC1
MIC2 MIC2_C
DLINE_IN_RC_R
DLINE_IN_RC_L
LINE_OUTL
LINE_OUTR
AC97_SDIN0_CODEC
L_HP
R_HP
AUD_REF
DLINE_IN_R_R
DLINE_IN_R_L
MONO_IN
SENSE_BSENSE_A
SENSE_B
SENSE_A
SENSE_A_C
LINE_IN_SENSE
INT_MIC
PCM_SPK<24>
SLP_S3#<20,22,24,26,30,32,33,40,41>
AC97_SDIN0 <19>
AC97_RST#_CODEC<19>
DLINE_IN_R<32>
DLINE_IN_L<32>
LINE_OUTR <26>
LINE_OUTL <26>
AC97_SDOUT_CODEC<19>
AC97_SYNC_CODEC<19>
AC97_BITCLK_CODEC <19>
EAPD<26,30>
PREP# <20,23,32>
PORT_A_SNS <26>
SENSE_A_A <26>
SENSE_A_B <26>
LINE_IN_SENSE <32>
MIC1<26>
MIC2<26>
R_HP <26>
L_HP <26>
INT_MIC<26>
SB_SPKR<20>
VDDA_CODEC
VDDA_CODEC
+5VAMP
VDDA_CODEC
VDDA_CODEC+3VS
VDDA_CODEC
VDDA_CODEC
VDDA_CODEC
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
AC97 CODEC AD1981B
25 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Place R258 between DGND & AGND & close to U14
Place close to U14
GNDAGND
PORT
MONO_OUT
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PLACE TO
X
X
Internal MIC
M/B SPK
DOCK LI
M/B MIC
HP OUT, DOCK HP LO
L53FBM-L10-160808-301-T_0603
1 2
R374 4.7K_0402_5%1 2
G
D
SQ35RHU002N06_SOT323
2
13
T20 PAD
T18 PAD
C424
1U_0603_10V4Z
1
2
C416
0.1U_0402_16V4Z
1
2
G
D
SQ37RHU002N06_SOT323
2
13
R359
150K_0402_1%
1 2
T5 PAD
C175
0.1U_0402_16V4Z
1
2
C402
0.1U_0402_16V4Z
1
2
R1399
0_0805_5%1 2
C409 0.1U_0402_16V4Z12
+ C548
22U_B_10V
1
2
C417
0.1U_0402_16V4Z
1
2
R37333_0402_5%
12
C396
0.1U_0402_16V4Z
1 2
R9740_0402_5%@
12
T7 PAD
C425 1U_0603_10V4Z1 2
R2580_1206_5%
1 2
T14PAD
C422 1U_0603_10V4Z1 2 C106410P_0402_25V8K@ 1 2
T19 PAD
R9800_0402_5%@
12
R350
10K_0402_5%
12
T17 PAD
C551100P_0402_50V8J
1
2C307
0.1U_0402_16V4Z
1
2
T3 PAD
C204 1U_0603_10V4Z1 2
R1400
0_1206_5%
12
R231 2.2K_0402_1%
1 2
R973 10K_0402_1%
1 2
R370 4.7K_0402_5%12
R9692.67K_0402_1%
12
T21PAD
R972 20K_0402_1%
1 2
R167 4.7K_0402_5%@1 2
T16 PAD
R457
143K_0402_1%
12
C423 1U_0603_10V4Z1 2
C147
0.1U_0402_16V4Z
1
2
R330
10K_0402_5%
12
C39310U_0805_10V4Z
1
2
R168 4.7K_0402_5%@1 2
C9771U_0402_6.3V4Z@
1
2
R375 4.7K_0402_5%1 2
C390
0.1U_0402_16V4Z
1 2
R369 4.7K_0402_5%12
R341
150K_0402_1%
1 2
R329
10K_0402_5%
12
T6 PAD
T11PAD
C978
0.1U_0402_16V4Z
1
2
C395
0.1U_0402_16V4Z
1
2
T13PAD
C148
10U_0805_10V4Z
1
2
T15 PAD
C156
0.1U_0402_16V4Z
1
2
R169 0_0402_5%@1 2
R32 4.7K_0402_5%@1 2
R456
49.9K_0402_1%
12
R970 39.2K_0402_1%
1 2
C427 0.1U_0402_16V4Z12
C552
1U_0603_10V4Z1
2
C431 0.1U_0402_16V4Z12
R1038 33_0402_5% @12
U14
AD1981HDJSTZ-REEL_LQFP48
AUX_L14
AUX_R15
MIC417
MIC316
LINE_IN_L23
LINE_IN_R24
CD_L18
CD_R20
CD_GND19
MIC121
MIC222
SENSEA13
PCBEEP 12
LINE_OUT_L 35
LINE_OUT_R 36
MONO_OUT 37
RESET#11
SYNC10
BIT_CLK 6
SDATA_OUT5
SDATA_IN 8
GPIO_2 2GPIO_3 3
MIC_BIAS_C 29MIC_BIAS_F 30
MIC_BIAS_B 28
VREF 27D
VDD
11
DVD
D2
9
AVD
D1
25
AVD
D2
38
MIC_BIAS_D 32
N/C 33EAPD47
SPDIFO48
DVSS14DVSS27
HP_LOUT_L 39
HP_LOUT_R 41
N/C 31
N/C 40
AVSS2 42AVSS1 26
NC 45NC 46
GPIO_0 43GPIO_1 44
SENSEB34
C377
0.01U_0402_16V7K1
2
R136 10K_0402_5%
1 2
C205 1U_0603_10V4Z1 2
C430 0.1U_0402_16V4Z1 2
G
D
S
Q97
2N7002_SOT23
2
13
T4 PAD
C426 1U_0603_10V4Z1 2
+ C309
22U_B_10V
1
2C553
0.01U_0402_16V7K1
2
R988
100K_0402_5%
12
U18
MIC5205BM5_SOT23-5
IN1
GND2
EN3 OUT 5
ADJ 4
T12PAD
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
L_SPK-R_SPK+R_SPK-
INT_MIC_2
INT_MIC_1 INT_MIC_3 INT_MIC_4INT_MIC
EXT_MICB_1
EXT_MICA
EXT_MICB
EXT_MICA_1
L_CR_HP
R_CR_HP R_CRL_HP
EXT_MICB
EXT_MICA
R_SPK+
R_SPK-
L_SPK-
LINE_C_R_OUTR
LINE_C_R_OUTL
LINE_C_OUTR LINE_C_R_OUTR
LINE_C_OUTL LINE_C_R_OUTL
J_R_HP
J_L_HP
J_MIC_SENSE
L_CRL_HPL_C_HP
R_C_HP
J_DLINE_OUT_L
MIC_SENSE
EXT_MICB_2J_MIC2
EXT_MICA_2J_MIC1
L_HP
J_R_HPJ_L_HP
J_MIC_SENSE
J_DLINE_OUT_L
J_MIC1
J_MIC2
MIC1
MIC2
R_HPMIC_SENSE
J_DLINE_OUT_R
J_DLINE_OUT_R
DLINE_OUT_L
EAPD
L_SPK+
L_SPK+
LINE_OUTR<25>
LINE_OUTL<25>
A_SD<30>
MUTE_LED#<31>
EAPD<25,30>
SLP_S3#<20,22,24,25,30,32,33,40,41>
PORT_A_SNS<25>
SENSE_A_A<25>
DOCK_HPS#<32>
SENSE_A_B<25>
R_HP<25>L_HP<25>
MIC1<25>
MIC2<25>
DLINE_OUT_R<32>DLINE_OUT_L<32>
INT_MIC <25>
VDDA_CODEC
MIC_REF
VDDA_CODEC
JJ_MIC_REF
VDDA_CODECVDDA_CODEC
+5VAMP+5VALW
J_VDDA_CODEC
VDDA_CODEC
J_VDDA_CODEC
+3VS
VDDA_CODEC
VDDA_CODEC
MIC_REF
VDDA_CODEC
J_VDDA_CODEC
J_MIC_REF
MIC_REF
VDDA_CODEC
J_VDDA_CODEC
J_VDDA_CODEC
J_MIC_REF
JJ_MIC_REFJJ_MIC_REF
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
AMP & Audio Jack
26 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
AMP. FOR INTERNAL MICROPHONE
AMP. FOR EXTERNAL MICROPHONE
7.6 dB
7.6 dB
10 dB
10 dB
Keep 10 mil width
AMP. FOR INTERNAL SPEAKER
Place close to JP24
Place close to U14 audio CODEC
Place close to U14
Place close to JP15
Place close to U14 audio CODEC
Place close to JP15
Place close to JP24
G
D
SQ28RHU002N06_SOT323@
2
13
JP27
ACES_87213-0600
1 12 23 34 45 56 6
JP15
SUYIN_010030FR006G101ZL_6P
12
3
4
5
6
78
C490
4.7U_0805_10V4Z 1
2
C503
0.1U_0402_16V4Z
1 2
R255
100K_0402_5%
1 2
C230
680P_0402_50V7K
1 2
R190
100K_0402_5%
1 2
C527
0.1U_0603_16V4Z
1
2
JP9
ACES_87213-1200
112233445566778899101011111212
C44
610
0P_0
402_
50V8
J
1
2
G
D
SQ32RHU002N06_SOT323
2
13
R426
47K_0402_5%
12
U27BTLV2462_SO8
+5
-6 O 7P
8G
4
R211
10K_0402_5%
1 2
C536
2.2U_0603_6.3V6K
1
2
JP36
ACES_85205-0200
12
C522
470P_0402_50V7K
1
2
L52
CHB1608B121_06031 2
C24
810
0P_0
402_
50V8
J
1
2
C982
4.7U_0805_6.3V6K
1
2
R4213.9K_0402_1%
1 2
R445
1K_0402_1%
12
G
D
S
Q48RHU002N06_SOT323
2
13
C226
4.7U_0805_6.3V6K
1
2
C539
0.1U_0402_16V4Z
1
2
+C662
150U_D_6.3VM@
1
2
R1411
10K_0402_5%
1 2
R1423 0_0402_5%@12
L46CHB1608B121_0603
1 2
C571
68P_0402_50V8J
1
2
C563
470P_0402_50V7K
1
2
C471 0.01U_0402_16V7K1 2
R388
10K_0402_5%
1 2
+
C577 150U_D_6.3VM1 2
U46B
TLV2462_SO8
+5
-6 O 7
P8
G4
JP28
ACES_87213-0600
1 12 23 34 45 56 6
C585
1200P_0402_50V7K@
1 2
R210
10K_0402_5%
1 2
R196
3K_0402_5%
1 2
G
D
S
Q44
RHU002N06_SOT323
2
13
L47CHB1608B121_0603
1 2
JP24
SUYIN_010030FR006G101ZL_6P
12
3
4
5
6
78
R1407
0_0402_5%12
R428
47K_0402_5%
12
L58
HLC0603CSCCR10JT_06031 2
C1098
10U_0805_10V4Z
1
2
C57568P_0402_50V8J
1
2
C508
470P_0402_50V7K
1
2
C276
0.22U_0603_10V7K
1 2
R418
470_0402_5%1 2
C514
100P_0402_50V8J1
2
+
C581 150U_D_6.3VM1 2
R1410
10K_0402_5%
1 2
R978100_0402_5%
12
L51
CHB1608B121_06031 2
C1044 1U_0603_10V4Z1 2
C502
0.1U_0402_16V4Z
1 2
U46A
TLV2462_SO8
+3
-2 O 1
P8
G4
C487
10U_0805_10V4Z
1
2
C660
1U_0603_10V4Z
1
2
C572
68P_0402_50V8J
1
2
R251
100K_0402_5%
12
R140612.1K_0402_1%1 2
R4243.9K_0402_1%
1 2
C470
0.1U_0402_16V4Z
1
2
R253
16_0805_1%
1 2
C44
10.
1U_0
402_
16V4
Z
1
2
C488
100P_0402_50V8J
1 2
R414
100K_0402_5%
1 2
U27ATLV2462_SO8
+3
-2 O 1
P8
G4
U73
S DIO(BR) NUP4301MR6T1 TSOP-6@
CH11
Vn2
CH23 CH3 4
Vp 5
CH4 6
R1424 0_0402_5%12
R429
47K_0402_5%
12
C506
100P_0402_50V8J
1
2
C526
1U_0603_10V6K@
1
2
R1421 0_0402_5%@12
R140512.1K_0402_1%1 2
R261
16_0805_1%
1 2
L57HLC0603CSCCR11JT_0603
1 2
R446
1K_0402_1%
12
C518
100P_0402_50V8J
1
2
C9840.1U_0402_16V4Z
1
2
C564
470P_0402_50V7K
1
2
C65910U_0805_10V4Z
1
2
C24
910
0P_0
402_
50V8
J
1
2
R193
3K_0402_5%1 2
G
D
SQ49
RHU002N06_SOT323
2
13
R427
47K_0402_5%
12
L61
HLC0603CSCCR10JT_06031 2
C231
0.22U_0603_10V7K
1 2
R425470_0402_5%
1 2
R430 10K_0402_5%1 2
U39
MAX9710ETP_QFN20
PGN
D1
6VD
D12
PVD
D1
8
MUTE4
NC1 3
OUTL- 17
OUTL+ 19
OUTR- 9
OUTR+ 7
INR5
INL1
BIAS 2PVD
D2
18
SHDN14
PGN
D2
11PG
ND
315
PGN
D4
20
NC2 10NC3 13NC4 16
PGN
D5
21
R97947K_0402_5%
12
R443
0_1206_5%
1 2
C489
100P_0402_50V8J
1 2
R413
100K_0402_5%
1 2
C486
10U_0805_10V4Z
1
2
R995100K_0402_5%
12
C275
0.22U_0603_10V7K
1 2
C492
4.7U_0805_10V4Z 1
2
C507
100P_0402_50V8J
1
2
D62
PACDN042_SOT23~D@
2
31
R423
100K_0402_5%
12
JP21
E&T_3801-04
11223344
R1427 0_0402_5%@12
G
D
S
Q50RHU002N06_SOT323
2
13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB20_P5USB20_N5USB20_N4_R
USB20_P4_RUSB20_N5_RUSB20_P5_R
USB20_N0USB20_P0
USB20_P4USB20_N4
SLP_S5
USB20_P0_RUSB20_N0_R
USB20_N3_RUSB20_P3_R
SLP_S5
SC_RFUSC_DATA
SC_CD#
SC_RSTSC_CLKSC_FCB
USB20_N4USB20_P4 USB20_N5
USB20_P5
USB20_N3USB20_P3
BT_OFF<20>
BT_LED <29>
USB20_P5 <20>USB20_N5 <20>
USB20_P4<20>USB20_N4<20>
CH_DATA <24>CH_CLK <24>
USB20_N0 <20>USB20_P0 <20>
USB20_N3<20>USB20_P3<20>
SLP_S5 <32,33>
SC_RFU <24>SC_DATA <24>
SC_CD# <24>
SC_RST <24>SC_CLK <24>SC_FCB <24>
+3VAUX_BT
+3VAUX_BT+3VALW
USB_VCCA+5VALW
USB_VCCA
+5VALW USB_VCCC
+SC_PWR
+5VALW
+5VALW
+SC_PWR
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
USB & BT Connector
27 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
W=80mils
Left side USB CONNECTOR 0
BT Connector
W=40mils
Right side USB CONNECTOR 0
Left side USB CONNECTOR 1
SMART Card connector
R458 1K_0402_5%1 2
R16310K_0402_5%
1 2
R518
100K_0402_5%
12
R16410K_0402_5%
1 2
C367
0.1U_0402_16V4Z
1
2
C5494.7U_0805_10V4Z
1
2
C558
4.7U_0805_10V4Z
1
2
R6060_0603_5%1 2
C550
4.7U_0805_10V4Z
1
2
JP3
ACES_85203-1002
1122334455667788991010
11 1112 1213 1314 1415 1516 1617 1718 1819 1920 20
JP23
SUYIN_020173MR004S558ZL
11223344GND5GND6GND7GND8
+
C56
715
0U_D
_6.3
VM
1
2
D61PJDLC05_SOT23~D
231
R6070_0603_5%1 2
C545
0.1U_0402_16V4Z
1
2
R6140_0603_5%1 2
R459 1K_0402_5%1 2
D53
PACDN042_SOT23~D@
231
C51
70.
1U_0
402_
16V4
Z
1
2
C51
50.
1U_0
402_
16V4
Z
1
2
JP26
SUYIN_020173MR004S558ZL
11223344GND5GND6GND7GND8
D51PJDLC05_SOT23~D
231
R6170_0603_5%1 2
C556
0.1U_0402_16V4Z
1 2
G
DS
Q51 SI2301BDS_SOT23
2
13
JP22
ACES_87212-0800
12345678
C306
1U_0603_10V4Z
1
2
R6040_0603_5%1 2
U65
TPS2061DGNRG4_MSOP8~N
GND1IN2
OC# 5OUT 6
OUT 8
IN3EN#4
OUT 7
U57
G548A2P1U
GND1IN2IN3EN#4 OC# 5OUT 6OUT 7OUT 8
C52
110
00P_
0402
_50V
7K
1
2
R5620_0402_5%12
R454
47K_0402_5%1 2
C546
0.01U_0402_16V7K
1
2
R6050_0603_5%1 2
C51
910
00P_
0402
_50V
7K
1
2
R5860_0402_5%12
+
C56
915
0U_D
_6.3
VM 1
2
JP25
SUYIN_020173MR004S558ZL
1 12 23 34 4
GND 5GND 6GND 7GND 8
D52PJDLC05_SOT23~D
231
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DCD#1RI#1CTS#1DSR#1
IRRX
CLK_14M_SIOCLK_PCI_SIO
LPC_AD3
LPC_AD1LPC_AD2
LPC_AD0
CLK_14M_SIO
LPC_FRAME#
LPD0LPD1LPD2LPD3LPD4LPD5LPD6LPD7
CTS#1RTS#1
RI#1
TXD1
DCD#1
DTR#1
DSR#1
RXD1
SIO_PD#
SIO_GPIO11
CLK_PCI_SIOSIRQ
LPC_DRQ#0
SIO_IRQ
PM_CLKRUN#
LPTBUSY
LPTSLCT
LPTACK#LPTERR#
LPTPE
LPTSTB#LPTAFD#
LPTINIT#LPTSLCTIN#
SIO_GPIO12
SIO_PME#
PID0PID1SIO_GPIO43SIO_GPIO44SIO_DPIO45CARD_ID#SER_SHD
SIO_GPIO11
SIO_GPIO40
SIO_GPIO10
PID1
PID0
SIO_GPIO40
LPTINIT#
LPTSLCTIN#EXPCRD_RST#
SIO_IRQ
SIO_GPIO44
SIO_GPIO12SIO_GPIO10
SIO_GPIO43
LPD3LPD2LPD1LPD0
LPD4
LPD7LPD6LPD5
LPTACK#
LPTSLCT
LPTBUSYLPTPE
LPTAFD#LPTSTB#
LPTERR#
CARD_ID#
SIO_DPIO45
IRRXSIO_RST#
EXPCRD_RST#
CLK_14M_SIO<15>
LPC_AD1<19,24,29,30>
LPC_FRAME#<19,24,29,30>
LPC_AD0<19,24,29,30>
LPC_AD2<19,24,29,30>LPC_AD3<19,24,29,30>
LPC_DRQ#0<19>
SIRQ<20,24,29,30>
PM_CLKRUN#<20,24,29,30>CLK_PCI_SIO<15>
LPD5 <32>LPD6 <32>
LPD4 <32>LPD3 <32>
LPD7 <32>
LPD0 <32>
LPD2 <32>LPD1 <32>
LPTBUSY <32>LPTPE <32>LPTSLCT <32>
LPTERR# <32>LPTACK# <32>
LPTINIT# <32>
LPTAFD# <32>LPTSTB# <32>
LPTSLCTIN# <32>
DCD#1 <32>
DTR#1 <32>CTS#1 <32>
TXD1 <32>DSR#1 <32>RTS#1 <32>
RXD1 <32>
RI#1 <32>
SER_SHD<32>
PLT_RST_B#<19,24,29>NPCI_RST#<20>
IRTXOUT <24>IRMODE <24>
IRRX <24>
EXPCRD_RST#<32>
+3VS
+3VS
+3VS
+3VS
+3VS
+5VS
+5VS_PRN
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
SUPER I/O LPC47N217
28 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Base I/O Address0 = 02Eh1 = 04Eh*
R109 0_0402_5%@ 1 2
C57
4.7U_0805_10V4Z
1
2
C76
0.1U_0402_16V4Z
1
2
R120
10K_0402_5%1 2
C9418P_0402_50V8J@
1
2
RP51
4.7K_1206_8P4R_5%
1 82 73 64 5
RP53
4.7K_1206_8P4R_5%
1 82 73 64 5
POWER
CLOCK
GPIO
LPC I/F SERIAL I/F
FIR
PARALLEL I/F
U8
LPC47N217_STQFP64
LAD010LAD112LAD213LAD314
LFRAME#15LDRQ#16
PCI_RESET#17LPCPD#18
CLKRUN#19PCI_CLK20SER_IRQ21IO_PME#6
RXD1 62TXD1 63
DSR1# 64RTS1# 1CTS1# 2DTR1# 3
RI1# 4DCD1# 5
IRRX2 37IRTX2 38
IRMODE/IRRX3 39
INIT# 41SLCTIN# 42
PD0 44PD1 46PD2 47PD3 48PD4 49PD5 50PD6 51PD7 53
SLCT 55PE 56
BUSY 57ACK# 58
ERROR# 59ALF# 60
STROBE# 61
GPIO4023GPIO4124GPIO4225GPIO4327GPIO4428GPIO4529GPIO4630GPIO4731GPIO1032GPIO11/SYSOPT33GPIO12/IO_SMI#34GPIO13/IRQIN135GPIO14/IRQIN236GPIO2340
CLK149
VTR 7
VCC 26
VCC 54
VSS8VSS22VSS43VSS52 VCC 45
VCC 11
RP52
4.7K_1206_8P4R_5%
1 82 73 64 5
C88
0.1U_0402_16V4Z
1
2
C84
0.1U_0402_16V4Z
1
2
RP6
10K_1206_8P4R_5%
18273645
R77
10K_0402_5%
1 2
R481
4.7K_0402_5%
1 2
R64 1K_0402_5%1 2
RP54
4.7K_1206_8P4R_5%
1 82 73 64 5
R99 10K_0402_5%1 2
C7010P_0402_25V8K@
1
2
R68
10K_0402_5%
1 2
R761K_0402_5%
1 2D36
CH751H-40_SC76
21
R119
10K_0402_5%
1 2
R80
10K_0402_5%
1 2
RP3
4.7K_1206_8P4R_5%
1 82 73 64 5
R108 0_0402_5%1 2
R480
4.7K_0402_5%
1 2
R100
10K_0402_5%
1 2
R9610_0402_5%@
12
R79
10K_0402_5%
1 2
R8110_0402_5%@
12
R67 10K_0402_5%1 2R121
10K_0402_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI_CS#
SPI_CLK
SPI_SI
SPI_WP#
SPI_HOLD#
SPI_WP#
SPI_HOLD#
USB20_N2_RUSB20_P2_R
SPI_SO_L SPI_SO
PLT_RST_B#
CLK_PCI_TCG
LPC_PD#
TPM_XTALO
TPM_GPIO
LPC_AD3
TPM_GPIO2
SIRQ
TPM_XTALI
LPC_AD2LPC_AD1
TPM_XTALI
TPM_XTALO
LPC_FRAME#
LPC_AD0
PM_CLKRUN#
WL_LED
BT_LED<27>
SPI_CS#<20>
SPI_CLK<20>
SPI_SI<20> SPI_SO <20>
WW_LED# <24>
WL_LED# <24>
WP_LED# <24>
USB20_P2<20>USB20_N2<20>
LPC_AD0<19,24,28,30>LPC_AD1<19,24,28,30>LPC_AD2<19,24,28,30>LPC_AD3<19,24,28,30>
CLK_PCI_TCG<15>LPC_FRAME#<19,24,28,30>PLT_RST_B#<19,24,28>SIRQ<20,24,28,30>
WL_BLUE_LED#<24,31>
LPC_PD# <20,30>
PM_CLKRUN#<20,24,28,30>
TPM_32K_CLK <30>
+3VS
+3VALW
+3VALW
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
TCG/BIOS ROM/PS2/LED/SW
29 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
TPM1.2
BIOS ROM
Finger printer
R1291 place cloe to U66
Mini-PCIE Card LED
Base I/O Address
* 1 = 04Eh0 = 02Eh
BLUE
Footprint need to update
R1379 0_0402_5%12
R1288
3.3K_0402_5%1 2
G
D
S
Q78RHU002N06_SOT323
2
13
R1409
0_0402_5%
12
T87PAD
10K
47K Q75DTA114YKA_SC59
2
13
C989
0.1U_0402_16V4Z
1
2
C1054
0.1U_0402_16V4Z1
2
R13774.7K_0402_5%
12
C1056
18P_0402_50V8J
1 2
10K
47K
Q89DTA114YKA_SC59
2
13
R13804.7K_0402_5%@
1 2
R101 0_0402_5%@1 2
C1052
0.1U_0402_16V4Z
1
2
C206
0.1U_0402_16V4Z
1
2
R1287
3.3K_0402_5%1 2
TPMSLB 9635 TT 1.1
U69
SLB9635TT_TSSOP28
GN
D4
GN
D11
GN
D18
GN
D25
VDD
24VD
D19
LAD026LAD123LAD220LAD317
LCLK21LFRAME#22LRESET#16SERIRQ27CLKRUN#15PP7 NC 1
NC 3NC 12
VDD
10
VSB
5
TESTB1/BADD 9TEST1 8
GPIO 6
XTALO 14XTALI 13
LPCPD# 28
GPIO2 2
10K
47K
Q88DTA114YKA_SC59
2
13
T62PAD
D54PACDN042_SOT23~D@
231
U66
SST25LF080A_SO8-200mil
S1
VCC8
Q 2
HOLD7
VSS 4
D5
C6
W3
C1055
0.1U_0402_16V4Z
1
2
C1053
0.1U_0402_16V4Z
1
2
R505100K_0402_5%
12
R13784.7K_0402_5%@
12
R504100K_0402_5%
12
R1291
47_0402_5%1 2
Y8
32.768KHZ_12.5P_Q13MC30610018
OUT4
IN1
NC 3
NC 2R1381
10M_0402_5%
12
R13350_0402_5%
12R1334
0_0402_5%12
G
D
S
Q79RHU002N06_SOT323
2
13
JP38
ACES_85205-0400
11223344
C105718P_0402_50V8J
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EA#
LPCPD#
FWP#
LPCPD#
MODE
TP_CLK
TP_DATA
PS2_CLKKBD_DATAKBD_CLK
PS2_DATA
FWP#
PGM
PGM
FWP# PM_POK
TEST
EC_GPIO8EC_GPIO9
VCC1_PWRGD
KSI6
KSI4KSI5
KSI7
AB1B_DATA
AB1A_CLK
AB1B_CLKAB1A_DATA
VCC1_PWRGDNUM_LED#STB_LED#CAPS_LED#
CLK_14M_KBC
THM_MAIN#
EC_GPIO13
RUNSCI_EC#
KSI3KSI2KSI1
KSI0
ADP_PS1
AB1B_CLK
KSO14
BATSELB_A#
KBD_CLK
KSI5
PWR_GD
BATCON
KSO15
KSI7
KSO5
KSO0
KBD_DATA
STB_LED#
PGM
PCI_SERR#
FAN_PWM
RUNSCI_EC#
KSI0
NUM_LED#
LOW_BAT#
SIRQPM_CLKRUN#
VCC1_PWRGD
PM_POK
ON/OFFBTN_KBC#
PS2_DATA
TP_CLK
KSI2
KSO3
CLK_14M_KBC
FWP#
THM_MAIN#
KSI6 THM_MBAY#
GREEN_BATLED#
KSI3
KSO11KSO10
EA#
KSO8
KSO[0..13]
ADP_PS1
TEST
LPC_AD0
LPC_AD3
CLK_PCI_EC
KSO13
KSO2
CLK_PCI_EC
AB1B_DATA
AB1A_DATA
EC_GPIO8
AMBER_BATLED#
EC_GPIO9
CHGCTRL
INV_PWM
CAPS_LED#
MODE
EC_GPIO13
KBRST#
KSI1
AB1A_CLK
SLP_S3#
KSO12
KSO4
PM_RSMRST#
PLT_RST#LPC_FRAME#
LPC_AD2
PS2_CLK
KSI4
KSO9
KSO6
32K_CLK
CRY2
LPC_AD1
KSO7
KBC_PWR_ON
TP_DATA
KSO1
A20M
CRY1
32K_CLK
SIRQ<20,24,28,29>
LPC_AD3<19,24,28,29>
LPC_AD0<19,24,28,29>
LPC_AD2<19,24,28,29>LPC_AD1<19,24,28,29>
KBD_DATA<32>KBD_CLK<32>
LPC_PD#<20,29>
LPC_FRAME#<19,24,28,29>
PM_CLKRUN#<20,24,28,29>
CLK_PCI_EC<15>
PS2_CLK<32>
TP_CLK<31>
PS2_DATA<32>
TP_DATA<31>
KB_RST# <19>
PLT_RST#<7,16,18,19,20,22,24>
GATEA20 <19>
RUNSCI_EC#<20>
KBC_PWR_ON <39>
ADP_PRES <22,37,38,39,43>
KSO[0..13]<31>
KSO14 <31>
KSI[0..7]<31>
EAPD <25,26>
A_SD <26>
ADP_EN <43>
TPM_32K_CLK <29>
ADP_EN<43>
INV_PWM
GREEN_BATLED# <24>
VCC1_PWRGD <34>
PCI_SERR# <18,24>
STB_LED# <24,31,32>
ADP_ID <43>
AB1A_DATA <36>
NUM_LED# <24,31>
PM_RSMRST# <20>
PM_POK <7,20>PWR_GD <33,34,42,43>
CHGCTRL <37,38>
SLP_S3# <20,22,24,25,26,32,33,40,41>
THM_MBAY# <36>
ADP_PS1 <43>
AB1B_CLK <36>
KSO15 <31>
FAN_PWM <4>
LOW_BAT# <20>
CAPS_LED# <24,31>
BATSELB_A# <38>
BATCON <38>
AMBER_BATLED# <24>ADP_PS0 <43>
AB1B_DATA <36>
ON/OFFBTN_KBC# <31>
AB1A_CLK <36>
THM_MAIN# <36>
CLK_14M_KBC <15>
+RTCVCC
+3VS
+3VL
+5VS
+3VL
+3VS
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
LPC47N1021
30 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
AGND FILTER
1. For normal operation:Un-install R29,R65
2. For KBC internal ROM flash:Install R29,R65
Pin3 250 : KSO12/OUT8/KBRST
Pin34 250 -- LPCPD#
Pin49 250 -- Reset Out
Pin50 250 -- 24MHz_Out
Pin52 250 -- XOSEL
Pin56 250 -- PGMPin58 250 -- 32KHz_OUT
Pin82 250 -- nFWP
Pin91 250 -- nDMS_LED
BIOS debug portPlace under KB area
For KBC debugging used.
Pin57 250 -- MODEPin1 250 -- TEST Pin ( NC !! )
Pin83 250 -- nEA ( pull up !! )
R1271021@
R977R128
250@
R62R78R131R129
R62 250@
Note: R94 must be removed whenR1354 stuff and R87 remove.
Remove from daughter board
R3110K_0402_5%
12
JP31
ACES_85201-0602@
123456
R91 0_0402_5%1 2
R25
10K_0402_5%
1 2
R30
10K_0402_5%
12
R141 0_0402_5%1 2
R60 100K_0402_5%1 2
R28
1K_0402_5%@12
R58 100K_0402_5%1 2
C34918P_0402_50V8J1
2
R538100K_0402_5%@
1 2
D7
CH751H-40_SC76
21
Gene
ral
Purp
ose
I/O
Inte
rfac
e
Keyboard/Mouse InterfaceLPCBus
Power Mgmt/SIRQ
Misc
ella
neou
s
Access Bus Interface
SMSC_LPC47N250_TQFP-100P
KBC1021_TQFP100
U47
AGN
D55
KSO017KSO116KSO215KSO314KSO413KSO512KSO610KSO79KSO87KSO96KSO105KSO114KSO12/GPIO00/KBRST3KSO13/GPIO182
KSI025KSI124KSI223KSI322KSI421KSI520KSI619KSI718
IMCLK26IMDAT27KCLK29KDAT31EMCLK32EMDAT33
CLKRUN#44SER_IRQ46PCI_CLK43EC_SCI#59
LAD[3]40LAD[2]39LAD[1]37LAD[0]35
LFRAME#41LRESET#42LPCPD#/GPIO2334
XTAL153XTAL254
VCC051
TEST PIN 52
GN
D92
GN
D79
GN
D65
GN
D45
GN
D36
GN
D28
GN
D8
VCC
111
VCC
167
VCC
181
VCC
194
VCC
230
VCC
238
VCC
247
OUT0 99OUT1/IRQ8# 100
OUT7/SMI# 98OUT8/KBRST 97OUT9/PWM2 96
OUT10/PWM0 95OUT11/PWM1 93
GPIO02 62GPIO03 63
GPIO04/KSO14 64GPIO05/KSO15 66
GPIO07/PWM3 68GPIO08/RXD 69GPIO09/TXD 70
GPIO11/AB2A_DATA 71GPIO12/AB2A_CLK 72
GPIO13/AB2B_DATA 73GPIO14/AB2B_CLK 74
GPIO15/FAN_TACH1 75GPIO16/FAN_TACH2 76
GPIO17/A20M 77
GPIO20/PS2CLK 78GPIO21/PS2DAT 80
AB1A_DATA 86AB1A_CLK 87
AB1B_DATA 84AB1B_CLK 85
PGM Strap/GPIO25 56
GPIO01 82
EA Strap#/GPIO26/KSO17 83CLOCK 48
32KHZ_OUT/GPIO22 58RESET_OUT#/GPIO06 49
PWRGD 61VCC1_PWRGD 60
24MHZ_OUT/GPIO19/WINDMON 50
GPIO24/KSO16 1GPIO27 57
DMS_LED#/GPIO10 91BAT_LED# 88
PWR_LED#/8051TX 90FDD_LED#/8051RX 89
R75
120K_0402_5%
12
C80
10P_0402_25V8K@1
2
C78
0.1U_0402_16V4Z
1
2
R102 0_0402_5%@1 2
C34
4.7U_0805_10V4Z
1
2
R282
10_0402_5% @
1 2
C92
10P_0402_25V8K @
1 2
RP1
4.7K_1206_8P4R_5%
1 82 73 64 5
C67
0.1U_0402_16V4Z
1
2
R33100K_0402_5%1 2
JP43
ACES_85201-0602@
123456
R86
10_0402_5%@
12
R29
1K_0402_5%@
1 2
C79
0.1U_0402_16V4Z
1
2
C37
0.1U_0402_16V4Z
1
2
J3
NO SHORT PADS
1 2
C58
0.1U_0402_16V4Z
1 2
R977 300_0402_5%1 2
R94
10K_0402_5%
1 2
RP44
10K_1206_8P4R_5%
1 82 73 64 5
C51
0.1U_0402_16V4Z
1
2
C81
4.7U_0805_10V4Z
1
2
C52
0.1U_0402_16V4Z
1
2
R742M_0402_5%@
1 2
R27
1K_0402_5%12
D10
CH751H-40_SC76
2 1
R52
1K_0402_5%@
1 2
R78
1K_0402_5%@12
R59 100K_0402_5%1 2
R87 0_0402_5%@1 2
R62
10K_0402_5%@
1 2
C69
1U_0603_10V4Z1
2
R65
1K_0402_5%
1 2
R84
10K_0402_5%
1 2
RP43
10K_1206_8P4R_5%
1 82 73 64 5
C75
0.1U_0402_16V4Z
1
2
C35018P_0402_50V8J 1
2
R1354 0_0402_5%@1 2
RP5
10K_1206_8P4R_5%
1 82 73 64 5
R85
10K_0402_5%
1 2
Y2
32.768KHZ_12.5P_Q13MC30610018
OU
T4
IN1
NC
3
NC
2
R1400_0402_5%1 2
C36
0.1U_0402_16V4Z
1
2
R1289
10K_0402_5%
1 2
D6
CH751H-40_SC7621
R600210K_0402_1%1 2
AC97_SDOUT_MDC
AC97_RST#_MDC
AC97_SYNC_MDCAC97_SDIN1_MDC
ON/OFFBTN#
ON/OFFBTN_KBC#
ON/OFF#
KSI[0..7]
KSO[0..15]
TP_CLK
SP_CLK
SP_DATA
TP_DATASP_DATA
SP_CLK
AC97_BITCLK_MDC
KSO1KSI0
KSO6
KSO7
KSI3
KSO12KSO3
KSO4
KSO13
KSO2
KSO5
KSO8
KSO11
KSO15
KSO14
KSO10
STB_LED#ON/OFF#KSO12KSI1
MUTE_LED#WL_BLUE_LED#KSO12
KSI7
KSI0KSI4KSI5KSI6
KSO0KSI5
KSO9
KSI1
KSI4
KSI2
KSI6KSI7
KSO15
KSI1KSI7KSI6
KSO9KSI4KSI5
KSO0KSI2KSI3
KSO5KSO1KSI0
KSO2KSO4KSO7KSO8KSO6KSO3
KSO12KSO13KSO14KSO11KSO10
NUM_LED#CAPS_LED#
ON/OFFBTN# <20>
ON/OFF#<32>
ON/OFFBTN_KBC# <30>
KSI[0..7]<30>
KSO[0..15]<30>
TP_CLK<30>TP_DATA<30>
AC97_RST#_MDC<19>
AC97_SDOUT_MDC<19>
AC97_BITCLK_MDC <19>AC97_SDIN1<19>
AC97_SYNC_MDC<19>
STB_LED# <24,30,32>
WL_BLUE_LED# <24,29>MUTE_LED# <26>
LID_SW# <17,20>
NUM_LED# <24,30>CAPS_LED# <24,30>
+3VS
+3VS
+3VALW
+3VL
+3VL
+3VL
+5VS
+5VS
+5VS
+5VS
+3VS +5VS
+3VALW+3VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
MDC/KBD/ON_OFF/LID
31 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
SWITCHBOARD.
MDC 1.5 Conn.
Power button
INT_KBD CONN.
TrackPoint CONN. T/P BOARD.
On/off ,information buttonWL,Vol up,Vol down,Mute,Present button
CP5
100P_1206_8P4C_50V8
234 5
6781
JP14
ACES_87153-0801L
1357
2468
JP18
ACES_85203-1402conn@
11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414
15 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 28
Connector for MDC Rev1.5
JP32
TYCO_1-179396-2~D
GND11IAC_SDATA_OUT3GND25IAC_SYNC7IAC_SDATA_IN9IAC_RESET#11
RES0 2RES1 43.3V 6
GND3 8GND4 10
IAC_BITCLK 12
1313
1414
1515
1616
1717
1818
1919
2020
R22
100K_0402_5%
12
D42CH751H-40_SOD323
1 2
C11
1U_0603_10V4Z
1
2
U5FSN74LVC14APWLE_TSSOP14
O 12I13
P14
G7
C321
0.1U_0402_16V4Z
1
2
G
D
S
Q70RHU002N06_SOT323
2
13
JP20
ACES_85205-07001
1 12 23 34 45 56 67 7
GND8GND9
R536
100K_0402_5%
12
R8
100K_0402_5%1 2
JP6
ACES_85203-2402conn@
1 12 23 34 45 56 67 78 89 910 1011 1112 1213 1314 1415 1516 1617 1718 1819 1920 2021 2122 2223 2324 24
2525 2626 2727 2828 2929 3030 3131 3232 3333 3434 3535 3636 3737 3838 3939 4040 4141 4242 4343 4444 4545 4646 4747 4848
CP2
100P_1206_8P4C_50V8
234 5
6781
D66
PACDN042_SOT23~D@
231
R1084 0_0402_5% 12
C23
1U_0603_10V4Z
1
2
R1313
33_0402_5%12
CP7
100P_1206_8P4C_50V8
234 5
6781
CP1
100P_1206_8P4C_50V8
234 5
6781
CP6
100P_1206_8P4C_50V8
234 5
6781
R26
100K_0402_5%
1 2
R1096 0_0402_5%@12
C5
0.1U_0402_16V4Z
1
2
C319
0.1U_0402_16V4Z
1
2
CP3
100P_1206_8P4C_50V8
234 5
6781
JP17
ACES_87212-0800
12345678
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DCD#1
LAN_ACT#_DOCK
MDO0-
ON/OFF#
PWR_LED
RXD1
MDO3+MDO3-
MDO1-MDO1+
MDO2-
DSR#1
BLUE
ISO_PREP#GREEN
ISO_PREP#
RED
ISO_PREP#
LPTSTB#
D_DDCCLK
RI#1
SLP_S5#_5R
LPTAFD#
DETECT
RTS#1
TXD1
DVI_DETECT
MDO0+
DVI_DATDVI_CLK
CTS#1
MDO2+
DTR#1
LANLINK_STATUS#_DOCK
LPTERR#
D_DDCDATA
SLP_S5#_5RDOCK_MOD_TIPDOCK_MOD_RING
DOCK_HPS#
CPPE#
CLK_PCIE_DOCK#
CLK_PCIE_DOCK
LPTBUSY
SER_SHD
LPTSLCTIN#LPTINIT#
PREP#
LPTACK#
LPTSLCT
DLINE_IN_RDLINE_IN_L
DETECT
LPTPE
PCIE_TXP4
PCIE_TXN4
EXPCRD_RST#
PS2_DATAPS2_CLK
LPD0LPD1
LPD4
LPD2
LPD5LPD6
LPD3
LPD7
VA_ON#
DOCK_MOD_TIPDOCK_MOD_RING
DLINE_OUT_L
KBD_DATAKBD_CLK
DLINE_OUT_R
LAN_ACT#_DOCK
LAN_ACT#
LANLINK_STATUS#_DOCK
LANLINK_STATUS#
PWR_LED
PCIE_C_RXP4
PCIE_C_RXN4 PCIE_RXN4
PCIE_RXP4
INTEL_GREEN
DOCK_ID
DOCK_IDDOCK_ADP_SIGNAL
DOCK_ADP_SIGNAL
INTEL_BLUEINTEL_RED
INTEL_BLUEINTEL_GREEN DOCK_GRN
DOCK_BLU
DOCK_COMPDOCK_CRMADOCK_LUMA
DOCK_DVI_TX2-
DOCK_DVI_CLK-
DOCK_DVI_TX0+
INTEL_GREEN
INTEL_BLUE
INTEL_RED
INTEL_RED DOCK_RED
DOCK_DVI_TX1+
DOCK_DVI_CLK-
DOCK_DVI_TX0-
DOCK_DVI_TX2+
DOCK_DVI_TX0+
DOCK_DVI_TX1-
DOCK_DVI_CLK+
DOCK_DVI_TX2-
DOCK_DVI_TX2+
DOCK_DVI_TX1+
DOCK_DVI_TX1-
DOCK_DVI_CLK+
DOCK_DVI_TX0-
BLUE<16>GREEN<16> RED<16>
MDO1- <23>MDO1+ <23>
MDO3- <23>MDO3+ <23>MDO2+<23>
MDO2-<23>
MDO0-<23>MDO0+<23>
D_VSYNC<16>D_HSYNC<16>
DVI_DETECT<16>
ON/OFF#<31>
D_DDCCLK<16>D_DDCDATA<16>
RXD1<28>
RTS#1<28>
DCD#1<28>RI#1<28>
DTR#1<28>
DSR#1<28>
CTS#1<28>
TXD1<28>
LPTSTB#<28>LPTAFD#<28>LPTERR#<28>
DVI_TX1+ <16>
DVI_TX2+ <16>
DVI_TX1- <16>
DVI_CLK- <16>
DVI_CLK+ <16>
DVI_TX0- <16>
DVI_TX0+ <16>
SLP_S5<27,33>
SER_SHD<28>PREP# <20,23,25>
LPTACK#<28>
LPTINIT#<28>LPTSLCTIN#<28>
LPD5<28>LPD4<28>
LPD1<28>LPD0<28>
LPD2<28>LPD3<28>
LPD7<28>LPD6<28>
LPTBUSY<28>LPTPE<28>
LPTSLCT<28>
KBD_DATA <30>KBD_CLK <30>
PS2_DATA <30>PS2_CLK <30>
CLK_PCIE_DOCK <15>
CLK_PCIE_DOCK# <15>
PCIE_TXN4 <20>
PCIE_TXP4 <20>
DOCK_HPS# <26>
DLINE_IN_L <25>DLINE_IN_R <25>
DLINE_OUT_L <26>DLINE_OUT_R <26>
CPPE# <15,18>
USB20_N7<20>
USB20_P7<20>
EXPCRD_RST#<28>
USB20_P6<20>
USB20_N6<20>
LAN_ACT# <22,23>
LANLINK_STATUS# <20,22,23>
STB_LED#<24,30,31>
SLP_S3#<20,22,24,25,26,30,33,40,41>
ISO_PREP#<20>
PCIE_RXP4 <20>
PCIE_RXN4 <20>
DOCK_ID <20>
DVI_DAT <16>DVI_CLK <16>
INTEL_BLUE<9>INTEL_GREEN<9> INTEL_RED<9>
LINE_IN_SENSE<25>
ACOCP_EN#<43>
COMP<9,16>CRMA<9,16>LUMA<9,16>
DVI_TX2- <16>
DOCKVINVIN
+3VS+3VS
DOCKVIN
+3VS
+5VALW
+5VS
+3VALW
V_3P3_LAN
+3VS
ADP_SIGNAL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
Docking CONN.
32 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
DOCK CONN. 184PIN
SWAP
L10KC FBM-L18-453215-900LMA90T_1812
12
R529
100K_0402_5%
12R1433 110_0402_1%
1 2
R526
10K_0402_5%
12
R515 1K_0402_5%1 2
R1429 0_0603_5%1 2
C360
0.1U_0402_16V4Z
12
L79
WCM2012F2SF-900T04
11 2 2
3 344
+
C555
22U_1206_10V4Z@
1 2
U50
FSA66P5X_SC70-5
A1B2
GND3
OE4
VCC5
C365
0.1U_0402_16V4Z12
R1387
10K_0402_5%@
1 2
L80
WCM2012F2SF-900T04
11 2 2
3 344
L82
WCM2012F2SF-900T04
11 2 2
3 344
R13470_0402_5%1 2
U51
FSA66P5X_SC70-5
A1B2
GND3
OE4
VCC5
R1430 0_0402_5%1 2
L81
WCM2012F2SF-900T04
11 2 2
3 344
C73
1000P_0402_50V7K
1
2
D65PACDN042_SOT23~D@
231
R1401
1K_0402_1%
1 2
C746 1000P_0402_50V4Z@1 2
G
D
S
Q62RHU002N06_SOT323
2
13
U52
FSA66P5X_SC70-5
A1B2
GND3
OE4
VCC5
R527
10K_0402_5%12
R1431 0_0402_5%1 2
G
D
S
Q63RHU002N06_SOT323
2
13
R1434 110_0402_1%
1 2
C72
1000P_0402_50V7K
1
2
JP29
ACES_85205-0200
12
R1432 0_0402_5%1 2
C747 1000P_0402_50V4Z @1 2
C59
0.1U_0402_16V4Z
1
2
R66
1K_0402_5%
12
R1404 0_0603_5%1 2
G
D
S
Q65
RHU002N06_SOT323
2
13
JP30B
JAE_SP03-14588-PCL03
4646474748484949505051515252535354545555565657575858595960606161626263636464656566666767686869697070717172727373747475757676777778787979808081818282
128 128129 129130 130131 131132 132133 133134 134135 135136 136137 137138 138139 139140 140141 141142 142143 143144 144145 145146 146147 147148 148149 149150 150151 151152 152153 153154 154155 155156 156157 157158 158159 159160 160161 161162 162163 163164 164
G2165
RING166 TIP 168
P2 167
GND176GND169GND175GND179GND181
GND 178GND 180GND 182GND 174GND 171GND 170GND177
R1435 110_0402_1%
1 2
C366
0.1U_0402_16V4Z
1 2
JP30A
JAE_SP03-14588-PCL03
P1 173G1172
83 8384 8485 8586 8687 8788 8889 8990 9091 9192 9293 9394 9495 9596 9697 9798 9899 99
100 100101 101102 102103 103104 104105 105106 106107 107108 108109 109110 110111 111112 112113 113114 114115 115116 116117 117118 118119 119120 120121 121122 122123 123124 124125 125126 126127 127
112233445566778899101011111212131314141515161617171818191920202121222223232424252526262727282829293030313132323333343435353636373738383939404041414242434344444545
R13460_0402_5%1 2
C748 1000P_0402_50V4Z@1 2
R1436 110_0402_1%
1 2
R1428 0_0603_5%1 2
G
D
SQ59RHU002N06_SOT323
2
13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SLP_S3#
RUNON
SLP_S5
SLP_S5#
SLP_S3
SLP_S3 SLP_S3 SLP_S3 SLP_S3
SLP_S3
RUNON
SLP_S3SLP_S5SLP_S5
RUNON
SLP_S3
SLP_S3#<20,22,24,25,26,30,32,40,41>
SLP_S5#<20,41>
SLP_S5<27,32>
PWR_GD <30,34,42,43>
VDD_MEM18
+3VL
+2.5VS
+5VS+5VALW
+5VALW
+3VS+5VS
+3VS+3VALW
+0.9V +1.5VS+1.8V
B+
+1.8V VDD_MEM18
+1.8V
+VCCP+VCC_CORE
+1.5VS
+VCCP +1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
DC/DC Circuits
33 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Discharge circuit
+5VALW to +5VS Transfer +3VALW to +3VS Transfer
+1.8V to +1.8VS Transfer VRAM
G
D
SQ17RHU002N06_SOT323
2
13
R134
470_0402_5%1
2
G
D
SQ18RHU002N06_SOT323
2
13
C120
0.01U_0402_25V7Z
1
2
R135
100K_0402_5%
12
R1310
470_0402_5%
12
G
D
SQ19RHU002N06_SOT323
2
13
C93
0.1U_0402_16V4Z
1 2
G
D
SQ47RHU002N06_SOT323
2
13
R188
470_0402_5%
12
C132
0.1U_0402_16V4Z
1
2
G
D
SQ22RHU002N06_SOT323
2
13
C71
0.1U_0402_16V4Z
1
2
G
D
S
Q27RHU002N06_SOT323
2
13
J34
SHORT PADS1
2
R139
330K_0402_5%
12
C184
0.1U_0402_16V4Z
1 2
U10
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
C86
10U_0805_10V4Z
1
2
G
D
SQ90RHU002N06_SOT323
2
13
C77
10U_0805_10V4Z
1
2
R13120_0402_5%
1 2
G
D
SQ16RHU002N06_SOT323
2
13
G
D
SQ14RHU002N06_SOT323
2
13
C91
0.1U_0402_16V4Z
1 2
C171
10U_0805_10V4Z
1
2
C127
10U_0805_10V4Z
1
2
R130
470_0402_5%
12
U9
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
G
D
SQ21RHU002N06_SOT323
2
13
R469
470_0402_5%
12
R125
100K_0402_5%
12
R151
470_0402_5%
12
C160
0.1U_0402_16V4Z
1
2
R116
470_0402_5%
12
C128
10U_0805_10V4Z
1
2
U13
SI4800DY_SO8
S 1S 2S 3G 4
D8D7D6D5
R95
470_0402_5%
12
R1311 0_0402_5%@1 2
C170
10U_0805_10V4Z
1
2
PWR_GD
CLK_ENABLE#
PGD_IN
PWR_GD
VCC1_PWRGD <30>
PWR_GD <30,33,42,43>
VCCP_POK<40>
CLK_ENABLE#<15,42>
PGD_IN <42>
+1.5VS +2.5VS+2.5VS
+3VL
+3VL
+3VL
+5VS
+3VS
+3VS+3VSVDD_MEM18 +3VL+3VL
+3VL
+3VL
+3VS +3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
POK CKT
34 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Need be tune to3msec time delay
U62
SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1
U63
SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1
R1402
0_0402_5%@1 2
FM11
H28HOLED
1
R281
330_0402_5%
12
H15HOLEC
1
R24
100K_0402_5%
12
D60CH751H-40_SOD323
1 2
H34HOLED
1
H1HOLEA
1
H8HOLEA
1
C47
0.1U_0402_16V4Z
1
2
H20HOLED
1
CF81
CF111
G
D
SQ9RHU002N06_SOT323
2
13
C992
0.1U_0402_16V4Z
1
2
H21HOLED
1
H9HOLEA
1
CF91
C
BE
Q15
PMST3904_SOT323
1
2
3
H33HOLED
1
H2HOLEA
1
R7
10K_0402_5%
12
CF121
U5C
SN74LVC14APWLE_TSSOP14
O 6I5
P14
G7
CF101
R123
0_0402_5%1 2
R89
1K_0402_5%
12
H10HOLEB
1
H22HOLED
1
H35HOLED
1
H16HOLEC
1
C
BE
Q26
PMST3904_SOT323
1
2
3
H3HOLEA
1
H32HOLED
1
R43
180K_0402_5%
12
R38
47K_0402_5%1 2
H23HOLED
1
CF131
G
D
SQ2RHU002N06_SOT323
21
3
H11HOLEB
1
R82
330_0402_5%
12
C25
0.1U_0402_16V4Z
1
2
H36HOLED
1
H4HOLEA
1
H37HOLED
1
CF141
U5D
SN74LVC14APWLE_TSSOP14
O 8I9
P14
G7
H24HOLED
1
C48
0.1U_0402_16V4Z
1
2
R113
330_0402_5%
12
D8CH751H-40_SOD323
1 2
H12HOLEB
1
CF71
R1303
0_0402_5%@1 2
C991
0.1U_0402_16V4Z
1
2
H5HOLEA
1
H17HOLEC
1
C
BE
Q11PMST3904_SOT323
1
2
3
R122
1K_0402_5%
12
FM31
R1350
150K_0402_1%1 2
R37
560K_0402_5%
12
J32
SHORT PADS
1 2
G
D
SQ3RHU002N06_SOT323
2
13
H25HOLED
1
H13HOLEB
1
C
BE
Q10PMST3904_SOT323
1
2
3
U5E
SN74LVC14APWLE_TSSOP14
O 10I11
P14
G7
FM41
H6HOLEA
1
U5A
SN74LVC14APWLE_TSSOP14
O 2I1
P14
G7
C99
0
0.47
U_0
603_
10V7
K
1
2
C26
0.1U_0402_16V4Z
1
2
H18HOLED
1
H27HOLED
1
R47
10K_0402_5%
12
FM21
R283
330_0402_5%
12
H14HOLEB
1
H7HOLEA
1
U5B
SN74LVC14APWLE_TSSOP14
O 4I3
P14
G7
H19HOLED
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
POWER BLOCK DIAGRAM
35 47Friday, April 28, 2006
ACAdapterin
BatteryConnectorA
BatteryConnectorB
Battery A6 Cell
Battery B8 Cell
MAX8734ADC/DC (3V/5V)
ISL6260 &ISL6208DC/DC (CPU_CORE)
+3VALWP 4A
+5VALWP 4A
CPU_CORE ( 44A)
VCC SHDN#
PWR_GD+5VS
BQ24703Charger
VL
B+ B+
B+
+3VLP 0.1A
+1.5VSP 4.2A
+1.05V_VCCP 6.4A
BATT_A
BATT_B
BATT
VS
VIN
SWITCHACOK
VS
VMB
VMB_A VMB_B
ENBL1/ENBL2SLP_S3#
MAINPWON
B+TPS51116DC/DC (+1.8VP/+0.9VSP)
VCC
+0.9VP 2AS3/S5SLP_S5#
+1.8VP 7A
+5VALWP
ENBL2 ENBL1
MAX8743DC/DC (1.05V/1.5V)
VIN
SWITCHSWITCH
VMB
BatterySelectorCircuit
BATSELB_A
SWITCH
BATSELB_A#
LM358ThermalProtector
+5VALWP
G965LDO(2.5V)
+3VS
+2.5VS 1A
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMC_A1
EC_SMD_A1
EC_SMC_B1
EC_SMD_B1
TS_B
EC_SMD_BEC_SMC_B
EC_SMC_AEC_SMD_A
AB/I_B
ADPIN
THM_MBAY# <30>
AB1B_DATA <30>
AB1A_CLK <30>
AB1A_DATA <30>
AB1B_CLK <30>
THM_MAIN# <30>
AB/I_A <38>VMB_A
+3VL
VMB_B
BATT_A
BATT_B
VINADP_SIGNAL
+3VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
BATTERY CONNCustom
36 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
PR14100_0402_5%
12
PR115K_0402_5%
12
PCN3
SUYIN_20163S-06G1-K
BATT+ 1
TS 5
SMD 2
GND 6
SMC 3B/I 4
PR4100_0402_5%
12
PC60.01U_0402_50V4Z
12
PC145220P_0402_25V8K
12
PC
110
0P_0
402_
50V
8J
12
PL3FBM-L18-453215-900LMA90T_1812
1 2
PR5100_0402_5%
12
PL1FBM-L18-453215-900LMA90T_1812
1 2
PC90.01U_0402_50V4Z
12PR9
210K_0402_1%
1 2
PC21000P_0402_50V7K
12
PR71K_0402_5%
12
PL2
FBM-L18-453215-900LMA90T_1812
1 2
PR10210K_0402_1%
1 2
PC143220P_0402_25V8K
12
PR2
1M_0402_1%12
PC
144
220P
_040
2_25
V8K
12
PC81000P_0402_50V7K
12
PR15
100_0402_5%
12
PR31K_0402_5%
12
PCN2
TYCO_C-1746706_6P
BATT+ 1
TS 5
SMD 2
GND 6
SMC 3RES 4
PC
310
0P_0
402_
50V
8J
12
PCN1
FOX_JPD113E-LB103-7F
SINGAL 5
PWR1 1
PWR2 2GND24
GND47
GND69
GND58
GND36
GND13
PC51000P_0402_50V7K
12
PR111K_0402_5%
12
PC
410
00P
_040
2_50
V7K
1
2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DH_CHG
LX_CHG
SE_CHG+
SE_CHG-
ALARM
AC_CHG
AC_CHG
ACDRV#
ACDRV#
ACDET
CHG_B+
ADP_PRES
ALARM <38>
AC_CHG <38>
ADP_EN# <43>
ACN <43>
ADP_PRES <22,30,38,39,43>
CELLSEL# <38>
CHGCTRL<30,38>
SRSET <43>
VIN
P4
BATT
P2
VL
BQ24703VREF+3VL
+3VL
BQ24703VREF
+3VL
VL
P2
+3VL
1.24VREF
+3VL
P2B+
BATT
BATT
BATT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
ChargerCustom
37 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
AC detectorHigh 11.689VLow 9.879V
Airline detectorHigh 17.521VLow 16.871V
CV=12.6V(6 CELLS LI-ION) 16.8V(8 CELL LI-ION)
Icharger=3ACELLSEL# =0,Vcharger= 12.6VCELLSEL# =1,Vcharger= 16.8V
CC=3A for 2.4AHrCC=3.57A for 2.55AHr
PU3B
LM393M_SO8
+5
-6 O 7
P8
G4
PL5
8.2UH_MPL73-8R2_4A_20%
1 2
PC250.1U_0402_10V6K
12
PR18
47K_
0402
_5%
1
2
PR54
33K_0402_1%
1 2
G
D
S
PQ9
RHU002N06_SOT3232
13
PR36
100K
_060
3_1%
12
PQ7SI4835BDY_SO8
365 7 8
2
4
1
PR51
@47
K_04
02_1
%12
PR19
0_04
02_5
%
12
PR251K_0402_1%
12
PR447.68K_0603_0.1%
12
PD8SKS30-04AT_TSMA
21
PR41100K_0603_0.1%
12
PU3A
LM393M_SO8
+3
-2 O 1
P8
G4
PC15
4.7U
_120
6_25
V6K
12
PC18
1U_0
603_
6.3V
6M
12
PC28
100P
_040
2_50
V8J
12
PR16200K_0402_5%
12
PR26639.2_0402_1%
12
PR45130K_0402_1%
12
PC19
4.7U
_120
6_25
V6K
12
G
D
S
PQ8RHU002N06_SOT3232
13
PQ4AO4407_SO8
365
78
2
4
1
PC13
47P_
0402
_50V
8J
12
PU4SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1
PR392.15K_0402_1%
1 2
PR527.87K_0402_1%
12
PC12
0.1U
_060
3_16
V7K
12 PR20
0.015_2512_1%
1 2
PC23
1U_0
603_
6.3V
6M
12
G
D
S
PQ10
RHU002N06_SOT323
2
13
PR33
80.6
K_04
02_1
%
12
PR38866K_0603_1%
12
PC24
150P
_040
2_50
V8J
12
PC29
0.02
2U_0
402_
16V7
K
12
PR40
12.4
K_06
03_1
%
12
PU2
BQ24703_QFN28
ENABLE5ACSEL28ALARM19SRSET2ACSET3
IBAT13VREF4
ACN8ACP9ACDET26
ACPRES27 VHSP 20
GND 17BATDEP 1BATSET 6
BATDRV# 24BATP 12SRN 15SRP 16PWM# 21
COMP7
VCC 22
VS 18
ACDRV# 25
NC4 23NC3 14NC110
NC211
PR230_0402_5%
12
PR32
3K_0
402_
1%
12
PR532.8K_0603_0.5%
12
PR4827K_0402_1%
12
PR49100_0402_5%
12
PR30
100K
_040
2_1%
12
PR42174K_0603_1%
12
PU5
LMV431ACM5X_SOT23-5
NC 2
REF4
NC 1
CATHODE 3
ANODE5
PR21150K_0402_5%
12
PC26
4.7U
_080
5_10
V6K
12
PR50
10K_
0603
_1%
12
PR37
10K_
0402
_1%
12
PR280.015_2512_1%
1 2
PR22100_0402_1%
12
PR170_0402_5% 1 2
PL4FBM-L11-322513-151LMAT_1210
1 2
PR26
191K_0402_1%
1 2
PC161U_0603_6.3V6M
1 2
PR434.7K_0402_5%
12
PC20
10U
_120
6_25
V6M
1
2
PR27100K_0402_5%
12
PC17
1U_0
805_
25V4
Z
12
PR47
100K_0402_5%
1 2
PR35150_0402_1%
12
PR46
1M_0402_5%
1 2
PQ2AO4407_SO8
3 65
78
2
4
1
PR241K_0402_1%
1 2
G
D
S
PQ11
RHU002N06_SOT323
2
13
PR31
3K_0
402_
1%
12
PC21
4.7U
_080
5_6.
3V6K
12
PQ3AO4407_SO8
3 65
78
24
1
[email protected]_0402_16V7K
12
PD5RLZ16B_LL34 2
1
PC22
0.1U_0402_16V7K
1 2
PR29
133K
_040
2_1%
12
PD7
1SS355_SOD323
12
PC14
10U
_120
6_25
V6M
1
2
PR34
330K_0402_5%
1 2
47K
47K
PQ5DTA144EUA_SC70
2
13
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ADP_PRES
BATT_IN
BATSELB_A#
BATSELB_A
BATSELB_A#
BATSELB_A#
BATT_IN
CFET_A
CFET_B
CFET_A
BATT_IN
CFET_B
BATT_IN
BATT_IN
BATSELB_A
CELLSEL#
I_A#
CFET_B
CHGCTRL30,37>
AC_CHG<37>
BATSELB_A#<30>
ALARM<37>
ADP_PRES <22,30,37,39,43>
BATCON <30>
CELLSEL#<37>CFET_B<43>
AB/I_A<36>I_A <43>
BATT
+3VL
+3VL
BATT
+3VL
+3VL
+3VL
+3VL
+3VL
+3VL
BATT_A
BATT_B
+3VL
BATT_A
BATT_B
+3VL
+3VL +3VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
Battery selectorCustom
38 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
2005.8.26
G
D
S
PQ31
RHU002N06_SOT323
2
13
PR69
220K
_040
2_5%
12
PR7110K_0402_1%
12
PR262
330K_0402_5%
1 2G
D
S
PQ76
RHU002N06_SOT323
2
13
PR67470K_0402_5%
12
PQ24AO4407_SO8
3 65
78
2
4
1
G
D
S
PQ16RHU002N06_SOT323
2
13
PR65
10K_0402_5%
1 2
PR66470K_0402_5%
12
G
D
S
PQ75
RHU002N06_SOT323
2
13
G
D
S
PQ23
RHU002N06_SOT323
2
13
G
D
S
PQ30
RHU002N06_SOT323 2
13
PR74
10K_
0402
_5%
12
PR56
0_0402_5%
1 2
PR581.5M_0402_5%
12
PR59
22K_
0402
_5%
12
PQ21AO4407_SO8
3 65
78
2
4
1
G
D
S
PQ19RHU002N06_SOT323 2
13PU10
SN74AHC1G08DCKR_SC70
IN11
IN22 G3
O 4
P5
PR68470K_0402_5%
12
PD14
1SS355_SOD323
12
G
D
S
PQ15RHU002N06_SOT323 2
13
G
DS
PQ13RHU002N06_SOT323
2
13
PU9
SN74LVC1G14DCKR_SC70-5
A2 Y 4
P5
NC
1
G3
PR55
100_0402_5%
1 2
PR72
470K
_040
2_5%
12
PC30
@0.
1U_0
402_
10V6
K
12
C
BE PQ
18PM
BT22
22_S
OT2
3
1
2
3
PD101SS355_SOD323
12
PU12
SN74AHC1G08DCKR_SC70
IN11
IN22 G3
O 4
P5
G
DS
PQ27RHU002N06_SOT323
2
13
C
BE PQ
26PM
BT22
22_S
OT2
3
1
2
3
PU6
74LVC1G02_04_SOT353
INB1
INA2
P5
G3
O 4
PR57
47K_
0402
_5%
12
PC35
0.22
U_0
402_
10V4
Z
12
PR70
470K
_040
2_5%
12
G
D S
PQ12RHU002N06_SOT323
2
1 3
PD16
1SS355_SOD323
1 2
PD11
RLZ6.2C_LL34 2
1
PU11SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1
PR77
100K
_040
2_5%
12
PR264330K_0402_5%
12
PQ22AO4407_SO8
365
78
2
4
1
PR60
22K_
0402
_5%
12
PR63
10K_
0402
_5%
12
G
D
S
PQ29RHU002N06_SOT323 2
13
G
D
S
PQ20
RHU002N06_SOT323
2
13
PD13SKS30-04AT_TSMA
21
PR75
10K_0402_5%
1 2G
D
S
PQ28
RHU002N06_SOT323
2
13
PR62470K_0402_5%
12
PU7
74LVC1G02_04_SOT353
INB1
INA2
P5
G3
O 4
PR734.7K_0402_5%
12
PR644.7K_0402_5%
12
PD17
RB715F_SOT323
2
31
PC33
1000P_0402_50V7K
1 2
PR263330K_0402_5%
12
G
D
S
PQ32
RH
U00
2N06
_SO
T323
2
13
PD9
RB715F_SOT323
2
31
G
D
S
PQ14RHU002N06_SOT323 2
13
PC34
220P
_040
2_50
V7K
12
PC32
0.1U
_060
3_50
V4Z
12
PR61470K_0402_5%
12
PR76100K_0402_5%
12
PC31
1000P_0402_50V7K
1 2
PQ25AO4407_SO8
365
78
2
4
1
G
D
S
PQ17RHU002N06_SOT323 2
13
PD12
1SS355_SOD323
1 2
PU13
SN74LVC1G17DBVR_SOT23-5
O 4I2
P5
G3
NC 1
PD15
SKS30-04AT_TSMA
21
PU8
SN74LVC1G14DCKR_SC70-5
A2 Y 4
P5
NC
1
G3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DL3
DH3
5HG
LX5
BST3A
BST3BBST5B
DL5
DH5
BST5A
3HG
LX3
2VREF_1999
2VREF_1999
MAINPWON
KBC_PWR_ON <30>
LX_5V<43>
ADP_PRES <22,30,37,38,43>
B++
+3VALWP
VL
+5VALWP
B+
VL
B++
B++
2VREF_1999
+3VLP
+3VL
+3VL+3VLP
VL+3VALWP
B++
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
3.3V / 5V
B
39 47Friday, April 28, 2006
2005/03/01 2006/03/01
+3.3V/+5V
PR84
200K
_040
2_1%
12PL
710
UH
_D10
4C-9
19AS
-100
M_2
0%
12
PC520.1U_0603_16V7K
12
PC480.1U_0603_25V7K
12
PR86
499K
_040
2_1%
12
PC400.1U_0603_16V7K
12
AO4916_SO8
PQ34
D22 G2 8
G13D1/S2/K 5
D21D1/S2/K 7
S1/A4 D1/S2/K 6
PD18CHP202U_SC70
1
3 2
PC50
0.22
U_0
603_
10V7
K
1
2
PU14
MAX1999EEI_QSOP28
LX515DL519
BST514
DH516
OUT521FB59
SHDN#6ON54
GN
D23
ILIM5 11
DH3 26
LX3 27
TON
13
DL3 24
OUT3 22
FB3 7PGOOD 2SKIP#12
ON33
REF8
PRO
#10
VCC
17
V+20
ILIM3 5
BST3 28
LDO
325
LD05
18
N.C.1
+
PC47
150U
_B2_
6.3V
M
1
2
PR950_0402_5%
12
+
PC49
150U
_B2_
6.3V
M
1
2
PR97499K_0402_1%
12
PR98100K_0402_5%
12
PR890_0402_5%
1 2
PR96
0_04
02_5
%
12
G
D
S
PQ36RHU002N06_SOT323
2
13
PR94
3.57
K_04
02_1
%@
12
AO4916_SO8
PQ35
D22 G2 8
G13D1/S2/K 5
D21D1/S2/K 7
S1/A4 D1/S2/K 6
PJP1
PAD-OPEN 2x2m
2 1
PC370.1U_0603_50V4Z
1 2
PR92
0_04
02_5
%
12
PR780_0402_5%
1 2
PC43
4.7U
_120
6_25
V6K
12
PR790_0402_5%
12
PR87
499K
_040
2_1%
12
PC42
4.7U
_120
6_25
V6K
12
PR90
47K_
0402
_5%
12 PR93
0_0402_5%1 2
PR83
200K
_040
2_1%
12
PR80
47_0
402_
5%
12
PR850_0402_5%
12
PC51
4.7U
_080
5_10
V4Z
12
PR242100K_0402_5%1
2
PR910_0402_5%@1 2
PR814.7_1206_5%
12
G
D
S
PQ37RHU002N06_SOT323
2
13
PC46
0.1U
_060
3_50
V4Z
1
2PC45
4.7U
_080
5_10
V4Z
12
G
D
S
PQ77RHU002N06_SOT323
2
13
PC39
10U
_120
6_25
V6M
1
2
PC360.1U_0603_50V4Z
1 2
PC38
2200
P_04
02_5
0V7K
12
PR820_0402_5%
12
PR88
10.2
K_04
02_1
%
@
12
PC41
2200
P_04
02_5
0V7K
12
PL6FBM-L18-453215-900LMA90T_1812
12
PL84.7UH_SIQB74-4R7_3A_30%
12
PC44
1U_0
805_
16V7
K
12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
LX_1.05VDH_1.5V_1
BST_1.05V_1
BST_1.5V_1
VCC_MAX8743
BST_1.5V_2
DH_1.05V_1
DH_1.05V_2
BST_
1.05
V_2
DL_1.05V
VCC_MAX8743
DL_1.5V
DH_1.5V_2
SLP_S3#SLP_S3#
LX_1.5V
VCCP_POK <34>
SLP_S3# <20,22,24,25,26,30,32,33,41>
SLP_S3#<20,22,24,25,26,30,32,33,41>
SLP_S3#<20,22,24,25,26,30,32,33,41>
B+
+5VALW
+1.05V_VCCP +1.5VSP
MAX8743_B+
2VREF
+1.5VS
+VCCP
+1.5VSP
+0.9V+0.9VP
+1.05V_VCCP
+5VALWP
+3VALWP
+5VALW
+3VALW
+2.5VSP +2.5VS
+5VALW
+5VALW
+2.5VSP
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
2.5VALW/1.5VS/1.05VCCPCustom
40 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
1.5VSP/ +1.05V_VCCP/+2.5VALWP
(6A,240mils ,Via NO.= 12)
(7A,280mils ,Via NO.= 14)
(4A,160mils ,Via NO.=8)
(2A,80mils ,Via NO.= 4)
(3A,120mils ,Via NO.= 6)
(4.5A,180mils ,Via NO.= 9)
(1A,40mils ,Via NO.= 2)
Fine tune power sequence
PJP11PAD-OPEN 2x2m
21
PR107100K_0402_1%
12
PC590.1U_0603_50V4Z
12
PU26
G965-18P1U_SO8
ADJ 4
GND5
VIN2 VO 3
EN1
GND 8
GND 7
GND6
PJP5
PAD-OPEN 4x4m
1 2
+
PC63
220U
_B2_
2.5V
M
1
2
PJP9
PAD-OPEN 2x2m
2 1
PC54
10U
_120
6_25
V6M
1
2
PQ38AO4422_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PL9FBM-L11-322513-151LMAT_1210
12
PR112100K_0402_5%
12
PD19
CHP202U_SC70
1
3 2
G
D
SPQ43
RHU002N06_SOT323
2
13
PR119100K_0402_5%
12
PJP6PAD-OPEN 4x4m1 2
PC554.7U_1206_16V4Z
12
G
D
S PQ44RHU002N06_SOT323
2
13
PR11
810
0K_0
402_
1%
12
PR109@0_0402_5%
12
PC13510U_1206_6.3V6M
12
PR12247K_0402_5%
1 2
PC53
2200
P_04
02_5
0V7K
12
PR11
110
K_04
02_1
%
12
PQ40AO4702_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PR11547K_0402_5%
12
PU15
MAX8743EEI_QSOP28
OUT2 15
BST2 19
FB2 14
CS2 16
VDD 21
UVP
9
SKIP
6
V+4
GN
D23
ON111
DH126
LX127
ILIM2 13
DL124
VCC
22
PGOOD 7
FB12 ON2 12
ILIM1 3
OVP
8
REF
10
LX2 17DL2 20
TON 5
CS128
BST125
DH2 18
OUT11
PL113.3UH_SIQB74-3R3_4.8A_30%
1 2PC61
1U_0
805_
16V7
K
12
PR116
@0_0402_5%12
PC58
4.7U
_120
6_25
V6K
12
PR1040_0402_5%
1 2
PR990_0402_5%
12
PJP3
PAD-OPEN 4x4m
1 2
AO4916_SO8
PQ39
D22 G2 8
G13D1/S2/K 5
D21D1/S2/K 7
S1/A4 D1/S2/K 6
PC57
2200
P_04
02_5
0V7K
12
PR117100K_0402_1%
12
PR1020_0402_5%
1 2
PR1130_0402_5%
12
PC69
0.22
U_0
603_
10V7
K
12
PC64
2.2U
_060
3_6.
3V6K1
2
PR24413K_0603_1%
12
PC620.1U_0603_50V4Z
12
PR110@0_0402_5%1 2
PR10
65.
1K_0
402_
1%
12
PC13410U_1206_6.3V6M
12
PR243
10K_0402_5%
1 2
PL103.3UH_MPL73-3R3_6A_20%
12
PR10020_0603_5%
12
PJP8
PAD-OPEN 3x3m
1 2
G
D
SPQ41
RHU002N06_SOT323
2
13
PR1032.2_0402_5%
1 2
PR1080_0402_5%
12
PR1140_0402_5%
12
PR1230_0402_5%
1 2
G
D
SPQ42RHU002N06_SOT323
2
13
+
PC66
220U
_B2_
2.5V
M
1
2
PR1200_0402_5%
12
PR1010_0402_5%
1 2
PC60
0.1U
_060
3_50
V4Z
12
PR1210_0402_5%
12
PC71
@0.
001U
_040
2_50
V7M
12
PJP2
PAD-OPEN 3x3m
1 2
PR24512K_0402_1%
12
PC561U_0805_50V4Z
12
PC70
@0.
001U
_040
2_50
V7M
12
PR10
55.
1K_0
402_
1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DH_1.8V_1
BST_1.8V_1 BST_1.8V_2
DH_1.8V_2
LX_1.8V
DL_1.8V
SLP_S5# <20,33>
SLP_S3# <20,22,24,25,26,30,32,33,40>
V_DDR_MCH_REF<7,13,14>
SLP_S4# <20>
SLP_S5# <20,33>
+5VALWP
B+
DDR_B+
+1.8V
+1.5VS
+0.9VP
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
1.8V/0.9VSB
41 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
PL12FBM-L11-322513-151LMAT_1210
12
PR1260_0402_5%
1 2
PR1330_0402_5%
12
PC7310U_1206_25V6M
1
2
PC82
4.7U
_080
5_10
V6K
12
PC84
@0.
001U
_040
2_50
V7M
12
PR134
@0_0402_5%12
PR1320_0402_5%@
12
PR1270_0402_5%1 2
PR12814K_0402_1%
12PC
810.
033U
_040
2_16
V7K1
2
PQ46AO4702_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PR12
40_
1206
_5%1
2
PR12
920
K_06
03_1
%
12
PC740.1U_0603_50V4Z
1 2
PC76
10U
_080
5_10
V4Z
12
+
PC78
330U
_D2E
_2.5
VM
1
2
PR1250_0402_5%
1 2PU17
TPS51116RGE_QFN24
PGND 18
LL 20
S5 11
PGOOD 13
VDDQSET9
VTT24
VTTREF5
CS 16
GND3
V5FILT 14
COMP6
S3 10
MODE4
DRVH 21
DRVL 19
VDDQSNS8
VTTGND1
VLDOIN23 VBST 22
VTTSNS2
V5IN
15
CS_
GN
D17
NC
7
NC
12
Ther
mal
pad
25
PC7922U_1206_6.3V6M
12
PC7510U_0805_10V4Z
12
PC80
22P_
0402
_50V
8J
12
PQ45AO4422_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC83
0.00
1U_0
402_
50V7
M
12
PR1303_0402_5%
12
PC85
@0.
001U
_040
2_50
V7M
12
PC72
2200
P_04
02_5
0V7K
12
PL13
2.2UH_IHLP-2525CZ-01_8A_+-20%_2525CZ
1 2
PR13510K_0402_1%
12
PR1310_0402_5%
12
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
PWM1
NTC
VSUM
ISEN1
VSUM
DH_CPU1
DL_CPU2
DH_CPU2
LX_CPU2
VSUM
PWM2
DL_CPU1
ISEN2
+VCC_CORE
NTC
LX_CPU1
VO
VO
VO
BST_
CPU
1_1 BST_C
PU1_2
BST_
CPU
2_1 BST_C
PU2_2
PWR_GD<30,33,34,43>
DPRSLPVR<7,20>H_PSI#<5>
VGATE_INTEL<7,20>
CPU_VID0<5>CPU_VID1<5>CPU_VID2<5>CPU_VID3<5>CPU_VID4<5>CPU_VID5<5>CPU_VID6<5>
H_PROCHOT#<4>
H_DPRSTP#<4,19>
CLK_ENABLE#<15,34>PGD_IN<34>
VCCSENSE<5>
VSSSENSE<5>
VGATE
B+
+VCC_CORE
+CPU_B+
+5VS
+CPU_B+
+5VS
+3VS
+5VS
+VCC_CORE
+CPU_B+
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
CPU_COREC
42 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
PR1735.11K_0402_1%
12
PR1604.22K_0603_1%
12
PR18
53K
_040
2_1%
12
PR154
@0_0402_5%
12
PR18
64.
53K_
0402
_1%
12
+
PC14
868
U_2
5V_M1
2
PC10
60.
01U
_040
2_25
V7K
12
PC125
1000P_0402_50V7K
12
PC10
41U
_060
3_10
V6K
12
PR1610_0402_5%
12
PR1680_0402_5%
12
PR177
0_0402_5%
12
PC1201800P_0402_50V7K
1 2
PR181
11.5K_0402_1%
12
PC11310U_1206_25V6M
1
2PC11
122
00P_
0402
_50V
7K1
2
PR1551.91K_0603_1%
12
PC10310U_1206_25V6M
1
2
PC10
00.
01U
_040
2_50
V4Z
12
PC1070.22U_0603_16V7K
12
PC11
24.
7U_1
206_
25V6
K1
2
PR1690_0402_5%
12
PR18010_0402_1%
12
PU19
ISL6260CRZ-T_QFN40
VW8
PGD_IN2
PSI#1
DPRSLPVR36
DPRSTP#37
VID634 VID533
RTN13
FB10
COMP9
VS
S19
VDIFF11
DFB
15
VO
16
ISEN3 21
OCSET 7
PWM3 25
FCCM 24
CLK_EN#38
VR_TT#4
RBIAS3
NTC5
SOFT6
VID028VID129VID230VID331VID432
3V3
39
VSUM 17
VSEN12
VR_ON35
PWM1 27
ISEN2 22
ISEN1 23
PWM2 26
DR
OO
P14
VD
D20
VIN
18
PG
OO
D40
CS_GND 41PC
122
1000
P_04
02_5
0V7K
12
PR183
0_0402_5%
12
PR182180_0603_1%
12
PR16710_0402_1%
12
PC12
6
0.1U
_040
2_16
V7K
12
PR15110K_0402_1%
1 2
PR188
6.98K_0402_1%
12
PR1841.2K_0402_1%
12
PC10
24.
7U_1
206_
25V6
K
12
PR1570_0402_5%
12
PH2
470KB_0402_5%_ERTJ0EV474J
12
PR1911K_0402_1%
12
PU18
ISL6208CRZ-T_QFN8
BOOT 1
FCCM6
VCC5
PWM2
LGATE 4GND3
PHASE 7
UGATE 8
PR1906.19K_0603_1%
12
PR1480_0402_5%
12
PR159147K_0402_1%
12
PQ53
FDS6
676A
S_SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PH3
10KB
_060
3_5%
_ER
TJ1V
R10
3J
12
PC109
0.01U_0402_16V7K
12
PR1760_0402_5%
12
PR1660_0402_5%
12
PC115
0.015U_0402_16V7K
12
PQ54SI7840DP_SO8
35
2
4
1
PC119
1000P_0402_50V7K
12
PR1620_0402_5%
12
PC127
330P_0402_50V7K
12
PR17910_0402_1%
12
PR15
210
_060
3_5%
1
2
PR14910_0603_5%
12
PC1210.022U_0402_16V7K
1 2
PC11
41U
_060
3_10
V6K
12
PR1740_0402_5%
12
PR1720_0402_5%
12
PC1050.22U_0603_16V7K
1 2
PR1650_0402_5%
12
PC10
81U
_060
3_10
V6K
12
PR1630_0402_5%
12
PC118
1000P_0402_50V7K
12
PR15010_0402_1%
12
PC12
30.
22U
_060
3_16
V7K
12
PC1160.22U_0603_16V7K1 2
PR17010K_0402_1%
1 2
PQ50SI7840DP_SO8
35
2
4
1
PC11
00.
01U
_040
2_50
V4Z
12
PR18
9@
1K_0
402_
1%
12
PQ57
FDS6
676A
S_SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PR1560_0402_5%
1 2
PR18751K_0603_1%
12
PR1640_0402_5%
12
PC1170.22U_0603_16V7K
12PR171
499_0402_1%
12
PL16
.36UH_MPC1040LR36_ 24A_20%
1 2
PC124
220P_0402_25V8K
1 2
PL17
.36UH_MPC1040LR36_ 24A_20%
1 2
PC10
122
00P_
0402
_50V
7K
12
PR175
@0_0402_5%
12
PR1535.11K_0402_1%
12
PU20
ISL6208CRZ-T_QFN8
BOOT 1
FCCM6
VCC5
PWM2
LGATE 4GND3
PHASE 7
UGATE 8
PQ52
FDS6
676A
S_SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PQ56
FDS6
676A
S_SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PR1580_0402_5%
12
PL15FBM-L18-453215-900LMA90T_1812
1 2
PR1780_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_GD <30,33,34,42>
ACN <37>
ADP_EN# <37>
ADP_ID <30>
ADP_EN <30>
ADP_PS0 <30>
ADP_PS1 <30>
LX_5V <39>
OCP# <4,20>
ADP_PRES <22,30,37,38,39>
ADP_PRES <22,30,37,38,39>
ACOCP_EN#<32>
I_A <38>
CFET_B <38>
SRSET<37>
+5VS
B+
VINVIN
+5VS
+5VS
+3VS
+3VS
+3VS
VIN
+3VS
P4
+5VS
+3VL
+5VS
ADP_SIGNAL
VIN
VIN
+3VSADP_SIGNAL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P
ADP_OCPCustom
43 47Friday, April 28, 2006
2005/03/10 2006/03/10Compal Electronics, Inc.
2005.8.24
2005.8.20
PR194330K_0402_5%
12
PR203604K_0603_1%
1 2
PR254150K_0402_5%
12
PR22271.5K_0402_1%
12
PR24110K_0402_1%
12
EB
CPQ63MMBT3904_SOT323
2
31
PU25A
LM393M_SO8
+3
-2 O 1
P8
G4
PR
202
2K_0
402_
5%
12
PR
196
0_04
02_5
%
12
PR2073.9K_0402_5%
12
PR26547K_0402_5%
12
G
D
S
PQ74RHU002N06_SOT323
2
13
PR20810_0402_5%
12
PU22A
LM358A_SO8
+ 3
- 201
P8
G4
PR23610K_0402_1%
12
EB
CPQ61MMBT3904_SOT323
2
31
PR23221K_0603_1%1 2
PR193
100K_0402_5%
1 2
PR22110K_0402_5%
12
G
D S
PQ72NDS0610_SOT23
2
1 3
47K
47K
PQ70DTA144EUA_SC70
2
13
PR200100K_0603_0.5%
1 2
PR2381M_0402_5%
1 2
PR
251
220K
_040
2_5%
12
PR22710K_0402_5%
12
PD22@CH751H-40_SOD323
1 2
PR225100K_0402_5%@
12
PR255
1K_0402_5%
1 2
PR22821K_0603_1%
12
PR21810K_0402_5%
12
PD25
1SS355_SOD323
12
PU23
LMV431ACM5X_SOT23-5
NC 2
REF4
NC 1
CATHODE 3
ANODE5
PR201
0_0402_5%
1 2
PD271SS355_SOD323
12
PR
240
0_04
02_5
%
12
PR
215
470K
_040
2_5%
12
PU21B
LM393M_SO8
+5
-6 O 7
P8
G4
PU22B
LM358A_SO8
+5
-6 0 7
PR
206
7.87
K_0
402_
1%
12
PR19910K_0402_1%
1 2
G
D
S PQ65@RHU002N06_SOT323
2
13
PR
214
3.9K
_040
2_5%
12
PR197
6.81K_0402_1%
1 2
PR
239
220K
_040
2_5%
12
PR2191M_0402_5%1 2
PR2291M_0402_5%1 2
PR253210K_0402_1%
12
PR2343.48K_0402_1%
12
G
D
S
PQ60RHU002N06_SOT323
2
13
PC1330.1U_0603_16V7K
12
PR
210
422_
0603
_1%
12
PC
131
0.02
7U_0
402_
16V
7K
12
PR
260
39.2
K_0
402_
1%
12
PD21CH751H-40_SOD323
1 2
PR23510K_0402_1%
12
PR
195
0_04
02_5
%
12
PD26
1SS355_SOD323
1 2
PR23047K_0402_5%
12
PR257
10K_0402_5%
12
PR223182K_0402_1%
12
PC1290.22U_0603_16V7K
1 2
G
D
S
PQ
73N
DS
0610
_SO
T23
2
13
C
BE
PQ
58M
MB
T390
6_S
OT2
3
1
2
3
PC
147
3900
P_0
402_
50V
7K
1
2
PR256
10K_0402_5%
12
PC
128
1U_0
805_
16V
7K
12
PU24B
LM393M_SO8
+5
-6 O 7
P8
G4
G
D
S
PQ64RHU002N06_SOT323
2
13
PU21A
LM393M_SO8
+3
-2 O 1
P8
G4
PD281SS355_SOD323
12
PU24A
LM393M_SO8
+3
-2 O 1
P8
G4
PR22010K_0402_5%1 2
PR211
0_0402_5%
1 2
PR25822.6K_0402_1%
12
PR21747.5K_0402_1%
1 2
PD
241S
S35
5_S
OD
323
12
PU25B
LM393M_SO8
+5
-6 O 7
P8
G4
PD20CH751H-40_SOD323
1 2
PR233100K_0402_5%
1 2
PR192133K_0402_1%
12
PR2611M_0402_1%
12
G
DS
PQ62NDS0610_SOT23
2
13
PC
130
1U_0
805_
50V
4Z
12
PR
237
47K
_040
2_5%1
2
PR2261M_0402_5%1 2
PC
132
0.1U
_040
2_16
V7K
12
PR22422.6K_0402_1%
12
PR
252
220K
_040
2_5%
12
PR2591M_0402_1%
12
PR216
470K_0402_5%
12
PD23
1SS355_SOD323
1 2
PR231220K_0402_5%
12
PC1461U_0603_16V6K
12
G
D
S
PQ71
RH
U00
2N06
_SO
T323
2
13
PR
205
80.6
K_0
402_
1%
12
PR2120_0402_5%
12
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
H/W2 EE Dept. PIR SHEET
44 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
06/01/2005 schematics review start :06/02/2005 Page38 : Add R58,R59,R60 ,those are removed from daughter board
Page39 : JP18 pin3 change from ground to BT_LED
Page37 : Remove JP16 & change debug port interface to JP44
Page27 : ICH7M pin R7 change to +3VS
Page32 : JP44 PLT_RST# change to PLT_RST_B# to reduce the loading
Page33 : Update audio amp to MAX9710
06/03/2005 Page10 : Add R260 to reduce one 330U cap C666
Page25 : 1. R27 change to +3VS 2..Add R1035 for H_DPSLP#
Page26 : 1.Add T80 for GPIO25 2. GPIO21 change net name to VGARST# 3. Add T88 for GPIO23 4. Add T89 for GPIO26 5. GPIO30 change net name to USB_OC#6 6. GPIO31 change net name to USB_OC#7 7. Add R1036/7 for RESET option 8. Remove the connection of USB_OC#3/4/5
Page24 : Add ALS_EN on JP35 pin24 for light sensor
Page32 : 1.JP13 change to 90 pins connector 2.Add U72 for ESD protection
06/04/2005 Page10 : A. U71 change to U43D (the fourth gate in U43) B. Add +3VS_TVBG R/C filters & voltage follower D12,D21,R127,R520 Page34 : audio change-- add R1419 ,R431,R434,R435 for BIASA/B/C
Page35 : Add JP3 for Smart card FFC connector
Page18 : 1.R1365 CHANGE TO 2K_0402_1% 2. R1366 change to 562_0402_1% 3. R1367 change to 1.47K_0402_1%
Page31 : JP4 update to RJ45 connector
Page15 :Add the connection for UMA VGA clock , & SRC0/2 SWAP 1.Add R1148/R1149 , R1129/R1132 , R1118/R1121 2.Add R1242/R1248,R1253/R1272
Page09 : Change 0 ohm resistors before filters , and delete the other group of filtes at page 19
06/07/2005
Page47 : PQ34 pin5/6/7 change netname to LX_5V
Page38 : Pin96: INVPWM rename to OUT9 & add T90
Page36 : Delete R500 & rename to EXPCRD_RST#
06/08/2005 Page7 : Delete PD resistor R1340~R1343.
Page16 : add R671~R678 ,R530,R531 for DVI
Page19 : Swap I2C bus for LVDS/Thermal sensor
Page35 : Add JP3 for Smart card FFC connector
Page17 : Update JP35 LVDS connector
Page26 : A. GPIO28 ==Delete R1321 & A_SD , change to VGA_RST# B. GPIO21 ==Change to MB_PWR C. GPIO19 ==Change to PD
EE PIR list
Page17 : Delete Q56 ,R510 ,Caymus support 3V PWM
06/09/2005
Page25 : Update Q92 to AOS4407
Delete Cardbus 6612 circuit & move to daughter board LS-2953
Page26 : Delete R252
Page37 : Add PD RP42,R273
06/10/2005
Page17 : Add R458,R459 for ch_data,ch_clk
Page33 : Add C367 0.1U for +SC_PWR
06/11/2005
Page28: 1.Delete R15 ,due to Internal PD 2.Delete R69 ,due to Internal PD 3. Add U70,U71,R69,R92 R1297 for serial falsh support.
Page19 : Add T8/T9 for GPIO10/14
Page23 : Change L1,L2,L63,L6,L7,L9,L11-16,L65,L66 to FB
Page30 : Disconnect the I2C bus / WL_LED#/WP_LED# on JP46
Page10 : 1. Add R504/R505 for VCC_SYNC 2. Add R490/R491 for VCCTX_LVDS 3. Add R494 for VCCA_CRTDAC 4. Add R492/R493 for VCCA_LVDS 5. Add R495 for +3VS_TVBG 6. Add R500 for +3VS_TVDACA 7. Add R502 for +1,5VS_TVDAC 7. Add R499 for +3VS_TVDACB 8. Add R496 for +3VS_TVDACC
Page09 : 1.Add R460,R461, R550,R552,R553 for CRT discrete/uma option 2. Add R462,R463,R464 for TV discrete/uma option
06/13/2005
Page23 : Add R6 R15,R106,R128,R129 GPIO PD
06/14/2005 Page21 : Change L1,L2,L63 to FB
Page16 : 1. Add C174,C150,C142,C371,C358 for DVI 2. R103 change to 1%Page35 : U69 pin7 change to PD
06/15/2005 Page04 : R1265 change to 51_0402_5% & install
Page07 : Install R1344
Page28 : Delete U70 ,reserve U71 for 200 mil
Page35 : Delete U61 , resevre U66 for 200 mil
Page29 : Update U7 symbol pinB7/B8/C8
06/16/2005
Page32 : 1,Delete Q28 . 2. D49,D50 change to U73 3. Add C577,C581 for Lead free
Page36 : Delete R32 ,double PU
Page41 : Delete R180,Q49 ,the same function for +1.8VS
Page10 : Delete C982 for Lead-free
Page20 : Add C570 for Lead free
Page33 : Add R163,R164,R165 for USB power switch PU
Page26 : Separate PCIE_WAKE# to NIC/Mini-card PCIE_WAKE# to avoid battery mode can't enter S3 issue
Page23 : Delete L65,C270,C269,C271 for M52-T
Page18~23 : ATI VGA controller change to M52T
06/22/2005 Page09 : Add R554 , R555 for CRT disable
Page10 : 1. Add R508,R510 for VCCD_LVDS1/1/2 2. R504,R505 chnage for +2.5VS_GMCH,&delete R490,R491,R492,R493Page30 : Delete JP48,49 & change screw holes
06/23/2005 Page16 : Change SDVOB_INT+/- net name to PEG_RXP1/N1
Page10 : 1.R505 / R510 for M52 , R504 / R508 for UMA 2. R499,R500,R496 connect to +1.5VS for diable CRT
Page36: Delete R49 & CB_CLK
Page25: JP42 change to wire to board connector
Page19: 1.Add CRT,TV filters for M52T 2. Add DVI BOM option 0 ohm Page16 : Move 0 ohm to TV-out connector for TV
Page38 : Move 0 ohm to docking connector for CRT
06/24/2005
Page19 : Add LVDS L-shape BOM option resistors
Page10 : Enable TV/ CRT when using 945PM
Page9 : Enable TV/ CRT when using 945PM
06/25/2005 Page33 : Delete U58, R165,C568,C1,C312,C311 FOR LAYOUT SPACE
06/27/2005 Change All 2N7002_SOT23 to RHU002N06_SOT323 to save layout space
06/28/2005 Page40 : Change Q10,Q11,Q15,Q26 from SOT23 to SOT323 to save layout spacePage37 : 1 . Update JP20 to 6 pin connector 2. Update JP20 & JP18 pin assignments to follow Taos
06/30/2005 Page28 : Y1 update to smaller package 6x3.5
Page25 : Y4 update to smaller package 14M-J
Page15 : Y3 update to smaller package 6x3.5
07/01/2005 Page23 : Add HW strpping pin on DVPDATA20,21,22,23 for VRAM ID0,1,2,3
Page33 : U57 change to 2A current limit power switch G548
07/04/2005 Page17 : Add R131 for inverter PWM when ATI PWM issue
Page19 : 1. Add R49 , R189 for 1.2V voltage divider 2. Add Q12 for M52_therm# & change to GPIO14Page32 : The limitation for 5 pin audio jack can't switch headphone/docking line-out ,so add R1420,R1421,C526,R252 Delete R256,R255,C536.
Page39 : Delete C984~C988
Page33 : Delete C527
Page10 : Delete C823 reserved pad
Page25 : Add JP5 slim type ODD connector
07/12/2005 Page25 : Add C629,C630,C631 for SATA connector
Page33 : Swap JP3 samrt card pin assignment for FFC
07/14/2005 Page25 : Add R133 100 ohm to avoid RTC short
Page15 : 1. clock gen. pin 5 change to connect to +ck_vdd_dp 2. C731,C732,C733 change from 0.1u to 0.01u 3. C361,C364 change from 33p to 27p
07/19/2005
Page39 : Add C91,C93,C181 for low speed signal
Page30 : Add R1422 pad for XMIT_OFF
07/20/2005
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
H/W2 EE Dept. PIR SHEET
45 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
For DB2 Modification
08/11/2005
Page31/32 : Update Audio portion for jack sensing
Page35 : Delete LED circuit & connect to LS-2953 directly
Page11 : Change R1154 to NI
Page30 : Add C554 for UIM power
Page25 : Delete JP37 MB2 conector
Page19 : Change C611 to NI ,R662 to 0 ohm for clcok spectrum
Page15 : Add R1136 PD for clk_pcie_m52 ,R1084 change to NI
Page24 : R1388 change to Install
Page26 : R1364 change to NI
Page36 : R1354 change to NI
08/15/2005 Page30 : R1418 , R1360 change to NI
Page21 : Add C140, C172 , C141 , L17 for VDDPLL
08/26/2005
Page32 : Add R427,R429,C492 for J_MIC_REF
Page23 : Add R173 for Therm_SCI#
08/19/2005
Page35 : Delete FWH , SPI change to +3VALW
Page25 : Add D15,D16,R88,R90 for HDD_LED
Page23 : R154 change to NI
Page38 : Delete R551 ,R548,R549,R541
Page36 : R538 change to NI
Page36 :Delete R538
Page10 : Delete L39
Page30 : Add SW1 C986, R521 , D65,D66 for SIM power off
08/31/2005 Page32 : Delete R1419, R1420
Page19 : R189 change to 56_0402_1%
08/29/2005 Page32 : Add 1423,R1424 for MIC_REF , & MIC_SENSE connection
08/30/2005
Page15 : Add C373 for clk_debug_port
08/25/2005 Page31/32 : Add JP16 for audio cable
Page15 : Add C353~C372 for clk cap 08/24/2005
Page29 : Add C333 for NIC
Page25 : Add D15, D16 , R90 , R88 for HDD LED
Page30 : Internal MIC signal change to JP13
08/20/2005 Page30 : Change +3VL / Caps_LED# to Pin45/51
10/04/2005
Page26 : R251.2/C526.1 connect to DLINE_OUT_L
Page32 : PR255.1 connect to pin 29 of the docking connector. (ACOCP_EN#)Page29 : Add discharge circuit for BT_LED and WL_LED(R504,R505) (this issue occurs when there is no WLAN card)
Page20 : Delete R1323 (EAPD to ICH7)
Page22 : Add Q40,R1419, reserve R1420
Page24 : Add R996,reserve R519,Q41,Q42
Page29 : Install R1409, Make R1380 NI;reserve R101
Page30 : Reserve R91,R102
Page27 : Change R454 to 47K , add C556
Page25 : Install R136
Page15 :Delete R1071,R1073,R1076,R1082,R1094,R1096,R1258,R1260 R1112,R1116,R1250,R1252,R1124,R1127,R1134,R1137,R1238 R1239,R1242,R1248,R1253,R1272(NOLP@)
10/04/2005 Page32 : Reserve C555
10/06/2005 Page24: NI D64 ,install R1355
Page07: NI R1202,R1203
Page22: NI R1397,U36;Install Q94;Add R1076
Page29:Reserve U61
Page24:Add R1364;Reserve R1363
Page30:Install R91
Page24:Add R1366;Reserve R1365
10/07/2005 Page24: Add R1071,R1073
Page07: NI R1209
Page22: Install R275,R289;NI R1396,R1398
Page20: Install R1384,R1395;Reserve R1385,R1427 Del Q71,R1345
Page20: Add R1040,R871;Reserve Q106;Del R1404
Page22 : Add R1091,R1082,R1088,R1085,Q105,R1023, R1024,D63,C1042,U55,R1021,R1076; Reserve Q103,Q104,R1090, Del R601.Page15 : Del R1084,R1136
10/08/2005 Page28 :Install Q103;NI R1091
10/13/2005 Page33 :Delete J33
Page18 :Delete BIOS_SEL jump
10/26/2005 Page26 :NI C526
Page32 :Add R1404,R1428,R1429,R1430,R1431,R1432, R609,R608,R611,R610,R613,R612,R616,R615Page31 :Install CP1~CP6
10/31/2005 Page06 :NI C933;Modify 330U cap from ESR9 to ESR7.
For SI2 Modification
12/06/2005 Page06 :Del C938.
Page24 :NI R1355 , Install D64
Page31 :exchange netname between JP18's pin 25 and pin 24
Page30 :Install R33;Change RP43,44 to 10K ohm
Page34 :Del U45,U48,R1306,R117,R1307,C33,C993,C87
Page19 :Del C646
12/07/2005 Page20 :Del R1384,R1385,R1427; Connect LP_EN# to GPIO8
12/13/2005 Page15 :Add C740,C741,C744,C745 for EMI request
Page20 :Add Q43 HALT LED issue12/14/2005
Page31 :Add R1084 and reserve R1096
12/15/2005 Page32 :Modify R1404 ,R1428,R1429 to 0603
Add C746,C747,C748 for EMI request
12/16/2005
Page22 :Del U71,R69,R92,R1297
Page24 :UI R1364,Install R1363
12/16/2005 Page16 :Add R1369,R1367,R1368
Page32 :Add D16 for EMI request
Page30 :Change C350,C349 to 18pF
Page15 :Change C361,C364 to 18pF
Page19 :Change C516,C528 to 15pF
Page31 :Add D66 for EMI request
Page07 :Install R1201,R1204
Page15 :Change R1075,R1081,R1129,R1132,R1148 ,R1149,R1111,R1115 to 22ohm
For PV Modification
Page07 :UI R1201,R1204 for SI-2 shutdown issue01/16/2006
Page15 :Change R1148,R1149,R1070,R1072,R1075,R1081,R1129,R1132
R1093,R1095,R1257,R1259,R1144,R1145,R1123,R1126,R1133,R1111
R1115,R1143,R1249,R1251 to 24Ω for CLK GEN vendor recommand
Page24 :R996 change to SM010014500 (220ohm impedance) for improve WLAN performance
02/07/2006 Page24 : Modify R996 to 1000ohm/100MHz bead
Modify R996's location to L78
For power noise impact WLAN performance
Page24 : Connect R1363.2 to V_3P3_LAN, INSTALL R1363 and UI R1364
For support wake on WLAN from S3.
Page15 : Install R1245 and UI R1247
Page31 : Change Num_LED# and CAPS_LED#
For LED reverse issue
Layout:Modify +3VALW power trace width for LCDVDD
02/14/2006 Page20 : Add R1437
For HALTLED turn on 100ms when power on.
Page29 : Del U61. (150mil SPI ROM)
Page15 : Add C357,C372,C373,C374,C375,C376,C378,C379
To improve WWAN performance
02/16/2006 Page32 : Add R1433~R1436 on each DVI differential pair for EMI request.
02/20/2006 Page26 : Connect JP24 and JP15's 7,8pin to DGND.
For ESD concern.
02/21/2006 Page09 : Reserve ESD diode(D67) for C_HSYNC and C_VSYNC
02/23/2006 Page27 : Add D51,D52,D61 for EMI team request
02/24/2006 Page16 : Change C140 to 22u, R103 to 1.3K to fix DVI EMI issue
For MV1 Modification03/24/2006
Page22 : Change R70 to 1.21K to improve signal amplitude
03/08/2006 Page26 : Change R1405 and R1406 to 12.1K
Page19 : Change Y4 to a LF part.
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2951 1.0
H/W2 EE Dept. PIR SHEET
46 47Friday, April 28, 2006
2005/05/26 2006/07/26Compal Electronics, Inc.
Page32 : Change R1433~R1436 to 110Ω;04/06/2006
Page16 : Change C310,C313,C314 to 18P
Change R609~R613,R615,R616 to L79~L82 (common mode choke 90 ohm)
For DVI EMI issue
For CRT EMI issue
Page09 : Change L28,L35,L27 to 0 ohm;C193,C232,C237 to 12P
Change L31,L34,L26 to 39nH inductor
For CRT EMI issue
04/28/2006 Page22 : Install R1022 and UI R1021
For clock can't shut down under DC mode
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-2952P 1.0
PWR PIR Sheet (1)
Custom
47 47Friday, April 28, 2006
2005/03/01 2006/03/01
Version Change List ( P. I. R. List ) for Power Circuit
Item Issue DescriptionDateRequestOwner Solution Description Rev.Page# Title
1
2
3
DB42,44,508/26/2005(DB) HP To implement 4 cell main battery
Add PR2,PR259,PR261(1M ohm), Add PQ73,PQ74,PQ75,PQ76(RHU002N06_SOT323)Add PR260(39.2k)
488/30/2005(DB) HP To fix VDD_CORE in 1V(Only for Discrete).
Remove PQ49,PQ66
10/18/2005(SI) HP Changes for OCP circuit
Add PC147 3900pF capacitor across PR214 Change PR207 from 0 Ohm to 3.9K_5% Change PC131 from 0.22uF to 0.027uF Change PR203 from 649K to 604K_1% Change PR221 from 47K to 10K_5% Add a newPR265 47K_5% resistor in series with PR216-2 Add a new PC146 1uF X7R capacitor from PR216-2 to GND Change PC133 from 10uF to 0.1uF X7R Change PR228 from 10K to 21K_1% Change PR234 from 11.5K to 3.48K_1% Change PR232 from 3.3K to 21K_1%
4
43
37 10/18/2005(SI) HP sets Max charge current to 3.75A Change PR29 from 100K to 143K_1%
DB
SI
SI
5 PR225 is open and PR26.2 connects to PQ63.112/06/2005(SI2)43 37 HP Changes for OCP circuit
Correct PR223 from 180K to 182K.Change PR258 from 29.4K to 22.6K
SI
SI26 4312/12/2005(SI2) HP Changes for OCP circuit for 50W adapter
7 41 12/19/2005(SI2) compal
DDR2 issue Change PC78 from 220u to 330uDelete PC81,PR127
8 4212/21/2005(SI2) compal OTS#181928
Electrical printed circuit assembly acoustic noise test fail-Add PC148(68uF)
SI2
SI2
For 1.8V thermal shut down issuecompal01/16/2006
(PV)9 41 Add PC81,PR127 PV
10 02/08/2006(PV) compal OTS#184638
SVTP_SI1:PC Card Wireless Radio Interference fail on GSM 850 and GSM 900 channel.
Change PL8,PL11 to shielded inductors PV
This change will slightly increase the battery life11
3702/17/2006(PV) HP Change PR38 to 866_1% Ohms
Change PR41 to 100K_0.1% Change PR44 to 7.68K_0.1% Change PR53 to 2.80K_0.5% Add a 39.2_1% resistor in series with PR53. Connect one end to PR53.2 and the other end to GND.
PV
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