Pascal LECLAIRE
European AE team leader
IcDesign Test & Manufacturing
High Density Advanced Packaging Sign-off and Verification solutions
D43D workshop , July 2018
© Mentor Graphics Corp. Company Confidential
IRT Nanoelec – Mentor participation
� CEA-LETI is the project lead
� Mentor is a founding partner
� Mentor’s interests/objectives in this program:— Enhance process flow and tools to support 3D-IC and Si Photonic
technology specific requirements
� Mentor’s benefits: — Direct interaction with researchers and engineers allows us to have
earlier access to data and information
— Both 3D-IC and Si Photonics programs require interaction with multiple
disciplines, design, manufacturing and packaging– Being part of IRT Nanoelec offer access to all these capabilities
PLeclaire, D43D workshop , July 20182
© Mentor Graphics Corp. Company Confidential
Outcomes , Phases 1&2
PLeclaire, D43D workshop , July 20183
3D-IC program Si Photonics program
Phase 1 Successful introduction and tool maturing of Calibre 3Dstack , Tessent
• Demonstrate Calibre DRC/LVS capabilities • Brought high visibility of Mentor R&D
Phase 2 • Calibre 3Dstack : 3D sign-off verification tool in use
• Successful new Calibre flow exploration (thermal analysis prototype)
• Demonstrate DFT design flow capabilities in a 3D environment
• Calibre DRC flow compliant with SiPhotonic constraints
• Calibre SmartFill successfully introduced
… Phase 3 on going
3D Architecture
- 3D partitioning & co-design
- 3D Thermal & Power Profile
3D Architecture
- 3D partitioning & co-design
- 3D Thermal & Power Profile
3D Physical
Implementation - 2D Synthesis
- 3D Floorplanning
- 2D Place & Route
- 3D DFT & ATPG
3D Physical
Implementation - 2D Synthesis
- 3D Floorplanning
- 2D Place & Route
- 3D DFT & ATPG
3D Sign-Off- 3D thermal validation
- 3D IR-Drop analysis
- 3D parasitic extraction/TA
- 3D DRC & LVS verif
3D Sign-Off- 3D thermal validation
- 3D IR-Drop analysis
- 3D parasitic extraction/TA
- 3D DRC & LVS verif
Sta
nd
ard
iza
tio
n E
ffo
rts
INTACT
Active Interposer
Manycore
2017
96 cores (32bit MIPS)
cache-coherent memory
FDSOI 28nm + CMOS 65nm
µbump 20µm pitch
3DNOC
Logic-on-Logic
2015
Async robust links
DFT & Fault Tol.
CMOS 65nm
µbump 40µm pitch
Sucessfully applied
on IRT3D Demonstrators
3D Current Reference Design Flow
4
Used for standard 3D technologies,
For coarse grain partitionning
(TSV, µ-bumps , up to ~ 10 µm pitch)
Courtesy of Pascal Vivet CEA/Leti
© Mentor Graphics Corp. Company Confidential
Calibre 3DSTACK2.5D/3D Package/Interposer sign-off and verification
� Foundry supplied – rule deck— Package/Interposer layers
– Layer Numbers
– Connectivity Stack
— Connectivity Checks
— Geometric Checks
� Designer supplied— Stacking Configuration
– Die placement locations
– Rotations, magnifications, …
— Die Definitions– Interfaces only (pins)
GDSIILEF/DEF
GDSIIODB++
Design SpecificFoundry / OSAT
Supplied
PLeclaire, D43D workshop , July 20185
© Mentor Graphics Corp. Company Confidential
CAD perspective , Disrupting Ecosystem
PLeclaire, D43D workshop , July 20186
• Gerber output
• Windows based tools
• Design drives manufacturing
• Non-Manhattan shapes
• Organic RDL layers
• Built-in DRC checks performed
within design database
• GDSII output
• Linux based tools
• Manufacturing drives design (PDKs)
• Manhattan based shapes
• Silicon RDL layers
• Separate verification (DRC)
performed on mfg. output
Impact• Developing ADK/PDKs
and reference flows• Adopting verification tools
Impact• Driving PDK/ADK methodology• Assembly level verification• Adopting “packaging” tools
© Mentor Graphics Corp. Company Confidential
Heterogeneous planning and prototypingInterdependences and impact
PLeclaire, D43D workshop , July 20187
© Mentor Graphics Corp. Company Confidential
� TSV/Bumps (“3D devices”) — Interactions between the 3D devices— Interaction between 3D devices & interconnect
� Stress — Impact of TSVs, substrate on device performance — Strain-induced variations: 3D stacking effects
� Thermal— 2.5D/3D-IC interactions
PLeclaire, D43D workshop , July 20188
Challenges in 3D Pex , Stress , Thermal Modeling
© Mentor Graphics Corp. Company Confidential
Key Transformation Focus areas for HDAP
Multi-substrate/devices architectures• Connectivity/interface planning across substrate boundaries
• 2.5D/3D stacking, device transforms and scaling
• Management of heterogeneous data and formats
Manufacturing focused implementation• Database capacity and tool performance
• Robust, in-tool shape processing (areafill and planes)
• Accuracy and quality of GDS output
Validation and Verification • LVS/LVL of final 2.5D/3D assembly and individual substrates
• Multi-substrate electrical extraction and analysis
• Electrical modeling
PLeclaire, D43D workshop , July 20189
© Mentor Graphics Corp. Company Confidential
Mentor design flow foundation for HDAP
OSAT Alliance ProgramPDK/ADK enablement
PLeclaire, D43D workshop , July 201810
© Mentor Graphics Corp. Company Confidential
… Applied to TSMC/Mentor InFO FlowCertified solutions for InFO_S and InFO_PoP
Windows platform supportNot intended for sign-off
InFOHL DRC rule deck
HL DRCIn-process DRC
GDSII
Source Netlist (LVS)
Xpedition Packaging
Substrate Integrator
Connectivity planning &
optimization, and library generation
PackageDesigner
Constraints, routing, and
plane generation
Calibre 3D-StackSign-off verification
CalibreResults
TSMCInFO
rule deck
MentorXpedition
InFOrule deck
Sourcesubstrate data
(AIF, LEF/DEF,
GDSII etc.)
PLeclaire, D43D workshop , July 201811
© Mentor Graphics Corp. Company Confidential
Key Transformation Focus areas for HDAP
Multi-substrate/devices architectures• Connectivity/interface planning across substrate boundaries
• 2.5D/3D stacking, device transforms and scaling
• Management of heterogeneous data and formats
Manufacturing focused implementation• Database capacity and tool performance
• Robust, in-tool shape processing (areafill and planes)
• Accuracy and quality of GDS output
Validation and Verification • LVS/LVL of final 2.5D/3D assembly and individual substrates
• Multi-substrate electrical extraction and analysis
• Electrical modeling
PLeclaire, D43D workshop , July 201812
© Mentor Graphics Corp. Company Confidential
Planning and prototyping platformto facilitate heterogeneous integration
13
xDX Designer
PCB Schematic
AIF/CSV
Package ball pad geometry
and net assignments
Footprint
Logic
XpeditionPackage Designer
Package layout
Package Data
Key PCB componentsand routes
Xpedition PCB
PCB layout
Optional data source
and pathway
Xpedition ® Substrate Integrator
Multi-substrate prototyping, connectivity planning and
optimization
PCB Design TeamIC/Architect TeamPackage Design Team
PLeclaire, D43D workshop , July 2018
© Mentor Graphics Corp. Company Confidential
Calibre 3DSTACK & Xpedition Substrate Integrator Package assembly sign-off and verification flow
Source SystemNet list
Assembly Description
Files
Xpedition® Substrate Integrator
Heterogeneous system assembly and visualization
Import source design content to define system assembly and automatically
generate decks to run Calibre 3DSTACK
IndividualDie Data
Interposer Data
PackageData
DRC/LVS of completepackage assembly
Calibre® 3DSTACK
Final assembly sign-offand verification
PLeclaire, D43D workshop , July 201814
© Mentor Graphics Corp. Company Confidential
HDAP design and verification flow
Xpedition Package Designer (XPD)
Calibre3DSTACK
die.txtbga.txt
GDSODB++
NativeintegrationXpedition Substrate
Integrator (XSI)
Golden system net listAssembly description
GDS
TXT/CSVAIF
LEF/DEFGDSKYN
LEF/DEF(TXT/CSV)
Pass/Fail
CadenceInnovus/Encounter
Virtuoso
SynopsysICC/ICC2
Laker
MentorL-Edit
CadenceAPD/SIP
PLeclaire, D43D workshop , July 201815
© Mentor Graphics Corp. Company Confidential
Xpedition Substrate IntegratorGraphical connectivity management and system assembly
� Import source content to define intelligent system assembly— Aggregates heterogeneous data
into cohesive system assembly
� System connectivity visualization and reporting— Ability to trace connectivity through
system assembly
— LVS, STA net list generation
� Automatically generate files necessary to run Calibre 3DSATCK— Graphical setup
— Augments missing GDS data with virtual device, i.e. package
� Scales with design complexity
System assembly and connectivity visualization
PLeclaire, D43D workshop , July 201816
© Mentor Graphics Corp. Company Confidential
Xpedition Substrate IntegratorCalibre 3DSTACK Automation
� Property Manager
— Import/management functions for each device
� C3DS XPD Deck / (GUI) Deck
— Create system net list using input fromXPD or external tool like APD
� C3DS Part / Stack Wizard
— Define/manage layer and device stack-up
� C3DS Check Wizard
— Define/manage LVS checks to perform
� STA Utilities
— Verilog net list options
3DSTACK automation menu
PLeclaire, D43D workshop , July 201817
© Mentor Graphics Corp. Company Confidential
Key Transformation Focus areas for HDAP
Multi-substrate/devices architectures• Connectivity/interface planning across substrate boundaries
• 2.5D/3D stacking, device transforms and scaling
• Management of heterogeneous data and formats
Manufacturing focused implementation• Database capacity and tool performance
• Robust, in-tool shape processing (areafill and planes)
• Accuracy and quality of GDS output
Validation and Verification • LVS/LVL of final 2.5D/3D assembly and individual substrates
• Multi-substrate electrical extraction and analysis
• Electrical modeling
PLeclaire, D43D workshop , July 201818
© Mentor Graphics Corp. Company Confidential
Assembly Parasitic extraction
19
� Verify micro-bumps physical alignment
� Verify proper electrical connectivity
� Generate system level netlist
Parasitic Extraction
� Extract parasitics of the dies (front and back side metal stacks)
� Extract the die interfaces/interactions (F2F, F2B)
� Insert provided TSV circuit into integrated parasitics/TSV netlists, or
� Extract Interposer TSV to TSV couplings
PLeclaire, D43D workshop , July 2018
© Mentor Graphics Corp. Company Confidential
Electrical modeling and analysis of the entire systemHyperLynx Advanced Solvers
� Full-wave solver HPC— Full-wave 3D EM analysis env.
— Die-package-board analysis
— Superior speed and accuracy
— S, Y, Z parameters & EMI/EMC plots
� Fast 3D Solver — Quasi-static full package extraction
— SPICE, IBIS and RLCG matrices
� Hybrid solver— Power-aware SI analysis
— DC voltage drop and current density
— AC decoupling analysis
— Return path analysis
Fully integrated with Xpedition Package Designer
PLeclaire, D43D workshop , July 201820
© Mentor Graphics Corp. Company Confidential
Thermal Analysis:Calibre Project Sahara
Static and Transient Thermal Simulations
3D Geometry Specification Project Sahara
Die-level Power Maps
Thermal Results Database
Thermal Waveforms
Thermal Violations
Detailed & Summary reports
Die layouts
Thermal Constraints
Gate-level / Device-level
Power Analysis
IPF parser
Thermal Maps
Package model & air flow conditions
Boundary Conditions
Optional for higher accuracy
3D IC/package Assembly View
21
SPICE Back-annotation
Thermal Material Properties
PLeclaire, D43D workshop , July 2018
© Mentor Graphics Corp. Company Confidential
Stress Analysis:Calibre Project Glacier
22
� Analyze layout for CPI stresses and impact on device performance— Combines Calibre layout processing with proprietary modeling— MOSFET channel mechanical stress— Stress-induced variation of transistor electrical parameters, such as
mobility and current
� Invocation and result visualization in familiar environments
PLeclaire, D43D workshop , July 2018
© Mentor Graphics Corp. Company Confidential
Key Transformation Focus areas for HDAP
Multi-substrate/devices architectures• Connectivity/interface planning across substrate boundaries
• 2.5D/3D stacking, device transforms and scaling
• Management of heterogeneous data and formats
Manufacturing focused implementation• Database capacity and tool performance
• Robust, in-tool shape processing (areafill and planes)
• Accuracy and quality of GDS output
Validation and Verification • LVS/LVL of final 2.5D/3D assembly and individual substrates
• Multi-substrate electrical extraction and analysis
• Electrical modeling
PLeclaire, D43D workshop , July 201823
© Mentor Graphics Corp. Company Confidential
Legacy packaging tools struggle
• GDS edits never back-annotate to layout database• Layout database out of sync with outputs
• What about ECOs or SI/PI analysis?
Yes
No
Addition orsubstitution of
unique geometries• Mesh pads
• Graduate voids
Sign-off &Verification
Tool
Package Physical
Layout Tool
GDS EditingTool
GDS
GDS
Clean GDS
Done
Missing pathwayfor back-annotation
1 2
Mystery spike(short) Short
Acute errors
3
All passed native DRC
Caught by Calibre!
4
PLeclaire, D43D workshop , July 201824
© Mentor Graphics Corp. Company Confidential
Dynamic cross-probing with CalibreXpedition Package Designer
� Fastest path to design signoff
� Quickly identify & resolve issues
� Ensure layout database matches manufacturing outputs
� Works across Windows/Linux
Direct integration between xPD and Calibre
PLeclaire, D43D workshop , July 201825
© Mentor Graphics Corp. Company Confidential
Mentor Comprehensive solution
with industry leading products
High Density Advanced Packaging (HDAP)
Heterogeneous multi-substrate connectivity authoring,
prototyping and optimization
Providing productivity and interoperability across IC,
interposer, package, and PCB
FOWLP, 2.5D/3D, SiP, and high performance flip-chip
Providing design efficiency, capacity, and accuracy with predictable manufacturing
Comprehensive verification, sign-off, and analysis
Ensuring physical, logical, electrical, and thermal
compliance
OSAT Alliance - Enabling the design and supply chain
Calibre FloThermHyperLynxXpedition
PLeclaire, D43D workshop , July 201826
Tessent
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