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LOW POWERVLSI
UNIT-1
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PRINCIPLES OF LOW- POWER
DESIGN
The main key principles of low-power design
are
Using the lowest possible supply voltage,
Operating at lowest possible frequency,
Using parallelism and pipelining to lower
required possible frequency,
Power management when the system is idle,
Designing systems to have lowestrequirements on subsystem performance.
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HIERARCHY OF LIMITS
Hierarchy of limits have five levels:
Fundamental
material
device
circuit
system
Each level has two types of limits:
Theoretical considerations
Practical considerations
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THEORETICAL LIMITS
The basis for practical limits are:
- Theoretical limits are constrained by the laws
of physicsand technological invention
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PRACTICAL LIMITS
The basis for practical limits are: The cost of designing, manufacturing,
testing andpackaging.
These will cause the cost per function tolevel off and begin to increase.
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FUNDAMENTAL LIMITS
Independent of devices, materials and
Circuits.
Fundamental limits are derived from three
basic principles:
Thermodynamics,
Quantum Mechanics and
Electromagnetic Theory
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THERMODYNAMICSAt any node the average signal power Psshould exceedthe available noise powerPavail.
QUANTUM MECHANICS Derived from Heisenberg uncertainty
principle.
To measure the effect of a switchingtransition of duration t, it must involve an
energy greater than h/ t.P h /
where h is the Plancks constant.
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MATERIAL LIMITS
They are Independent of the particular devices built
with the materials and
The circuits composed from these devices.
The attributesof material limits are carrier
mobility, carrier saturation velocity, electricfield strength andthermal conductivity.
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TWO LEVELS OF LIMITS
Consider a cube of undoped material of
dimension x, imbedded in a three-
dimensional matrix of similar cubes.
The first limit is on switching energy and
timecan be calculated as the amount of
electrostatic energy stored in the cube.
The second limit arises from heat removal
considerations.
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DEVICE LIMITS These are independent of the circuits that may have
been composed with the devices.
Consider the MOSFET, in which its important
attributeis its minimum effective channel length
Lmin.
To achieve Lmin, both the gate oxide thickness Tox
and source-drain junction depth Xjshould be small.
Also consider the thickness of the oxide layer and itspermittivity for short channel effects.
For the device limits the switching energy is
considered.
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CIRCUIT LIMITS These are independent of the architecture of
a particular system.
Here CMOS circuits are considered fordiscussing the circuit limits.
Four Basic Principal circuit level limits: Basic requirement is the zero error.
Switching energy per transition.
Intrinsic gate delaygiven by the time taken
to charge/discharge the load capacitance. Global interconnectrepresented as a
distributed R-C network.
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SYSTEM LIMITS
These depends on all other limits and are
more restrictive ones in the hierarchy.
Five generic system limits:
Architecture of the chip, Power-delay product of the CMOS
technology,
Heat removal capacity of the chip package, Clock frequency and
Physical size
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End
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