© 2005 JW Ryder
CSCI 232 Computer Architecture
1
Half Adders
Half adders add 2 binary digits Full adders add 2 binary digits plus a previous
carry bit They are combinational c ircuits 2 half adders needed to make a full adder Input variables are augend and addend Output variables are the Sum and Carry See figure 232ppt05.1 Below is half adder truth table
x y C S0 0 0 00 1 0 11 0 0 11 1 1 0
S = x'y + xy' = x y
C = xy
© 2005 JW Ryder
CSCI 232 Computer Architecture
2
x
yS
C
S = x’y + xy’ = x y
C = xy
Half Adder
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CSCI 232 Computer Architecture
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Full Adders
Sum of 3 input bits x, y are 2 bits to be added, z is the previous
carry bit from the next lower order digit
x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
C = xy + (x'y + xy')z
S = x y z
S is an 'odd' function - When an odd number ofinputs are 1, the output is 1 so an XOR of thevariables can be used to represent the function.
© 2005 JW Ryder
CSCI 232 Computer Architecture
4
x
y
z
S
C
S = x y z
C = xy + (x y) z
x
y
z
S
CFA
Full Adder
© 2005 JW Ryder
CSCI 232 Computer Architecture
5
Digital Components
Integrated Circuits
Digital c ircuits constructed with integratedcircuits
IC = small silicon semiconductor crystal,called a chip containing electroniccomponents form digital gates
Gates interconnected inside chip to formcircuit
Chip mounted on ceramic or plastic container Connections welded by this gold wires to
external pins to form IC
A few internal gates to thousands
Small Scale Integration (SSI) - severalindependent gates
Medium Scale Integration (MSI) - 10 - 200gates; decoders, MUX, adders, regs
Large Scale Integration (LSI) - 200 - fewthousand; processors, memory chips,programmable modules
Very Large Scale Integration (VLSI) - severalthousands; large memory arrays and complexprocessors
© 2005 JW Ryder
CSCI 232 Computer Architecture
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Decoders
Combinational c ircuit that converts binary infofrom n bit inputs to 2n unique outputs
n to m line decoders (m <= 2n) n x m decoder same name See figure 2-1 on page 44
3 inputs - A0, A1, A2
8 outputs ==> 3 x 8 line decoder Enable lines
See figure 2-2 and table 2-1 on page 45 truth table for 3 x 8 D only marked once NAND gate decoder - all in reverse
Decoder expansion See figure 2-3 on page 46 Two 2 x 4 decoders make one 3 x 8 line
decoder 2 LSb of input connected to both decoders MSb of input acts as input to E
Inverter on other Enabled when E=1 Disabled all outputs 0
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CSCI 232 Computer Architecture
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Encoders
Digital c ircuit that performs the inverseoperation of the decoder
Has 2n (or less) input lines and n output lines
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CSCI 232 Computer Architecture
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Flip-Flops
Only considered digital c ircuits which havebeen combinational so far
Outputs have been entirely dependent on theinputs that are present at the time
Most systems also have storage elementswhich require that the system be described(the behavior) in terms of sequential c ircuits
Synchronous sequential c ircuits affect storageelements only at discrete instances in time
Synchronization, timing pulse generator, c lockpulses
Clock pulses distributed such that storageelements affected only with arrival of c lockpulse
Synchronous c locks most frequent and easy tocontrol
Storage elements employed in c lockedsequential c ircuits are called flip-flops
Binary cell capable of storing 1 bit ofinformation
2 outputs, one for normal value, one forcomplement
Flip-flop maintains a state until directed tochange by a c lock pulse
© 2005 JW Ryder
CSCI 232 Computer Architecture
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SR Flip-Flop
3 inputs, S (set), R (reset), C (c lock) 1 output Q (sometimes a complement output
Q') small c irc le at other output terminal Arrowhead shape symbol in front of C to
designate dynamic input Denotes fact that FF responds to a positive
transition (0 -> 1) of input c lock signal
Operation
If no signal at c lock input C, output of c ircuitcan't change without regard to the values onthe S or R lines
Change can only occur in output when c locksignal changes from 0 -> 1 (rising edgetriggered FF)
S R Q(t + 1)0 0 Q(t) No Change0 1 0 Clear to 01 0 1 Set to 11 1 ? Indeterminate
Characteristic Table for SR Flip-Flop
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CSCI 232 Computer Architecture
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S
C
R
Q
SR Flip-Flop
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CSCI 232 Computer Architecture
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Summary of SR Flip-Flop
Q(t) is binary state of output Q at a given time(present state)
Q(t + 1) is binary state of Q output after aclock transition (next state)
"If S and R are both 0 during a c lock transitionthen the c lock transition produces no changeof state" [Q(t) = Q(t + 1)]
Clock should not be pulsed when S=R=1 Causes an indeterminate state for SR-FF,
difficult to manage, therefore seldom used!
© 2005 JW Ryder
CSCI 232 Computer Architecture
12
D Flip-Flop
Data FF, slight modification of SR-FF Convert an SR to a D by inserting an inverter
between S and R and assigning the symbol Dto the single input
Sampled during c lock transition from 0 -> 1 If D = 1 then output of FF goes to 1 but if D = 0
then the output is 0 state Characteristic table shows the next state [Q(t
+ 1)] determined from the D input [Q(t + 1) = D] Q receives value from D each time c lock
transitions from 0 -> 1 No input condition exists that will leave state
of D unchanged Advantage of D - only 1 input Disadvantage - characteristic table has no
values to keep output state Q(t + 1) unchanged Can be accomplished by
disabling c lock feeding output back into D input
D Q(t + 1)0 0 Clear to 01 1 Set to 1
Characteristic Table for T Flip-Flop
© 2005 JW Ryder
CSCI 232 Computer Architecture
13
D
C
Q
D Flip-Flop
© 2005 JW Ryder
CSCI 232 Computer Architecture
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J K Flip-Flops
Refinement of SR flip-flop Indeterminate condition of SR is defined in J K -
FF J like S, K like R J =K =1, a c lock transition switches outputs of
the FF to their complement state Q(t + 1) = Q'(t) when J =K =1
J K Q(t + 1)0 0 Q(t) No Change0 1 0 Clear to 01 0 1 Set to 11 1 Q'(t) Complement
Characteristic Table for J K Flip-Flop
© 2005 JW Ryder
CSCI 232 Computer Architecture
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J
C
K
Q
JK Flip-Flop
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CSCI 232 Computer Architecture
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T Flip-Flop
Created from J K -FF when J K inputs connectedto provide a single input T
T=0 (J =K =0), c lock transition does not changestate
T=1 (J =K =1), c lock transition toggles state ofFF (complements it)
Q(T + 1) = Q(t) T when T=1
T Q(t + 1)0 Q(t) No change1 Q'(t) Complement
Characteristic Table for T Flip-Flop
© 2005 JW Ryder
CSCI 232 Computer Architecture
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T
C
Q
T Flip-Flop
© 2005 JW Ryder
CSCI 232 Computer Architecture
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Edge Triggered Flip-Flops
Most common type of mechanism used tosynchronize triggering of state changes duringa c lock transition
Output transitions occurs either during therising edge or the falling edge of the c locktransition
Rising = positive edge transition; Falling =negative edge transition
Rising edge triggered flip-flops more common See figure 232ppt05.7
Excitation Tables
Characteristic tables specify next state whenpresent state and inputs are known
During sequential c ircuit design we usuallyknow what behavior we want to see from theoutputs of the FFs
We need to find FF conditions which match thebehavior we want to see
Need a table which defines required inputcombinations for a given change of state
Flip-Flop Excitation Tables
© 2005 JW Ryder
CSCI 232 Computer Architecture
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D Q
C
Output cannot change
Positive clock transition
Clock Time
232ppt05.7
D Q
C
Output cannot change
Negative clock transition
TimeClock
© 2005 JW Ryder
CSCI 232 Computer Architecture
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Four Excitation Tables
SR Flip-flop
Q(t) Q(t + 1) S R
0 0 0 x
0 1 1 01 0 0 11 1 x 0
J K Flip-flop
Q(t) Q(t + 1) J K
0 0 0 x0 1 1 x1 0 x 11 1 x 0
D Flip-flop
Q(t) Q(t + 1) D
0 0 00 1 11 0 01 1 1
© 2005 JW Ryder
CSCI 232 Computer Architecture
21
T Flip-flop
Q(t) Q(t + 1) D
0 0 0
0 1 11 0 11 1 0
x = don't care SR - to make the next state be a 0 when the
present state is a 0 we're gonna have to get a0 value to S and we don't give a hoot about theR value!
More examples with each excitation table
© 2005 JW Ryder
CSCI 232 Computer Architecture
22
Sequential Circuits
A interconnection of FFs and gates Gates = combinational c ircuit See figure 232ppt05.8
Flip-flop Equations DA = Ax + Bx DB = A'x y = Ax' + Bx'
See figure 232ppt05.9
State Table
Behavior of sequential c ircuit determined byinputs, outputs, and the state of its FFs
Outputs and next state are fns of inputs andpresent state
Sequential c ircuit specified by a state table 4 sections - Present state, Input, Next state,
Output Next is 1 c lock period later Output gives values of y at each present state
and input condition
© 2005 JW Ryder
CSCI 232 Computer Architecture
23
Combinational circuit
Flip-flopsClock
Outputs
232ppt05.8
Clocked Synchronous Sequential Circuit
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CSCI 232 Computer Architecture
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D Q
C
D Q
C
x
Clock
232ppt05.09
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CSCI 232 Computer Architecture
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State Table Creation
List all possible combinations of present stateand input
Next state values determined from logicdiagram or input equations
Next value of each D-FF = the D input to thepresent state
Next state of A will = 1 when either Ax or Bx =1
Present State Input Next StateOutput
A B x A B y0 0 0 0 0 00 0 1 0 1 00 1 0 0 0 10 1 1 1 1 01 0 0 0 0 11 0 1 1 0 01 1 0 0 0 11 1 1 1 0 0
State Table for Sequential Circuit
© 2005 JW Ryder
CSCI 232 Computer Architecture
26
State Diagram
State represented by a c irc le Transition between states is represented by
arcs connecting states State diagram provides same info as the state
table and is derived from the state table Binary number inside c irc le is the AB pair
present state Arcs labeled with two numbers separated by a
slash First number is input value during present
state Second number is output during the present
state Arc from 00 -> 01 is labeled 1/0 Explain and
examples See figure 232ppt05.10
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CSCI 232 Computer Architecture
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00
01 11
10
0/11/0
0/1
0/1
1/0
1/0
1/00/0
232ppt05.10
© 2005 JW Ryder
CSCI 232 Computer Architecture
28
Sequential Circuit Design Example
Problem: Design a c locked sequential c ircuitthat goes through a sequence of repeated binarystates 00, 01, 10, 11 when an external input x isequal to 1.
x = 0 ? --> State of c ircuit remains unchanged 2-bit binary counter Input x is the control variable that specifies
when the count should proceed Use 2 J K flip-flops
Design Procedure
1. Draw state diagram2. Transform the state diagram into a state table3. Extend the state table by adding an excitation
table to it4. By use of the excitation table, transform the
state table into a truth table.5. Extract the flip-flop input equations from the
excitation table6. Simplify all input equations7. Using the simplified flip-flop input equations
and the input to the combinational c ircuit,draw the logic diagram for the 2-bit binarycounter
© 2005 JW Ryder
CSCI 232 Computer Architecture
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Excitation Table for Binary Counter
PresentState Input Next State Flip-Flop Inputs
A B x A B J A K A J B K B
0 0 0 0 0 0 x 0 x0 0 1 0 1 0 x 1 x0 1 0 0 1 0 x x 00 1 1 1 0 1 x x 11 0 0 1 0 x 0 0 x1 0 1 1 1 x 0 1 x1 1 0 1 1 x 0 x 01 1 1 0 0 x 1 x 1
Recall the block diagram showing thecombinational logic and the flip-flops -232ppt05.8
232ppt05.8
© 2005 JW Ryder
CSCI 232 Computer Architecture
30
K -MapsSomehow they just won't disappear ...
A \ Bx 00 01 11 100 11 x x x x
J A = Bx
A \ Bx 00 01 11 10
0 x x x x1 1
K A = Bx
A \ Bx 00 01 11 100 1 x x1 1 x x
J B = x
A \ Bx 00 01 11 100 x x 11 x x 1
K B = x
See page 35 of textbook for logic diagram
© 2005 JW Ryder
CSCI 232 Computer Architecture
31
Multiplexers
Combinational c ircuit that receives binaryinformation from one of 2n input data lines anddirects it to a single output line (many to one)
Selection of a particular input data line is donevia selection lines
A 2n to 1 multiplexer has n selection line and2n input lines and 1 output line
Show 4 to 1 multiplexer in figure 2-4 on page48 Show how a line is selected Show function table 2-3 on page 49 (4 inputs + 2 selects = 26)
AND gates and inverters in the multiplexerresemble decoder c ircuit
In general, a 2n-to-1 line multiplexer can bebuilt from an n-to-2n decoder by adding to it 2n input lines ORing 2n outputs to create a single output Show conversion of 3 x 8 decoder to a 8-to-1
multiplexer
Show quadruple 2-to-1 multiplexer in figure 2-5on page 50 S = 0 then A enabled else B enabled Ouptut Y 0 can come from A0 or B0
© 2005 JW Ryder
CSCI 232 Computer Architecture
32
Registers
Group of FFs, each of which stores 1 bit of data
Register consists of FFs and gates that controltheir transition
Simplest - only FFs See figure 2-6 on page 51
common c lock 4 inputs enter FFs at c lock transition Outputs can be sampled any time Clear = 0 ? ==> All FFs reset simultaneously
out of c lock sync Transfer of info into FF called loading If all bits loaded at same c lock transition
then loading done in parallel See figure 2-7 on page 52
Master c lock Separate control to signal when c lock
transition should be obeyed Load control input directed through gates
into D inputs C receives c lock pulses all the time Load = 1, all I0 -> I3 go in; load = 0 output
from D passed back into input of D
© 2005 JW Ryder
CSCI 232 Computer Architecture
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Shift Registers
Register capable of shifting its binary info inone or both directions
FFs in cascade, Serial input in and Q goes tonext input
Draw 4-bit simple shift register (53) Most general shift register contains
Input c lock Shift right operation Shift left operation parallel load operation Control state leaving register data
unchanged See figure 2-9 on page 55 Bidi shift reg c/ ||
load Each stage is 4 x 1 MUX and D-FF 2 selection inputs select one of the 4 data
inputs for the D-FF SS=00, no change; SS=01, shft-rt; SS=10,
shft=lf; SS=11, || load
© 2005 JW Ryder
CSCI 232 Computer Architecture
34
Binary Counters
Note pattern of when bits change low order bit is complemented after every
count every other bit is complemented from one
count to the next if all its lower order bitsare 1 0111 to 1000
complement low order bit complement 2nd order bit because first
bit of 0111 is a 1 complement the 3rd order bit because
the first 2 bits of 0111 are 1s complement the 4th order bit because
the first 3 bits of 0111 are 1s
Show figure 2-10 on page 57Do first few numbers
Binary counter with a parallel loader
See figure 2-11 on page 59
Clear=1 set all K to 1 causing a c lear of all FFs Load=1 disables count operation and allows
data to move from Ix into FFs (providingClear=0)
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