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Reliability assessment for new materials: Generation and activation of electrical defects in high-k gate stacks
Reliability assessment for new materials: Generation and activation of electrical defects in high-k gate stacks
Gennadi Bersuker
Dielectric degradation: multilayer gate stack
- Defect location: in high-k or IL?
- Defect origin: intrinsic or
process-related?
- Defect generation mechanism:
stress condition-dependent or
‘universal’?
• Defects in interfacial SiO2
Process-related High-k-induced: O-vacancies & Hf impurities
• Defects in high-k As-grown: O-vacanciesStress generated – at high stress biasesPolarons
• CharacterizationCombining electrical and physical
techniques, and modeling
SILC evolution for monitoring breakdown
100 101 102 103 10410-8
10-7
10-6
TiN/3nm HfO2/2.1 nm IL
9.4 9.6 9.8 10.0 10.210
20
30
40
50
60
70
80
90
100
Gat
e C
urre
nt [n
A]
Time [103 sec]
Gat
e C
urre
nt [A
]
Time [sec]
65 nA
500 nASBD
nFET 1x10-8 cm2
CVS 4.6 V
TiN/ 3nm HfO2/2.1nm SiO2
CVS 4.6V
0.0 0.5 1.0 1.5 2.010-15
10-13
10-11
10-9
10-7
10-5
10-3
10-1
101
500 A
1 mA
10 mA
I g[A
]Gate Voltage [V]
TiN/3nm HfO2/ 2.1 nm IL
nMOSFET 1x10-8 cm2
65 nA
100nA; 500 nA1 A; 100 A
0.0 0.5 1.0 1.5 2.010-15
10-13
10-11
10-9
10-7
10-5
10-3
10-1
101
0.0 0.5 1.0 1.5 2.010-15
10-13
10-11
10-9
10-7
10-5
10-3
10-1
101
500 A
1 mA
10 mA
I g[A
]Gate Voltage [V]
TiN/3nm HfO2/ 2.1 nm IL
nMOSFET 1x10-8 cm2
65 nA
100nA; 500 nA1 A; 100 A
Stress-induced leakage current reflects on the formation of percolation path
G.B., IRPS 2007
Probing SiO2 traps
1.E-01
1.E+00
1.E+01
1.E+02
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Stress time (sec)
DN
it /
Nit
0 @
CP
frq
. 1
KH
z
7nm/1nm;4.6V5nm/1nm;4.2V3nm/1nm;4.1V
TiN/HfO2/IL/p-Si
nMOSFET W/L = 1 / 0.2 m
A: 2x10-8 cm2
tH-K / tIL ; Vstress
t1.0
0.5
0.9
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Stress time (sec)
DJ
g/J
g0
@ V
g =
2V
7nm / 1nm; 4.6V5 nm / 1nm 4.2V3nm / 1nm; 4.1V
0.4
1.0
t0.9
TiN/HfO2/IL/p-Si
nMOSFET W/L = 1 / 0.2 m
A: 2x10-8 cm2
tH-K / tIL ; Vstress
SILC Charge Pumping
Since CP probes IL, similar CP and SILC growth rates for each dielectric stack points to the same contributing defects in IL
Effect of stress voltage on reliability assessments
0
2
4
6
8
10
12
14
16
18
0 1 2 3 4
Stress periods (sec)
Nit
grow
th r
ate
Rit
X10
10/c
m2
0
0.5
1
1.5
2
2.5
3
3.5
4
SIL
C g
row
th r
ate
RS
ILC0.67nm
0.84nm
1.0nm
Vg=0.6V
Vg=1.0V
1st 300s 2nd 300s 3rd 300s
Nit probing distance from Si:
SILC voltage:
0
2
4
6
8
10
12
14
16
18
0 1 2 3 4
Stress periods (sec)
Nit
grow
th r
ate
Rit
X10
10/c
m2
0
0.5
1
1.5
2
2.5
3
3.5
4
SIL
C g
row
th r
ate
RS
ILC0.67nm
0.84nm
1.0nm
Vg=0.6V
Vg=1.0V
1st 300s 2nd 300s 3rd 300s
Nit probing distance from Si:
SILC voltage:
1.1nm SiO2/ 3nm HfO2
Vstress = 2.4 V
0 100 200 300 400 500 600 7000
2
4
DNit
/Nit0
Stress time (s)
4KHz
1MHz
1.1nm SiO2/3nm HfO2
Vstress = 4.1 V
Low voltage High voltage
• Low voltage: activation of precursor defects in IL• High voltage: defect generation in IL
High-k–induced O vacancies in SiO2 IL: EELS
Higher O deficiency higher density of precursor defects (Si-Si) converted by stress into electron traps Si-
HfO2
SiO2
Si
Solid – as-depositedDashed – after 1000C anneal
100 110 120
5000
10000
15000
20000
25000
30000
35000
40000
Y A
xis
Title
Energy-loss [eV]
Si
Si/SiO2
SiO2
SiO2/HfO2
Si L2,3-edge EELS
G.B., JAP 2006
K. van Benthem, Pennycook
Metal/high-k-induced O defects in SiO2: ESR
Metal/high-k process significantly enhances E’
center density in interfacial SiO2 layer
J. Ryan et al., APL 2007
3nm HfO2/1nm SiO2/TiN+ 1000C PDA
3nm HfO2/1nm SiO2
3nm HfO2/1nm SiO2 +1000C PDA
3461 3463 3465 3467 3469
Magnetic Field (Gauss)
ES
R A
mp
litu
de
(Arb
. Un
its)
g = 2.0025
g = 2.0035
g = 2.0005
a
b
SiO2 (20Å) + HfO2 (30Å)/TiN + 1000ºC/10s
12
SiO2 (10Å) +HfO2 (30Å)/TiN + 1000ºC/10s
Metal/high-k-induced O defects in SiO2: ESR
High-k-induced (process-related) generation of E’ centers is much more effective in thinner SiO2 layers
J. Ryan et al.
Fast interface trap generation: DCIV
High-k devices show strong initial increase of both trapped charges and interface traps
SiO2
Neugroschel, IEDM 2006
0
1000
2000
3000
4000
5000
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
VG(V)
DI B
(pA
)
3 nm HfO2
EOT @ 1.2 nm
125 oC, VG = - 1.8 V
Eo @ 3.4 MV/cm
t = 10 s 5 s 2 s 1 s 0 s
High-k
DDit
DVt
DCIV measurements
3430 3440 3450 3460 3470 3480
Magnetic Field (G)
SDR
Inte
nsity
(Arb
. Uni
ts)
g = 2.0060 ± 0.0003
g = 2.0033 ± 0.0003
Possible E' Center
0
3
6
9
12
3360 3375 3390 3405 3420 3435Magnetic Field (G)
SDR
Ampl
itude
(Arb
Sca
le)
g = 1.9998
Magnetic Field (G) Magnetic Field (G)
Lenahan, IRW 2006
Hf defects in IL: spin dependent recombination
Fast transient defect generation might be
associated with Hf atoms in interfacial SiO2 layer
SiO2HfO2/SiO2
Fast degradation: Hf in SiO2 IL
S. Rashkeev, INFOS 2005Hf can diffuse through voids in SiO2
SiO2Si Amorphous layers
SiO2 HfO2Si
Hf
“Regular” structure
G.B., JAP 2006
Long-term instability: defects in SiO2
10
100
1000
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
Stress Time (s)
VTH
(m
V)
75 oC, VG = - 1.6 V
n @ 0.19
3.3 nm SiO2
75 oC, VG = - 4 V
HF-last + 3 nm HfO2
Filled: DVTH
Open: adjusted DVTH n @ 0.13
n @ 0.2
103
102
101
100 102 104 106 108 1.E+10
1.E+11
1000 10000 100000
Stress Time (s)D D
IT (1
/cm
2-e
V)
HF-last + 3 nm HfO2
28 oC, - 1.6 V
n @ 0.16
SiO2High-k DDIT - DDIT(1s)High-k
1011
1010
103 104 105
Similar degradation rates in high-k stack and control SiO2 same mechanism
Neugroschel, IEDM 2006
Threshold voltage Interface states
Defect generation in high-k film
Low Vg:mostly reversible
High Vg:w/ continues degradation
020406080
100120140160180200
-0.5 0.5 1.5 2.5 3.5 4.5 5.5Stress time x1000 (sec)
after discharge
020406080
100120140160180200
-0.5 0.5 1.5 2.5 3.5 4.5 5.5Stress time x1000 (sec)
after discharge20
60
100
140
180
0.5 1.5 2.5 3.5 4.5 5.5
Stress time x1000 (sec)
after discharge
DVt (
mV
)
1.1nm SiO2/ 3 nm HfO2
Vstress= 2.4 V
• Low stress voltage: reversible filling of pre-existing traps• High voltage: trap generation
0.1
1.0
101 102 103
Stress time (sec)D
Vt
(V)
after detrappingbefore detrapping
0.1
1.0
101 102 103
Stress time (sec)D
Vt
(V)
after detrappingbefore detrapping
1.1nm SiO2/3nm HfO2
Vstress = 5 V
Defect generation in high-k: pulse measurements
102 103
100
DVth
(m
V)
Stress Time (sec)
Breakdown
VSTRESS
= 3.5 V
T = 25 oCPulse time = 300 ns
0.0 0.5 1.0 1.5 2.0
Dra
in C
urr
en
t
Gate Voltage [V]
102 103
100
DVth
(m
V)
Stress Time (sec)
Breakdown
VSTRESS
= 3.5 V
T = 25 oCPulse time = 300 ns
0.0 0.5 1.0 1.5 2.0
Dra
in C
urr
en
t
Gate Voltage [V]
1.1nm SiO2/3nm HfO2
High-k
GateGate
0 500 1000 1500 20000.0
0.1
0.2
0.3
0.4
Def
ect g
ener
atio
n ra
te (m
V/s
)
Stress Time (s)
Defect generation at as-grown defect precursors
Trapping in amorphous high-k
J. Gavartin, ECS 2006
Injected electron can trap via self-localization (polaron formation) No defects needed to charge high-k film
Summary• Interfacial SiO2 layer:
- Low bias stress: trap generation at as-processed precursor defects (O vacancies/Hf atoms) induced by high-k dielectric
- High bias stress: new “conventional” defects • High-k film:
- Low bias stress: instability due to reversible electron trapping on as-processed defects (O-vacancies) or polaron formation(?)
- High bias stress: defect generation at as-processed precursors: Defect nature? Mechanism?
Specifics of metal electrode/high-k dielectric gate stacks
– Multi-layer dielectric stacksInterfacial SiO2, high-k dielectric, metal/high-k
interface– Ultra-short characteristic times
Transient charging/discharging (relaxation) effects– High density of pre-existing defects
O vacancies, under-coordinated metal and Si atoms
Question applicability of SiO2 test methodologies
New Materials Reliability Issues
• Reversible parameter instability – sensitive to measurement times; can be partially addressed by design
• Stress-dependent degradation mechanisms - test close to use conditions
• Strong process-dependent characteristics – reliability assessment requires extensive set of gate stacks of variety of compositions/processing
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