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Programmable LogicProgrammable Logic
The simplest programmable logic devicesare PALs (see 22V10 figure next page).
PLD my students use them in their firstyear at PSU Programmable Logic Devices
What is the next step in the evolution ofPLDs?
More gates!
How do we get more gates? We could putseveral PALs on one chip and put aninterconnection matrix between them!!
This is called a Complex PLD (CPLD).
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22V10 PLD
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Cypress CPLD
Each logic block is
similar to a 22V10.
Programmable
interconnect matrix.
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Any other approaches?Any other approaches?Another approach to building a better PLD is place a lot of
primitive gates on a die, and then place programmable interconnectbetween them:
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FPGA TechnologyFPGA Technology
1. Birds Eye View of FPGA Technology
2. FPGAs in 2004: Virtex-4 Introduction
3. Software and Design
4. Special Problems and Solutions
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Field Programmable Gate ArraysField Programmable Gate Arrays
The FPGA approach to arrange primitive logic elements (logic
cells) arrange in rows/columns with programmable routing between
them.
What constitutes aprimitive logic element? Lots of different
choices can be made! Primitive element must be classified as acomplete logic family.
A primitive gate like aNAND gate
A 2/1 mux (this happens to be a complete logic family)
A Lookup table (I.e, 16x1 lookup table can implement any
4 input logic function).
Often combine one of the above with a DFF to form the primitive
logic element.
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Other FPGA featuresOther FPGA featuresBesides primitive logic elements and
programmable routing, some FPGAfamilies add other features
Embedded memory
Many hardware applications need memory fordata storage. Many FPGAs include blocks ofRAM for this purpose
Dedicated logic forcarry generation, orotherarithmetic functions
Phase locked loops forclocksynchronization, division, multiplication.
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Altera Flex 10K FPGA Family
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Altera Flex 10K FPGA Family (cont)
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Dedicated memory
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16 x1 LUT
DFF
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Emedded Array BlockEmedded Array Block
Memory block, Can be configured:256 x 8, 512 x 4, 1024 x 2, 2048 x 1
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EPROM/EEPROM TechnologyEPROM/EEPROM Technology
EPROM can be reprogrammed, no need forexternal storage.
EPROM can notbe re-programmed in circuit.
EEPROM can be re-programmed in circuit.
EEPROM consumes 2X more area as EPROM.
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Erasable PLD (EPLD)Erasable PLD (EPLD)
Logic array Registers I/Os
Configured toD, T, JK, SR FFs.
Programmable clockto each FF.
SOP-based PAL In, Out, bidirection
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Programming the FPGAProgramming the FPGA
Configuration.
Readback - design verification anddebugging.
Security - a security-bit to preventreadback.
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AdvantagesAdvantages andandDisadvantagesDisadvantages of FPGAof FPGA
Fast turnaround.Low NRE (non-recurring engineering)
changes.Low risk.Effective design verification.
low testing cost.Chip size & cost.Slow speed.
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CPLD versus FPGACPLD versus FPGA
Interconnect style Continuous SegmentedArchitecture and timing Predictable Unpredictable
Software compile times Short Long
In-system performance Fast Moderate
Power consumption High ModerateApplications addressed Combinational and Registered
registered logic logic only
CPLD FPGA
Source: Altera
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FPGAsFPGAsWhat? - Programmable logic +programmable routing = FPGAs.
Why? - Zero NREs, easy bug fixes, andshort time-to-market.
How?
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Comparison of DifferentComparison of DifferentDesign TechnologiesDesign Technologies
Custom Std Cells Gate Arrays FPGAs
Design time Long Short Short Short
Fabrication Long Long Short None
Chip area Small Med. Large Very large
Design cost High Med. Low Very low
Unit cost Low Low Med. HighDesign cycle Long Med. Short Very short
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Emerging FPGA-basedEmerging FPGA-basedApplicationsApplications
Low-volume production.
Urgent time-to-market competition.
Rapid prototyping.Logic emulation.
Custom-computing hardware.
Reconfigurable computing.
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DesignDesign
ConsiderationsConsiderations
Target architecture.Fixed logic and routing resources.
Fixed I/O pins.
Slow signal delays.
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FPGA Selection CriteriaFPGA Selection Criteria
Density.
Speed.
Price.Flexibility.
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COSTS of TechnologiesCOSTS of Technologies
Lower CostMoores Law is alive
Smaller geometries and larger wafersand lower defect density (=higher yield )continue to achieve lower cost per function
LUT + flip-flop: $1.- in 1990, $ 0.002 in 2003
State-of-the-art: 90 nm on 300 mm wafers
Spartan-3 uses this technology for lowest cost
Rapid price reductions, intense
competition
Ch i t f FPGA d
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Changing costs of FPGAs and
technologies
More Logic and Better Features:>100,000 LUTs & flip-flops
>200 BlockRAMs, and the same number of 18 x 18multipliers
1156 pins (balls) with > 800 GP I/O50 I/O standards, incl. LVDs with internal termination
16 low-skew global clock linesMultiple clock management circuits
On-chip microprocessor(s) and Gbps transceiversGate count is really a meaningless metric
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A Birds Eye View
Higher SpeedSmaller and faster transistors
90 nm technology, using 193 nm ultra-violet lightCu interconnect ( instead of Al ) was easily achieved
Low-K dielectric progress is disappointing
System speed: up to 500 MHz,Mainly through smart interconnects, clock management,
dedicated circuits, flexible I/O.Integrated transceivers running at 10
Gigabits/sec
-
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A Birds Eye ViewBetter tools
Back-End Place&Route and XST synthesisVHDL and Verilog becoming entry point
IP/Cores speed up design and verification
Embedded Software Development Toolssupport architectures and merge HW and
SW
Domain-Specific LanguagesSystem Generator bridges the gapbetween
Matlab/Simulink and FPGA circuitdescription
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ASICs Are Losing Ground
Mask set >$1M + design + verification + risk
ASICS are only for extreme designs::
Extreme volume, speed, size, low power
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
MaskCosts
(inmillion$)
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
MaskCosts
(inmillion$)
Source:IBM
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SPGASPGAAllow multiple building blocks.
Logic.
Memory.Data path.
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Applications Using SPGAsApplications Using SPGAs
Intellectual property (IP).
Communication & networking.
Graphical processing.Embedded processing.
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Designing with SPGAsDesigning with SPGAs
A team-based approach.
Understanding how to use SPGA system
features will be the key to pulling the entiredesign into a single device.
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CMOS PLD Market ShareCMOS PLD Market Share
Othe
Cpre
AT&TActel
Lattic
AMD
Alter
Xilinx
Source:dataquest
5% 3%
5%
6%
11%15%
24%
31%
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CMOS Logic MarketCMOS Logic Market
Std logic
ProgrammGA
Std cell
Custom
Chipset
Source:dataquest
10%
9%
29%
30%
8%14%
But the market
share is growing
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FPGAs GrowthFPGAs Growth
1996 1997 1998 1999 20000
500
1000
1500
2000
2500
1996 1997 1998 1999 2000
M US
Source: Integrated Circuit Engineering
Milions
USdollars
CMOS P bl l iCMOS P bl l i
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CMOS Programmable-logicCMOS Programmable-logicMarketMarket
1997 1998 1999 20000
1
2
3
4
5
1997 1998 1999 2000
B US
Source:dataquest
BillionsUS
dollars
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Rapid PrototypingRapid Prototyping
What?
Why?
How?
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What is prototyping?What is prototyping?
Basic components: FPGAs and FPICs.
Hardware : boards, boxes, and cabinets.
Software: methodologies and CAD tools.
Field ProgrammableGate Arrays
Field Programmable
Interconnect Devices
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Product Development CycleProduct Development Cycle
Market survey
Product developmentCustomeracceptance
Production
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Pressures on TodaysPressures on TodaysProduct DevelopmentProduct Development
Time-to-market!
Design complexity!
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Why Needs Prototyping?Why Needs Prototyping?
Design verification.
Limited production.
Concurrent engineering.
This requires cooperationof engineers, computer sciencespecialists and marketing
D i V ifi i
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Design VerificationDesign Verification
Specification
Final product
Functionality &requirements
Final functionality& performance
?
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Design ProcessDesign Process
Simulation
Formal verification
Logic emulation
Fast prototyping
Specification
System-level design
RTL design
Logic-level design
Physical-level design
Final chipsFormal verification is justFormal verification is just
one of optionsone of options
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Verification AlternativesVerification Alternatives
Event Driven Simulation High No Short SlowCycle-Based Simulation Med. No Short Med.
Behavioral Simulation Low No Short Med.
Hardware Accelerated Sim Varies No Med. Med. Fast
Breadboarding Med. Yes Long Very Fast
Emulation or Prototyping Med. Yes Med. Very Fast
Modelingaccuracy
Systemintegration
Preparetime Speed
A Mi i h if f
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A Minute in the Life of aA Minute in the Life of a100K Gates Design100K Gates Design
1 --------- Actual hardware at 50MHz
10 -------- Logic emulatoror prototype at 5MHz100-------
2K-------- HW acceleratorat 250M evals/sec
50K------- Cycle-based simulator at 1K insts/sec
120K----- Compiled-code logic simulator at 125MIPs
800K----- Event-driven logic simulatorat 125 MIPs
1 Mon.
3 Mon.
1.5 Yr.
One minute
tenminutes
We need FPGA emulation because simulation is too slow
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SW Design Code
Fab Debug
Build IntegrationDesign
Design
Debug
Integration Debug
Development with PrototypingDevelopment with Prototyping
HW
CHIP
Big gap
small
gap
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Development with PrototypingDevelopment with Prototyping
SW Design Code
FabChip debug
BuildHW Integration& Debug
Design
Design
FinalIntegrationHW
CHIP
System Integration& SW Debug
You speed up development through parallelism
How to Develop aHow to Develop a
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How to Develop aHow to Develop aPrototyping using FPDsPrototyping using FPDs
Custom-designed prototyping board.
Logic-emulation systems.
Field-programmable printed-circuit-boards.
Field ProgrammableDevices
FPGA St t f th A t 2004FPGA St t f th A t 2004
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FPGA State of the Art 2004FPGA State of the Art 2004
90-nanometermanufacturing technology
Ten Gigahertz serial I/O (SerDes) in silicon
0.07 femtosecondasynchronous data capture windowcauses 1.5 ns metastable delay
I i FPGAI i FPGA
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Issues in FPGAIssues in FPGA
TechnologiesTechnologies
Complexity of Logic Element
How many inputs/outputs for the logic element?
Does the basic logic element contain a FF? What type?
Interconnect
How fast is it? Does it offer high speed paths that cross thechip? How many of these?
Can I have on-chip tri-state busses?How routable is the design? If 95% of the logic elements areused, can I route the design?
More routing means more routability, but less room for
logic elements
I i FPGA T h l i ( t)I i FPGA T h l i ( t)
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Issues in FPGA Technologies (cont)Issues in FPGA Technologies (cont)
Macro elementsAre there SRAM blocks? Is the SRAM dual ported?
Is there fast adder support (i.e. fast carry chains?)
Is there fast logic support (i.e. cascade chains)
What other types of macro blocks are available (fastdecoders? register files? )
Clock support
How many global clocks can I have?Are there any on-chip Phase Logic Loops (PLLs) or DelayLocked Loops (DLLs) for clock synchronization, clockmultiplication?
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Issues in FPGA Technologies (cont)Issues in FPGA Technologies (cont)
What type of IO support do I have?
TTL, CMOS are a given
Support for mixed 5V, 3.3v IOs?
3.3 v internal, but 5V tolerant inputs?Support fornew low voltage signaling standards?
GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II
HSTL - High Speed Transceiver Logic
SSTL - Stub Series-Terminate LogicUSB - IO used for Universal Serial Bus (differential signaling)
AGP - IO used for Advanced Graphics Port
Maximum number of IO? Package types?
Ball Grid Array (BGA) for high density IO
Altera FPGA FamilyAltera FPGA Family
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Altera FPGA FamilyAltera FPGA Family
SummariesSummaries
Altera Flex10K/10KE
LEs (Logic elements) have 4-input LUTS (look-up tables)+1 FF
Fast Carry Chain between LEs, Cascade chain for logicoperations
Large blocks of SRAM available as well
Altera Max7000/Max7000A
EEPROM based, very fast (Tpd = 7.5 ns)Basically a PLD architecture with programmableinterconnect.
Max 7000A family is 3.3 v
Now we discuss some
popular families
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Xilinx FPGA Family SummariesXilinx FPGA Family Summaries
Virtex FamilySRAM Based
Largest device has 1M gates
Configurable Logic Blocks (CLBs) have two 4-input LUTS,
2 DFFsFour onboard Delay Locked Loops (DLLs) for clocksynchronization
Dedicated RAM blocks (LUTs can also function as RAM).
Fast Carry LogicXC4000 Family
Previous version of Virtex
No DLLs, No dedicated RAM blocks
Actel FPGA FamilyActel FPGA Family
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Actel FPGA FamilyActel FPGA FamilySummariesSummaries
MXDS Family
Fine grain Logic Elements that contain Mux logic + DFF
Embedded Dual Port SRAM
One Time Programmable (OTP) - means that no
configuration loading on powerup, no external serialROM
AntiFuse technology for programming (AntiFuse meansthat you program the fuse to make the connection).
Fast (Tpd = 7.5 ns)Low density compared to Altera, Xilinx - maximumnumber of gates is 36,000
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Cypress CPLDsCypress CPLDs
Ultra37000 Family
32 to 512 Macrocells
Fast (Tpd 5 to 10ns depending on number ofmacrocells)Very good routing resources for a CPLD
E l ti
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2010(
?)
1000
0.05
12
25
10-20
1995
100
0.5
3
1004-8
1980
10
5
2
5002-4
1965
1
-
1
20001-2
Max Clock Rate(MHz)
Min IC Geometries()
# of IC MetalLayers
PC Board TraceWidth ()
# of PC-BoardLayers
Evolution
Every 5 years:
System speed doubles, IC geometry shrinks 50%
Every 7-8 years:
PC-board min trace width shrinks 50%
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The Ever-Shrinking Circuitry
Number of LUTs + flip-flops + routing
that fit on the cross section of a human hair
2000 2 LUTs in Virtex-II (150 nm)2002 3 LUTs in Virtex-IIPro (130 nm)
2004 4 LUTs in Virtex-4 (90 nm)
2005 8 LUTs = one CLB in 65 nm
Moores law is alive and well in FPGAs
Middl f h R d Xili FPGA
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Middle-of-the-Road Xilinx FPGAs
1990 XC3042 288 LUTs + flip-flops1994 XC4005 512LUTs + flip-flops1998 XC4013XL 1,152 LUTs + flip-flops2000 XCV300 6,144LUTs + flip-flops
2002 XC2V1000 10,240LUTs + flip-flops2004 XC2VP30 27,382LUTs + flip-flops2005 XC4V60-LX 53,248 LUTs + flip-flops
Same price for each: One days engineering salary
Thirteen Years of Progress of Xilinx
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gDevices
200x More Logic
plus memory, P,DSP, MGT
40x Faster50x Lower Power
per function x MHz
500x Lower Cost
per function
CLB CapacitySpeed
Power per MHz
Price
ITRS Roadmap
Virtex &Virtex-E
XC4000
100x
10x
1x
Spartan-2
1000x
Virtex-II &Virtex-II Pro
Virtex-4
XC4000 &Spartan
Spartan-3
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
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65 70 75 80 85 90 95 00 05 10Year
Clock Frequency in MHz
Trace Length in cm per 1/4 clock period
2048
1024
512
256
128
64
32
16
8
4
2
1
Moore Meets Einstein
Speed Doubles Every 5 Years...but the speed of light never changes
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Higher Leakage CurrentHigh Leakage current = static power consumption
Was 100 mA, even amps (!)
Caused by:Gate leakage due to 16 gate thickness
Sub-threshold leakage currentincomplete turn-off because threshold does not scale
Tyranny of numbers:10 nA x 100 million transistors = 1 A
evenly distributed, thus no reliability problem
Sub-100 nm is notideal for portable designs
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FPGAs in 2003
1000 to 80,000 LUTs and flip-flops,
millions of bits in dual-ported RAMs
Low-skew Global Clocks,Frequency synthesis, 50 ps phase control
18 Kbit BlockRAMs and 18 x 18 multipliers
FPGAs are not glue-logic anymore
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FPGAs in 2003
1000 to 80,000 LUTs and flip-flops,
millions of bits in dual-ported RAMs
Low-skew Global Clocks,Frequency synthesis, 50 ps phase control
18 Kbit BlockRAMs and 18 x 18 multipliers
FPGAs are not glue-logic anymore
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FPGAs in 2003
300+ MHz system clock,800 MHz I/O3+ Gigabit transceivers
Embedded hard and soft microprocessorsDesign security: Triple-DES encryptionVHDL/Verilog entry, synthesis, auto place and route
FPGAs are a compelling alternative to ASICs
FPGAs in 2004FPGAs in 2004
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FPGAs in 2004FPGAs in 2004
Vi t 4 i S t b 2004
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Virtex-4 in September 2004
ASMBLColumn-Based
Architecture
500 MHzSmartRAMBRAM/FIFO
0.6 - 11.1 GbpsRocketIO
SelectIO withChipSyncTechnology:
- 1 Gbps LVDS- 600 Mbps SE
500 MHzXtreme DSP Slice
500 MHzXesium Clocking
IntegratedSystem Monitor
Integrated
Tri-ModeEthernet MAC
Cores
Integrated 450 MHz
PowerPC Cores
4th GenerationAdvanced Logic
S C
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New ASMBL Columnar Architecture
Enables Dial-In
Resource Allocation Mix
Logic, DSP, BRAM, I/O, MGT,
DCM, PowerPC
Made possible by
Flip-Chip Packaging
I/O Columns Distributedthroughout the Device
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FPGA Innovation: Virtex-4
90 nm technology, triple-oxide, 1.2-V Vccint supplyGeneral-purpose I/O up to 1 Gbps,Vcco=1.5, 2.5, or 3.3-V0.6 to 11.2 Gigabit/sec RocketI/Otransceivers
Advanced Silicon Modular Block architecture
Three sub-families:V4-LXfor logic-intense applicationsV4-SX for DSP-intensive applicationsV4-FX with PPC micros and multi-gigabit transceivers
Common architecture for diverse applications
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FPGA Innovation: Virtex-4
Higher Performance:500 MHz for all sub-blocks
More Versatility
New innovative functionsHigher Level of Integration
More LUTs, flip-flops, RAMs, multipliers
Lower CostSmaller area = lower cost per functionLower Power per( Function times MHz )
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FPGA Innovation: Virtex-4
Flip-chip packaging:lower pin-inductance, stiffer Vcc distribution
Lower power per function and MHz
Triple-oxide gates, multiple thresholds,smaller size, lower Vcc, better design
Betterclocking, less skew, more flexibility
Better configuration control, partial reconfigurationRobust configuration cell, SEU tolerant like 130 nm
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FPGA Innovation: Virtex-4
Improved I/O Flexibility and PerformanceSupports >50 standards, on-chip terminationSource-synchronous and system-synchronous
Serializer/deserializer behind each pinProgrammable delay available for each pin> 1Gbps SelectI/O on each pin>10 Gbps transceivers on dedicated pins (-FX
family only)
Source-synchronous I/O improves performance
Serial I/O saves pins and pc-board area
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FPGA Innovation: Virtex-4
Faster logic and memory500+ MHz operation of all on-chip functions
32-bit arithmetic48-bit adders and synchronous loadable counters
Up to 72-bit wide memory4- to 36-bit wide FIFO control in each BlockRAM
Operates with fully independent write and read clocks
Reliable EMPTY and FULL outputsalso ALMOST Empty and ALMOST Full
FIFOs need no fabric resources and no design expertise
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Advanced Clocking
Proper clocking is extremely important
for performance and reliability
Most design need many global clock lineswith minimal clock delay and clock skew
Digital Clock Manager(DCM) provides:
Four-phase outputs,Frequency multiplication and division
Fine phase adjustment
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Advanced I/O
>50 Different Output Standards(strength, voltage, input threshold, etc)multiple parallel output transistorswhich are either fully on or fully off,
Nothing is ever analog, except in LVDS
Digitally Controlled Impedance =DCI
for series-termination of transmission-line driversAdjusts up/down strength to be = external resistorOne external pull-up and pull-down resistor per bank
V2Pro and Virtex-4 can update-only-if-necessary
S tS t S h
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SystemSystem Synchronous
System-Synchronous when the clockarrives simultaneously at all chips
typically used below 200 MHz clock rate
On-chip clock distribution DCM
Zero clock delay controls set-up time,and avoids hold time requirements
The traditional design methodology
SS S h
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SourceSource Synchronous
Each data bus has its own clock tracetypically used at 200 to 800 MHz clock rate
On-chip clock-distribution DCMcenters the clock in the data eye
Adds more unidirectional-only clock lines
The only way above 300 MHz
S i l T i T h l
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3.125 Gbpsover each pair
32b @78 MHz
32b @78 MHz
Virtex-II Pro Virtex-II Pro
Serial Transceiver Technology
S i l T i T h l
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Up to 11.1 Gbpsover each pair
64b @168 MHz
64b @168 MHz
Virtex-4 Virtex-4
Serial Transceiver Technology
RocketIO
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RocketIO
Multi-Gigabit Transceiver
8 to 24 per device
622 Mb/s 11.1 Gb/s
Programmable Features:64b/66b or 8b/10b EnDecComma DetectRx and Tx FIFOPre-EmphasisReceiver EqualizationOutput SwingOn-Chip TerminationChannel bondingAC & DC Coupling
78MHzto
700MHz
Comma Detectand WordAlignment
TX Clock Generator
RX Clock Generator
REFCLK
De-
Serializer
Serializer
Receive
Buffer
Transmitter
Receiver
FIFOEncode
Decode
Elastic
Buffer
16X/20X Multiplier
Serial
Out
Serial
In
Transmit
Buffer
TXDATA
8-64b Wide
TXDATA
8-64b Wide
RXDATA
8-64b Wide
RXDATA
8-64b Wide
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Virtex-4 Capabilities
Any type of design runs at >400 MHzPipelining provides extra performance for freeSynchronous is best, but 32 clock are availableGigabit serial saves pins and board area
On-chip termination for board signal integrityI/O features support double-data rate operation
and source-synchronous design
Virtex 4 Capabilities
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Virtex-4 CapabilitiesPopular functions are hard-wired
for lower cost, higher performance, and ease-of-use:microprocessors, FIFOs, serial I/O, clock management, etc.
Many pre-tested soft cores are available
Some are free, some for a fee
One-hot state machines are preferredOne-hot state machines are preferredBut MicroBlaze and PicoBlaze may be better
Massive parallelism enhances DSP,Massive parallelism enhances DSP,Up to 1024 fast twos complement multipliers per chip,faster than dedicated DSP chips, but needs system-rethinking
2004 Challenges
8/2/2019 Fpga01.FPGAs Overview
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2004 ChallengesTechnology moves rapidly: 130, 90, 65 nm
Multiple Vcc, lower voltage - higher currentLower Vcc makes decoupling very critical
Moores law becomes more difficult to sustain
Leakage current has increased significantlyTriple-oxide transistors and clever design provide relief
Signal integrity on pc-boards is crucialhomebrew prototyping would waste money and time
Use Standard Evaluation Boards
Instead
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