Educational Computer Architecture Experimentation ToolDr. Abdelhafid Bouhraoua
Needs COE-308 course material is mainly
centered around ISA and Design. COE-308 course material focuses on:
Performance issues around the ISA. Design of the Datapath and Control Simple Memory Architecture
Existing tools are mainly assemblers Need an ISA/Datapath/Memory
Experimentation tool
Existing Capabilities MIPS Instruction Set Assembler
SPIM, DLX and others SPIM and DLX
Enable programming assignments only No support for ISA modification No Performance Measurement No Datapath design trade-offs
experimentation capabilities Others
Very advanced research tools that are less suitable for entry-level education purpose
General Requirements Ability to fully define ISAs
Hardware elements Instruction Sets
Ability to describe instruction execution flow.
Ability to define internal datapath blocks
Ability to simulate execution of sample programs
Ability to measure performances metrics (execution time)
Defining ISAs Define Hardware elements and
characteristics visible at the programmer level Registers Operations Execution flow
Define Instruction Set Instructions Instruction Description
Automatic Generation of the Assembler and Simulator for the target machine Includes syntax check Includes execution traces Includes measurement of certain metrics and
execution statistics
Fixed Choices Single Execution Unit No Floating Point Unit (at the
beginning) Two separate Instructions and
Data Memory Access Buses Single Execution Mode
No privileged/supervisor mode support
Single Instruction Set No Dual instruction set support
Single Hardware Interrupt
OrganizationOrganized as Several Areas:• Objects Area• Instruction Set Area• Datapath Area• Assembler Area• Simulator Area
Each Area is linked to the others through the use of its defined parameters in the definition of the other area parametersExample: A Register, defined in the Objects area can be referenced in the definition of an instruction in the Instruction Set Area
Defining the Objects Execution Unit
Clock Cycles per Instruction Single Clock Cycle per Instruction Multiple Clock Cycles per Instruction
Pipelined/non-pipelined Pipeline stages
Number of Operands per instruction 1, 2 or 3 operands per instruction
Registers Single or Array
If Array define its indexes (From k to n+k) Size (number of bits) Label
Operations Select Operations used by Instruction Set from a set of
predefined operations (+, -, x, shift, and, or, …) Define new operations as combination of existing
operations
Defining the Instruction Set Mnemonics
Label Number of Variants
Addressing Modes Addressing mode selection for every variant Possible Operands Selection for every
operand from the list of already defined registers or addressing modes
Description Cycle per Cycle Select operation (from list of defined
operations) Use non-visible (to the programmer)
temporary registers or hardware functional blocks (defined in datapath area) in description
Defining the Datapath Use Existing Hardware Blocks from
Library ALU Register File Muxes
Customize the blocks Size
Define new blocks using hierarchical definitions
Define block Connections Text Definition Possible Definition of Buses
Buses can be Tristate Map Objects to Hardware Blocks
The Assembler Choose the Syntax for representing
Instruction line Comment Data Definition Static Memory Allocation Every Addressing Mode used in the ISA
Choose Policy for Program location in Memory
Editor for writing programs Assembler translates text programs
into object code referencing Instruction Descriptions of Instruction Variants
The Simulator Executes object code Uses a flat memory model
Define Address Boundaries (for debugging)
Detects (during execution) Structural Conflicts Dependencies Contradictory Definitions
Integrates measurement of important metrics Code density Execution Time Program Size
Summary Provides the students with a powerful
experimentation tool Designed to Show the dependencies
that exist between: The Instruction Set The Operations The Hardware Elements The Datapath
Suitable for Pipelined and Non-pipelined Architectures COE-308 and COE-205 (Computer
Organization) as well
Usage
Assignments can be: Given an Instruction set; define a
possible implementation (with provided guidelines)
Given a given datapath; define a suitable instruction set
Evaluate the performances of two different implementations of the same Instruction Set
Aspect Toolset composed of multiple
interacting independent software module
Some are GUI-based Some are Text/Command Line based Define/Use Existing language to
describe: Instruction Set (Assembly side) Datapath Data Entry Probes
Extension of Usage
Extra module for Verilog/VHDL generation Generation of Datapath Unit Verilog
model Generation of Control Unit Verilog
model Generation of Testbench Verilog
Model Generation of Memory Verilog model
(to accept programs) Interface between assembler and Verilog
Model
Conclusion
Computer Architecture Experimentation Toolset for ISA/Processor Design and Education.
Easily Realizable if developed in modules (each module developed as a Senior Project)
If Possible: Collaboration with ICS department (software intensive) project.
Web-based Interface ?
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