ECE 301 – Digital Electronics
Multi-bit Adder Circuits,Multiplier Circuit,
andMagnitude Comparator Circuit
(Lecture #11)
ECE 301 - Digital Electronics 2
Implementations of Multi-bit Adders:
1. Ripple Carry Adder2. Carry Lookahead Adder
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Carry Lookahead Adder
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Carry Lookahead Adder
1 0 1 0
0 0 0 1+
1
Carry Generate
1 1 0 0
Carry End
11
Carry Propagate
0 1 1 1
1 0 1 0
0 0 0 1
0 0
1 0
1 0
11
X
Y
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Carry Lookahead Adder Carry Generate
Gi = X
i . Y
i
Always generates a carry if Gi evaluates to true.
Carry Propagate P
i = X
i xor Y
i
Propagates a carry if Pi evaluates to true AND
there is a carry-in into the adder stage. Carry-in into the first adder stage. Carry-out generated in the previous adder stage.
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The Full Adder in terms of Pi and G
i
Pi = A
i xor B
i
Gi = A
i.B
i
Si = A
i xor B
i xor C
i
Ci+1
= Ai.B
i + A
i.C
i + B
i.C
i
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Carry Lookahead Adder
The Carry Generate (Gi) and Carry Propagate
(Pi) can be created directly from the inputs.
no ripple delay only 1 gate delay
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Carry Lookahead Adder
Cout,i
is a function of Gi and P
i
Cout,i
= (Xi.Y
i) + ( (X
i + Y
i).(C
in,i) )
This is the Cout of the Full Adder
Cout,i
= (Gi) + ( (P
i).(C
in,i) )
where Cin,i
= Cout,i-1
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Carry Lookahead Adder
For the LSB, C
out,0 = (G
0) + ( (P
0).(C
in,0) )
no ripple delay
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Carry Lookahead Adder For LSB+1:
Cout,1 = (G1) + ( (P1) . Cin,1 )
Cout,1 = (G1) + ( (P1) . Cout,0 )
Cout,1 = (G1) + ( (P1) . (G0 + P0.Cin,0) )
Cout,1 = G1 + P1.G0 + P1.P0.Cin,0 All G and P terms derived directly from
associated inputs No ripple delay
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Carry Lookahead Adder For LSB+2:
Cout,2 = (G2) + ( (P2) . Cin,2 )
Cout,2 = (G2) + ( (P2) . Cout,1 )
Cout,2 = (G2) + ( (P2) . (G1 + P1.Cin,1) )
Cout,2
= (G2) + ( (P
2) . (G
1 + P
1.C
out,0) )
Cout,2 = G2 + P2.G1 + P2.P1.Cout,0
Similar for LSB+3, LSB+4, etc.
Must be expanded in terms of G
0, P
0,
and Cin,0
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Carry Lookahead Adder Sum: Si is a function of Xi, Yi, and Cin,i
Si = X
i xor Y
i xor C
in,i
Si = X
i xor Y
i xor C
out,i-1
Carry: Cout,i derived from Gi and Pi
Gi and P
i are functions of the inputs
Carries do not ripple from one stage to the next Delay ~ log
2(n)
Area required ~ (n)*(log2(n))
Greater than area required for RCA
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Carry Lookahead Adder
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Carry Lookahead Adder
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Carry Lookahead Adder
74LS283: 4-bit Binary Adder with Fast Carry
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Adder/Subtractor using 2's Complement
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Adder / Subtractor using Two’s Complement
Could build separate binary adder and subtractor Not common
Use Two’s Complement integer representation Addition uses binary adder Subtraction uses binary adder with the Two’s
Complement representation for the subtrahend Issues
Cannot directly convert the most negative n-bit binary number to its (positive) magnitude in Two’s Complement representation
Must detect overflow
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Adder / Subtractor
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Detecting Overflow Compare sign of operands with sign of result
Overflow occurs if operands have same sign and result has different sign
Addition of two positive #s results in negative # Addition of two negative #s results in positive #
Logic function(s) for overflow (for 4-bit Adder)
Overflow = X3.Y
3.S
3' + X
3'.Y
3'.S
3
Overflow = C3 xor C
4 = C
3'.C
4 + C
3.C
4'
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Multiplier Circuit
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Multiplier Circuit
Multiplication requires two basic operations:
Addition Logical Shift
A binary multiplier circuit can be designed hierarchically using
Full Adders AND gates
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Binary Multiplication
1 1 1 0
1 1 1 01 0 1 1
1 1 1 0
1 0 0 1 1 0 1 0
Multiplicand MMultiplier Q
Product P
(11)(14)
(154)
+
1 0 1 0 10 0 0 0+
0 1 0 1 0
1 1 1 0+
Partial product 0
Partial product 1
Partial product 2
4 bits
4 bits
8 bits
# of bits in P = # of bits in M + # of bits in Q
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Binary Multiplication M (Multiplicand) = m3m2
m1m
0
Q (Multiplier) = q3q
2q
1q
0
PP0 = m3.q0 m
2.q
0 m
1.q
0 m
0.q
0
0 pp03 pp0
2 pp0
1 pp0
0
+ m3.q1m
2.q
1 m
1.q
1 m
0.q
1 0
PP1 = pp14 pp13 pp1
2 pp1
1 pp1
0
partialproduct
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Multiplier Circuit
PP1
PP2
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Multiplier Circuit
Bit of PPi
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Magnitude Comparator
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Magnitude Comparator
How many rows are there in the Truth Table for an n-bit magnitude comparator?
For a 2-bit magnitude comparator 4 inputs, 16 rows
For a 3-bit magnitude comparator 6 inputs, 64 rows
For an n-bit magnitude comparator 2n inputs, 22n rows
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Magnitude Comparator
Designing a magnitude comparator using a Truth Table is too cumbersome.
The magnitude comparator has a certain amount of regularity.
Take advantage of the regularity.
Design the circuit using an algorithm.
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Magnitude Comparator
A = a3a
2a
1a
0B = b
3b
2b
1b
0
Xi = a
i.b
i + a
i'.b
i' = a
i xnor b
i(equivalence)
(A = B): X3.X
2.X
1.X
0
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Magnitude Comparator
A = a3a
2a
1a
0B = b
3b
2b
1b
0
Xi = a
i.b
i + a
i'.b
i' = a
i xnor b
i(equivalence)
(A = B): X3.X
2.X
1.X
0
(A > B): a3b
3' + X
3a
2b
2' + X
3X
2a
1b
1' + X
3X
2X
1a
0b
0'
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Magnitude Comparator
A = a3a
2a
1a
0B = b
3b
2b
1b
0
Xi = a
i.b
i + a
i'.b
i' = a
i xnor b
i(equivalence)
(A = B): X3.X
2.X
1.X
0
(A > B): a3b
3' + X
3a
2b
2' + X
3X
2a
1b
1' + X
3X
2X
1a
0b
0'
(A < B): a3'b
3 + X
3a
2'b
2 + X
3X
2a
1'b
1 + X
3X
2X
1a
0'b
0
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Magnitude Comparator
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