CMOS UNIVERSAL REAL-TIME LABEL-FREE DNAANALYSIS SYSTEM-ON-CHIP
by
Hamed Mazhab Jafari
A thesis submitted in conformity with the requirementsfor the degree of Doctorate of Philosophy
Graduate Department of Electrical and Computer EngineeringUniversity of Toronto
Copyright c⃝ 2013 by Hamed Mazhab Jafari
II
Abstract
CMOS UNIVERSAL REAL-TIME LABEL-FREE DNA ANALYSIS
SYSTEM-ON-CHIP
Hamed Mazhab Jafari
Doctorate of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
2013
Amperometric electrochemical DNA sensors have emerged as a low-cost, high-
throughput and real-time alternative to the conventional optical sensory methods. This
thesis presents the design, implementation, and validation of a fully integrated, mixed-
signal CMOS thermally controlled amperometric electrochemical DNA-sensing system-
on-chip (SoC).
The microsystem includes 54 current-to-digital channels, 600 on-chip nanostruc-
tured DNA sensors and 54 on-chip pH sensors. It reuses key circuits to perform three
key functions: 1) cyclic voltammetry and pH sensing, 2) impedance spectroscopy, and
3) temperature regulation.
Cyclic voltammetry DNA analysis and pH sensing is implemented by utilizing
the current-to-digital channel and an on-chip programmable waveform generator. The
current-to-digital channel is multiplexed between a bank of DNA sensors and a pH sen-
sor. The on-chip programmable waveform generator provides a wide range of user-
controlled rate, shape, and amplitude parameters of the sensor interrogation wave-
form, with a maximum scan range of 1.2V and a scan rate ranging from 0.1mV/sec
to 300V/sec.
Impedance spectroscopy DNA analysis is implemented by utilizing frequency re-
sponse analysis (FRA) to extract the impedance components of the biosensor. The most
III
computationally intensive operations, the multiplication and integration, required by
the FRA algorithm are performed by the in-channel dual-slope multiplying ADC in the
mixed-signal domain resulting in small integration area and power consumption.
The on-chip heating and temperature-sensing elements are implemented without
any post-CMOS processing. Temperature is regulated to within 0.5C using PID feed-
back control. This enables precise thermal control of on-chip DNA hybridization. The
two computationally intensive operations, multiplication and subtraction, required by
the PID algorithm are also efficiently performed by the same in-channel dual-slope mul-
tiplying ADC in the mixed-signal domain. A digital ultra-wideband transmitter based
on a delay line architecture provides wireless data communication capabilities.
The 3mm×3mm prototype fabricated in a 0.13µm standard CMOS technology has
been experimentally validated in the context of prostate cancer synthesized DNA marker
detection. Each recording channel occupies an area of only 0.06mm2 and consumes
42µW of power from a 1.2V supply. The digital ultra-wideband transmitter provides
wireless data communication capabilities with data rates of up to 50 Mb/s while con-
suming 400µW.
IV
Acknowledgements
First and foremost I would like to express my sincere thanks and deep appreciation
to my supervisor, Professor Roman Genov, for his thoughtful and constant guidance
throughout the course of this thesis, and for giving me the opportunities for the academic
advancements I have made. His regular encouragement, support and technical insights
were invaluable to me throughout the course of this work. Further, it enabled me to
perform to the best of my abilities and he provided me with opportunities and exposure
that I would otherwise never have had. I am thankful to work with such an outstanding
researcher and mentor.
I would like to thank my defense committee: Professor Glen Gulak, Professor David
Johns, Professor Ng and my external examiner, Professor Mason for their feedback that
helped improve this thesis. I would also like to thank our collaborators at the McMaster
University, Professor Leyla Solyemani for assisting us in DNA testing. I would also like
to thank CMC for fabrication access to to IBM 130nm CMOS, Jaro for CAD support
and NSERC for providing funding for my project.
I also thank the following members of Professor Genovs Microelectronics Research
Laboratory Alireza Nilchi, Ritu Raj Singh, Farzaneh Shahrokhi, Ruslana Shulyzki,
Derek Ho, Arezu Bagheri, Hossein Kassiri, Nima Soltani, and Arshya Feyzi for their
support, comments and assistance during the course of this research. I especially thank
Karim Abdulhalim, who was always helpful to me during the Ph.D program and spe-
cially during the tape-out.
Finally, I would like to express my deepest acknowledgements and appreciation to
my dear friend Morvarid Akhbari, for being a constant and unconditional source of
support during the writing of this thesis. Thank you for all you have done for me during
the past year and thank you for all your caring and support specially during the hard
time. This thesis is dedicated to you.
V
Contents
List of Tables xi
List of Figures xiii
List of Acronyms xxiii
1 Introduction 1
1.1 Basics of DNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 DNA Structure and Chemical Properties . . . . . . . . . . . . . 3
1.1.2 DNA Concentration . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.3 DNA Amplification by the Polymerase Chain Reaction (PCR) . 5
1.2 Conventional Bench-top DNA Analysis Methods . . . . . . . . . . . . 8
1.2.1 Optical Fluorescent DNA Sensing . . . . . . . . . . . . . . . . 8
1.2.2 Commercial Optical DNA-Sensing Instruments . . . . . . . . . 10
1.2.3 pH-based DNA Sensing . . . . . . . . . . . . . . . . . . . . . 11
1.2.4 Commercial pH-based DNA Sensing Instruments . . . . . . . . 12
1.3 Existing Integrated Circuits for DNA Sensing . . . . . . . . . . . . . . 14
1.3.1 CMOS Fluorescent DNA Contact Imaging . . . . . . . . . . . 15
1.3.2 CMOS Magnetic Field-Based DNA Sensing . . . . . . . . . . . 15
1.3.3 CMOS Capacitance-Based DNA Sensing . . . . . . . . . . . . 17
1.4 Amperometric Electrochemical Sensing Principles . . . . . . . . . . . 17
1.4.1 Three-electrode Sensing Configuration . . . . . . . . . . . . . 19
VI
1.4.2 Electrode-Electrolyte Interface . . . . . . . . . . . . . . . . . . 21
1.4.3 Reduction-Oxidation Current . . . . . . . . . . . . . . . . . . . 22
1.4.4 Labeled vs Label-free DNA Sensing . . . . . . . . . . . . . . . 22
1.4.5 Electrode Material . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Amperometric Electrochemical Sensing Methods . . . . . . . . . . . . 24
1.5.1 Fast-Scan Cyclic Voltammetry . . . . . . . . . . . . . . . . . . 26
1.5.2 Amperometric Impedance Spectroscopy . . . . . . . . . . . . . 26
1.5.3 Temperature Regulation for DNA Analysis . . . . . . . . . . . 27
1.5.4 Commercial Amperometric Instruments . . . . . . . . . . . . . 28
1.6 Integrated Circuits for Amperometric DNA Sensing . . . . . . . . . . 28
1.7 Main Specifications for Amperometric Electrochemical DNA Sensing
Integrated Circuits Design . . . . . . . . . . . . . . . . . . . . . . . . 30
1.7.1 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.7.2 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.3 Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.4 Non-electrical Design Specification . . . . . . . . . . . . . . . 33
1.8 Additional Considerations for DNA-sensing Amperometric Integrated
Circuits Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.8.1 Low-Level Current Acquisition for Amperometry . . . . . . . . 34
1.8.2 Wireless Data Transmission of DNA Results . . . . . . . . . . 35
1.8.3 DNA Temperature Regulation . . . . . . . . . . . . . . . . . . 37
1.8.4 On-chip Computation for DNA Analysis: Analog vs. Digital
vs. Mixed-Signal VLSI Multiplication . . . . . . . . . . . . . . 38
1.9 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.9.1 Complete DNA Analysis SoC . . . . . . . . . . . . . . . . . . 47
1.9.2 Cyclic Voltammetry and Sample pH Level Sensing . . . . . . . 48
1.9.3 Impedance Spectroscopy . . . . . . . . . . . . . . . . . . . . . 48
1.9.4 Temperature Regulation . . . . . . . . . . . . . . . . . . . . . 49
1.10 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VII
2 Current Acquisition Circuits for Electrochemical Amperometric Biosen-
sors 51
2.1 Transimpedance Amplifier (TIA) . . . . . . . . . . . . . . . . . . . . . 52
2.1.1 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . 53
2.1.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 55
2.2 Current Conveyer (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.1 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . 57
2.2.2 Channel Noise Analysis . . . . . . . . . . . . . . . . . . . . . 61
2.2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 66
2.3 Comparative Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3 Cyclic Voltammetry and pH sensing 73
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.2 DNA Detection Principle . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3 Integrated Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.1 DNA Sensing Microelectrodes . . . . . . . . . . . . . . . . . . 76
3.3.2 pH Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4 VLSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.4.1 Top-Level VLSI Architecture . . . . . . . . . . . . . . . . . . 79
3.4.2 Channel VLSI Architecture . . . . . . . . . . . . . . . . . . . 81
3.5 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.1 Current Conveyer . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.2 Dual-slope ADC Comparator . . . . . . . . . . . . . . . . . . 88
3.5.3 Ultra-wideband Transmitter . . . . . . . . . . . . . . . . . . . 88
3.6 Electrical Experimental Results . . . . . . . . . . . . . . . . . . . . . . 89
3.7 Experimental Electrochemical Results . . . . . . . . . . . . . . . . . . 95
3.8 Synthetic Prostate Cancer DNA Detection . . . . . . . . . . . . . . . . 102
3.9 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
VIII
4 Impedance Spectroscopy DNA 111
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.2 DNA Detection Principle . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3 Impedance Spectroscopy VLSI Architecture . . . . . . . . . . . . . . . 113
4.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.4.1 Multi-channel System-Level Architecture . . . . . . . . . . . . 116
4.4.2 Waveform Generator and Pattern Generator . . . . . . . . . . . 118
4.4.3 Dual-slope Multiplying ADC Channel . . . . . . . . . . . . . . 120
4.4.4 Three-electrode Regulation Loop . . . . . . . . . . . . . . . . 125
4.5 Electrical Experimental Results . . . . . . . . . . . . . . . . . . . . . . 126
4.6 Analog vs Digital vs Mixed-Signal Multiplication . . . . . . . . . . . . 131
4.7 Electrochemical Experimental Results . . . . . . . . . . . . . . . . . . 135
4.8 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5 Temperature Regulation 140
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2 Thermal Control Principles . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2.1 Temperature regulation . . . . . . . . . . . . . . . . . . . . . . 142
5.2.2 Temperature sensing . . . . . . . . . . . . . . . . . . . . . . . 144
5.2.3 Temperature Regulation . . . . . . . . . . . . . . . . . . . . . 148
5.3 VLSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.4.1 Current-to-Digital Channel . . . . . . . . . . . . . . . . . . . . 150
5.4.2 CTAT Current Source . . . . . . . . . . . . . . . . . . . . . . . 153
5.4.3 PTAT Current Source . . . . . . . . . . . . . . . . . . . . . . . 155
5.4.4 Digital Pulse Width Modulator . . . . . . . . . . . . . . . . . . 156
5.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
IX
6 Conclusions and Future Work 167
6.1 Contributions and Related Publications . . . . . . . . . . . . . . . . . . 167
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.2.1 Power Harvesting and Wireless Communication Chip . . . . . . 171
6.2.2 Improvements to the SoC . . . . . . . . . . . . . . . . . . . . . 171
References 173
Appendix 187
A Supplementary Hardware and Software Documentation 187
A.1 Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
A.2 DNA Sensing protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 190
A.3 Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
A.4 FPGA Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
A.4.1 Top Level Module . . . . . . . . . . . . . . . . . . . . . . . . 197
A.4.2 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 206
A.4.3 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . 208
A.4.4 USB Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . 209
A.4.5 One Channel FIFO Controller . . . . . . . . . . . . . . . . . . 210
A.4.6 FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . 214
A.4.7 16-bits Parallel to Serial Converter . . . . . . . . . . . . . . . . 217
A.4.8 Timing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
A.4.9 Waveform Generator . . . . . . . . . . . . . . . . . . . . . . . 224
A.4.10 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
A.4.11 Seven Bit Counter . . . . . . . . . . . . . . . . . . . . . . . . 227
A.4.12 Chip Timing Coefficients . . . . . . . . . . . . . . . . . . . . . 228
A.4.13 SRAM Timing Coefficients . . . . . . . . . . . . . . . . . . . 229
A.4.14 Channel Range Controller Coefficients . . . . . . . . . . . . . 233
A.4.15 Impedance Spectroscopy SRAM Coefficients . . . . . . . . . . 235
X
A.4.16 Temperature Regulation SRAM Coefficients . . . . . . . . . . 236
A.4.17 Test Channel Controller . . . . . . . . . . . . . . . . . . . . . 237
A.5 Example CV Recording Verilog Code . . . . . . . . . . . . . . . . . . 238
A.6 Example IS Recording Verilog Code . . . . . . . . . . . . . . . . . . . 247
A.7 Example Temperature Regulation Verilog Code . . . . . . . . . . . . . 258
XI
List of Tables
1.1 Comparative Analysis of Amperometric Biomolecular Sensory Microsys-
tems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.1 TIA OTA Transistors Sizing . . . . . . . . . . . . . . . . . . . . . . . 58
2.2 Current Conveyer Transistor Sizing . . . . . . . . . . . . . . . . . . . . 66
2.3 Experimentally Measured Transimpedance Amplifier (TIA) and Cur-
rent Conveyer (CC) Characteristics . . . . . . . . . . . . . . . . . . . . 71
3.1 ADC Comparator Transistor Sizing . . . . . . . . . . . . . . . . . . . 85
3.2 Experimentally Measured Electrical Characteristics . . . . . . . . . . . 100
3.3 Comparative Analysis of Amperometric Sensory Microsystems . . . . . 109
4.1 OTA1 and Comparator Transistor Sizing . . . . . . . . . . . . . . . . . 123
4.2 Analog Integrator Noise Summary . . . . . . . . . . . . . . . . . . . . 124
4.3 OTA2 and OTA3 Transistors Sizing . . . . . . . . . . . . . . . . . . . 126
4.4 Experimentally Measured Characteristics . . . . . . . . . . . . . . . . 130
4.5 Serial Digital Multiplier Area Breakdown . . . . . . . . . . . . . . . . 134
4.6 Comparison of Mixed-Signal vs Analog vs Digital Multiplication . . . . 135
4.7 Comparative Analysis of Reported Amprometric Sensory Microsystem 136
5.1 OTA Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.2 Experimentally Measured Characteristics . . . . . . . . . . . . . . . . 161
XII
5.3 Comparative Analysis of Reported Thermally Regulated Biosensory
Microsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
XIII
List of Figures
1.1 The structure of the DNA double helix [2]. . . . . . . . . . . . . . . . . 4
1.2 Schematic of polymerase chain reaction cycles. . . . . . . . . . . . . . 6
1.3 A fluorescence-based DNA microarray [14]. . . . . . . . . . . . . . . . 9
1.4 A typical scanner for fluorescence-based DNA detection [14]. . . . . . 10
1.5 Commercially available fluorescence-based DNA microarray scanners:
(a) Affymetrix GeneChip Scanner 3000 7G [35], (b) Agilent SureScan
Microarray Scanner [36], and (c) Spartan RX microarray scanner [37]. . 11
1.6 pH-based DNA sensing: (a) system cross-section, (b) complementary
DNA sequence and (c) and non-complementary DNA sequence [41]. . . 13
1.7 Commercially available pH-based DNA-sensing instruments: (a) Ion
Torrent [41], (b) DNA Electronics [44], and (b) GeneOnyx [42]. . . . . 14
1.8 Conceptual view of an electrochemical amperometric sensing microsys-
tem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.9 Charge profile of the electrode-electrolyte interface and its equivalent
circuit model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.10 Working electrode material examples: (a) diamond [71], (b) polymer [20],
and (c) flat gold [70]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.11 Fast-scan cyclic voltammetry principle of operation (a) cyclic redox po-
tential applied between the working and reference electrode, and (b)
cyclic voltammogram in the absence and presence of the target chemical. 25
XIV
1.12 Impedance spectroscopy principle of operation (a) potential difference
between working and reference electrode, and (b) change in redox cur-
rent frequency response due to the change in the chemical concentration. 27
1.13 Commercially available amperometric instruments: (a) Early Warning
biohazard water analyzer [38], (b) Palmsens 3 [39], and (c) PSTAT
mini [40]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.14 Biosensor SNR vs target analyte concentration [23]. . . . . . . . . . . . 32
1.15 Conceptual view of current acquisition circuits for electrochemical am-
perometric sensory system. . . . . . . . . . . . . . . . . . . . . . . . . 34
1.16 Conventional transimpedance amplifier (TIA) interfaced to a biosensor
model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.17 Conventional current conveyer (CC) interfaced to a biosensor model. . . 35
1.18 Trojan UV3000PTP wastewater solution [31]. . . . . . . . . . . . . . . 36
1.19 Analog multiplier block diagram [103]. . . . . . . . . . . . . . . . . . 39
1.20 Analog multiplier circuit schematic. . . . . . . . . . . . . . . . . . . . 39
1.21 The block diagram of the 16×16-bit serial multiplier [128]. . . . . . . . 40
1.22 (a) The critical path of the 16×16-bit parallel multiplier and (b) the
block diagram of the 16×16-bit two-cycle parallel multiplier [128]. . . 41
1.23 Reuse of the SoC architecture resources (blocks outlined in bold are
reused in all modes) (a) complete DNA analysis SOC, (b) cyclic voltam-
metry configuration, (c) impedance spectroscopy configuration and (d)
temperature regulation configuration. . . . . . . . . . . . . . . . . . . . 46
2.1 Chopper-stabilized bidirectional-input transimpedance amplifier (TIA). 53
2.2 Circuit schematic diagram of the OTA within the TIA. . . . . . . . . . 54
2.3 Simulated input-referred noise spectrum of the TIA from 0.01Hz to 1kHz. 55
2.4 Transimpedance amplifier noise summary: (a) flicker noise contribu-
tions, and (b) thermal noise contributions. . . . . . . . . . . . . . . . . 56
XV
2.5 Experimentally measured relative error of the output of the TIA for the
input current of (a) 10pA to 350nA, and (b) -350nA to -10pA. The
results are measured from one typical channel on one chip. . . . . . . . 57
2.6 Experimentally measured TIA output current of 16 channels (from 16
chips, one channel each) for the input current of (a) 100pA, and (b)
100nA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7 Conventional pseudo-bidirectional current conveyer with a DC offset
current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.8 Chopper-stabilized bidirectional current conveyer VLSI architecture. . . 59
2.9 Chopper-stabilized bidirectional current conveyer circuit schematic di-
agram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.10 Simulated current conveyer AC response . . . . . . . . . . . . . . . . . 61
2.11 Simplified noise model of the chopper-stabilized current conveyer. . . . 62
2.12 Simulated input-referred noise spectrum of the current conveyer from
0.01Hz to 1kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.13 Current conveyer noise summary: (a) flicker noise contributions, and
(b) thermal noise contributions. . . . . . . . . . . . . . . . . . . . . . . 67
2.14 Experimentally measured relative error of the output of the current con-
veyer for the input current of (a) 10pA to 350nA, and (b) -350nA to
-10pA. The results are measured from one typical channel on one chip. . 68
2.15 Experimentally measured current conveyer output current of 16 chan-
nels (from 16 chips, one channel each) for the input current of (a)
100pA and (b) 100nA. . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.16 Average current injected into the working electrode for (a) TIA and (b)
CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.17 Cyclic voltammogram of 2µM potassium ferricyanide in 1M potas-
sium phosphate buffer solution experimentally recorded with the tran-
simpedance amplifier (TIA) and the current conveyer (CC) using a 50µm×50µm
gold electrode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XVI
2.18 Cyclic voltammogram of 2µM potassium ferricyanide in 1M potas-
sium phosphate buffer solution experimentally recorded with the tran-
simpedance amplifier (TIA) and the current conveyer (CC) using a 2µm×2µm
gold electrode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.1 Label-free electrochemical DNA detection principle. (a) Bare elec-
trode: maximum charge transfer between working and reference elec-
trode in the absence of negatively charged probe and target DNA; (b)
non-complementary target DNA: reduction in the charge transfer rate
due to the presence of negatively charged probe DNA, and (c) comple-
mentary DNA: further reduction in the charge transfer rate due to the
presence of negatively charged target and probe DNA. . . . . . . . . . 75
3.2 (a) Passivation opening in standard CMOS and added metal layers of a
flat (2D) microelectrode after electroless nickel-palladium-gold plating,
(b) and (c) SEM photographs of such 55µm×55µm working electrodes. 78
3.3 Nanostructured DNA sensing working electrodes (NMEs): (a) Cross-
sectional view of a 2µm×2µm passivation opening in standard CMOS,
(b) SEM photograph of a 2µm×2µm working electrode passivation
opening over an aluminum base, (c) nanostructured 2µm×2µm work-
ing electrode grown on the passivation opening over an aluminum base
in standard CMOS, (c) (d) and (e) SEM photographs of nanostructured
microelectrodes grown at different electrodeposition conditions on the
passivation opening in (b). . . . . . . . . . . . . . . . . . . . . . . . . 79
3.4 Wireless DNA analysis microsystem functional block diagram. . . . . . 80
3.5 Simplified top-level VLSI architecture of one chopper-stabilized inte-
grated current-to-digital channel. . . . . . . . . . . . . . . . . . . . . . 81
3.6 Detailed implementation of the current conveyer OTA with internal
chopping and dynamically-matched low-current regulation. . . . . . . . 81
3.7 High-speed latched comparator circuit schematic diagram. . . . . . . . 84
XVII
3.8 (a) Ultra-wideband transmitter circuit schematic diagram, and (b) schematic
of one current-starved inverter. . . . . . . . . . . . . . . . . . . . . . . 86
3.9 Timing diagram of the ultra-wideband transmitter. . . . . . . . . . . . . 86
3.10 Die micrograph of the 3mm×3mm 54-channel wireless DNA analysis
SoC. The SoC was fabricated in a 0.13µm standard CMOS technology. 87
3.11 Experimentally measured spectrum of the electrochemical recording
channel output for a 15Hz sinusoidal full-scale (350nA) input. . . . . . 89
3.12 Experimentally measured transfer characteristics of the current-to-digital
channel for three sampling frequencies. . . . . . . . . . . . . . . . . . 90
3.13 Experimentally measured output ENOB of 32 channels (from 16 chips,
two channels each) for a 15Hz 350nA sinusoidal input (a) without cali-
bration (b) with in-channel calibration. . . . . . . . . . . . . . . . . . . 91
3.14 Experimentally measured ENOB vs. input frequency for the in-channel
ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.15 Experimentally measured relative error of the output digital code of the
current conveyer connected with the dual-slope ADC for (a) 10pA to
350nA and (b) -350nA to -10pA input current. . . . . . . . . . . . . . . 93
3.16 Experimentally measured output current of 32 channels (from 16 chips,
two channels each) for the input current of (a) 100pA without DEM
[32] and (b) 100pA with DEM (this work). . . . . . . . . . . . . . . . . 94
3.17 Experimentally measured output current of 32 channels (from 16 chips,
two channels each) for input current of (a) 100nA without DEM [32]
and (b) 100nA with DEM (this work). . . . . . . . . . . . . . . . . . . 95
3.18 Experimentally measured (a) Manchester-encoded input data to the UWB
transmitter and (b) the output pulses. . . . . . . . . . . . . . . . . . . . 96
3.19 Wirelessly measured UWB pulse at the distance of 5cm using a custom-
built UWB receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
XVIII
3.20 Experimentally measured UWB transmitter output spectrum (direct out-
put of the transmitter driving a 50 ohm load). The output spectrum is
compliant with the 0-1GHz FCC UWB band output power criteria . . . 97
3.21 (a) Manchester-encoded input data to the UWB transmitter and (b) the
corresponding data received wirelessly at a 5cm distance. . . . . . . . . 98
3.22 Experimentally recorded cyclic voltammograms of 1M potassium phos-
phate buffer and 20µM potassium ferricyanide solution using the 55µm×55µm
working electrode in Fig. 3.2(b) . . . . . . . . . . . . . . . . . . . . . 98
3.23 Experimentally recorded cyclic voltammograms of 10µM, 20µM, 30µM
and 40µM potassium ferricyanide solution using the 55µm×55µm work-
ing electrode in Fig. 3.2(b) . . . . . . . . . . . . . . . . . . . . . . . . 99
3.24 Calibration curve for the peak reduction current of potassium ferri-
cyanide solution for the 55µm×55µm Au . . . . . . . . . . . . . . . . 99
3.25 Experimentally recorded peak reduction current of the 40µM potassium
ferricyanide solution recorded using the 55µm×55µm working elec-
trode shown in Fig. 3.2(b) by 48-channel on the CMOS DNA analysis
SoC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.26 Experimentally measured on-chip pH sensor calibration curve relative
to pH of 7. A total of 60 measurements from 3 chips, 20 measurements
each, have been performed. The corresponding 3σ error bars are shown. 101
3.27 Experimentally measured cyclic voltammetry results of 5µM prostate
cancer synthetic DNA detection from the 55µm×55µm flat gold work-
ing electrode in Fig. 3.2(b) . . . . . . . . . . . . . . . . . . . . . . . . 103
3.28 Experimentally measured 5µM prostate cancer synthetic DNA cyclic
voltammetry recording 3σ error bars from 3 chips 60 measurements
each from 55µm×55µm flat gold working electrodes in Fig. 3.2(b). . . 104
3.29 Experimentally measured cyclic voltammetry results of 100aM prostate
cancer synthetic DNA detection, from 2µm×2µm nanostructured work-
ing electrodes in Fig. 3.3(e) . . . . . . . . . . . . . . . . . . . . . . . . 105
XIX
3.30 Experimentally measured 100aM prostate cancer synthetic DNA cyclic
voltammetry recording 3σ error bars from 3 chips, 60 measurements
each, from 2µm×2µm nanostructured working electrodes in Fig. 3.3(e) 105
3.31 Experimentally measured microelectrode characteristics, detection lim-
its and dynamic ranges in prostate cancer synthetic DNA detection us-
ing the three electrodes types shown in Fig. 3.3(d) and (e) and Fig. 3.2(b).
Error bars (3 sigma) are from 3 chips, 100 measurements each. . . . . . 106
4.1 Block diagram of a frequency-response analyzer (FRA) system for biosen-
sor impedance spectroscopy. . . . . . . . . . . . . . . . . . . . . . . . 113
4.2 Impedance spectroscopy microsystem functional block diagram. . . . . 114
4.3 Waveform generator functional block diagram. . . . . . . . . . . . . . 115
4.4 Principle of the sine wave generation. . . . . . . . . . . . . . . . . . . 115
4.5 Absolute value of the relative error of the biosensor R-C model impedance
as a function of frequency due to stepwise approximation of the inter-
rogation signal for the : (a) real, and (b) imaginary components. . . . . 116
4.6 (a) Dual-slope multiplying ADC VLSI architecture, and (b) timing dia-
gram of all relevant signals. . . . . . . . . . . . . . . . . . . . . . . . . 117
4.7 Timing diagram illustrating the ADC multiplication function. . . . . . . 118
4.8 Chopper-stabilized folded-cascode OTA1 in the analog integrator. . . . 122
4.9 Comparator circuit diagram. (a) One of the three identical gain stages,
and (b) the high-speed latch. . . . . . . . . . . . . . . . . . . . . . . . 122
4.10 Simulated input-referred noise spectrum of the analog integrator with
the chopper on and off (clocked at 100kHz) from 0.01Hz to 10kHz. . . 123
4.11 (a) Circuit architecture of the three-electrode regulation loop, and (b)
OTA2 and OTA3 circuit schematic. . . . . . . . . . . . . . . . . . . . . 124
4.12 Die micrograph of the 54-channel integrated impedance spectrum ana-
lyzer fabricated in a 0.13µm standard CMOS technology. . . . . . . . . 126
XX
4.13 Experimentally measured transfer characteristics of the impedance spec-
trum analyzer channel for three sampling frequencies. . . . . . . . . . . 127
4.14 Experimentally measured output spectrum of the ADC for a 10Hz sinu-
soidal input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.15 Experimentally measured MADC SNDR vs. the multiplication factor. . 128
4.16 Waveform generator DNL. . . . . . . . . . . . . . . . . . . . . . . . . 128
4.17 Waveform generator INL. . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.18 Total harmonic distortion of waveform generator DAC. . . . . . . . . . 129
4.19 Off-chip biosensor model impedance as a function of frequency exper-
imentally measured by the impedance spectroscopy microsystem: (a)
real, and (b) imaginary components. . . . . . . . . . . . . . . . . . . . 131
4.20 Absolute value of the relative error of the off-chip biosensor model
impedance as a function of frequency: (a) real, and (b) imaginary com-
ponents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.21 Potassium ferricyanide solution impedance as a function of frequency
experimentally measured by the impedance spectroscopy microsystem:
(a) real, and (b) imaginary components. . . . . . . . . . . . . . . . . . 133
4.22 (a) Impedance spectrum of 5µM prostate cancer synthetic DNA probe,
complementary, non-complementary targets and (b) the corresponding
3-sigma error bars (from 3 chips, 20 measurements each). . . . . . . . . 138
5.1 Block diagram of PID implementation of the temperature regulation loop.142
5.2 (a) A pair of BJTs for generating ∆VBE and VBE , (b) Temperature de-
pendence of the base-emitter voltage, (c) generation of PTAT and CTAT
current, (d) generation of temperature dependent current and (e) utiliza-
tion of a current-to-digital channel for temperature measurements. . . . 143
5.3 Top-level VLSI architecture of temperature regulation loop (shaded boxes
are in-channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.4 Timing diagram of the temperature regulation loop. . . . . . . . . . . . 148
XXI
5.5 Top-level VLSI architecture of one temperature sensing channel. . . . . 149
5.6 In-channel heater schematic. . . . . . . . . . . . . . . . . . . . . . . . 150
5.7 Timing diagram of the dual-slope multiplying ADC. . . . . . . . . . . . 151
5.8 Circuit diagram of the CTAT sensor and CTAT current source . . . . . . 153
5.9 Chopper-stabilized folded-cascode OTA in the CTAT (OTA1) and PTAT
(OTA2) current sources. . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.10 Simulated input-referred noise spectrum of the OTA with chopper en-
abled and disabled from 0.01Hz to 1kHz. . . . . . . . . . . . . . . . . 154
5.11 Simulated OTA noise summary: (a) thermal noise contribution, and (b)
flicker noise contribution. . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.12 Circuit diagram of the PTAT sensor and PTAT current source. . . . . . . 156
5.13 Block diagram of the digital pulse width modulator. . . . . . . . . . . . 157
5.14 Die micrograph of the 54-cell wireless temperature regulated DNA anal-
ysis SoC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.15 Experimentally measured output spectrum of the ADC for a 15Hz sinu-
soidal input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.16 Experimentally measured transfer function of the pulse-width-modulator. 158
5.17 Experimentally measured digital output of the dual-slope ADC vs tem-
perature (in-air). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.18 TP04390A ThermoStream [169] unit used for temperature sensor char-
acterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.19 Temperature sensor error experimentally measured on seven dies from
one wafer (in-air). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.20 Experimentally measured temperature from 54 channels in one chip (in-
air). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.21 Temperature regulation cycle with steps at 35, 45, 55 and 65 degree
Celsius (in-liquid). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.22 Measured absolute value of the relative error of PID regulation loop
(in-air). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
XXII
6.1 Die micrograph of the 2mm×3mm power harvesting and wireless com-
munication chip. The chip was fabricated in a 0.13µm standard CMOS
technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
A.1 PCB fabricated for characterizing the DNA analysis SoC. . . . . . . . . 188
XXIII
List of Acronyms
ADC analog-to-digital converter
DAC digital-to-analog converter
SNR signal-to-noise ratio
VLSI very-large-scale integration
OTA operational transconductance amplifier
TIA transimpedance amplifier
FOM figure-of-merit
LOC lab-on-chip
RMS root mean square
SC switched capacitor
DSP digital signal processing
LFSR linear feedback shift register
OPAMP operational amplifier
IC integrated circuit
1
Chapter 1
Introduction
The genetic blue print of every living organism is defined by its genome which is com-
prised of a sequence of nucleotide bases that contains deoxyribo-nucleic acid (DNA).
The microbiological culture techniques currently employed to identify disease-causing
pathogens are time consuming, labor-intensive, often have a high false positive rate,
do not provide the necessary information about the potential pathogenicity or virulence
of the identified organisms, and are not well suited for in-field managing of a large
number of samples. These limitations have stimulated efforts to develop DNA-based
pathogen detection methods. The advantage of DNA-based methods is the opportu-
nity to pinpoint precisely the unique DNA and ribonucleic acid (RNA) signature that
each pathogen carries, differentiating it from other organisms having vastly different
virulences.
This thesis focuses on the design, implementation, and experimental validation
of a fully integrated mixed-signal CMOS thermally controlled amperometric electro-
chemical DNA-sensing system-on-chip (SoC). The microsystem includes 54 current-
to-digital channels, 600 on-chip nanostructured DNA sensors, and 54 on-chip pH sen-
sors. The microsystem is universal since it reuses key circuits to perform three key
CHAPTER 1. INTRODUCTION 2
functions: (1) cyclic voltammetry and pH sensing, (2) impedance spectroscopy, and
(3) temperature regulation. Chapter 1 of this thesis provides a brief overview of the
DNA structure and DNA sensing techniques, which is followed by a literature review
and an overview of the work that is to be presented. Chapter 2 presents two different
analog current-recording front-end circuits for electrochemical sensing applications and
compares their advantages and disadvantages. Chapter 3 focuses on the cyclic voltam-
metry DNA-sensing capability of the SoC and presents a fully integrated 54-channel
wireless label-free cyclic voltammetry DNA analyzer. Chapter 4, which focuses on the
impedance spectroscopy DNA sensing capability of the SoC, shows the SoC configured
as an impedance analyzer that utilizes frequency response analysis (FRA) to extract the
real and imaginary impedance components of the biosensor. Chapter 5 discusses the
temperature regulation capabilities of the SoC and introduces a 54-site mixed-signal
CMOS thermal regulator with a compact mixed-signal PID controller. The conclusions
of the thesis and the possible directions of future work are discussed in Chapter 6.
In the introductory section of Chapter 1, basics of DNA analysis are presented in
Section 1.1. An overview of conventional bench-top DNA analysis methods and a sum-
mary of commercially available DNA sensing and analysis instruments are provided
in Section 1.2. Prior research works on non-amperometric CMOS integrated DNA
analysis SoCs are presented in Section 1.3. Background information and an overview
of amperometric electrochemical DNA-sensing principles and different amperometric
electrochemical sensing methods are provided in Sections 1.4 and 1.5. Prior research
works on CMOS amperometric integrated DNA analysis SoCs are presented in Sec-
tion 1.6. The specifications and requirements of an electrochemical DNA analysis SoC
are described in Section 1.7. Summary of additional design considerations for DNA-
sensing amperometric integrated circuits are provided in Section 1.8. Overview of the
work presented in the thesis is provided in Section 1.9. Thesis outline is presented in
CHAPTER 1. INTRODUCTION 3
Section 1.10.
1.1 Basics of DNA
1.1.1 DNA Structure and Chemical Properties
Deoxyribo-nucleic acid (DNA) is a nucleic acid that contains the genetic blueprint re-
quired for development and functioning of the living organisms. DNA is composed of
two polymer strands made of units called nucleotides. The backbone of DNA is made
of sugars and phosphate groups joined by ester bonds. Each nucleotide consists of three
units: a phosphate group, a five carbon deoxyribose group, and a nitrogen base group.
The phosphate group loses a proton in a neutral solution giving rise to the overall neg-
ative charge of the DNA. The nucleotides units in DNA include adenine (A), cytosine
(C), guanine (G), and thymine (T) as shown in Fig. 1.1. The four bases are bonded to
the sugar/phosphate DNA backbone to form the complete nucleotide [1].
DNA does not exist as a single molecule in any living organism, but exists as a
pair of molecules that are bonded together. Two long strands of DNA are twisted to-
gether like vines, in the shape of a double helix. The double helix DNA is stabilized by
hydrogen bonds between nucleotides [2].
The double helix DNA molecule can be separated into two single-stranded DNA
(ssDNA) molecules in a process called de-naturing. De-naturing is normally achieved
by heating the double helix DNA. In reverse, two complementary ssDNA molecules
can form a double-stranded DNA molecule in a process known as hybridization or re-
naturation [2].
Polymerase chain reaction (PCR) amplification technique is commonly used to am-
plify specific regions of a DNA strand for more accurate sensing (i.e, to make many
copies of these DNA regions in order to increase and then measure their concentration).
CHAPTER 1. INTRODUCTION 4
Figure 1.1: The structure of the DNA double helix [2].
1.1.2 DNA Concentration
Concentration of a constituent (e.g., DNA molecules) in a chemical mixture is defined
as the quantity of a constituent divided by the total volume of a mixture. There are
several mathematical description that can quantify concentration such as: mass con-
centration, molar concentration, number concentration, and volume concentration. The
term concentration can be applied to any kind of chemical mixture, but most frequently
it refers to solutes and solvents in solutions.
The most commonly used term for quantifying concentration is molar concentration.
CHAPTER 1. INTRODUCTION 5
The molar concentration is defined as the amount of a constituent in units of mol divided
by the volume of the mixture. The unit of molar concentration is mol/L.
Given the molar concentration of a sample, number of molecules in the sample can
be calculated as follows:
1. Calculate the absolute amount of the sample in units of mol:
Concentration(mol/L)×volume(L)= Amount(mol)
2. Next use the Avogadro constant to get the number of the molecules in the sample
as follows:
Amount(mol)×6.02214129×1023 mol−1 = number of the molecules in the volume
For example, 1mL solution containing 10aM concentration of a target DNA would
containing 10aM×1mL×6.02214129×1023 target DNA molecules. This corresponds
to 602 target DNA molecules.
1.1.3 DNA Amplification by the Polymerase Chain Reaction (PCR)
The polymerase chain reaction (PCR) is a procedure in biochemistry to amplify a single
or a few copies of a DNA sequence, generating up to millions of copies of the same
DNA sequence [62–65]. This method is utilized to increase the concentration of the
target DNA in a sample, thus increasing the detection accuracy. PCR relies on thermal
cycling which consists of cycles of repeated heating and cooling for DNA melting and
enzymatic replication of the DNA. Short DNA fragments (less than 100 base pairs [65]
containing sequences complementary to the regions of the target DNA sequence are
key components to enable selective and repeated amplification. As PCR progresses, the
DNA generated is itself used as a template for replication, setting a chain reaction in
which the DNA template is exponentially amplified.
An example of PCR is shown in Fig. 1.2. A brief descriptions of the PCR steps is
as follows:
CHAPTER 1. INTRODUCTION 6
Figure 1.2: Schematic of polymerase chain reaction cycles.
CHAPTER 1. INTRODUCTION 7
1. Initialization step: Heating the DNA solution to a temperature of 94 to 96 oC and
holding the solution at that temperature for 1 to 9 minutes [62].
2. Denaturation step: Heating the DNA solution to 94 to 98 oC for 20 to 30 seconds.
This results in melting of the DNA template by breaking the hydrogen bonds between
complementary bases, resulting in single-stranded DNA molecules.
3. Annealing step: Reducing the DNA solution temperature to 50 to 65 oC for 20
to 40 seconds resulting in annealing of the DNA oligonucleotides to the single-stranded
DNA template. DNA-DNA hydrogen bonds are formed when the DNA oligonucleotides
sequence closely matches the template sequence. The polymerase binds to the oligonucleotides-
template hybrid and begins DNA formation.
4. Extension step: The temperature is increased to 75 to 80 oC [62, 63]. At this
step the DNA polymerase synthesizes a new DNA strand complementary to the DNA
template strand by adding deoxynucleotide triphosphates that are complementary to
the template in 5’ to 3’ direction, condensing the 5’-phosphate group of the deoxynu-
cleotide triphosphates with the 3’-hydroxyl group at the end of the nascent DNA strand.
The amount of DNA target is doubled, resulting in exponential increase of the specific
DNA fragment over time.
5. Final elongation: This step performed at a temperature of 70 to 74 oC for 5 to 15
minutes after the last PCR cycle ensuring that any remaining single-stranded DNA is
fully extended.
6. Final hold: Temperature is reduced to 4 to 15 oC for an indefinite time for short-
term storage of the DNA samples.
CHAPTER 1. INTRODUCTION 8
1.2 Conventional Bench-top DNA Analysis Methods
Analysis of specific biomolecules, such as proteins and nucleic acids, finds applica-
tions that range from disease diagnostics to forensics. Detection, identification, and
quantification of nucleic acid sequences such as DNA, messenger RNA (mRNA), and
micro-RNA have recently been exploited for the diagnosis, prognosis, and treatment
choices for heredity and infectious diseases [3,4], the monitoring of the quality of food
and water [5], and the detection of bio-warfare agents [6].
1.2.1 Optical Fluorescent DNA Sensing
Fluorescence-based DNA sensing is currently the gold standard technique for DNA
analysis. It finds applications in gene expression [29], pharmacogenomics [32] and
drug development analysis [33].
As shown in Fig. 1.3, in this method groups of ssDNA probe molecules are immo-
bilized in an array format on a passive substrate. The DNA probes can be constructed
using solid-phase chemical synthesis techniques and they are immobilized on the mi-
croarray though spotting or non-contact ink-jet printing. ssDNA target molecules are
tagged with chemical labels. After absorbing a photon at a specific wavelength, these
labels emit photons at a higher wavelength. Common labels are fluorescent dyes and
fluorescent which emit lights with wavelength in the range of 500 to 700nm.
When the target ssDNA molecules are introduced onto the microarray, the probe
molecules and the complementary target molecules hybridize. The array is usually
exposed to the target molecules for several hours so that the hybridization reaches an
equilibrium. Next the array is washed so that the un-bonded targets are removed. The
washing step is a major drawback of optical DNA analysis method as it eliminates the
possibility of real-time monitoring of the hybridization. This is due to the fact that the
CHAPTER 1. INTRODUCTION 9
Modify substrate to
accept DNA probes
Immobilize and
pattern probesReact with DNA
target analyte
Scan and process
microarray
DNA target DNA probe
Fluorescence labeled
Sequence 3
Sequence 1
Sequence 4
Sequence 2
Figure 1.3: A fluorescence-based DNA microarray [14].
analyte must be removed from the array before a meaningful measurement can be done.
Next, as shown in Fig. 1.4, the microarray is illuminated with a laser light source
and the fluorescence light emitted from the hybridized DNA strands is recorded using
an image sensor (charge coupled device (CCD) or photomultiplier tube (PMT)) with
the help of necessary optical lenses and filters. The intensity of the emitted light is a
measure of the number of target DNA strands that are hybridized on the surface of the
microarray.
Optical DNA sensing instruments are in general bulky and expensive due to the need
for a laser source, optical lenses and filters. Another drawback of optical DNA sensing
is the labeling requirement of the target DNA, which is a costly and time consuming
process. Optical DNA sensing methods are in general slow. This is due to sequen-
tial scanning of the DNA microarrays by the image sensor, which requires mechanical
movement of the microarray or the image sensor as shown in Fig. 1.4. On the other
CHAPTER 1. INTRODUCTION 10
LASER
PMT
Excitation
lter
Emission
lter
Pin holeBeam
splitter
Mirror
Mirror
Sample
Figure 1.4: A typical scanner for fluorescence-based DNA detection [14].
hand the detection limit of DNA sensing instruments is very low and they can detect
signals down to 10 million hybridized target molecules per centimeter squared [34].
1.2.2 Commercial Optical DNA-Sensing Instruments
The Affymetrix GeneChip Scanner 3000 7G (Fig. 1.5 (a)) is an example of commer-
cially available optical fluorescent-based DNA microarray. Its dimensions are 33 × 46
× 56 cm3, and its weight is 32kg [35].
Agilent offers a variety of fluorescent-based DNA microarray scanners for DNA
sequencing. SureScan Microarray Scanner (Fig. 1.5 (b)) is one such example. Its di-
mensions are 42 × 43 × 67 cm3, and its weight is 56.8kg [36].
Spartan Bioscience produces a 4 kg portable fluorescent PCR-based DNA analyzer
(Fig. 1.5 (c)) that processes 12 samples, typically medical ones, in one hour [37].
There are also hand held lateral flow immunoassay pathogen testers such as the one
from Idetekt [43], but they are limited in their specificity and sensitivity.
CHAPTER 1. INTRODUCTION 11
(a) (b) (c)
Figure 1.5: Commercially available fluorescence-based DNA microarray scanners: (a)Affymetrix GeneChip Scanner 3000 7G [35], (b) Agilent SureScan Microarray Scanner [36],and (c) Spartan RX microarray scanner [37].
1.2.3 pH-based DNA Sensing
pH-based DNA sensing is a new alternative method to the optical DNA sensing that is
commonly used for DNA sequencing. DNA sequencing is the process of determining
the order of nucleotides (adenine, guanine, cytosine, and thymine) within a DNA strand.
As shown in Fig. 1.6 (a) [41], in this method an array of pH sensors are implemented
on a chip. Next an array of micromachined wells is placed on top of the pH sensors and
a single ssDNA strand probe is placed in each well.
The principle of label-free electrochemical DNA detection using pH sensors is de-
scribed in detail in [5]. In general the ssDNA strand is activated with an enzyme at
one of its end. The enzyme facilitates the bonding of the complementary base pair to
the ssDNA strand. Once the bonding of one base pair is done, the enzyme moves up
the DNA strand by one base pair thus enabling the next location to bond with the next
complimentary base pair molecule.
In a pH-based DNA sequencing microsystem, DNA base pairs (A, T, C or G) are
sequentially washed over the ssDNA. When a base pair bonds to the ssDNA strand, a
H+ ion is released changing the pH of the reagents inside the sensing well in which
the match took place. pH sensors are sensitive to the pH level (concentration of H+
CHAPTER 1. INTRODUCTION 12
ions) of reagents inside the sensing well and they convert this change in the pH into
an electrical signal as shown in Fig. 1.6(b). No signal is generated if there is no match
between the DNA base pairs and the probe DNA as shown in Fig. 1.6(c). This change
in the electrical signal can be used to sequence the target DNA.
pH sensors are in general implemented as an ion sensitive field effect transistor
(ISFETs) that can be readily fabricated on a CMOS chip with no post processing re-
quirements. This allows for low production cost and scalability of the DNA sensor. Ion
Torrent has reported a pH based DNA sensing CMOS chip with 1024 sensing sites on
a single chip [41]. The drawback of the pH based DNA sensing is large variation in
the electrical sensitivity of the on-chip pH sensors and also the drift in their sensing
properties over time. Extensive digital calibration circuitry is implemented to cancel
out the sensor-to-sensor variations and calibrate a DNA sequencing system over time
for the drift in the pH sensors electrical properties.
1.2.4 Commercial pH-based DNA Sensing Instruments
Ion Torrent offers a 60 kg rapid, genome-scale benchtop sequencing system (Fig. 1.7
(a)) based on pH sensors that produces one Gb of sequence data in a one run of two
hours. The system is capable of processing both short-base and long-base pair DNA
sequences with ranges from 35 to 400 base pair [41].
DNA Electronics is developing a hand-held, USB-connected, DNA sensing microar-
ray based on pH sensors as shown in Fig. 1.7 (b). The DNA microarray contains 40
sensing sites and enables nucleic acid tests (NATs) from sample to detection in under
30 minutes. The system is currently under development.
GeneOnyx offers a tissue box-size DNA analyzer based on pH sensors [42], as
shown in Fig. 1.7 (c). GeneOnyx is primarily used in skin care and is tailored for
recommending skin care solution and cosmetic products based on individual genetic
CHAPTER 1. INTRODUCTION 13
(a)
(b)
(c)
Figure 1.6: pH-based DNA sensing: (a) system cross-section, (b) complementary DNA se-quence and (c) and non-complementary DNA sequence [41].
CHAPTER 1. INTRODUCTION 14
(a) (b) (c)
Figure 1.7: Commercially available pH-based DNA-sensing instruments: (a) Ion Torrent [41],(b) DNA Electronics [44], and (b) GeneOnyx [42].
variation.
1.3 Existing Integrated Circuits for DNA Sensing
The size, weight, and price of today’s commercial DNA-sensing and sequencing mi-
crosystems make them impractical for use in point-of-care diagnostics applications. If
nucleic acid detection is to be widely used globally and at the point-of-care, the de-
tection process has to offer high throughput and automated, portable analysis at a low
cost.
A number of lab-on-a-chip systems based on complementary-metal-oxide-semiconductor
(CMOS) integrated circuit technology have been developed that translate nucleic hy-
bridization events to optical [15], pH [97], magnetic [16], and capacitive [17] signals.
These systems typically feature an array of single-stranded nucleic acid probe DNA
sequences that are immobilized on a solid surface. At the time of the capture of com-
plementary target sequences through Watson Crick base pairing, the sensor transduces
a measurable signal. A brief description of the most popular methods is presented next.
CHAPTER 1. INTRODUCTION 15
1.3.1 CMOS Fluorescent DNA Contact Imaging
Fluorescent DNA on-CMOS contact imaging relies on the same principle as bench-
top optical fluorescence-based DNA sensing as described in Section 1.2. Unlike the
standard optical fluorescence-based DNA sensing, in contact imaging the DNA probes
and targets are placed close to the CMOS image sensor focal plane [55–57]. This elimi-
nates the need for bulky and expensive lenses and mirrors, thus enabling miniaturization
of the DNA detection microsystem. Various on-chip color filters and color-selective
CMOS imagers have also been developed [58–61]. The latter eliminates the need for
optical filters thus further reducing the cost and the size of the DNA sensing microsys-
tem. The only part of the system that can not be integrated into the CMOS chip is the ex-
citation light source [60], which can be bulky and expensive. This method also requires
DNA labeling which is a major drawback compared to electrochemical amperometric
DNA sensing CMOS microsystems described next which can be label-free [58].
1.3.2 CMOS Magnetic Field-Based DNA Sensing
In recent years magnetically labeled biosensors have shown promising results in provid-
ing an alternative solution to the optical instruments used by conventional fluorescence-
based sensors [45–49]. Magnetic biosensors have the potential to achieve high sensitiv-
ity at low cost and low power consumption levels for a variety of applications such as
in-field medical diagnostics, epidemic disease control, biohazard detection and analy-
sis.
In general, magnetic field-based on-CMOS DNA sensing requires tagging of DNA
strands with a magnetic microbead, and also needs a giant magnetoresistance (GMR)
[45] and a bead counter [45, 46]. One major drawback of the traditional magnetic
biosensor is the requirement of externally generated magnetic biasing fields (to imple-
ment the GMR) [46, 47] in conjunction with exotic post-fabrication processes [48, 49].
CHAPTER 1. INTRODUCTION 16
This significantly increases the system form-factor, increases total power consumption
and cost.
A typical magnetic based DNA sensor operates in the following steps [45]:
1. ssDNA probes are immobilized on a gold electrode surface using gold-thiol chem-
istry.
2. Target DNA strands are extracted from the sample, denatured, and labeled with
the magnetic microbeads.
3. Target DNA is allowed to hybridize with the probes and the sensor spots are then
washed to remove any un-hybridized strands.
4. The sensor spots are subjected to an applied magnetic field (using the GMR), and
the CMOS chip picks up the resulting bead signal [45].
Recently an RF-based on-CMOS magnetic DNA sensors has been proposed to elim-
inate the need for the bulky GMR and the bead counter [25]. The system was imple-
mented in bulk CMOS and provides single bead detection sensitivity without any ex-
ternal magnets. In this method an RF electrical current is passed through the on-chip
inductor generating a magnetic field which polarizes the magnetic particles present in its
vicinity. Probe DNA are deposited on the surface of the on-chip inductor. Hybridization
of the the target DNA (tagged with the magnetic bead) with the probe DNA results in a
change in the inductor magnetic field, thus changing the inductance of the on-chip in-
ductor. A voltage-controlled oscillator (VCO) combined with a frequency-shift sensing
scheme is utilized to measure the change in the inductance value thus quantifying the
number of target DNA that have hybridized. Such a system [25] did not achieve results
comparable to the traditional magnetic field-based DNA sensors due to the complexity
of the RF receiver and sensitivity of the RF receiver to the environmental noise.
CHAPTER 1. INTRODUCTION 17
1.3.3 CMOS Capacitance-Based DNA Sensing
Another common method for on-CMOS DNA sensing is capacitance-based DNA sens-
ing [17, 21, 50, 51]. This method is a sub-set of the impedance spectroscopy method
[144] described in Section 1.5.2 as it senses the change in the electrode capacitance
CDB due to the DNA hybridization. In general in this method two gold electrodes are
placed in close proximity (1-10µm) [17] resulting in a simple two-plate capacitor with
the electrolyte solution acting as the dielectric. Next ssDNA probes are immobilized
on the surface of one, working, electrode using gold-thiol chemistry. A capacitance
measurement is conducted at this stage to measure the electrode capacitance before
hybridization. Next, target DNA is allowed to hybridize with the probe DNA and the
electrodes are washed after hybridization to remove any un-hybridized DNA strands. It
has been observed that the capacitance CDB decreases when the target DNA molecules
bond with the probe DNA [17]. The change in the capacitance can be mapped to the
target DNA concentration.
There are various methods to measure the change in the electrode capacitance in
CMOS. The most commonly used method is capacitance-to-frequency conversion as
described in [21, 50, 51].
1.4 Amperometric Electrochemical Sensing Principles
As described in Section 1.2, many conventional DNA-based pathogen detection sys-
tems rely on the gold-standard optical signal readout. Such systems are costly, require
bulky optics, typically require PCR for high sensitivity, and are often slow due to the
serial nature of the optical signal readout. DNA analyzers with non-optical parallel elec-
tronic readout, such as those described in Section 1.3, are a promising cost-effective,
highly sensitive and fast alternative to optical methods, often with their own limitations.
CHAPTER 1. INTRODUCTION 18
Another such method is known as amperometric electrochemical DNA sensing.
Amperometric DNA sensing methods have gained interest in recent years but are not
yet as developed as the optical or pH-based DNA sensing techniques. They have the
potential to reduce the instrumentation cost and provide portable diagnostic platform
for DNA analysis and detection. The main advantages of amperometric sensing versus
gold-standard optical are the elimination of light as the source of excitation and thus of
bulky optical equipment, and the real-time nature of DNA sensing. This provides an
opportunity to design and prototype a portable real-time DNA sensing microsystem for
point-of-care applications.
The polymerase chain reaction (PCR) is commonly utilized to increase the con-
centration of the target DNA in a sample, thus increasing the detection accuracy. As
described in Section 1.1.3, PCR is a procedure in biochemistry to amplify a single or a
few copies of a DNA sequence, generating up to millions of copies of the same DNA
sequence [62, 63]. This method relies on thermal cycling which consists of cycles of
repeated heating and cooling for DNA melting and enzymatic replication of the DNA.
This is generally costly and time consuming.
Signal transduction is typically performed by coupling the target sequence with a
reduction-oxidation (redox) or fluorescent label with a well-defined and easily detected
electrochemical or optical signature, respectively. This is known as label-based sensing
which requires sample labeling and the corresponding cost and time.
Label-free detection of DNA hybridization is also possible, by monitoring the elec-
trical signals, such as current, voltage, impedance, and conductance, at the sensor’s
solid-liquid interface. There are several label-free electrical nucleic acid detection plat-
forms, but most of these techniques rely on off-chip, expensive, and bulky instrumenta-
tion for signal readout and processing, characteristics that make the techniques unsuit-
able for many point-of-need and in-field applications.
CHAPTER 1. INTRODUCTION 19
Amperometric electrochemical DNA sensors [20, 21, 23–28, 99] have emerged as
a low-cost, high-throughput, and real-time alternative to conventional optical and pH-
based sensory methods. Electrochemical amperometric DNA analysis techniques have
the potential to provide real-time, label-free, PCR-free sensing in portable detection
platforms.
1.4.1 Three-electrode Sensing Configuration
Electrochemical sensing involves a chemical reaction that occurs on the surface of an
electrode in the presence of a potential difference. The chemical reaction results in a
charge transfer which results in a current or a voltage output. The current-mode output
has a wide dynamic range and is commonly used. Sensing methods in which a current
is measured are known as amperometric electrochemical sensing methods [66, 67].
A block diagram of a three-electrode electrochemical amperometric sensing sys-
tem is depicted in Fig. 1.8 [68]. It consists of a working electrode (WE), a reference
electrode (RE), a counter electrode (CE), a waveform generator and a current-to-digital
channel. In this configuration the waveform generator drives the reference electrode.
The working electrode is held at a known potential, VWE by the current-to-digital chan-
nel. In general the voltage difference between the working and reference electrode is set
to VREDOX . This is the voltage at which the chemical under test is reduced or oxidized.
The IWE current generated due to the voltage difference between the working and ref-
erence electrodes is recorded by the current-to-digital channel. If the voltage difference
is set to VREDOX , the resulted current is called IREDOX , which is the current generated
due to the reduction and oxidization of the chemical species.
In applications where the redox current level is high (greater than 1µA), there could
be a significant voltage drop between the working and reference electrode (due to the
finite impedance of the electrolyte solution) if the redox current is to flow from the
CHAPTER 1. INTRODUCTION 20
DIGITAL
OUTPUTCURRENT-TO
DIGITAL
CHANNEL
RE
RE CE
PROBE
DNA
TARGET
DNA
CE
WE
WAVEFORM
GENERATOR
REV
CEV
WEV
REDOXI
WEV
Figure 1.8: Conceptual view of an electrochemical amperometric sensing microsystem.
reference electrode to the working electrode. As a results of this voltage drop, the ac-
tual voltage in the vicinity of the working electrode will not be the same as the voltage
that was set by the reference electrode. This can significantly affect the redox poten-
tial required by the electrochemical experiment. To solve this issue a third (counter)
electrode is added to the electrochemical cell. In this configuration no current flows
from the reference electrode to the working electrode. The counter electrode provides
the current required to keep the voltage difference between the working and reference
electrodes exactly at the redox potential. In general the counter electrode is not required
for low-current applications (less than 1µA).
In amperometric electrochemical DNA sensing applications the working electrode
is coated with a single-stranded DNA (ssDNA) probe. Binding of the probe ssDNA
with the target ssDNA results in a variation of the working electrode surface properties
such as impedance or surface charge. The variation of the surface properties results in a
change in the recorded value and waveform features of the redox current, thus indicating
CHAPTER 1. INTRODUCTION 21
CWE
RS
RCT
CDB
+
+
-
-
-
-
-
+
+
+
WERE
RE WE
ELECTROLYTE
SOLUTION
DIFFUSION
LAYER
DOUBLE
LAYER
+
-PROBE
-TARGET
-
-
-
-
-
++
+ +
-REDUCTION
-OXIDATION+
+
-H O2
Figure 1.9: Charge profile of the electrode-electrolyte interface and its equivalent circuit model.
the thermodynamics and kinetics of chemical reactions at the sensory interface. In most
biochemical sensing applications the recorded redox current is in the range of pA to
nA [69–71].
Electrochemical amperometry provides a wide range of concentration measurement
because of its linear behavior. Cyclic voltammetry and impedance spectroscopy are
two common amperometric sensing methods. In general, the reference electrode poten-
tial, VRE , is set to a bidirectional ramp voltage for cyclic voltammetry or to a small-
amplitude sinusoid for impedance spectroscopy.
1.4.2 Electrode-Electrolyte Interface
When an electrode is in the presence of an electrolyte solution containing solvated and
unsolvated anions and cations and water molecules, a layer of charge forms at the
electrode-electrolyte interface in order to maintain the electrical neutrality, as shown
in Fig. 1.9. This layer can be electrically modeled by a set of resistors and capacitors.
A generic R-C biosensor impedance model is also depicted in Fig. 1.9. The counter
electrode is omitted for simplicity. In this model RS represents the electrolyte resistance
between the working and reference electrodes, CWE represents the diffusion layer ca-
CHAPTER 1. INTRODUCTION 22
pacitance, CDB models the interfacial double-layer capacitance at the WE-electrolyte
interface and RCT models the charge transfer resistance at the WE-electrolyte inter-
face [84]. The double layer consists of solvated positive ions physically separated from
the working electrode surface by a monolayer of water molecules and ions attached to
the working electrode surface. The diffusion layer is the layer beyond the double layer
where the capturing probe molecules are located. The ssDNA probes are negatively
charge, thus attracting the positively charged ions from the electrolyte solution.
1.4.3 Reduction-Oxidation Current
An example of the mechanism of generation of the redox current is also shown in
Fig. 1.9. In the presence of a potential difference between the working electrode and
the reference electrode the electroactive chemical species of the electrolyte solution
are either reduced (gain an electron) or oxidized (lose an electron). The amount of
charge transferred between the electrolyte solution and the working electrode depends
on the surface charge. The surface charge in term depends on the density of the target
molecules that are bonded to the probes. Measuring the current corresponding to the
charge transfer yields a measure of the concentration of the target molecules.
1.4.4 Labeled vs Label-free DNA Sensing
Amperometric electrochemical DNA sensors can be divided into two main categories:
label-based and label-free. In the label-based techniques an electroactive chemical label
is attached to the target DNA to provide a positive electrochemical signal. This signal
can also be derived from a redox indicator that associates with a ssDNA differently than
with a DNA duplex. On the other hand, a label-free DNA sensor does not require any
supporting redox species, indicator molecule or enzymes to provide the electrochemical
signal. This method relies on the oxidation of individual DNA bases or change in the
CHAPTER 1. INTRODUCTION 23
electrode-electrolyte interface properties such as capacitance and resistance changes
due to DNA hybridization.
1.4.5 Electrode Material
In general an electrochemical cell consists of a working electrode, a counter electrode
and a reference electrode.
A wide range of materials are used to fabricate working electrodes. These include
carbon, polymers and metals as shown in Fig. 1.10. The working electrode material is
chosen such that it provides a polarizable interface when it is in contact with the elec-
trolyte solution [26]. In this work gold (Au) has been chosen as the working electrode
material. Gold has the advantage of being electrochemically inactive and it does not
react with the electrolyte solution under normal operating conditions. Also, gold work-
ing electrodes can easily be fabricated on a CMOS chip, forming on-chip integrated
working electrodes. Another advantage of gold working electrodes is that it enables
straight-forward DNA attachment chemistry [26].
The reference electrode must meet the following criteria [78]:
• Must have a high exchange current density and be non-polarizable.
• The electrode potential must be reproducible.
• The electrode potential drift must be small during the life time of the electrode.
Depending on the application and solution chemistry, different reference electrodes
can be used. Due to its simple construction and the above-mentioned properties, silver
(Ag) coated by a layer of silver chloride (Ag/AgCl) is the most commonly used material
for a reference electrode. A conventional commercially available reference electrode
consists of a silver wire coated with silver chloride that is immersed in a Cl ion solution
CHAPTER 1. INTRODUCTION 24
such as KCl. The silver wire and the KCl solution are enclosed in a glass tube and
separated from the solution that is under test by an ion exchange membrane and a salt
bridge [79].
Another common type of the reference electrode is the saturated calomel electrode
(SCE), which consists of mercury covered by mercury chloride pates that are in contact
with saturated KCl solution and enclosed in a glass tubing. The advantage of this elec-
trode is its simple construction and stable potential. However, the toxicity of mercury
makes its use hazardous [80].
Another common reference electrode in electro-chemical sensing is the standard
hydrogen electrode. The electrode is constructed with a platinum surface that is covered
with black platinum. The black platinum helps with the reduction of protons and is a
catalyst for the electrode reaction. The platinum is submerged in an acidic solution.
The reference electrode cell is confined in a glass enclosure and is pressure- controlled
to keep the hydrogen pressure fixed and to maintain the electrode’s potential [81, 82].
Due to its non-reactive nature, platinum (Pt) is the most commonly used material
choice for counter electrode. Other nobel metals such as gold can be used as well [26].
In this work Au electrodes are used for the working and counter electrodes and off-
chip commercially available Ag/AgCl electrodes are used as the reference electrode.
In future work we are planning to implement the Ag/AgCl electrode on-chip using
the post-processing method described in [83] applied to the implemented on-chip Al
reference electrode bases.
1.5 Amperometric Electrochemical Sensing Methods
Different amperometric electrochemical sensing methods are distinguished by the wave-
form of the voltage difference between the working and reference electrode. The two
CHAPTER 1. INTRODUCTION 25
WE
(c)(b)
60µm
(a)
Figure 1.10: Working electrode material examples: (a) diamond [71], (b) polymer [20], and (c)flat gold [70].
OXIDATION
VOLTAGE
REDUCTION
VOLTAGE
VW
E-V
RE
REVERSE
SCAN
FORWARD
SCAN
TIME
Epc
Epa
VWE
I RE
DO
X
-VRE
OXIDATION
PEAK
REDUCTION
PEAK
BACKGROUNDTARGET CHEMICAL
REVERSE
SCAN
FORWARD
SCAN
Epa Epc
(a) (b)
Figure 1.11: Fast-scan cyclic voltammetry principle of operation (a) cyclic redox potential ap-plied between the working and reference electrode, and (b) cyclic voltammogram in the absenceand presence of the target chemical.
most commonly used electrochemical sensing methods are: cyclic voltammetry (CV)
and impedance spectroscopy (IS). Both have to be thermally regulated as the redox cur-
rent is highly dependent on the temperature [19]. In this work all these three methods
are implemented on-chip to perform thermally-regulated label-free DNA detection and
cross-validation.
CHAPTER 1. INTRODUCTION 26
1.5.1 Fast-Scan Cyclic Voltammetry
In the fast-scan cyclic voltammetry (CV) method, a cyclic ramp potential is intermit-
tently applied between the working and reference electrodes, as shown for one period
in Fig. 1.11(a). The time between scans, which can vary, determines the temporal reso-
lution of the technique. The halt time prevents successive scans from influencing each
other. The cyclic voltammogram shown in Fig. 1.11(b), represents the redox current
versus the applied redox potential and provides chemical information about the sub-
stance under measurement. For example, the location of the reduction and oxidation
peaks acts as a unique chemical identifier for different chemicals. The reduction and
oxidation peak heights change for different chemical concentrations. A background
current is generated due to the transient changes of the applied voltage (Fig. 1.11(b)).
This current occurs mainly because of the charging and discharging of the double layer
capacitance associated with the electrode-electrolyte interface. The background current
is proportional to the scan rate and also to the double layer capacitance.
1.5.2 Amperometric Impedance Spectroscopy
Impedance spectroscopy (IS) is a popular method of quantitative and qualitative moni-
toring of chemical reactions in many biosensors. A wide range of biosensors have been
developed which rely on impedance spectroscopy, including sensors for detection of
enzymes, antibodies and DNA [85, 86].
In the IS method, a small-amplitude perturbing sinusoidal voltage, as shown in
Fig. 1.12(a), is applied between working and reference electrode and the subsequent
current response is measured. The impedance is calculated as the ratio of the applied
voltage to the resulting current. A frequency response plot of a biosensor, as shown
in Fig. 1.12(b), is computed by applying a variable frequency excitation signal and
computing the biosensor impedance at each frequency point. The biosensor frequency
CHAPTER 1. INTRODUCTION 27
VWE-VRE
TIME FREQUENCY
CHANGE IN CHEMICAL
CONCENTRATION
I RE
DO
X
(a) (b)
Figure 1.12: Impedance spectroscopy principle of operation (a) potential difference betweenworking and reference electrode, and (b) change in redox current frequency response due to thechange in the chemical concentration.
response is directly related to the concentration of the electroactive substance.
1.5.3 Temperature Regulation for DNA Analysis
Temperature reliance is a key constraint in DNA sensing. DNA hybridization is highly
dependent on the temperature [4–6,19], and as a result, temperature plays an important
role in the sensitivity of DNA sensors. It is shown in [7] that the redox current is highly
dependent on the temperature. Generally the redox current drops by 10 percent, given
a 10 degree increase in the temperature above the ambient temperature. A temperature
regulation system for DNA sensing that has on chip-heating, temperature sensing and
regulation circuits, would be of great benefit for both the characterization and sensing
of DNA. Such a system would increase the accuracy of the measurements, improve the
speed and efficiency of the analysis, and also reduce reagent usage and improve the
sensitivity limit of the measurements.
CHAPTER 1. INTRODUCTION 28
1.5.4 Commercial Amperometric Instruments
Early Warning Inc. offers a beta-version of its amperometric biohazard water analyzer
that employs carbon nanotube DNA sensors to detect E.coli O157:H7, as shown in
Fig. 1.13(a). The analyzer weighs 200 kg and promises to detect up to 25 pathogens
in 10L of water within three hours, with the sensitivity of one bacterium cell per
100mL [38].
Palm Sens Inc offers Palmsens 3, Fig. 1.13(b), which is a portable wireless cur-
rent recording frontend (potentiostat) for electrochemical recording applications [39].
The unit consist of one current-to-digital recording channel and a wireless bluetooth
transmitter. The unit weighs 450g and achieves an 8 hour wireless battery powered
operation. It has an input dynamic range of 100pA to 10mA.
Metrohm Inc offers PSTAT mini [40], Fig. 1.13(c), which is a single channel portable
potentiostat weighting 0.985kg. The unit achieves an input dynamic range of 2nA to
200A and can be directly interfaced to DNA sensing microelectrodes.
The bulky and expensive commercially available instruments described in Sections
1.2.2, 1.2.4 and 1.5.4 generally attain very high sensitivity (0.1nM). Routine quantita-
tive pathogen detection with low-cost, fast (under one hour), highly specific (multiple
strands), and medium to high sensitivity (10µM down to 0.1nM) biosensors in an inte-
grated and portable lab-on-chip platform is a sought-after goal that is not yet commer-
cially available.
1.6 Integrated Circuits for Amperometric DNA Sensing
Several electrochemical DNA detection microsystems utilizing cyclic voltammetry (CV)
have been reported [20, 21, 26, 96, 97, 99]. The design in [99] is a 50-channel pro-
grammable electrochemical biosensor array implemented in a 0.13µm standard CMOS
CHAPTER 1. INTRODUCTION 29
(a) (b) (c)
Figure 1.13: Commercially available amperometric instruments: (a) Early Warning biohazardwater analyzer [38], (b) Palmsens 3 [39], and (c) PSTAT mini [40].
technology. The microsystem includes flat gold electrodes and analog recording chan-
nels, and utilizes impedance spectroscopy for DNA detection. The implementation
in [96] consists of one recording channel and 24×16 recording electrodes implemented
in a 0.5µm CMOS technology. The design, which consists of a three-electrode regula-
tion loop and an analog recording channel, utilizes CV for DNA detection and analysis.
A 128-channel DNA analysis microsystem implemented in a 0.5µm CMOS technology
is presented in [21]. The microsystem consists of on-chip gold electrodes, a three-
electrode regulation loop, and an in-pixel ADC. The design presented in [20] is imple-
mented in a 0.5µm CMOS technology and consists of 24 recording channels with an
in-channel ADC, 24×24 polymer-functionalized sensing electrodes, and a temperature
sensor. The microsystem utilizes CV for DNA detection and analysis. The design
in [26] presents the first fully-integrated CMOS DNA analysis microsystem, which
consists of 16 recording channels, a three-electrode regulation loop, a flat gold DNA
sensing microelectrode, and an in-channel ADC.
Several DNA analysis SoCs based on impedance spectroscopy have been reported
[84, 130, 131]. The design in [130] is a single-channel impedance extractor based on a
lock-in amplifier that extracts the sensor impedance from 1Hz to 10kHz. The implemen-
tation in [84] is a 100-channel impedance-to-digital converter based on a delta-sigma
modulator capable of extracting sensor impedance from 1mHz to 10kHz at the expense
CHAPTER 1. INTRODUCTION 30
of a long conversion cycle. A direct conversion receiver without an on-chip ADC [131]
extracts the electrode impedance from 10Hz to 50MHz at the cost of consuming 104mW
of power.
1.7 Main Specifications for Amperometric Electrochem-
ical DNA Sensing Integrated Circuits Design
1.7.1 Accuracy
Amperometric electrochemical DNA sensors use selective binding and interaction be-
tween probe molecules and target molecules to generate a detectable electrical signal
that correlates with the presence or absence of target molecules. The main components
of any electrochemical DNA sensing system are a molecular recognition layer, a sig-
nal generator, and a readout unit. To generate an electrical target-specific signal, first
the target molecule needs to come into proximity with the probe molecule. The target
molecule’s motion is typically dominated by diffusive spreading, which is a probabilis-
tic mass-transfer. In addition, the nature of the chemical bond forming the interaction
between the probe molecules and the analyte solution is also probabilistic, and the result
is more uncertainty (noise) in the biosensor [9–12, 23].
In addition to these processes, the interrogation signal generation circuits and the
readout circuits also add noise to the biosensor. On top of the noise generated by the
binding process and the electronic circuit, the binding of other species to the probe
molecules (non-specific binding) also adds noise to the system. Non-specific binding
is generally less frequent than specific binding if the concentration of both the specific
and non-specific analyte is in the same order of magnitude. If the concentration of non-
specific molecules becomes much larger than the concentration of the target molecules,
CHAPTER 1. INTRODUCTION 31
then the non-specific binding (noise) can overcome the detectable signal and thus in-
creases the minimum detectable level (MDL) [13]. Based on the biosensor noise, we
can define the MDL, the highest detection level (HDL), and the detection dynamic range
(DR).
In [23], a noise model was developed to capture the biosensor MDL, HDL, DR, and
SNR (signal-to-noise ratio). The model was applied to a simple biosensor that consisted
of a signal generator, an electrode-eletrolyte interface, and a generalized recording cir-
cuit. Fig. 1.14 plots the SNR of the generalized biosensor model vs. the analyte concen-
tration (DNA molecule concentration) in different background solution concentrations.
In an ideal system, increasing the concentration of analyte generates more noise, but, at
the same time, generates larger signals, a process that results in a linear increase of SNR
vs. analyte concentration. In a practical biosensor, this outcome is not possible, since
the probe saturation occurs, and, as a result, SNR drops as the analyte concentration
increases. As shown in Fig. 1.14, the HDL is limited by saturation and the finite value
of the probe density. The maximum SNR of the generalized biosensor model in [21]
is about 55dB, and the limiting factor is probe saturation and biochemical noise. The
overall dynamic range of the system for an SNR of 30dB varies from 84dB to 104dB,
depending on background solution concentration.
Based on Fig. 1.14 results, the conclusion may be drawn that the minimum SNR of
the interrogation signal generation and recording circuitry should be larger than 55dB,
which corresponds to approximately effective number of bits (ENOB) of 9-bits.
The model developed in [23] is only valid for flat gold electrode. The concentration
range that is presented in this plot is similar to the DNA concentration range that was
successfully detected by the CMOS DNA detection microsystem as presented in Section
3.8. The model developed in [23] is not valid for the nanostructured electrodes. Similar
model for the nanostructured electrodes have not been developed in the literature.
CHAPTER 1. INTRODUCTION 32
Figure 1.14: Biosensor SNR vs target analyte concentration [23].
1.7.2 Dynamic Range
In [26–28, 69, 70, 99], the output redox current level from a typical on-chip working
electrode (10µm to 100µm diameter) in electrochemical DNA-sensing applications is
shown to be in the range of low pA to mid nA. As a result, in this work, the current
range specification of the system is set to cover a range from one pA to 500 nA.
1.7.3 Frequency Range
In electrochemical sensing methods such as cyclic voltammetry and impedance spec-
troscopy, a high-frequency interrogation waveform generates a large background cur-
rent due to the charging and discharging of the double-layer electrode-electrolyte ca-
pacitor. The large background current puts stringent requirements on the accuracy and
dynamic range of the electrochemical recording front end. To relax the accuracy and
CHAPTER 1. INTRODUCTION 33
dynamic range requirements in general, the interrogation waveform frequency range of
electrochemical sensing systems is limited to a maximum 10 kHz [26].
1.7.4 Non-electrical Design Specification
The ultimate goal in this thesis is design and development of a low-cost semiconductor-
based technology for rapid and sensitive in-field DNA analysis of various DNA strands.
As a result, small form-factor, low-cost, high-throughput, as well as label-free and PCR-
free operation are the most important non-electrical design requirements of the DNA
sensing microsystem.
The size and the cost of the DNA sensing microsystem needs to be minimized to
enable widespread in-field utilization. This would require integration of both DNA
sensing electrodes and circuitry on the same chip. CMOS integrated circuits provide
versatile signal acquisition and processing functionalities at a low cost. The large scale
of integration allows for hundreds of sensors to be placed directly on a chip for simulta-
neous high-throughput sensing. On-chip microsensors are directly suitable for CMOS
surface functionalization yielding high sensitivity and selectivity thus eliminating the
need for the PCR amplification step which is both time consuming and expensive. Di-
rect deposition of sensors on a chip eliminates costly excessive wiring and minimizes
the interference noise. Label-free operation of the microsystem also eliminates the
costly and time-consuming labeling process further reducing the overall cost of the
DNA sensing microsystem.
CHAPTER 1. INTRODUCTION 34
WERE
ADC
AM
PE
RO
ME
TR
IC
RE
AD
OU
T
WE
CC
V
EXCITATION
WAVEFORM
IREDOX
TIA
CURRENT
ACQUISITION
CIRCUIT OUTV
OUTI
BIOSENSOR-
FUNCTIONALIZED
SURFACE
Figure 1.15: Conceptual view of current acquisition circuits for electrochemical amperometricsensory system.
1.8 Additional Considerations for DNA-sensing Amper-
ometric Integrated Circuits Design
1.8.1 Low-Level Current Acquisition for Amperometry
The use of a transimpedance amplifier (TIA) or a current-conveyer (CC) are the most
common approaches for redox current acquisition [26], as shown in Fig. 1.15.
In the TIA approach, the transimpedance amplifier sets a virtual potential at the
working electrode and at the same time generates an output voltage that is propor-
tional to the redox current. This can be implemented as a resistive feedback configu-
ration [89] or a switched-capacitor circuit [90]. The size of the resistor in the resistive
feedback configuration makes it impractical for massively-parallel array sensing imple-
mentations. Additionally in a resistive feedback configuration the thermal noise can be
injected back into the biosensor. The switched-capacitor TIA configuration is a com-
mon choice for arrayed implementations [99]. A circuit diagram of a conventional
transimpedance amplifier with a captive feedback is shown in Fig. 1.16.
A current conveyer (CC), as shown in Fig. 1.17, is another common compact circuit
for measuring the redox current [91]. The WE is held at a virtual potential. Instead
CHAPTER 1. INTRODUCTION 35
−
+
IIN
VWE
VOUTCWE
RS
RCT
RE
CDB
VRE
WE
Figure 1.16: Conventional transimpedance amplifier (TIA) interfaced to a biosensor model.
IIN
VWEIOUT
−
+
CWE
RS
RCT
WERECDB
VRE
Figure 1.17: Conventional current conveyer (CC) interfaced to a biosensor model.
of converting the redox current directly to voltage, it is conveyed from WE to a high-
impedance output node and can then be converted to a voltage. A number of current
conveyer designs for amperometric sensing applications have been reported [91–95]. In
general, these designs do not support bidirectional current recording or offer pseudo-
bidirectional current acquisition capability by means of adding a large bias current to
the input so the current becomes unidirectional [69].
1.8.2 Wireless Data Transmission of DNA Results
Wireless communications capabilities is necessary in applications such as at-home health
care, food safety and water quality monitoring where in-field DNA sensing and analysis
are required.
One such example is placement of the DNA analysis microsystem in a water treat-
ment plant to quickly and accurately monitors the water quality and adjust the treatment
methods to disinfect water for municipal, industrial and residential customers. For ex-
ample in Trojan UV 3000PTP waste water solution [31], shown in Fig. 1.18, the waste
CHAPTER 1. INTRODUCTION 36
Figure 1.18: Trojan UV3000PTP wastewater solution [31].
water is passed thought a set of UV lights that are used for disinfecting the waste water.
The intensity of the UV light in this system is adjusted based on the contamination level
in the water. Currently water samples are taken on daily basis and the samples are sent
to a lab for analysis to determine the effectiveness of the water treatment. Based on the
lab results the UV light level is adjusted to maximize the effectiveness of the disinfec-
tion. The wireless DNA analysis microsystem integrated with a microfluidic chamber
(capable of taking and conditioning the water samples) can be placed inside the waste
water flow. The microsystem can take samples periodically, analysis the contamination
level (by looking for bacterial DNA) and send the results wirelessly to a nearby central
unit. The central unit can transmitter the results over cellular network to the water treat-
ment control center which can adjust the UV light intensity based on the DNA analysis
results.
High number of recording channels and wireless operation of the DNA sensing mi-
crosystem put stringent requirement on the design and choice of the wireless transmitter.
In DNA sensing applications, high number of recording electrodes is required to pro-
vide a sufficient number of probe strands and enough redundancy for accurate results.
CHAPTER 1. INTRODUCTION 37
For example, if a DNA analysis microsystem consists of 500 recording channels each
outputting data at 10kbps, this results in a 5MB/s data rate requirement for the wireless
transmitter. Also, power consumption of the wireless transmitter should be small to
increase the battery life of the wireless DNA analysis microsystem.
A single channel wireless DNA system-on-chip (SoC) based on a monolithic polysil-
icon nanowire CMOS process is reported in [98]. The design utilizes polysilicon nanowires
as DNA sensors and consists of a single recording channel, an on-chip temperature sen-
sor and a wireless OOK (on-off-keying) transmitter.
In this work an ultra-wideband (UWB) transmitter was chosen for wireless data
transmission. Compared to other wireless transmitter architectures such as phase-locked
loop (PLL) based transmitters [72,73] and open loop voltage controlled oscillator (VCO)
transmitters [74–77], the ultra-wideband transmitter achieves lower power consumption
and integration area for the same data rate as the ultra-wideband protocol allows for a
lower-power all-digital implementation of the transmitter as described in Chapter 3.
1.8.3 DNA Temperature Regulation
A number of CMOS temperature sensing and regulation integrated circuits for chemi-
cal sensing applications have been reported in the literature. These microsystems use
a resistive heating and sensing element to form what is known as a micro-hotplate.
The work in [132] presents a temperature sensing and regulation microsystem for bi-
ological applications that achieves a single fixed temperature of 37 degrees Celsius on
the back side of a CMOS chip, with an off-chip digital proportional-integral-derivative
(PID) controller. The work in [135] presents a 3×3 micro-hotplate array for a protein
sensing application. In this design, the temperature of the chip is regulated up to 45
degrees Celsius, with an off-chip digital PID controller. The work presented in [25]
is a 16-channel, frequency-shift CMOS magnetic biosensor array for a protein sens-
CHAPTER 1. INTRODUCTION 38
ing application. The design consists of an array of in-channel heaters, with a single
temperature sensor and an off-chip analog PID controller. The design in [136] is a
digital CMOS micro-hotplate array architecture for a gas sensing application. The ar-
ray consists of 3×3 gas sensing sites, and each site consists of a heater, a temperature
sensors, and a delta-sigma modulated PID controller. The micro-hotplate achieves an
operating temperature of up to 350 degrees Celsius. A 40-channel DNA analysis SoC
based on ISFET sensors for rapid point-of-care DNA detection is reported in [97]. The
design includes an in-channel delta-sigma modulated ADC, in-channel temperature-
sensing elements and heaters, and a dedicated ADC for temperature sensing. A fully
digital on-chip PID controller is utilized for temperature regulation. In summary, exist-
ing closed-loop temperature regulation microsystems generally use either off-chip PID
controllers or on-chip digital PID controllers. This requires large integration area and
high power, typically prohibitive for generating accurate 2D temperature profiles on a
CMOS die as needed for arrayed biosensing applications.
1.8.4 On-chip Computation for DNA Analysis: Analog vs. Digital
vs. Mixed-Signal VLSI Multiplication
Multiplication is the most computationally intensive operation required by the impedance
extraction algorithm (Chapter 4) and the temperature regulation algorithm (Chapter 5).
If the multiplication required by these algorithms can be performed within the recording
channel re-using available mixed-signal VLSI circuits, then significant area and power
can be saved. Conventional analog and digital VLSI multiplication techniques are re-
viewed next and our mixed-signal VLSI approach is introduced last in this section.
A number of analog multipliers have been reported in literature [103–112]. Ana-
log multipliers find applications in a variety of analog signal processing circuits such
as adaptive filters and frequency modulators. The basic idea of an analog multiplier is
CHAPTER 1. INTRODUCTION 39
V (t)1
V (t)2
Nonlinear
Device
V =aV +bV
+cVi i
i
2
3
Nonlinearity
cancellation
scheme
V (t)1
V (t)2
V =O
O
V i
Figure 1.19: Analog multiplier block diagram [103].
Figure 1.20: Analog multiplier circuit schematic.
shown in Fig. 1.19. In an analog multiplier two signals V1(t) and V2(t) are applied to a
nonlinear device. The non-linear device can be characterized by a high-order polyno-
mial function as shown in Fig. 1.19 [103]. This polynomial function generates a number
of terms besides the desirable input product. Next a nonlinearity cancelation circuit is
used to remove the undesired terms and produce the desired V1(t)V2(t) signal.
An example of a fully differential low-power state-of-the-art analog multiplier is
shown in Fig. 1.20 [113]. The input signals are applied to transistors (P1 to P4) and
(N1 to N4) and the products of the input signals are taken at VO1 and VO2. The analog
multiplier achieves a linearity of 4.5 percent for a 200mV input signal while consuming
45µW with a bandwidth of 1GHz. All the transistors in this implementation have the
same size of W/L = 0.8µm/0.35µm. This results in a total area of 40µm2 (including
the routing requirements). Another implementation of a low-power analog multiplier is
presented in [114]. In this work the analog multiplier achieves a linearity of 4.2 percent
for an input range of 120mV while consuming 6.7µW with a bandwidth of 200kHz.
The area and power requirements, the limited input range and linearity degradation
CHAPTER 1. INTRODUCTION 40
Figure 1.21: The block diagram of the 16×16-bit serial multiplier [128].
of analog multipliers makes them unsuitable for high-throughput sensory applications
with stringent power, area and accuracy requirements.
There are several techniques for digital multiplication implementation [115–117,
126,127]. These vary from basic serial multipliers [125] to advanced parallel multipliers
[120–124]. The serial multiplier implements the multiplication in N cycles for an N ×
N-bit multiplier with minimum hardware requirements. Serial multipliers are based on
the principle of shift and add algorithm [126–128]. An efficient adder design provides
the required energy and delay requirements for serial multipliers. A state-of-the-art
implementation of a serial multiplier is shown in Fig. 1.21. The multiplier fabricated
in 45nm CMOS generates an output every 16 clock cycles and consists of 436 logic
cell. It consumes 550pJ/MMPS (multiplications per second) while operating at 0.5V
supply [128].
Parallel multipliers are commonly used in high-speed applications and require more
hardware compared to serial multipliers in order to achieve the speed requirements. The
most commonly used architectures for parallel multiplication are single cycle parallel
multiplier [128] and two-cycle parallel multiplier [129]. The schematic diagrams for
both these implementations are shown in Figs. 1.22 (a) and (b). The single cycle par-
CHAPTER 1. INTRODUCTION 41
(a)
(b)
Figure 1.22: (a) The critical path of the 16×16-bit parallel multiplier and (b) the block diagramof the 16×16-bit two-cycle parallel multiplier [128].
CHAPTER 1. INTRODUCTION 42
allel multiplier fabricated in 45nm CMOS technology generates an output every clock
cycle and requires 1794 logic cells. It consumes 2.5pJ/kMPS while operating at 0.5V
supply [128]. The two-cycle parallel multiplier fabricated in 45nm CMOS technol-
ogy generates an output every clock cycle and requires 1901 logic cells. It consumes
2.6pJ/MMPS while operating at 0.5V supply [128]. Although the digital multipliers
can achieve very low power operation, the area requirements of these multipliers make
them unsuitable for sensory array applications.
In this work the multiplications required by the impedance extraction and the tem-
perature regulation algorithms are performed by an in-channel dual-slope multiplying
ADC (MADC) in the mixed-signal VLSI domain resulting in small area and low power
consumption.
1.9 Thesis Overview
Table 1.1 provides a comparative analysis of existing amperometric biochemical sen-
sory microsystems.
Based on this survey of the current state-of-the-art electrochemical DNA analysis
SoCs, there is currently no wireless DNA analysis SoC capable of performing all key
electrochemical analysis techniques while regulating the test environment temperature.
Integrating a large number of DNA sensing electrodes with on-chip circuits required to
perform various electrochemical analysis techniques and temperature regulation poses
many challenges. The challenges include excessive power consumption, large silicon
area and digital circuits interference with sensitive analog circuits. The work previously
reported in the literature in general lacks sensitive on-CMOS DNA sensing electrodes
capable of performing PCR-free and label-free DNA detection. Also these systems
perform only one electrochemical sensing protocol such as CV or IS and are not capable
CHAPTER 1. INTRODUCTION 43
of regulating the chip temperature while performing DNA sensing.
CHAPTER 1. INTRODUCTION 44
Tabl
e1.
1:C
ompa
rativ
eA
naly
sis
ofA
mpe
rom
etri
cB
iom
olec
ular
Sens
ory
Mic
rosy
stem
s
Syst
emIS
SCC
08JS
SC08
JSSC
09IS
SCC
10B
IOC
AS
09T
BIO
CA
S07
1IS
SCC
101
ISSC
C10
[20]
[26]
[84]
[131
][1
35]
[132
][2
5][9
7]Te
chno
logy
(CM
OS)
0.18
µm
0.25
µm
0.5µ
m0.
35µ
m0.
5µm
0.5µ
m0.
13µ
m0.
6µm
Pow
er25
mW
160m
W0.
6mW
84.5
mW
30m
W—
165m
WN
/ASu
pply
Volta
ge5.
0V2.
5V3.
0V3.
3V5V
5.0V
1.2V
3.3V
Chi
pA
rea
11.2
mm
215
mm
22.
25m
m2
4mm
23m
m2
6mm
27.
5mm
225
.8m
m2
Ele
ctro
deC
ount
576
5410
010
09
116
40C
hann
elSe
nsin
gPr
otoc
olC
VC
VIS
ISC
V—
Mag
netic
CA
Cha
nnel
Cou
nt24
1610
010
09
116
40Ty
peof
Ele
ctro
des
2D2D
2D2D
Mic
roho
tpla
teM
icro
hotp
late
Mag
netic
2DPo
lym
erG
old
Gol
dG
old
pHPo
wer
N/A
10m
W6µ
W0.
84m
WN
/AN
/AN
/AN
/AD
ynam
icR
ange
N/A
60dB
58dB
N/A
Off
-Chi
pO
ff-C
hip
55dB
50dB
Con
vers
ion
Rat
e10
Hz
10kH
z10
kHz
N/A
——
—1H
zSe
nsiti
vity
97pA
240p
A10
kHz
330p
A—
—0.
3Hz
25µ
VE
NO
B11
bits
9bi
ts8
bits
No
AD
C—
—D
irec
tCon
vers
ion
12bi
tsW
avef
orm
Gen
erat
orN
oN
oY
esY
esN
oN
oY
esN
oTy
pe—
—Sq
uare
Wav
eSq
uare
Wav
e—
—Si
neW
ave
—Fr
eque
ncy
(Per
iod)
——
10kH
z50
MH
z—
—1G
Hz
—Po
wer
——
——
——
——
Tran
smitt
erN
oN
oN
oN
oN
oN
oN
oN
oPr
otoc
ol—
——
——
——
—D
ata
Rat
e—
——
——
——
—Po
wer
——
——
——
——
Tem
pera
ture
Sens
ing
Yes
——
—Y
esY
esY
esY
esSe
nsor
Cou
nt1
——
—9
11
40C
ontr
olN
o—
——
PID
PID
PID
PID
——
——
(Ana
log)
(Ana
log)
(Ana
log)
(Dig
ital)
——
——
Off
-Chi
pO
ff-C
hip
Off
-Chi
pO
n-C
hip
Acc
urac
y—
——
—0.
7o
C2
oC
1o
C0.
5o
CSe
nsor
sTy
peD
NA
DN
APr
otei
nD
NA
Prot
ein
—D
NA
DN
AO
n-di
eY
esY
esY
esY
esN
o—
Yes
Yes
Lab
el-f
ree
No
Yes
No
No
No
—N
oN
oPC
R-f
ree
No
No
No
No
No
—N
oY
esB
iom
olec
ule
Type
30B
ase
18B
ase
Bila
yerL
ipid
Bov
ine
Seru
m—
—1K
Bas
eSi
ngle
Nuc
leot
ide
Pair
sPa
irs
Mem
bran
eA
lbum
in—
—Pa
irs
Poly
mor
phis
ms
Con
cent
ratio
n10
nM-1
00nM
100n
M1µ
M10
0mM
N/A
——
1nM
CV
:cyc
licvo
ltam
met
ry,I
S:im
peda
nce
spec
tros
copy
,CA
:con
stan
t-po
tent
iala
mpe
rom
etry
.1
Non
-am
pero
met
ric
bios
enso
rinc
lude
dfo
rcom
plet
enes
s.
CHAPTER 1. INTRODUCTION 45
This thesis presents a CMOS microsystem for amperometric electrochemical DNA
sensing and analysis that overcomes these challenges by employing advanced mixed-
signal VLSI computing circuits to efficiently implement computationally intensive al-
gorithms required for the DNA analysis and by reusing on-chip circuits for multiple
functions in order to save both area and power. The presented system is capable of
performing DNA analysis using both cyclic voltammetry and impedance spectroscopy
while regulating the chip temperature using an on-chip temperature regulator. This
make it universally suitable for a wide range of DNA analysis applications. Addition-
ally, in this work, on-chip nano-textured DNA sensing electrodes were fabricated to
enable label-free DNA analysis utilizing potassium-ferrocyanide redox reporter.
CHAPTER 1. INTRODUCTION 46
D
NA
p
H
CT
AT
PT
AT
×5
4
PID
SR
AM
WE
WE
P
ID
SR
AM
MA
DC
I RE
F
I IN
WAVEFORM
GENERATOR CE
RE
CC
/
TIA
CL
OC
K
G
EN
BIA
S ∑
WAVEFORM
GENERATOR SRAM
HE
AT
ER
PW
M
MU
LT
IPL
ICA
TIO
N
C
OE
FF
ICIE
NT
S
SR
AM
GL
OB
AL
CL
OC
K
GL
OB
AL
B
IAS UWB TX
I RE
F
CH
AN
NE
L
D
NA
×5
4
SR
AM
WE
MA
DC
CE
RE
TIA
CL
OC
K
G
EN
BIA
S ∑
HE
AT
ER
PW
M G
LO
BA
L
CL
OC
K
GL
OB
AL
B
IAS UWB TX
I RE
F
CH
AN
NE
L
CT
AT
PT
AT
×5
4
PID
SR
AM
P
ID
SR
AM
MA
DC
CC
CL
OC
K
G
EN
BIA
S ∑
HE
AT
ER
PW
M
MU
LT
IPL
ICA
TIO
N
C
OE
FF
ICIE
NT
S
SR
AM
GL
OB
AL
CL
OC
K
GL
OB
AL
B
IAS UWB TX
CH
AN
NE
L
(a)
(c)
(d)
I RE
F
I IN
I RE
F
I IN
(b)
MU
LT
IPL
ICA
TIO
N
CO
EF
FIC
IEN
TS
SR
AM
WAVEFORM
GENERATOR WAVEFORM
GENERATOR SRAM
CL
K1
.2 V
I BIA
SV B
IAS
CL
K1
.2 V
I BIA
SV B
IAS
CL
K1
.2 V
I BIA
SV B
IAS
D
NA
p
H
×5
4
SR
AM
WE
WE
MA
DC
I RE
F
I IN
CE
RE
CC
CL
OC
K
G
EN
BIA
S ∑
HE
AT
ER
PW
M G
LO
BA
L
CL
OC
K
GL
OB
AL
B
IAS UWB TX
I RE
F
CH
AN
NE
L
WAVEFORM
GENERATOR WAVEFORM
GENERATOR SRAM
CL
K1
.2 V
I BIA
SV B
IAS
CE
LL
CE
LL
CE
LL
CE
LL
MU
LT
IPL
ICA
TIO
N
C
OE
FF
ICIE
NT
S
SR
AM
Figu
re1.
23:
Reu
seof
the
SoC
arch
itect
ure
reso
urce
s(b
lock
sou
tline
din
bold
are
reus
edin
allm
odes
)(a
)co
mpl
ete
DN
Aan
alys
isSO
C,(
b)cy
clic
volta
mm
etry
confi
gura
tion,
(c)i
mpe
danc
esp
ectr
osco
pyco
nfigu
ratio
nan
d(d
)tem
pera
ture
regu
latio
nco
nfigu
ratio
n.
CHAPTER 1. INTRODUCTION 47
1.9.1 Complete DNA Analysis SoC
The functional block diagram of the wireless electrochemical DNA analysis SoC is
shown in Fig. 1.23(a) [87]. The microsystem includes a 9×6 array of low-power
low-noise sensory circuit cells, a programmable waveform generator, on-chip SRAM
memories, a shared proportional-integral-derivative (PID) controller for regulating the
chip temperature, a digital pulse-width-modulator (PWM), an all-digital ultra-wideband
transmitter, and on-chip biasing and clock generation circuits. Each sensory cell in-
cludes a current-to-digital channel, an array of DNA sensors, a pH sensor (only for
sample pH level sensing not for indirect DNA sensing), several BJTs to generate the
CTAT and PTAT currents required for temperature sensing and a heater required for
temperature regulation. To enable independent cell programmability, each cell includes
a bias voltage generator, clock generation circuitry, and SRAM memory.
Each current-to-digital channel consists of either a transimpedance amplifier (TIA)
or a current conveyer (CC) and a multiplying ADC (MADC). The selectable TIA or
CC acquires the sensory current at a low impedance. The dual-slope multiplying ADC
multiplies the sensor response with a set of digital coefficients and outputs the corre-
sponding digital word. The digital output of each channel is serialized on the chip and is
wirelessly transmitted, using the all-digital ultra-wide band transmitter [137]. The SoC
can be configured to perform either cyclic voltammetry (Fig. 1.23(b)), or impedance
spectroscopy (Fig. 1.23(c)), or temperature regulation (Fig. 1.23(d)). The SoC reuses
a number of blocks (denoted by bold outlines in Fig. 1.23) in different configurations
resulting in significant saving in the integration area. For completeness the three key
distinct functionalities of the SoC: cyclic voltammetry, impedance spectroscopy, and
temperature regulation, are briefly summarized next in sections 1.9.2-1.9.4 respectively.
The cyclic voltammetry (and concurrently pH sensing) integrated circuit configuration
is then further detailed in Chapter 3 [137]. The impedance spectroscopy integrated cir-
CHAPTER 1. INTRODUCTION 48
cuits configuration is detailed in Chapter 4 [144]. The temperature regulation integrated
circuits configuration is detailed in Chapter 5.
1.9.2 Cyclic Voltammetry and Sample pH Level Sensing
The functional block diagram of the wireless electrochemical DNA analysis SoC con-
figured for DNA cyclic voltammetry analysis and pH sensing is shown in Fig. 1.23(b).
In this configuration of the SoC, each channel is multiplexed among a bank of DNA sen-
sors and a pH sensor. The sensors are interrogated by the on-chip programmable wave-
form generator that is shared among all channels [137]. The current conveyer front-end
is utilized in this configuration. The digital data representing the stimulation waveform
properties are stored in the on-chip waveform generator SRAM. The current-to-digital
channel quantizes the input current and outputs the corresponding digital word. No
computation is required in this case and the MADC digital multiplication coefficients
are set to one. The chip temperature is held at a constant value by the pre-configured
on-chip PWM controlling the in-channel heating element. The pH sensors are only used
to measure the pH level of the electrolyte solution under test.
1.9.3 Impedance Spectroscopy
The functional block diagram of the wireless electrochemical DNA analysis SoC con-
figured for impedance spectroscopy is shown in Fig. 1.23(c). In this mode, the SoC uti-
lizes the 54 current-to-digital recording channels to extract the DNA sensor impedance.
The microsystem utilizes the frequency response analysis (FRA) algorithm to extract
real and imaginary components of the biosensor [144]. Two computationally intensive
operations, the multiplication and integration required by the FRA algorithm, are per-
formed by the in-channel MADC in the mixed-signal domain resulting in small area
and power consumption. The waveform generator produces a variable frequency sinu-
CHAPTER 1. INTRODUCTION 49
soidal interrogation waveform and drives the reference electrode with it. The front-end
transimpedance amplifier acquires DNA sensor response. The MADC multiplies the
biosensor response with a set of digital FRA algorithm coefficients (stored in the multi-
plication coefficient SRAM). Next the MADC accumulates the results over one period
of the interrogation signal (integration), thus extracting the biosensor impedance. In
this mode the channel temperature is also held constant using the pre-configured PWM
and the in-channel heater.
1.9.4 Temperature Regulation
The functional block diagram of the wireless electrochemical DNA analysis SoC con-
figured for temperature regulation is shown in Fig. 1.23(d). In this mode, the SoC uti-
lizes the 54 current-to-digital recording channels to measure temperature. The on-chip
PID controller is used to regulate the 2D chip temperature profile, on-chip SRAMs are
utilized to store PID and multiplication coefficients. The channel measures temperature
by taking the ratio of a CTAT to PTAT currents. The CTAT current is used as the input
and the PTAT current is used as the reference to the current-to-digital recording chan-
nel. The CTAT and PTAT currents are generated using the in-cell BJTs. The measured
temperature is fed to the on-chip PID controller. The PID controller regulates the 2D
chip temperature profile by modulating the in-cell heaters. Two computationally inten-
sive operations, the multiplication and subtraction required by the PID algorithm, are
performed by the in-channel MADC in the mixed-signal domain, yielding small area
and power consumption.
1.10 Thesis Outline
The rest of this thesis is organized as follows:
CHAPTER 1. INTRODUCTION 50
• Chapter 2 focuses on the current acquisition front end of the DNA analysis SoC
that is shared among all mode of operations, as shown in Fig. 1.23(a). This
chapter presents design, comparative analysis and experimental results of two
low-noise bidirectional current acquisition circuits for interfacing with electro-
chemical amperometric biosensor arrays: a transimpedance amplifier (TIA) and
a current conveyer (CC).
• Chapter 3 focuses on the cyclic voltammetry DNA sensing capability of the SoC,
as shown in Fig. 1.23(b). This chapter presents a fully integrated 54-channel
wireless label-free cyclic voltammetry DNA analyzer. The microsystem includes
600 nanostructured DNA sensors and 54 pH sensors, and reuses key circuits for
cyclic voltammetry and for pH sensing.
• Chapter 4 focuses on the impedance spectroscopy DNA sensing capability of the
SoC, as shown in Fig. 1.23(c). This chapter presents a 54-channel mixed-signal
CMOS DNA impedance analyzer that utilizes frequency response analysis (FRA)
to extract the real and imaginary impedance components of the biosensor.
• Chapter 5 focuses on the temperature regulation capabilities of the DNA analysis
SoC, as shown in Fig. 1.23(d). This chapter presents a 54-sites mixed-signal
CMOS thermal regulator with a compact mixed-signal PID controller.
• Chapter 6 contains a summary of the original contributions in this thesis and
provides directions for future work.
51
Chapter 2
Current Acquisition Circuits for
Electrochemical Amperometric
Biosensors
We present a study of the utility of the switched-capacitor TIA and CC circuits in ac-
quisition of bidirectional currents in electrochemical amperometric biosensing applica-
tions. Advantages and disadvantages of the TIA and CC circuits in such applications
are described and experimentally confirmed. This work builds on the theoretical noise
analysis presented in [133, 134]. Specifically, we show that the main drawbacks of the
switched-capacitor TIA is the injection of the the switching noise into the sensor work-
ing electrode. The switching noise injected into the working electrode alters the charge
at the working electrode surface, thus degrading the electrochemical recording results
accuracy.
We introduce a solution to this problem, a low-noise bidirectional current conveyer
for small currents. The advantage of this method, compared to a transimpedance ampli-
fier, is that the working electrode is isolated from the clocked circuitry (e.g, switches,
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 52
ADC, comparator) thus reducing the effect of charge injection into the working elec-
trode due to high-frequency switching. Generally current conveyers suffer from the
amplifier flicker noise as it is not integrated as in the case of the TIA. Internal OTA
chopper stabilization is utilized to reduce the effect of the flicker noise, the dominant
noise of the amplifier. Full chopping at the input and output of the OTA was not pos-
sible due to the single ended nature of the design. The CC achieves a dynamic range
of 8.6pA to 350nA. Finally, we present a comparative analysis of a bidirectional-input
TIA and a bidirectional CC fabricated in 0.13µM CMOS technology.
This chapter extends on an earlier report of the current conveyer design presented
in [166], and offers a more detailed analysis of the design and additional electrochemi-
cal experimental results characterizing the circuit implementation and comparing the
current conveyer implementation to a transimpedance amplifier implementation for
electrochemical recording. The rest of the chapter is organized as follows. Section II
presents the TIA design and implementation and includes experimentally measured re-
sults. Section III details the circuit implementation of the CC and also includes exper-
imentally measured results. Section IV presents a comparative analysis of the TIA and
CC designs and their utility in electrochemical sensing applications.
2.1 Transimpedance Amplifier (TIA)
As described in Chapter I, most electrochemical biosensing applications require sourc-
ing and sinking the redox current. One way to measure a bidirectional redox current
is to directly convert it to a voltage. The conversion can be done by a resistive or a
capacitive feedback across an OTA, known as a transimpedance amplifier (TIA). To
convert a low-level current in the nano-ampere or pico-ampere range, a very large re-
sistor is required. A capacitive feedback allows to keep the area small. In addition, a
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 53
−
+
S
IIN
VWE
CF
VOUTCWE
RS
RCT
RE
CDB
VRE
WE
IINJECTION
Figure 2.1: Chopper-stabilized bidirectional-input transimpedance amplifier (TIA).
capacitive TIA has an averaging behavior and acts as a low-pass filter to remove the
high-frequency noise [90].
2.1.1 Circuit Implementation
The circuit diagram of the presented TIA is shown in Fig. 2.1. The TIA consist of a
chopper-stabilized OTA with a capacitive feedback. The TIA operates in two phases.
In phase one switch S is open. In this phase the OTA feedback ensures that the negative
terminal of the OTA is at the working electrode potential. The input current is integrated
over the feedback capacitor. This is the integrating phase of the TIA. In the next phase,
switch S is closed to discharge the feedback capacitor. This removes any residual charge
on the feedback capacitor at the end of one full cycle.
The OTA has a folded cascode topology as shown in Fig. 2.2. To reduce the effect
of flicker noise, the amplifier utilizes input PMOS devices with a high aspect ratio and
internal chopping. One set of the chopper switches is placed at the input of the OTA.
Another set is placed at the folding nodes as depicted in Fig. 2.2. This significantly
reduces the flicker noise and DC offsets [134] caused by the input pair transistors, M1
and M2, and the NMOS current mirror transistors, M3 and M4. The size of the feedback
capacitor is 10pF. The chopper clock frequency can be set up to 20kHz. This is lim-
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 54
VWE
VbiasP
VbiasN
VcascP
cascNV
IIN
IOUT
M1M
2
M3 M
4
M5
M6
M7
M8
M9 M
10M
11
Figure 2.2: Circuit schematic diagram of the OTA within the TIA.
ited by the bandwidth of the OTA. The chopper frequency should be set high enough
such that the low frequency noise that is up converted is placed beyond the OTA 3dB
frequency (to be filtered out). Also the chopping frequency should be below the OTA
3dB bandwidth so that the OTA provides adequate gain (speed) required for the noise
up conversion at the chopping frequency [52,53]. The chopping frequency is in general
optimized by circuit level simulations.
Correlated double sampling is another circuit technique to reduce the OTA input
offset and flicker noise [54]. This method was not utilized in this work as the leakage
from the extra required switches would have reduced the overall system accuracy.
The simulated input-referred noise of the integrator for the cases where the chopper
is disabled and enabled is shown in Fig. 2.3. The integrated input-referred noise from
0.01Hz to 1kHz is 0.12pA when the chopper is disabled and 0.07pA when the chopper
is enabled. In this design the internal chopping yield a noise improvement of -5dB
at 10Hz as shown in Fig. 2.3. The integrator transistor sizes are shown in Table I.
Contribution of each transistor to the total input-referred noise is shown in Fig. 2.4.
When the chopper is disabled the main contributions are from the OTA current mirror
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 55
10−2
10−1
100
101
102
103
−130
−120
−110
−100
−90
−80
−70
FREQUENCY (Hz)
CHOPPER ON
CHOPPER OFF
INPUT NOISE ( A / Hz ) (dB)
rms
1/2
Figure 2.3: Simulated input-referred noise spectrum of the TIA from 0.01Hz to 1kHz.
transistors M3 and M4 and the input pair transistors M1 and M2. When the chopper
is enabled, the current mirror transistors M9 and M10 are the main contributors to the
input-referred noise.
2.1.2 Experimental Results
The transimpedance amplifier was fabricated in a 0.13µm CMOS process with a 1.2V
supply and occupies an area of 80µm×60µm.
The experimentally measured relative errors of the digital output for the input cur-
rent swept between ±10pA and ±350nA are shown in Fig. 2.5. The relative error stays
below 5 percent over the whole operating range. The TIA achieves a dynamic range of
10pA to 350nA. The lower limit is defined by the LSB of the on-chip ADC. The higher
limit is defined by the input current that saturates the TIA.
Figs. 2.6(a),(b) show the experimentally recorded output current distribution for
the input currents of 100pA and 100nA, respectively, measured from 16 channels on
16 chips (one channel per chip). The mean output current and the corresponding stan-
dard deviation are 80.89pA and 6.9pA, respectively, for the input current of 100pA.
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 56
M 3,4
M 1,2
M 9,10
M 5,6
M 7,8
TO
TA
L N
OIS
E (
%)
0
10
20
30
TRANSISTOR
CHOPPER ON
CHOPPER OFF
(a)
TO
TA
L N
OIS
E (
%)
5
0
10
15
20
25
3,4 1,2 9,10 5,6M M M M M
7,8
TRANSISTOR
CHOPPER ON
CHOPPER OFF
(b)
Figure 2.4: Transimpedance amplifier noise summary: (a) flicker noise contributions, and (b)thermal noise contributions.
They are 100.10nA and 17.8pA for input current of 100nA. Table III summarizes the
experimentally measured characteristics of the TIA.
2.2 Current Conveyer (CC)
Another common method to acquire a bidirectional current is to use a unidirectional
current conveyer and to add a DC offset current to its input as shown in Fig. 2.7 [7-
12]. This requires high resolution in the subsequent ADC and adds noise to the redox
current, given that the current mirror generating the DC currents directly contributes
thermal and flicker noise to the output noise of the current conveyer. Also, depending
on the WE impedance, a portion of the DC offset current, IERROR, can leak into the
electrochemical cell and disturb the charge balance on the WE-electrolyte interface.
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 57
-4
-2
0
2
4
6
10p 100p 1n 100n 1µINPUT CURRENT (A)
10nRE
LA
TIV
E E
RR
OR
(%
)
(a)
-1µ -100n -10n -1n -100p -10pINPUT CURRENT (nA)
-2
0
2
4
6
-4RE
LA
TIV
E E
RR
OR
(%
)
(b)
Figure 2.5: Experimentally measured relative error of the output of the TIA for the input currentof (a) 10pA to 350nA, and (b) -350nA to -10pA. The results are measured from one typicalchannel on one chip.
2.2.1 Circuit Implementation
The top-level VLSI architecture of the presented bidirectional current conveyer is shown
in Fig. 2.8. It is comprised of a PMOS and an NMOS transistors Mn and Mp connected
in the feedback of the OTA. The negative feedback ensures a known potential at the
working electrode is set by the voltage at the non-inverting input of the OTA. It also
enables the current conveyer to source and sink input current without the need for a
DC offset current. The currents through Mn and Mp are mirrored to the output of the
current conveyer.
Internal OTA chopping has been utilized to reduce the effect of its flicker noise. The
current mirrors are implemented in a low-current regulated cascode topology to enable
accurate current copying down to the pA level. To facilitate a comparative analysis with
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 58
CURRENT (pA)0 20 40 60 80 100 120 140
0
1
2
3
4
5
6MEAN= 80.89pA
SD(3σ) = 6.9pA
N= 16
NU
MB
ER
OF
OC
CU
RA
NC
ES
(a)
CURRENT (nA)100.00 100.05 100.10 100.15 100.20 100.25100.30012
3
45
67
MEAN= 100.10nA
SD(3σ) = 17.8pA
N= 16
NU
MB
ER
OF
OC
CU
RA
NC
ES
(b)
Figure 2.6: Experimentally measured TIA output current of 16 channels (from 16 chips, onechannel each) for the input current of (a) 100pA, and (b) 100nA.
the TIA presented in section IV, the output current is integrated on the load capacitor
CF of 10pF and sampled.
The schematic diagram of the current conveyer is shown in Fig. 2.9. The OTA is
implemented as a folded-cascode amplifier and the current mirrors are implemented as
a low-current regulated cascode current mirror comprised of the transistors M12 to M20
and M21 to M29 [11]. The regulated cascode current mirrors ensure high precision and
Table 2.1: TIA OTA Transistors Sizing
Transistor W/L (µm)M1,2 8× 1/0.4M3,4 1× 0.5/5M5,6 4× 0.5/4M7,8 8× 0.5/4M9,10 2× 0.5/0.5M11 4× 1/4MS 4× 1/0.13
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 59
IIN
VWE
Mp
IOUT
IDC
CWE
RS
RCT
WERECDB
VRE
IERROR
−
+
Figure 2.7: Conventional pseudo-bidirectional current conveyer with a DC offset current.
IN
I OUTVWE
Mn
Mp
CcI
CWE
RS
RCT
WERECDB
VREV OUT
S
CF
−
+
Figure 2.8: Chopper-stabilized bidirectional current conveyer VLSI architecture.
high output impedance of the current conveyer. The regulated current mirrors monitor
IIN through M13 and M22. The input current is used to bias the regulating amplifiers
consisting of transistors M14, M16, M17, M19, M20 and M23, M25, M26, M28, M29. The
regulating amplifies sense the drain voltage of M15 and M24 through transistors M14
and M26 and adjust the gate voltage of M18 and M27 such that the drain-source voltage
of M12-M15 pair and M21-M24 pair are equal pairwise thus ensuring accurate current
copying down to pA level.
In more detail, for the NMOS section of the regulated cascode current mirror, tran-
sistors M14, M17 and M20 form a common-source amplifier. The common-source am-
plifier forms a negative feedback loop with the help of source follower transistor M18.
This ensures a high impedance at the output of the current mirror. Vds of M15 should
be equal to Vds of M12 to ensure accurate current copying. This is achieved as follows:
the common-source amplifier is biased with the current IIN using a (1:1) current mirror
consisting of transistors M19 and M20. The sizes of transistors M14 and M13 are equal
to those of the transistors M12 and M15 respectively. Transistors M16 and M17 are sized
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 60
VWE
VbiasP
VbiasN
VcascP
cascNVIIN
IOUTCc
M1 M2
M3 M4
M5 M6
M7 M8
M9 M10M11
M12M13 M14 M15
M16M17
M18
M19 M20
M21 M22 M23 M24
M25
M26
M27
M28 M29
M
Mn
p
Figure 2.9: Chopper-stabilized bidirectional current conveyer circuit schematic diagram.
such that they provide enough voltage drop to ensure that transistors M12, M13, M14,
M15 have all the same Vds. The value of the capacitor Cc is set to 0.5pF to ensure OTA
stability over the operating current range.
Similarly to the TIA, internal OTA chopping has been implemented to reduce the
effect of both flicker noise and the input offset voltage. As shown in Fig. 2.9, chopper
switches are placed at the input of the OTA. Another set is placed after the NMOS tail
current source. This significantly reduces the flicker noise and offsets due to the input
pair transistors and the NMOS tail current source transistors. Minimum size switches
are utilized to reduce the effect of charge injection into the working electrode. The
current conveyer transistor sizes are shown in Table IV.
In typical electrochemical sensing applications, the current conveyer operates in the
frequency range of 0.01Hz to 1kHz. To achieve efficient flicker noise reduction, the
chopper frequency needs to be higher than the input signal frequency. The chopper
clock frequency was set to 10kHz. As a result the current conveyer bandwidth should
be higher compared to the case where no chopper stabilization is utilized. Simulated
bandwidth of the current conveyer is shown in Fig. 2.10. The current conveyer achieves
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 61
102
103
104
105
−5
−4
−3
−2
−1
0
13dB = 35.7 kHz
CURRENT GAIN (dB)
FREQUENCY (Hz)
Figure 2.10: Simulated current conveyer AC response
a 3dB bandwidth of 35.7kHz.
2.2.2 Channel Noise Analysis
An important consideration in the design of the current conveyer is its intrinsic noise
as it limits the sensitivity of the recording channel. The output noise originates from
the OTA, the feedback transistors Mp, Mn and the regulated cascode output current
mirror as shown in Fig. 3.6. The sub-circuit in Fig. 2.11 (active during the positive
current recording) includes these elements and is used for noise analysis to simplify the
derivation.
The impedance between the reference and working electrodes is modeled with a
generic R-C biosensor impedance model shown in Fig. 2.11, left. In this model RS
(typical value of 1MΩ) represents the electrolyte resistance between the working and
reference electrodes, CWE (typical value of 500pF) represents the diffusion layer ca-
pacitance, and CDB (typical value of 300pF) models the interfacial double-layer capac-
itance at the WE-electrolyte interface and RCT (typical value of 1GΩ) models the charge
transfer resistance at the WE-electrolyte interface [84]. The input-referred noise of the
OTA is due to its thermal and flicker noise. Both noise sources can be referred to the
positive input of the OTA and are modeled as the voltage source Vn in Fig. 2.11 [100].
According to the simplified model given in Fig. 2.11, the output noise power of the
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 62
OUT
M12M13
M14
M15
M16M17
M18
M19M20
Mp
IN
VWE
I
WE
Inp
In12
In16
In19
In13 In14
In17
In20In18
In15
I
CWE
RS
RCT
RECDB
VRE Vn
−
+
Figure 2.11: Simplified noise model of the chopper-stabilized current conveyer.
current conveyer is given by
I2n,OUT = β1
(∣∣∣∣ gmpA
1 + gmpAZ
∣∣∣∣2 V 2n +
∣∣∣∣ 1
1 + gmpAZ
∣∣∣∣2 I2np)
+ I2n,18 + I2n,15 + g2m18
(β2(
∣∣∣∣ gmpA
1 + gmpAZ
∣∣∣∣2 V 2n
+
∣∣∣∣ 1
1 + gmpAZ
∣∣∣∣2 I2n) + I2n,13,14,16,17,18,19,20
), (2.1)
where V 2n is the OTA input-referred noise, I2np is the noise due to the feedback transistor
Mp, gmp is the transconductance of the PMOS feedback transistor Mp, A is the open-
loop gain of the OTA and Z is the equivalent impedance of the electrode. β1 and β2 are
the current mirror ratios between the transistors M12, M13 and M12, M15, respectively.
In this design both ratios are set to one.
For practical values of gmp, A and Z, the contribution of I2np in equation (1) is
negligible, resulting in the total output current noise
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 63
I2n,OUT ≈ β1
(∣∣∣∣ 1Z∣∣∣∣2 V 2
n
)+ I2n,18 + I2n,15
+ g2m18
(β2(
∣∣∣∣ 1Z∣∣∣∣2 V 2
n )
+ I2n,13,14,16,17,18,19,20
). (2.2)
Since the electrolyte resistance, RS , is typically small, and the charge transfer resis-
tance, RCT , is very large, the electrode equivalent impedance is approximately capaci-
tive
Z ≈ 1
jω(CWE + CDB), (2.3)
where CWE represents the diffusion layer capacitance and CDB models the interfacial
double-layer capacitance at the WE-electrolyte interface as shown in Fig. 2.11. Substi-
tuting equation (3) into (2) results in
I2n,OUT ≈ β1
(|2πf(CWE + CDB)|2 V 2
n
)+ I2n,18 + I2n,15
+ g2m18
(β2(|2πf(CWE + CDB)|2 V 2
n )
+ I2n,13,14,16,17,18,19,20
). (2.4)
According to equation (4), the output noise level is proportional to the input-referred
noise of the OTA as shown in Fig. 2.11, the current noise contributions from the reg-
ulated cascode current mirror transistors and the electrode capacitance. The electrode
capacitance is determined by the electrode surface area. In general the larger the area
of the electrode the more biomolecules there are to undergo a redox reaction resulting
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 64
in a larger input signal. As a result, the electrode size and thus capacitance do not affect
the SNR of the electrochemical recording system significantly.
The input-referred noise of the OTA consists of two components, the thermal noise
power and the 1/f noise. The thermal noise component can be expressed as [100]
V 2n,thermal
∆f=
4KT
gm1
(4
3
)(1 +
gm3
gm1
+gm9
gm1
), (2.5)
where K is Boltzmann constant and T is the absolute temperature. The noise contribu-
tion of M3,4,9,10 is minimized by biasing M3,4,9,10 such that gm3,4,9,10<<gm1,2. The key
to minimize the gm ratios is to bias the input differential pair transistors in the weak
inversion region, where the transconductance efficiency, gm/ID, is high, and to bias
M3,4,9,10 in the strong inversion region to lower their gm.
The input-referred 1/f noise power can be expressed as [100]
V 2n,1/f
∆f=
2KP
COXW1L1f+
2KN
COXW3L3f
(gm3
gm1
)2
+
2KP
COXW9L9f
(gm9
gm1
)2
, (2.6)
where COX is gate oxide capacitance per unit area. In order to minimize the 1/f noise,
large PMOS input-pair transistors, long-channel current mirrors and internal OTA chop-
ping are employed.
The noise contribution of the output regulated cascode current mirror is mostly gov-
erned by the transistors transconductance. The channel noise of a transistor is given
by [100]
I2n = 4KT
(2
3
)gm +
K
WLCOXfgm. (2.7)
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 65
Thus, the gm of the current mirror transistors should be reduced and the length of the
transistor should be increased in order to reduce the current mirror noise contribution
to the output of the current conveyer.
The simulated input-referred noise of the current conveyer for the cases where the
chopper is disabled and enabled is shown in Fig. 2.12. The electrode model shown in
Fig. 2.11 was included in the noise simulation to model the effect of the voltage ripple
and the leakage current [155]. In this simulation RS was set to 1MΩ, CWE was set to
500pF, CDB was set to 300pF and RCT was set to 1GΩ. This takes into account the
effect of the high sensor output impedance on the noise performance of the chopper.
The integrated input-referred noise from 0.01Hz to 1kHz is 0.27pA for the case when
the chopper is disabled and is 0.13pA when the chopper is enabled.
The chopper implementation yields an 8dB improvement in the noise floor with
the realistic high-impedance electrode model. Off-chip access to the analog output of
the current conveyer is not available, and as a result, the noise can not be measured
directly before the quantization noise is added. The dual-slope ADC integrates the
output current of the current conveyer in every ADC conversion cycle. This integration
significantly reduces the effect of the ripples caused by chopper switches on the output
of the current recording channel. Also, given that the chopper is implemented inside
the OTA (internal OTA chopping) the limited bandwidth of the OTA combined with the
2pF integrating capacitor, act as a low-pass filter thus further reducing the ripple levels.
The contribution of each transistor to the total input-referred noise is shown in
Fig. 2.13. When the chopper is disabled the main contributions are from the OTA
current mirror transistors M3,4 and the input pair transistors M1,2. When the chopper
is enabled, the current mirror transistors M12,21,24,15 are the main contributors to the
input-referred noise.
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 66
10−2
10−1
100
101
102
103
−140
−120
−100
−80
FREQUENCY (Hz)
CHOPPER ONCHOPPER OFF
INPUT NOISE ( V / Hz ) (dB)
rms
1/2
Figure 2.12: Simulated input-referred noise spectrum of the current conveyer from 0.01Hz to1kHz.
Table 2.2: Current Conveyer Transistor Sizing
Transistor W/L (µm) Transistor W/L (µm)M1,2 8× 3/0.4 M16,17,18 1× 0.5/4M3,4 1× 0.5/5 M19,20 8× 0.3/5M5,6 4× 0.5/4 M21,22,23,24 2× 0.4/8M7,8 8× 0.5/4 M25,26,27 4× 0.7/3M9,10 2× 0.5/0.5 M28,29 4× 0.3/4M11 4× 1/4 Mp 1× 1/1M12,13,14,15 1× 0.4/8 Mn 1× 0.4/4
2.2.3 Experimental Results
The current conveyer was fabricated in a 0.13µm CMOS process with a 1.2V supply
and occupies an area of 100µm×100µm.
The experimentally measured relative errors (absolute error divided by the magni-
tude of the exact value) of the digital output for the input current swept between ±10pA
and ±350nA are shown in Fig. 2.14. The relative error stays below 8 percent over the
whole operating range. The current conveyer achieves a dynamic range of 8.6pA to
350nA. The lower limit is defined by the ADC LSB and the higher limit is defined by
the input current that saturates the current conveyer. Fig. 2.15 shows the experimen-
tally recorded output current distribution for the input currents of 100pA and 100nA
measured from 16 channels on 16 chips (one channel per chip). The mean output cur-
rent and the corresponding standard deviation are 81.19pA and 20.31pA, respectively,
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 67
CHOPPER ON
CHOPPER OFF
M 3,4
M 1,2
M 12
M 15
M 21
M 24
0
0.005
0.010
0.015
0.020
0.025
INT
EG
RA
TE
D I
NP
UT
NO
ISE
( p
A )
0.035
(a)
CHOPPER ON
CHOPPER OFF
M 3,4
M 1,2
M 21
M 12
0
0.005
0.010
0.015
0.020
0.025
0.030
INT
EG
RA
TE
D I
NP
UT
NO
ISE
( p
A )
(b)
Figure 2.13: Current conveyer noise summary: (a) flicker noise contributions, and (b) thermalnoise contributions.
for the input current of 100pA. They are 100.21nA and 29.0pA for the input current of
100nA. Table III summarizes the experimentally measured characteristics of the current
conveyer.
2.3 Comparative Analysis
The electrical characteristics of TIA and CC are compared first. When the chopper
is enabled, the TIA achieves and input-referred noise of 0.07pArms and CC achieves
an 0.13pArms. This is due to the fact that the TIA integrates noise over one sampling
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 68
-8
-4
0
4
6
8
10p 100p 1n 100n 1µINPUT CURRENT (A)
10n
RE
LA
TIV
E E
RR
OR
(%
)
(a)
-1µ -100n -10n -1n -100p -10pINPUT CURRENT (nA)
0
2
4
6
8
−2RE
LA
TIV
E E
RR
OR
(%
)
(b)
Figure 2.14: Experimentally measured relative error of the output of the current conveyer forthe input current of (a) 10pA to 350nA, and (b) -350nA to -10pA. The results are measured fromone typical channel on one chip.
period.
The chip-to-chip output current variation of TIA, in Fig. 2.6, is lower compared
to that of the CC design shown in Fig. 2.12. The variation in CC is mainly due to
the mismatch in the output current mirrors. The maximum relative error of the output
over the operating current range is 5 percent for the TIA and 8 percent for the CC.
Mismatch in the regulated cascode current sources limits the linearity of the current
conveyer. The mismatch in the regulated cascode current mirrors is due to the mismatch
in the transistor pairs M12-M15 and M21-M24, as shown in Fig. 2.9. Dynamic element
matching (DEM) can be employed to reduce the effect of the mismatch in the current
mirrors [166].
To study the effect of charge injection into the working electrode, two sets of simu-
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 69
CURRENT (pA)
NU
MB
ER
OF
OC
CU
RA
NC
ES
0 20 40 60 80 100 120 14001
2
3
4
5
6MEAN= 81.19pA
SD(3σ) = 20.31pA
N= 16
(a)
CURRENT (nA)100.15 100.2 100.25 100.3 100.35 100.401
234
5
67
MEAN= 100.21nA
SD(3σ) = 29pA
N=16
NU
MB
ER
OF
OC
CU
RA
NC
ES
100.5
(b)
Figure 2.15: Experimentally measured current conveyer output current of 16 channels (from 16chips, one channel each) for the input current of (a) 100pA and (b) 100nA.
lations were performed with the working electrode model in both Fig . 2.1 and Fig. 2.8
connected to the voltage VRE . The average current integration into the working elec-
trode, due to current integration and sampling, is calculated for the cases where the
sampling frequency is varied from 1kHz to 12kHz and the chopping frequency is set to
20kHz. As it can be seen from Figs. 2.16(a) and (b), the average current injected into
the working electrode at 6kHz for the case of the TIA is significantly higher compared
to the average current injected by the CC.
To compare the performance of the TIA and CC in electrochemical sensing appli-
cations, two sets of CV scans of a DNA reporter, potassium ferricyanide, have been
performed. Potassium ferricyanide K3[Fe(CN)6] is commonly used in electrochemi-
cal sensing systems as a redox reporter [87]. Cyclic voltammetry recordings of 2µM
potassium ferricyanide in a 1M potassium phosphate buffer (pH 7.3) have been carried
out. A 100mV/sec 0.7V peak-to-peak CV waveform with 50ms resting period was ap-
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 70
0 2 4 6 8 10 12
INP
UT
CU
RR
EN
T (
fA)
130
180
230
280
330
SAMPLING FREQUENCY (kHz)
(a)
0 2 4 6 8 10 12
INP
UT
CU
RR
EN
T (
fA)
20
40
60
80
100
SAMPLING FREQUENCY (kHz)
(b)
Figure 2.16: Average current injected into the working electrode for (a) TIA and (b) CC.
−700 −600 −500 −400 −300 −200 −100 0−12
−10
−8
−6
−4
−2
0
2
4
6
8
V -V (mV)
CU
RR
EN
T (
nA
)
OXIDATION
VOLTAGE
RE WE
REDUCTION
VOLTAGE
TIA
CC
Figure 2.17: Cyclic voltammogram of 2µM potassium ferricyanide in 1M potassium phosphatebuffer solution experimentally recorded with the transimpedance amplifier (TIA) and the currentconveyer (CC) using a 50µm×50µm gold electrode.
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 71
Table 2.3: Experimentally Measured Transimpedance Amplifier (TIA) and Current Conveyer(CC) Characteristics
TIA CCTechnology 0.13µm CMOS 0.13µm CMOSSupply Voltage 1.2V 1.2VArea 80µm×60µm 100µm×100µmSensitivity 135fA 8.6pAMax Relative Error 5.1 8.0(10pA to 350nA)Max Relative Error 4.8 7.8(10pA to 350nA)Input Referred Noise 0.07pA 0.13pA(0.01Hz to 1kHz)Charge Injection at 6kHz 221fA 53fA(Simulated)Power Consumption
Core Circuit 1µW 2µWBiasing 1µW 1µWDigital 1µW 1µWTotal 3µW 4µW
plied between a 55µm×55µm on-chip gold working electrode and an off-chip Ag-AgCl
reference electrode. The resulting CV curves recorded by the chopper-stabilized TIA
and the chopper-stabilized CC are shown in Fig. 2.17. The CV curves for both TIA
and CC show two distinct peaks at the reduction and oxidation voltages of potassium
ferricyanide at -250mV and -450mV respectively. The measurements match as well.
Next the same set of CV recordings have been conducted using a 2µm×2µm on-chip
gold working electrode. The resulting CV curves recorded by the chopper-stabilized
TIA and the chopper-stabilized CC are shown in Fig. 2.18. The CV curve for the CC
shows two distinct peaks at the reduction and oxidation voltages of potassium ferri-
cyanide, as expected. The CV curve for the TIA shows no reduction or oxidation peaks.
In the TIA case the switching charge from switch S is injected into the working elec-
trode. This disturbs the charge balance at the electrode-electrolyte interface thus affect-
ing the electrochemical reaction required for reduction and oxidation of the potassium
ferricyanide. As expected, this effect is more pronounced for smaller electrode size,
given that the amount of the charged injected into the working electrode is comparable
to the double layer capacitance charge.
CHAPTER 2. CURRENT ACQUISITION CIRCUITS FOR ELECTROCHEMICAL AMPEROMETRICBIOSENSORS 72
−700 −600 −500 −400 −300 −200 −100 0
−0.6
−0.4
−0.2
0.0
0.4
0.6
0.8
1.0
V -V (mV)
CU
RR
EN
T (
nA
)
OXIDATION
VOLTAGE
RE WE
REDUCTION
VOLTAGE
TIA
CC
0.2
−0.8
Figure 2.18: Cyclic voltammogram of 2µM potassium ferricyanide in 1M potassium phosphatebuffer solution experimentally recorded with the transimpedance amplifier (TIA) and the currentconveyer (CC) using a 2µm×2µm gold electrode.
Both circuits inject small amount of charge generated by the chopper switches into
the biosensor. This injected noise is negligibly small compared to the switching noise
due to the feedback switch in the TIA and is due to the chopper switches mismatch.
2.4 Chapter Summary
Designs of two low-noise chopper-stabilized bidirectional current acquisition circuits
for electrochemical sensing applications have been presented. The first design has a
switched-capacitor transimpedance amplifier topology. The second one has a current
conveyer topology. Both designs are implemented in a 0.13µm CMOS technology.
Electrical and electrochemical performance of both design has been characterized. The
TIA and CC consume 3µW and 4µW from a 1.2V supply, respectively. It is shown
that the TIA marginally outperforms the CC for high-amplitude input currents. For
small input currents corresponding to low concentration of biochemicals the CC is the
preferred choice as it better isolates the working electrode from current injection.
73
Chapter 3
Cyclic Voltammetry and pH sensing
A fully integrated 54-channel wireless fast-scan cyclic voltammetry DNA analysis SoC
is presented. The microsystem includes 546 3D nanostructured and 54 2D gold DNA
sensing microelectrodes as well as 54 pH sensors. Each channel consists of a chopper-
stabilized current conveyer with dynamic element matching. It is utilized as the am-
perometric readout circuit with a linear resolution from 8.6pA to 350nA. The on-chip
programmable waveform generator provides a wide range of user-controlled rate and
amplitude parameters with a maximum scan range of 1.2V, and scan rate ranging be-
tween 0.1mV/sec to 300V/sec. A digital ultra-wideband transmitter based on a de-
lay line architecture provides wireless data communication with data rates of up to 50
Mb/sec while consuming 400µW. The 3mm×3mm prototype fabricated in a 0.13µm
standard CMOS technology has been validated in prostate cancer synthetic DNA detec-
tion with 10aM label-free PCR-free detection limit. Each channel occupies an area of
only 0.06mm2 and consumes 42µW of power from a 1.2V supply.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 74
3.1 Introduction
We have reported in Nature Nanotechnology amperometric electrochemical sensors
fabricated on passive silicon, not on CMOS, that do not require cumbersome tagging of
DNA with chemical or optical labels [138]. These gold microelectrodes have fine-tuned
nanostructured patterns on their surface that yield an over 140dB input dynamic range
and 10aM detection limit sufficient for PCR-free DNA detection.
In this paper, we present a 0.13µm CMOS DNA analysis SoC with 600 such nanos-
tructured microelectrodes (NMA) grown directly on the die. This paper extends on
an earlier report of the principle and demonstration in [87], and offers a more detailed
analysis of the design and additional experimental results characterizing the circuit im-
plementation and the DNA detection performance. This SoC performs label-free PCR-
free DNA analysis using fast-scan cyclic voltammetry with a 10aM detection limit and
pH sensing for cancer detection. The microsystem consists of a fully programmable
arbitrary waveform generator with an on-chip memory and 54 chopper-stabilized cur-
rent recording channels. The chopper-stabilized current conveyer frontend, with an
input-referred noise of 0.13pArms over one kHz bandwidth, is utilized as the ampero-
metric readout circuit in each channel. The current conveyer achieves linear resolution
from 10pA to 400nA. A chopper-stabilized dual-slope ADC is utilized to digitize the
recorded current. The waveform generator provides stimulation waveforms with a max-
imum scan range of 1.1V and a scan rate ranging from 0.1mV/sec to 300V/sec. A fully
digital 10Mb/s ultra-wideband (UWB) transmitter performs wireless communication.
The rest of this paper is organized as follows. Section II provides background on
DNA detection principles. Section III describes the process of fabrication of the nanos-
tructured DNA sensing microelectrodes. Section IV presents the DNA analysis SoC
VLSI architecture. Section V details the circuit implementation of the VLSI archi-
tecture. Section VI demonstrates the electrical experimental results obtained from the
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 75
PR
OB
E D
NA
TAR
GE
T D
NA
K [Fe(CN) ] 6
K [Fe(CN) ] 6
e e
e
e e
e
e
e
e
e
e e
e
e
e
e
e
e
e
e
e
BA
RE
GO
LD
I RE
DO
X1
I RE
DO
X1
I RE
DO
X2
<
4 3
(a) (b)
Au WE
e e
Au WE
e
Au WE
(c)
VRE
I RE
DO
X1
-VWE
VRE
I RE
DO
X2
-VWE V
RE
I RE
DO
X3
-VWE
Ag/AgCl RE Ag/AgCl RE Ag/AgCl RE
I RE
DO
X2
I RE
DO
X3
<
REDUCTION OXIDATION
Figure 3.1: Label-free electrochemical DNA detection principle. (a) Bare electrode: maximumcharge transfer between working and reference electrode in the absence of negatively chargedprobe and target DNA; (b) non-complementary target DNA: reduction in the charge transfer ratedue to the presence of negatively charged probe DNA, and (c) complementary DNA: furtherreduction in the charge transfer rate due to the presence of negatively charged target and probeDNA.
0.13µm CMOS prototype. In Section VII, the results of on-chip electrochemical record-
ing of calibration chemicals are presented. In Section VIII, the results of on-chip CV
recording of a synthetic DNA marker in prostate cancer screening are presented.
3.2 DNA Detection Principle
The principle of the label-free DNA detection method based on potassium ferricyanide
reporter is shown in Fig. 3.1. Potassium ferricyanide K4[Fe(CN)6] is a negatively
charged redox complex with a well-defined electrochemical signature exhibiting oxi-
dation and reduction currents at VRE-VWE voltage of -450mV and -250mV, respec-
tively. Maximum electron transfer between the bare gold electrode and potassium fer-
ricyanide is achieved in the absence of both the DNA target and probe, as denoted by
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 76
IREDOX1, in Fig. 3.1(a). Electron transfer is decreased when a negatively charged self-
assembled monolayer of probe DNA (SSDNA) is deposited on the electrode, as shown
in Fig. 3.1(b). This corresponds to smaller redox current IREDOX2, which results in
relatively smaller reduction or oxidization peaks. Upon bonding of the probe DNA and
target DNA (if present) the resulting DSDNA is more negatively charged and causes
potassium ferricyanide to be repelled farther from the electrode surface reducing the
generated faradaic current, as shown in Fig. 3.1(c). The redox current IREDOX3 is sig-
nificantly smaller compared to the first two cases and lacks the reduction and oxidation
peaks. In other words, the presence of negatively charged DNA on the biosensor sur-
face translates to a decrease in the potassium ferricyanide oxidation/reduction current
creating a detectible signal change [140–142].
3.3 Integrated Sensors
3.3.1 DNA Sensing Microelectrodes
To improve the sensitivity and dynamic range of the DNA sensor, nanostructured micro-
electrodes (NMEs) [138] are grown on the CMOS aluminum working electrode base,
using a combination of electroless plating and electroplating techniques.
It is shown in [138] that nanostructuring the working electrode allows for fabri-
cation of DNA sensors on passive silicon that have a broad range of sensitivities and
dynamic ranges. Highly branched electrodes with fine nanostructuring are capable of
achieving a 10aM detection limit [138]. It is postulated that the DNA probes which are
functionalized on nanostructured electrodes are more accessible and, as a result, bond
much easier and faster with target molecules. Microelectrodes with different degrees
of nanostructuring result in different sensitivities and dynamic ranges. By placing an
array of different electrodes on the same CMOS chip the sensor system can achieve a
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 77
sensitivity of two to six orders of magnitude [138].
In this design DNA sensing working electrodes are created by forming 2µm×2µm
passivation openings on the top metal layer (aluminum) of the CMOS chip (as it is
commonly done for bond pads) as shown in Figs. 3.2(a) and (b). An electroless metal
plating technique is employed to sequentially deposit nickel (Ni), palladium (Pd) and
then flat gold (Au) base on the exposed Al surface to form an electrode foundation as
shown in Fig. 3.3(c). Next NMEs are grown electrostatically in a solution containing
69µL of gold solution (544385-10G Aldrich) diluted in 2.5mL of deionized (DI) water
2.5mL of 5µM HCl [138] as also shown in Fig. 3.3(c). The shape and the size (defin-
ing the sensitivity and dynamic range) of the NMEs depend on the potential difference
between the working electrode and the reference electrode and the duration of the elec-
troplating. Examples of NMEs grown on a CMOS chip for 60sec at 100mV, 0 and
-100mV voltage difference between an on-chip Au working electrode and an off-chip
(Ag/AgCl) reference electrode are shown in Figs. 3.3(d), (e) and (f), respectively. Two
examples of arrays of NMEs grown on a CMOS chip are also shown in Fig. 3.3(f),
middle and right. For comparison purposes, large flat (2D) working electrodes have
also been fabricated on-CMOS. These flat gold electrodes are fabricated using the same
electroless plating technique as that used for the NME foundation fabrication, as shown
in Fig. 3.2(a). For example, the SEM photographs of such a gold-plated 55µm×55µm
on-CMOS flat working electrode are shown in Figs. 3.2(b) and (c).
3.3.2 pH Sensors
The in-channel ion-sensitive-field-effect-transistor (ISFET) based pH sensor is imple-
mented by a floating gate PMOS with the size of 0.5µM×0.35µM. The poly-gate
of the PMOS is connected to the top metal layer to form a floating gate electrode,
and the CMOS passivation layer (Si3N4 and SiO2) is used as the pH-sensitive mem-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 78
(a)
(b) (c)
(a)
(c)
FLAT Au WE
25µm 1µm
FLAT Au WE
1.0μm0.2μmPd
NiAl
Au
SiO2
Si N43
POLYAMIDE
Figure 3.2: (a) Passivation opening in standard CMOS and added metal layers of a flat (2D)microelectrode after electroless nickel-palladium-gold plating, (b) and (c) SEM photographs ofsuch 55µm×55µm working electrodes.
brane [101]. It is shown in [143] that the passivation layer (exposed section where
there is no polyamide) gives a linear pH response with a sensitivity of approximately
56mV/pH [101], depending on the stoichiometry of the passivation layer. The 54 pH
sensors are directly interfaced to the 54 current-recording channels. The source of the
PMOS is connected to the VDD (1.2V), and the drain is connected to the input of a
current conveyer. The pH sensor gate voltage is set by the on-chip reference electrode.
In this configuration, both the Vgs and the Vds of the pH sensor PMOS transistor are
fixed. Any change in the pH level effectively changes the PMOS threshold voltage.
This change results in a corresponding change in the drain current, which is digitized
by the recording channel.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 79
5µm
5µm
30µm
VRE
-V = -100 mVWE
RE-V = 0 mV
WE
VRE
-V = -100 mVWE
555555µµµµµmmmmm3µm
6µm1µm
Al BASE
VRE
-V = 100 mVWE
VR
mV RE
-V
= 100 mV
WE
VRE
-V = 100 mVWE
(b)
V
(d)
(e)
(f)
VRE -V = -100 m
V
WE
VRE
-V = 0mVWE
5µm7µm
VRE
-V = 100 mVWE
GROWN @
GROWN @
GROWN @
1µm
Au BASE
PdNiAl
1.0μm0.2μmSiO2
Si N43
POLYAMIDE
~5.0μmAu WE
(c)
Al
SiO2
Si N43
POLYAMIDE
~2.0μm
(a)
VRE
-V = -100 mVWE
40µm
(d)
(e)
VRE
-V = 0 mVWE
5µm
RE-V = 0 mV
WEV
5µm
Figure 3.3: Nanostructured DNA sensing working electrodes (NMEs): (a) Cross-sectional viewof a 2µm×2µm passivation opening in standard CMOS, (b) SEM photograph of a 2µm×2µmworking electrode passivation opening over an aluminum base, (c) nanostructured 2µm×2µmworking electrode grown on the passivation opening over an aluminum base in standard CMOS,(c) (d) and (e) SEM photographs of nanostructured microelectrodes grown at different elec-trodeposition conditions on the passivation opening in (b).
3.4 VLSI Architecture
3.4.1 Top-Level VLSI Architecture
The top-level VLSI architecture of the wireless DNA analysis SoC is shown in Fig. 3.4.
The SoC consists of 54 current-to-digital recording channels. Each channel is multi-
plexed between a bank of DNA sensors and a pH sensor.
The sensors are interrogated by the on-chip arbitrary waveform generator that is
shared among all channels. The arbitrary waveform generator consists of a 8-bit R-2R
DAC, an 8-bit up-down counter and a 3-electrode-configuration RE voltage regulation
circuit [144]. The waveform generator provides stimulation waveforms with a maxi-
mum scan range of 1.1V and the scan rate ranging from 0.1mV/sec to 300V/sec. It
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 80
DNA
PH
×54
SRAM
WE
WE IREF
IIN
WA
VE
FO
RM
GE
NE
RA
TO
R
CE
RE
CLK 1.2 VIBIAS VBIAS
CCII
CLOCK
BIAS
GLOBAL
CLOCK
GLOBAL
BIAS
U
WB
TX
IREF
CHANNEL
DUAL-
SLOPE
ADC
TIMING
COEFFICIENTS
SRAM
WAVEFORM
GENERATOR SRAM
Figure 3.4: Wireless DNA analysis microsystem functional block diagram.
consumes 900µA from a 1.2V supply when driving a 5nF load at the maximum scan
rate of 300V/sec. This maximum rate is not required for the DNA sensing applica-
tion as the scan rate is limited to low 100s of mV/sec. Other amperometric biochemical
sensing applications (such as, for example, neurotransmitter sensing [70]) require much
higher scan rates of up to 300V/sec. The microsystem presented here is designed so that
it can also be used in applications other than DNA sensing. As a result, the waveform
generator is designed such that it meets requirements for a general purpose biochemical
sensing microsystem but with the power scaling with the frequency. The digital data
representing the stimulation waveform properties are stored in the on-chip waveform
generator SRAM (Fig. 3.4).
A current conveyer is placed at the frontend of each channel to acquire the result-
ing sensory current at a low impedance. A dual-slope ADC quantizes the input redox
current and outputs a corresponding digital word. The digital output of each channel is
serialized on the chip and is wirelessly transmitted at a data rate of up to 10Mbps, using
an all-digital ultra-wide band transmitter. To enable independent channel programma-
bility, each channel also includes a bias voltage generation circuit, a clock generation
circuit, and an in-channel SRAM for setting the channel dynamic range and sensitivity.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 81
−
+
S1
S2
S2
VWE
CONTROL
LOGIC
IREF+
IREF-
CINT
VOUT2
(S1,S2)
−
+
VWE
CHOPPER
STABILIZATION
VLATCH
S2
S1
DIGITAL
OUTPUT
−
+
CURRENT CONVEYER DUAL-SLOPE ADC
WEs
VWE
Mn
Mp
Cc
DYNAMIC ELEMENT
MATCHING
−
+ IOUT
IIN
9-BIT
COUNTER
CHOPPER CLK
GENERATOR
−
+
Figure 3.5: Simplified top-level VLSI architecture of one chopper-stabilized integrated current-to-digital channel.
VWE
VbiasP
VbiasN
VcascP
cascNVIIN
IOUTCc
M1 M2
M3 M4
M5 M6
M7 M8
M9 M10M11
M12M13 M14 M15
M16M17
M18
M19 M20
M21 M22 M23 M24
M25
M26
M27
M28 M29
M
Mn
p
I-to-V
I-to-V
Figure 3.6: Detailed implementation of the current conveyer OTA with internal chopping anddynamically-matched low-current regulation.
3.4.2 Channel VLSI Architecture
The top-level VLSI architecture of one current-to-digital channel of the integrated elec-
trochemical sensory microsystem is shown in Fig. 3.5. Each channel consists of a
chopper-stabilized bidirectional current conveyer (Fig. 3.5, left) and a 9-bit dual-slope
ADC (Fig. 3.5, right).
The current conveyer buffers the input current and maintains the working electrode
at a fixed potential, VWE , as needed to induce a redox reaction. DNA analysis applica-
tions require both sourcing and sinking the redox current. A number of current conveyer
designs for electrochemical sensing applications have been reported [91–94]. In gen-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 82
eral, existing designs do not support bidirectional current recording and suffer from the
amplifier flicker noise and the mismatch within current mirrors. Fig. 3.5(left) depicts a
low-noise and accurate current conveyer VLSI architecture that overcomes these lim-
itations. Internal OTA chopper stabilization is utilized to reduce the effect of flicker
noise. The current conveyer utilizes low-current regulated-cascode current mirrors to
record small (i.e., as small as 10pA) bidirectional currents. Dynamic element matching
is utilized to improve the accuracy by averaging the mismatch in the current mirrors.
The current conveyer is comprised of a PMOS and an NMOS transistors Mn and
Mp connected in the feedback of the chopper-stabilized OTA. The negative feedback
ensures a known potential, VWE , at the working electrode is set by the voltage at the
negative terminal of the OTA. It also enables the current conveyer to source and sink
input current without the need for a DC offset current [92], which can disturb the DNA
charge balance. The currents through Mn and Mp are mirrored by dynamically-matched
current mirrors to the output of the current conveyer and are added.
Based on previously published results of DNA hybridization experiments on NME
working electrodes [138], it is determined that the on-chip ADCs must be able to dig-
itize bidirectional current in the 10pA to 100nA range or greater, and to cover a fre-
quency range of 0.01Hz to at least 1kHz. The dual-slope ADC architecture is selected
for this purpose because its dynamic range, sampling frequency, and nominal resolution
suit these requirements and can all be easily adjusted.
The dual-slope ADC shown in Fig. 3.5(right) consists of an integrating on-chip
variable capacitor CINT (adjustable from 1pF to 10pF, all the measurements here are
done using a 2pF capacitor value), regulated-cascode current sources IREF+ and IREF−,
a four-stage track-and-latch comparator, a 9-bit digital counter and control logic. All
switches are implemented as low-leakage switches as shown in an inset in Fig. 3.5.
The reference current sources are implemented as regulated-cascode current mirrors
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 83
to ensure accurate current sourcing over the operating dynamic range. The IREF+ is
implemented with PMOS devices and the IREF− is implemented with NMOS devices.
This can result in some mismatch between the IREF+ and IREF−. The effect of the
mismatch between the positive and negative current source does affect the linearity of
the ADC. These effects are within the specification and are reflected in the measured
spectrum of the ADC output and its ENOB presented in Section VI. The first stage of
the comparator is chopper-stabilized to reduce the effect of its offset and low-frequency
noise.
The dual-slope ADC operates in two phases. In phase one, the integrating capac-
itor CINT is charged by the input current IIN for a predetermined period of time T1.
Next, during the second phase of the operation, the capacitor is discharged to zero
by a DC reference current IREF (IREF+ or IREF−). By counting the duration of the
second phase, the time T2, a digital representation of IIN can thus be obtained as -
sign(IREF )×(T2/T1)×|IREF |. In this design the value of the IREF is programmable
(using an off-chip variable resistor) between 100pA to 50nA.
The in-channel SRAM can also be used to adjust the duration of the charging and
discharging cycles of the dual-slope ADC for the purpose of channel gain calibration.
For example if IREF is higher in the first channel compared to the second channel, then
the duration of the charging time T2 can be reduced for the first channel to compensate
for larger IREF and thus generating the same output digital code for both channels for a
given input current. This effectively calibrates each channel independently and reduces
the channel-to-channel gain mismatch.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 84
VLATCH
V
OUT+V
OUT-
VLATCHVLATCH
VBIAS
M1
M2
M3
M4 M
5M
6 M7
M9 M10
M8
M11 M12
M13M14 M15 M16
VIN+
VIN-
−
+
STAGE2 STAGE3
−
+
Figure 3.7: High-speed latched comparator circuit schematic diagram.
3.5 Circuit Implementation
3.5.1 Current Conveyer
As shown in Fig. 3.6 the OTA has been implemented as a folded-cascode amplifier
to provide a wide input dynamic range and a high gain. In this design, internal OTA
chopping has been implemented to reduce the effect of both flicker noise and the input
offset voltage. A set of chopper switches are placed at the input of the OTA. Another
set is placed after the NMOS tail current source. This significantly reduces the flicker
noise and offsets due to the input pair transistors and the NMOS tail current source
transistors. Minimum size switches are utilized to reduce the effect of charge injec-
tion into the working electrode. The output current mirrors are implemented using a
low-current regulated cascode topology. The regulated current mirrors M12, M15, M18
and M21, M24, M27 replicate IIN (fed through the NMOS and PMOS transistors) at the
output node with a high output impedance. The I-to-V blocks consisting of transistors
M13,14,16,17,19,20 and M22,23,25,26,28,29 adjust the gate voltage of the NMOS and PMOS
output cascode transistors M18 and M27 such that the drain-source voltages of the cur-
rent mirror transistor pairs M12, M15 and M21, M24 are pairwise equal thus ensuring
accurate current copying down to the pA level.
Mismatch in these regulated cascode current sources can significantly reduce the
linearity of the current conveyer. Dynamic element matching (DEM) [145] is employed
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 85
Table 3.1: ADC Comparator Transistor Sizing
Transistor W/L (µm) Transistor W/L (µm)
M1,2 24/1 M9,10 3/0.4M3 2/4 M11,12 36/0.5M4,5 4/1 M13,14 6/4M6,7 8/1 M15,16 36/0.5M8 4/4 — —
to reduce the effect of the mismatch in the current mirrors. The main source of mis-
match in the regulated cascode current mirrors is due to the mismatch in the transistor
pairs M12, M15 and M21, M24. To reduce the effect of the mismatch between these tran-
sistors, the DEM technique is applied by means of the chopper switches at the drains
of the current source transistors, so that the critical transistor pairs are dynamically
matched. In this method, the locations of the transistors M12, M15 and M21, M24 are
swapped periodically, at 500Hz, effectively averaging the current mirrors mismatch.
Ideally the error due to the mismatch in the current mirrors is reduced with a higher
DEM switching frequency which results in better averaging over one ADC conversion
cycle. Due to the non-ideality of the switches, an increase in the switching frequency
results in high-frequency switching noise and an increase in the charge injected into the
current path. This in turn causes an error at the output of the current conveyer. Based
on these considerations the 500Hz DEM frequency was chosen.
To achieve efficient flicker noise reduction, the chopper frequency needs to be higher
(at least twice) than the input signal maximum frequency (1kHz). The chopper clock
frequency was set to 10kHz to place the switching noise well outside the operating
frequency range. As a result the current conveyer bandwidth should be higher compared
to the case where no chopper stabilization is utilized so that the output settles in each
switching period. The current conveyer 3dB bandwidth is 35.7kHz.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 86
V6
V5
V4
V3
V2
V1
OUTV
D
C
C
C
CBP
M
ON-OFF KEYING (OOK)
MANCHESTER MODULATION
D IN
OUTVINV
PV
NV
(a) (b)
Figure 3.8: (a) Ultra-wideband transmitter circuit schematic diagram, and (b) schematic of onecurrent-starved inverter.
V6
V5
V4
V3
V2
V1
OUTV
DM
Figure 3.9: Timing diagram of the ultra-wideband transmitter.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 87
1Х6 BANK OF CROSS-VALIDATION CHANNELS
UWB TX
WAVEFORM
GENERATOR & SRAMCONTROL
LOGIC
9×6 ARRAY OF
CHANNELSRECE
WE
2X2μm2
55X55μm
ISFET
5X5μm2X2μm
2
2
2ONE CHANNEL
8Х8 ARRAY OF
2Х2μm WE2
ARRAY OF
WEs
Figure 3.10: Die micrograph of the 3mm×3mm 54-channel wireless DNA analysis SoC. TheSoC was fabricated in a 0.13µm standard CMOS technology.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 88
3.5.2 Dual-slope ADC Comparator
The ADC comparator is implemented with three stages of pre-amplifiers, with a total
gain of 60dB and the last stage with a high-speed latch as shown in Fig. 3.7. The first
stage of the comparator is implemented as a cross-coupled diode-connected gain stage.
This topology provides a moderate gain and a high frequency bandwidth. Chopper-
stabilization suppresses the input offset and ensures 9-bit accuracy. The second and
third stages are identical to the first one but with no chopping. The high-speed latch is
implemented with an NMOS input pair gain stage and a NMOS-PMOS cross-coupled
load. This topology provides high accuracy, low offset and a high frequency bandwidth.
The comparator transistor sizes are listed in Table 4.1.
3.5.3 Ultra-wideband Transmitter
The circuit diagram of the all-digital pulsed UWB transmitter is shown in Fig. 3.8(a).
The input data are modulated using on-off keying (OOK) Manchester modulation.
UWB pulses are generated on the rising edge of the modulated data (DM ). A delay line
bank is employed together with a capacitively coupled output combiner [150] as shown
in Fig. 3.8(a). The modulated data are passed through a delay line, and a delayed ver-
sion of the data are passed through three pulse generators. The pulse generators shape
a first-order Gaussian pulse at the rising edge of the input data. The presented digital
UWB transmitter achieves both power efficiency and spectral compliance in a much
smaller chip area compared to earlier designs [151, 152].
As illustrated in Fig. 3.9, each pulse generator forms pulses that are delayed, and
have opposite signs. By capacitively combining the three paths, the opposite signs
are canceled, and the zero-DC double-differentiated Gaussian pulse propagates to the
single-ended antenna [151, 152]. The width of the output pulse depends on the delays
in the delay line. The delay cells in all the paths are implemented as current-starved
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 89
0 5 10 15 20 25 30 35 40 45 50−140
−120
−100
−80
−60
−40
−20
0
2nd HARMONIC
3rd HARMONIC
SFDR = 59 dB
NORMALIZED POWER (dB)
SNR = 57 dB
FREQUENCY (Hz)
I = 350nAin
ELECTROCHEMICAL RECORDING
CHANNEL OUTPUT SPECTRUM
Figure 3.11: Experimentally measured spectrum of the electrochemical recording channel out-put for a 15Hz sinusoidal full-scale (350nA) input.
inverters, shown in Fig. 3.8(b), to allow for tuning of the UWB pulse width.
3.6 Electrical Experimental Results
The fabricated prototype die micrograph is depicted in Fig. 3.10. The 54 channels are
arranged in a 9×6 array on a 3mm×3mm 0.13µm CMOS die. Two channel types with
two different WE aluminum base configurations are implemented. A set of 48 channels
of the first type scan 4 WEs each, in order to perform initial detection of DNA. They
have three different WE aluminum base sizes of 2µm×2µm (twice), 5µm×5µm and
55µm×55µm each as needed to cover a wide combined dynamic range. An additional
set of 6 channels of the second type (at the bottom of the array in Fig. 3.10) additionally
scan a sub-array of 8×8 2µm×2µm WEs each. These redundant-electrode sub-arrays
are utilized for DNA detection results cross-validation and for titer DNA concentration
measurements.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 90
100
101
102
103
104
SNDR=48dB LSB=8.6pA
f = 23 kHzs
SNDR=53dBLSB=132pA
SNDR=59dB LSB=1.05nA
f = 2 kHzs
10p 100p 1n 10n 100n 1μ
DIG
ITA
L O
UT
PU
T C
OD
E
f = 11kHzs
INPUT CURRENT (A)
CHANNEL
TRANSFER
CHARACTERISTIC
Figure 3.12: Experimentally measured transfer characteristics of the current-to-digital channelfor three sampling frequencies.
Dynamic performance of the entire channel was measured by applying a 15Hz full-
scale (350nA) sinusoidal input current sampled at 23kHz. Fig. 3.11 shows the 65536-
point FFT of the measured ADC output. The strong second harmonic is due to the
single-ended nature of the architecture of the ADC. The resulting effective number of
bits (ENOB) is 9.1.
For static performance characterization the input DC current of one typical channel
was swept between 10pA and 350nA as shown in Fig. 3.12. The input dynamic range
is 93dB cumulatively for the three sampling frequency settings, or 48dB at one fixed
sampling frequency of 2kHz. The dynamic range for each setting is computed by taking
the ratio of the maximum signal that saturates the ADC to the LSB for a given sampling
frequency setting.
Two sets of ENOB measurements were conducted to study the effectiveness of the
in-channel gain calibration using the in-channel SRAM to adjust the ADC timing. In
the first measurement no calibration has been performed and the timing parameters
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 91
ENOB (BITS)
NU
MB
ER
OF
OC
CU
RA
NC
ES
8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.60
2
4
6
8
10
12
MEAN= 9.01 BITS
SD(3σ) = 0.307 BITS
N= 32
(a)
ENOB (BITS)
NU
MB
ER
OF
OC
CU
RA
NC
ES
8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.60
2
4
6
8
10
12
MEAN= 9.15 BITS
SD(3σ) = 0.252 BITS
N= 32
(b)
Figure 3.13: Experimentally measured output ENOB of 32 channels (from 16 chips, two chan-nels each) for a 15Hz 350nA sinusoidal input (a) without calibration (b) with in-channel cali-bration.
of all channels are set to a constant value (all the ADCs have the same charging and
discharging phases duration). Fig. 3.13(a) shows the experimentally recorded ENOB
for a 15Hz full-scale (350nA) sinusoidal input current from 32 channels on 16 chips
(two channels per chip), with the ADC clocked at 12MHz. The mean ENOB and the
corresponding standard deviation are 9.01 and 0.307 respectively. Next, the same set
of experiments were repeated with the calibrated channels, as described at the end of
Section IV.B. Fig. 3.13(b) shows the experimentally recorded ENOB for the same input
tone as the pervious case. The mean ENOB and the corresponding standard deviation
are 9.15 and 0.252 respectively. The calibration improves the ENOB standard deviation
by 17 percent.
Fig. 3.14 shows the ADC ENOB versus the frequency for a full-scale (350nA) si-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 92
101
102
103
104
5
6
7
8
9
10
EN
OB
(B
ITS
)
FREQUENCY (Hz)
I = 350nAin
Figure 3.14: Experimentally measured ENOB vs. input frequency for the in-channel ADC.
nusoidal input current. The ADC maintains an ENOB of greater than 8.5 bits at up to
3.4kHz. The drop in the ENOB is due to the limited bandwidth of the frontend current
conveyer and high-frequency switching interference noise.
The experimentally measured relative errors of the digital output for the input cur-
rent swept between ±10pA and ±350nA are shown in Fig. 3.15. The relative error stays
below 6 percent over the whole operating range. This is an improvement of 33 percent
compared to the design without the DEM [155]. Fig. 3.15 illustrates an improvement
in the output relative error of approximately 25 percent due to the use of DEM in this
design as compared to a previously reported design without DEM [155]. The current
conveyer achieves a dynamic range of 8.6pA to 350nA or 93dB. The lower limit is de-
fined by the ADC LSB and the higher limit is defined by the input current that saturates
the current conveyer.
Fig. 3.16 shows the experimentally recorded output current distribution for the input
current of 100pA measured from 32 channels on 16 chips (two channels per chip) with-
out dynamic element matching [155] and with dynamic element matching implemented
in this design. The mean output current and the corresponding standard deviation with-
out dynamic element matching [155] are 81.26pA and 20.2pA, respectively. In this de-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 93
−4
-2
0
2
4
6
10p 100p 1n 100n
INPUT CURRENT (A)
10n
RE
LA
TIV
E E
RR
OR
(%
)
(a)
-100n -10n -1n -100p -10p
INPUT CURRENT (nA)
−2
0
2
4
6
−4
RE
LA
TIV
E E
RR
OR
(%
)
(b)
Figure 3.15: Experimentally measured relative error of the output digital code of the currentconveyer connected with the dual-slope ADC for (a) 10pA to 350nA and (b) -350nA to -10pAinput current.
sign, with dynamic element matching added, they are 92.12pA and 9.2pA, respectively.
Adding DEM results in a 54 percent improvement in channel-to-channel accuracy.
As shown in Fig. 3.17 the same experiment is repeated with the input current level
of 100nA. The mean output current and the corresponding standard deviation without
dynamic element matching [155] are 100.26nA and 34pA, respectively. In this design,
with dynamic element matching added to the design, they are 100.18nA and 22pA,
respectively. Adding DEM results in a 35 percent improvement in channel-to-channel
accuracy.
The input Manchester-encoded data to the UWB transmitter and its measured output
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 94
CURRENT (pA)
NU
MB
ER
OF
OC
CU
RA
NC
ES
0 20 40 60 80 100 120 1400
2
4
6
8
10
12
MEAN= 81.26pA
SD(3σ) = 20.2pA
N= 32
(a)
CURRENT (pA)
NU
MB
ER
OF
OC
CU
RA
NC
ES
0 20 40 60 80 100 120 140
0
2
4
6
8
10
12
MEAN= 92.12pA
SD(3σ) = 9.2pA
N= 32
(b)
Figure 3.16: Experimentally measured output current of 32 channels (from 16 chips, two chan-nels each) for the input current of (a) 100pA without DEM [32] and (b) 100pA with DEM (thiswork).
UWB pulses are shown in Fig. 3.18. The UWB pulses are measured using custom-built
UWB antennas (5cm spacing between the transmitter and receiver) and an custom-built
receiver. A zoomed-in version one such the measured UWB pulse overlayed on a simu-
lated UWB pulse is shown in Fig. 3.19. As it can be seen the measured pulse resembles
the expected UWB pulse but includes minor ringing due to the package bondwire in-
ductance. The measured output power spectrum of the UWB transmitter is plotted in
Fig. 3.20. The power spectrum complies with the FCC-defined 0-1 GHz UWB spectrum
(mask) also shown. An example of the input data to the UWB transmitter Manchester-
encoded at the rate of 10Mb/s and the data received at the distance of 5cm using a
custom-built UWB receiver is shown in Fig. 3.21.
Table II provides a summary of experimentally measured characteristics of the
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 95
CURRENT (nA)100.10 100.15 100.20 100.25 100.30 100.35 100.400
1
2
3
4
5
6
7MEAN= 100.26nA
SD(3σ) = 34pA
N= 32
NU
MB
ER
OF
OC
CU
RA
NC
ES
(a)
CURRENT (nA)100.10 100.15 100.20 100.25 100.30 100.35 100.400
1
2
3
4
5
6
7
MEAN= 100.18nA
SD(3σ) = 22pA
N= 32
NU
MB
ER
OF
OC
CU
RA
NC
ES
(b)
Figure 3.17: Experimentally measured output current of 32 channels (from 16 chips, two chan-nels each) for input current of (a) 100nA without DEM [32] and (b) 100nA with DEM (thiswork).
integrated CMOS DNA analyzer SoC.
3.7 Experimental Electrochemical Results
To validate the performance of the channel in electrochemical sensing applications,
CV, first, scans of a DNA reporter potassium ferricyanide and a buffer solution were
performed. Potassium ferricyanide K4[Fe(CN)6] is commonly used in electrochemical
DNA detection systems as a redox reporter. Cyclic voltammetry recordings of 20µM
potassium ferricyanide solution and 1M potassium phosphate buffer (pH 7.3) have been
carried out. On-chip waveform generator was utilized to generate the CV excitation
waveform. A 500mV/sec 0.7V peak-to-peak ramp-up-ramp-down CV waveform with
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 96
100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0−0.5
0
0.5
1
TIME (μs)
AMPLITUDE (V)
1 1 0 1 0 1 1 1
(a)
−0.1
−0.05
0
0.05
0.1
TIME (μs)
AM
PL
ITU
DE
(V
)
100.6 100.8 101.0 101.2 101.4 101.6 101.8 102.0
(b)
Figure 3.18: Experimentally measured (a) Manchester-encoded input data to the UWB trans-mitter and (b) the output pulses.
a 50ms resting period was applied between a 55µm×55µm flat gold working electrode
in Fig. 3.2(b) and an off-chip Ag/AgCl reference electrode (Basi, RE-5B). The result-
ing CV curves recorded by the chopper-stabilized channel with DEM are shown in
Fig. 3.22. The phosphate buffer CV curve occurs mainly because of the charging and
discharging of the electrode-electrolyte double layer capacitance and thus has no peak.
In contrast, the potassium ferricyanide CV curve shows two distinct peaks at the re-
duction and oxidation voltages of potassium ferricyanide. Indeed, such flat electrodes,
typically produce such distinct redox peaks.
The recorded CV waveforms characteristics (redox peaks location and spacing) are
similar to those reported in the literature [141, 142]. A typical CV curve is shown in
Fig. 1.11(b). The separation between the two peak potentials, ∆Ep=Epc-Epa, can be
used determine the electrochemical reversibility for a redox couple. For a reversible
CV reaction one has [102]
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 97
80.42 80.43 80.44 80.45 80.46−0.12
−0. 1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
TIME (μs)
AM
PL
ITU
DE
(V
)
SIMULATED
MEASURED
RINGING
Figure 3.19: Wirelessly measured UWB pulse at the distance of 5cm using a custom-built UWBreceiver.
109
−100
−90
−80
−70
−60
−50
−40
−30
108
FREQUENCY (Hz)
OU
TP
UT
PO
WE
R (
dB
m)
FCC MASK
Figure 3.20: Experimentally measured UWB transmitter output spectrum (direct output of thetransmitter driving a 50 ohm load). The output spectrum is compliant with the 0-1GHz FCCUWB band output power criteria
.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 98
0 0.25 0.750.5 1
0
0.5
1
TIME (µS)
TRANSMITTED DATA @ 10Mb/s
MANCHESTER-ENCODED DATA
AM
PL
ITU
DE
(V
)
(a)
0 0.5 10.25 0.750
0.5
1
TIME (µS)
RECEIVED DATA (5cm)
AM
PL
ITU
DE
(V
)
(b)
Figure 3.21: (a) Manchester-encoded input data to the UWB transmitter and (b) the correspond-ing data received wirelessly at a 5cm distance.
−700 −600 −500 −400 −300 −200 −100 0−12
−10
−8
−6
−4
−2
0
2
4
6
8
V -V (mV)
CU
RR
EN
T (
nA
)
OXIDATION
VOLTAGE
RE WE
REDUCTION
VOLTAGE
FORWARD
SCAN
REVERSE
SCAN
1M POTASSIUM
PHOSPHATE BUFFER
20µM K [Fe(CN )]4 6
Figure 3.22: Experimentally recorded cyclic voltammograms of 1M potassium phosphatebuffer and 20µM potassium ferricyanide solution using the 55µm×55µm working electrodein Fig. 3.2(b)
.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 99
−700 −600 −500 −400 −300 −200 −100 0−12
−10
−8
−6
−4
−2
0
2
4
6
8
V -V (mV)
CU
RR
EN
T (
nA
)
RE WE
20µM K [Fe(CN) ]
10µM K [Fe(CN) ]
30µM K [Fe(CN) ]
40µM K [Fe(CN) ] 4 6
4 6
4 6
4 6
OXIDATION
VOLTAGEREDUCTION
VOLTAGE
Figure 3.23: Experimentally recorded cyclic voltammograms of 10µM, 20µM, 30µM and40µM potassium ferricyanide solution using the 55µm×55µm working electrode in Fig. 3.2(b)
.
CU
RR
EN
T (
nA
)
10 20 30 40 600
2
4
6
8
K [Fe(CN) ] CONCENTRATION (µM)4 6
Figure 3.24: Calibration curve for the peak reduction current of potassium ferricyanide solutionfor the 55µm×55µm Au
working electrode in Fig. 3.2(b).
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 100
Table 3.2: Experimentally Measured Electrical Characteristics
Technology 0.13µm CMOSSupply Voltage 1.2VArea 3mm×3mmArray Dimensions 9×6 channelsChannel Size 200µm×300µmSensitivity 8.6pAPower Consumption (System)
Waveform Generator 1.1 mWSRAM 1.3µWUWB Transmitter 400µW
Power Consumption (Channel)Current Conveyer 8µWComparator 19µWBiasing 4µWDigital 11µWTotal (channel) 42µW
CURRENT (nA)
NU
MB
ER
OF
OC
CU
RA
NC
ES
6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.80
3
5
7
9
11
13
MEAN= 7.10nA
SD(3σ) =0.22nA
N= 48
Figure 3.25: Experimentally recorded peak reduction current of the 40µM potassium ferri-cyanide solution recorded using the 55µm×55µm working electrode shown in Fig. 3.2(b) by48-channel on the CMOS DNA analysis SoC.
∆Ep =0.058
n, (3.1)
where n is the number of electrons transferred between the redox complex. This value
is independent of the scan rate for fast electron transfer. Increasing values of ∆Ep as a
function of increasing scan rate indicates the presence of electrochemical irreversibil-
ity. In practice, the theoretical value of 58/n mV for ∆Ep is seldom observed. In all
experiments the potassium ferrocyanide solution was diluted in 1M potassium phos-
phate buffer. This combined with the slow electron transfer kinetics present in case of
our complex multi-material electrodes have caused the peak voltage difference to de-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 101
∆ pH
CU
RR
EN
T (
nA
)
−2 −1.5 −1 −0.5 0 0.5 1 1.5 22
3
4
5
6
7
8
9
10
11
Figure 3.26: Experimentally measured on-chip pH sensor calibration curve relative to pH of 7.A total of 60 measurements from 3 chips, 20 measurements each, have been performed. Thecorresponding 3σ error bars are shown.
viate from the theoretical 58mV value [33, 34]. In all experiments, the first four CV
curves were discarded and the fifth curve was used as the recorded data. As a result,
the peak recorded redox current is consistent for different concentrations. Other record-
ings [33, 34] using a similar DNA detection method also achieve ∆Ep higher than the
theoretical value of 58mV.
Next, CV scans of a potassium ferricyanide solution with four different concen-
trations (10µM to 40µM) using a 55µm×55µm flat gold working electrode shown in
Fig. 3.2(b) have been performed to study the effect of a change in the DNA reporter
concentration on the recorded redox current. As shown in Fig. 3.23, the peak current
at the reduction and oxidation voltages of potassium ferricyanide increases with an in-
crease in its concentration. The corresponding calibration curve is shown in Fig. 3.24.
This curve demonstrates the linear relationship between the concentration of potassium
ferricyanide and the output redox current.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 102
CV scans of a potassium ferricyanide solution at 40µM have been conducted on
all 48 channels with 55µm×55µm flat gold working electrodes shown in Fig. 3.2(b)
to study the effect of the channel-to-channel variation on the CV recording results. A
500mV/sec 0.7V peak-to-peak ramp-up-ramp-down CV waveform with a 50ms resting
period was used in this experiment. Fig. 3.25 shows the resulting peak reduction cur-
rents recorded by the 48 channels. The mean peak reduction current is 7.02nA, and the
three-sigma variation is 0.22nA.
To validate the performance of the pH sensors, the sensitivity of the ISFET is mea-
sured in response to change in the solution pH level. A preliminary analysis of the
ISFET characteristics indicated that the pH sensors have different threshold voltages,
due to the trapped charge on the floating gates of the ISFETs. The UV radiation and
bulk substrate biasing (for 8 hours) technique was used to remove the trapped charge
and thus remove the threshold voltage mismatch among the pH sensors. Before the
pH sensor sensitivity is measured, the sensor array must be etched for 10s in a 10%
buffered hydrofluoric acid solution. Measurements made without this step are gener-
ally very noisy and result in a low sensitivity. After the threshold voltage calibration,
the sensitivity of the pH sensor is measured in a 0.1M NaCl electrolyte by adding small
quantities of hydrochloric acid to change the solution pH from five to nine. Recording
the calibrated steps in the measured current leads to the finding that the array has a lin-
ear response of 1.8nA/pH. The corresponding calibration curve with error bars (from
three chips, 20 measurements each) is shown in Fig. 3.26.
3.8 Synthetic Prostate Cancer DNA Detection
The SoC has been validated in label-free amperometric detection of synthetic prostate
cancer DNA. The DNA sequences are synthesized by Integrated DNA technology [154].
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 103
−12
−10
−8
−6
−4
−2
0
2
4
6
8
BARE GOLD ELECTRODE
GOLD ELECTRODE WITH PROBE DNA
NONCOMPLEMENTARY TARGET DNA
COMPLEMENTARY TARGET DNA C
UR
RE
NT
(n
A)
DETECTION
NO DETECTION
NO HYBRIDIZATION
K [Fe(CN) ] 64
OXIDATION VOLTAGE
(SSDNA)
−700 −600 −500 −400 −300 −200 −100 0
V -V (mV)RE WE
(DSDNA)
10
12
Figure 3.27: Experimentally measured cyclic voltammetry results of 5µM prostate cancer syn-thetic DNA detection from the 55µm×55µm flat gold working electrode in Fig. 3.2(b)
.
The following synthetic DNA sequences have been used in the experiments: DNA
probes (5ThioMC6-D/AG CGC GGC AGG AAG CCT TAT), complementary target
DNA (ATA AGG CTT CCT GCC GCG CT) and non-complementary DNA (TTT TTT
TTT TTT TTT TTT TT). All the DNA experiments were conducted at room tempera-
ture. In all the experiments a 500mV/sec 0.7V peak-to-peak ramp-up-ramp-down CV
waveform with a 50ms resting period was applied between the working electrode and a
commercially available off-chip Ag/AgCl reference electrode (Basi RE-5B) [153].
Fig. 3.27 shows cyclic voltammetry scans from an on-chip 55µm×55µm flat gold
electrode for the 5µM prostate cancer synthetic DNA cyclic voltammetry recording,
in a 40µM potassium ferricyanide solution. The CV scan rate and range were set
to 500mV/sec and 0.7V peak-to-peak, respectively, with a 40ms resting period. The
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 104
PROBE
DNA
NONCOMPLEMENTARY
TARGET DNA
COMPLEMENTARY
TARGET DNA
CU
RR
EN
T (
nA
)
−12
−10
−8
−6
−4
−2
0
AT V -V = -450mVRE WE
ABSTRACT TIME
BARE GOLD 55μm×55μm
FLAT ELECTRODE
DETECTIBLE SIGNAL
CHANGE
Figure 3.28: Experimentally measured 5µM prostate cancer synthetic DNA cyclic voltamme-try recording 3σ error bars from 3 chips 60 measurements each from 55µm×55µm flat goldworking electrodes in Fig. 3.2(b).
bare gold electrode CV scan demonstrates well-defined oxidation and reduction peaks,
whereas scans taken using 5µM single-stranded probe DNA attached to electrodes show
a reduction in the oxidation/reduction peaks. This is expected since thiolated DNA
probes create a negatively charged film on the electrode repelling the negatively charged
electrochemical reporter potassium ferricyanide as illustrated in Fig. 3.1. Further adding
a 5µM non-complementary DNA target does not change the CV signal oxidation peak
value significantly indicating that non-specific adsorption is negligible. On the other
hand, adding a 5µM complementary target single-stranded DNA onto the chip leads to
creation of double-stranded DNA on the biosensing electrode resulting in an additional
negative charge and elimination of potassium ferricyanide redox peaks. The corre-
sponding error bars (from 3 chips, 20 measurements each) are shown in Fig. 3.28. As it
can be seen, the detectible signal change in this case is 2.85nA.
The same set of experiments were repeated with the on-die nanostructured elec-
trodes to study their DNA detection capabilities. Fig. 3.29 shows the CV curves ob-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 105
−700 −600 −500 −400 −300 −200 −100 0
V -V (mV)RE WE
−4
−3
−2
-1
0
1
2
3
4
5
6
CU
RR
EN
T (
nA
)
BARE GOLD ELECTRODE
NONCOMPLEMENTARY TARGET DNA
COMPLEMENTARY TARGET DNA
GOLD ELECTRODE WITH PROBE DNA (SSDNA)
(DSDNA)
DETECTION
NO DETECTION
NO
HYBRIDIZATION
7
Figure 3.29: Experimentally measured cyclic voltammetry results of 100aM prostate cancersynthetic DNA detection, from 2µm×2µm nanostructured working electrodes in Fig. 3.3(e)
.
BARE NANOSTRUCTURED
2μm×2μm MICROELECTRODE
PROBE
DNA
NONCOMPLEMENTARY
TARGET DNA
COMPLEMENTARY
TARGET DNA
CU
RR
EN
T (
nA
)
6
5
4
3
2
1
0
AT V -V = -200mVRE WE
ABSTRACT TIME
DETECTIBLE SIGNAL
CHANGE
Figure 3.30: Experimentally measured 100aM prostate cancer synthetic DNA cyclic voltam-metry recording 3σ error bars from 3 chips, 60 measurements each, from 2µm×2µm nanostruc-tured working electrodes in Fig. 3.3(e)
.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 106
10−19
10−17
10−15
10−13
10−11
10−9
10−7
CONCENTRATION (M)
I -I
0
25
50
75
100
10−5
DS
DN
AS
SD
NA
SS
DN
AI
(%
)
NUMBER of DSDNA STRANDS
10 102
1040
106
108
1010
1012
1014
10aM
DETECTION
LIMIT
100fM
DETECTION
LIMIT
100nM
DETECTION
LIMITΔI
=
Figure 3.31: Experimentally measured microelectrode characteristics, detection limits and dy-namic ranges in prostate cancer synthetic DNA detection using the three electrodes types shownin Fig. 3.3(d) and (e) and Fig. 3.2(b). Error bars (3 sigma) are from 3 chips, 100 measurementseach.
tained for a nanostructured electrode grown at VRE-VWE = 0mV for 100aM prostate
cancer synthetic DNA concentration, in a 40µM potassium ferricyanide solution. As
expected, compared to the flat gold electrodes the nanostructured electrodes typically
do not exhibit the redox peaks [138]. As it can be seen from Fig. 3.29 the current level
in the presence of complementary target DNA (DSDNA) is smaller compared to the
case where only the probe DNA (SSDNA) is present. The corresponding error bars
(from 3 chips, 60 measurements each) are shown in Fig. 3.30. As it can be seen, the
detectible signal change in this case is 1.1nA.
DNA sensing experiments were conducted for the target DNA concentrations of
1aM to 10µM to study the detection limits of the on-die nanostructured electrodes and
the on-die flat gold electrode. The resulting characteristics, detection limits and dy-
namic ranges of the two nanostructured electrode types and the 55µm×55µm flat gold
electrode are given in Fig. 3.31. ∆I is computed as (IDSDNA-ISSDNA)/ISSDNA)×100,
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 107
where IDSDNA is the redox current after the hybridization and ISSDNA is the redox cur-
rent before the hybridization. All the current recordings for nanostructured electrodes
are taken at VRE-VWE of -200mV and at at VRE-VWE of -250mV for the flat gold
electrodes. The corresponding error bars (from 3 chips, 100 measurements each) are
also shown in Fig. 3.31.
The detection limit, defined as the lowest concentration for which the background-
subtracted signal is three times higher than the standard deviation at that concentra-
tion, for nanostructured electrodes grown at VRE-VWE = 0mV as shown in Fig. 3.31
is 10aM. The 10aM sensitivity achieved using the optimized on-CMOS nanostructured
electrode enables PCR-free detection for many applications. This limit corresponds to
the detection of fewer than 100 copies of the target sequence.
Another benefit of having several types of electrodes on the same chip is that dif-
ferent electrodes cover different concentration ranges. As it can be seen from Fig. 3.31,
the nanostructured electrodes grown at VRE-VWE = 0mV cover a dynamic range (de-
fined as the range at which the 3 sigma error bar of the given concentration is below 100
and above 0 on the y-axis) of 3aM to 100fM, the nanostructured electrodes grown at
VRE-VWE of 100mV cover a dynamic range of 100fM to 90pM, and the 55µm×55µm
flat gold electrodes cover a dynamic range of 1nM to 10µM. As a result, by fabricating
electrodes with different degrees of nanostructuring, we can significantly expand the
dynamic range of the CMOS DNA sensing microsystem (as wide as 140dB with these
types of nanostructured microelectrodes [138]).
Table 5.3 provides a comparative analysis of the presented design and existing
amperometric biochemical sensory microsystems. The design presented in this work
achieves the highest dynamic range and the lowest sensitivity in terms of ADC LSB.
We have shown successful detection of 20-base pair long synthetic prostate cancer DNA
from several types of on-chip Au electrodes. The 10aM detection limit is the lowest de-
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 108
tection limit reported in literature from an integrated circuit-based DNA sensor to date.
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 109
Tabl
e3.
3:C
ompa
rativ
eA
naly
sis
ofA
mpe
rom
etri
cSe
nsor
yM
icro
syst
ems
Syst
emIS
SCC
08JS
SC08
JSSC
09IS
SCC
10IS
SCC
10T
his
Wor
k[2
0][2
6][8
4][9
9][9
7]Te
chno
logy
(CM
OS)
0.18µ
m0.
25µ
m0.
5µm
0.35
µm
0.6µ
m0.
13µ
mPo
wer
25m
W16
0mW
0.6m
W84
.5m
WN
/A0.
35m
WSu
pply
Volta
ge5.
0V2.
5V3.
0V3.
3V3.
3V1.
2VC
hip
Are
a11
.2m
m2
15m
m2
2.25
mm
24m
m2
25.8
mm
29m
m2
Ele
ctro
deC
ount
576
5410
010
040
600
Cha
nnel
Sens
ing
Prot
ocol
CV
CV
ISIS
CA
CV
Cha
nnel
Cou
nt24
1610
010
040
54Ty
peof
Ele
ctro
des
2D2D
2D2D
2D2D
Flat
,3D
Poly
mer
Gol
dG
old
Gol
dpH
Nan
ostr
uctu
red
Gol
dPo
wer
N/A
10m
W6µ
W0.
84m
WN
/A42µ
WD
ynam
icR
ange
N/A
60dB
58dB
N/A
50dB
93dB
(3-m
ode)
Con
vers
ion
Rat
e10
Hz
10kH
z10
kHz
N/A
1Hz
10kH
zSe
nsiti
vity
97pA
240p
A10
kHz
330p
A25µ
V8.
6pA
EN
OB
11bi
ts9
bits
8bi
tsN
oA
DC
12bi
ts9.
1bi
tsW
avef
orm
Gen
erat
orN
oN
oY
esY
esN
oY
esTy
pe—
—Sq
uare
Wav
eSq
uare
Wav
e—
8-bi
tPro
gram
mab
leFr
eque
ncy
(Per
iod)
——
10kH
z50
MH
z—
10kH
zPo
wer
——
——
—1.
1mW
(5nF
Loa
d)Tr
ansm
itter
No
No
No
No
No
Yes
Prot
ocol
——
——
—0-
1,3-
10.6
GH
zU
WB
Dat
aR
ate
——
——
—10
Mbp
sPo
wer
——
——
—10
0µW
Sens
ors
Type
DN
AD
NA
Prot
ein
DN
AD
NA
DN
AO
n-di
eY
esY
esY
esY
esY
esY
esL
abel
-fre
eN
oY
esN
oN
oN
oY
esPC
R-f
ree
No
No
No
No
Yes
Yes
Bio
mol
ecul
eTy
pe30
Bas
e18
Bas
eB
ilaye
rLip
idB
ovin
eSe
rum
Sing
leN
ucle
otid
e20
Bas
ePa
irs
Pair
sM
embr
ane
Alb
umin
Poly
mor
phis
ms
Pair
sC
once
ntra
tion
10nM
-100
nM10
0nM
1µM
100m
MN
/A10
aM-1
0µM
CHAPTER 3. CYCLIC VOLTAMMETRY AND PH SENSING 110
3.9 Chapter Summary
A 54-channel 0.13µm CMOS fast-scan cyclic voltammetry DNA analysis SoC has been
presented. The microsystem includes 600 time-multiplexed DNA sensors and 54 pH
sensors. It also includes an arbitrary waveform generator, an on-chip memory, an in-
channel low-noise chopper-stabilized frontend current conveyer with dynamic element
matching, an in-channel dual-slope ADC and a fully digital ultra-wideband transmit-
ter. Chopper stabilization achieves input-referred noise of less than 0.13pA over the
operating bandwidth. Dynamic element matching improves current conveyer accuracy
by 54 percent at the 100pA input current level. The in-channel SRAM enables in-
channel calibration which results in a 17 percent improvement in channel-to-channel
ENOB variation. Each channel occupies an area of 0.06mm2 and consumes 42µW of
power from a 1.2V supply. The presented current-to-digital channel design achieves a
combined dynamic range of 93dB with the sensitivity of 8.6pA. Two types of nanostruc-
tured microelectrodes and one type of a flat gold electrode have been characterized in
on-CMOS DNA prostate cancer detection. The on-chip nanostructured microelectrodes
achieve label-free PCR-free detection limit of 10aM, which is the lowest reported on-
CMOS detection limit.
111
Chapter 4
Impedance Spectroscopy DNA
We present a 54-channel, mixed-signal CMOS DNA analyzer that utilizes frequency
response analysis (FRA) to extract the real and imaginary impedance components of
the biosensor. Two computationally intensive operations, the multiplication and in-
tegration required by the FRA algorithm, are performed by an in-channel dual-slope
multiplying ADC in the mixed-signal domain resulting in minimal area and power con-
sumption. Multiplication of the input current by a digital coefficient is implemented
by modulating the counter-controlled duration of the charging phase of the ADC. In-
tegration is implemented by accumulating output digital bits in the ADC counter over
multiple input samples. The 1.2mm×1.6mm prototype fabricated in a 0.13µm standard
CMOS technology has been validated in prostate cancer synthetic DNA detection. Each
channel occupies an area of only 0.06mm2 and consumes 42µW of power from a 1.2V
supply.
4.1 Introduction
This Chapter presents a scalable, multi-channel, compact and low-power CMOS impedance
spectroscopy DNA analyzer. Frequency response analysis (FRA) algorithm is utilized
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 112
to extract the real and imaginary components of the biosensor impedance [156]. The
proposed microsystem consists of a programable on-chip waveform generator and 16
impedance extraction channels. Each channel includes a current-mode input dual-slope
multiplying ADC. It efficiently performs multiplication and integration, two computa-
tionally intensive operations required to implement the FRA algorithm. Multiplication
of the input current by a digital coefficient is implemented by modulating the counter-
controlled duration of the charging phase of the ADC by that coefficient. Integration
is implemented by accumulating the output digital bits in the ADC counter. The dual-
slope multiplying ADC utilizes mostly the same circuits as a conventional dual-slope
ADC, and the multiplication and integration are achieved by modifying the ADC algo-
rithm. The rest of the chapter is organized as follows. Section II presents the principle
of DNA detection on a CMOS die. Section III presents the impedance spectroscopy
VLSI architecture. Section IV details the circuit implementation of the VLSI architec-
ture. Section V demonstrates the electrical experimental results obtained from a 0.13µm
CMOS prototype. In Section VI, results of on-chip impedance spectroscopy of DNA in
prostate cancer screening are presented.
4.2 DNA Detection Principle
The principle of the label-free DNA detection method is shown in Fig. 3.1. It employs
potassium ferrocyanide K4[Fe(CN6)] reporter. Potassium ferrocyanide is a negatively
charged redox complex with well-defined electrochemical signature exhibiting oxida-
tion and reduction currents at VWE-VRE of -450mV and -200mV respectively [140].
The maximum electron transfer between the electrode and potassium ferrocyanide is
achieved in the absence of DNA target and probe as illustrated in Fig. 3.1(a). The
oxidization current IOX drops when the Au electrode surface is hybridized with nega-
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 113
tively charged probe DNA, as illustrated in Fig. 3.1(b). When the complementary DNA
binds with the probe DNA, the surface negative charge further increases and the oxi-
dization current is further reduced, as shown in Fig. 3.1(c). This change in the current
is an indicator of the target DNA presence and concentration. In other words, the pres-
ence of negatively charged DNA on the biosensor surface is translated to a decrease
in the potassium ferrocyanide oxidation/reduction current creating a detectible signal
change [141, 142].
The DNA sensing electrodes are created by first forming passivation openings on
the top metal layer (aluminum) of the CMOS die similarly to how it is done for wire
bond pads. Electroless electroplating is then employed to deposit nickel (2µm), palla-
dium (0.2µm) and gold (0.1µm) on the exposed Al surface to form a bio-compatible
electrode surface. After the electrode fabrication, the die is wire-bonded and the bond-
ing wires are insulated with a biocompatible epoxy to enable on-chip electrochemical
experiments without damaging the bonding wires [157].
∫
∫
cos(ωt)
BIOSENSOR
sin(ωt)
FRA UNIT
REAL
IMAG
Asin(ωt+φ)
SIG
NA
L G
EN
ER
AT
OR
(Q
- O
SC
ILL
AT
OR
)
Figure 4.1: Block diagram of a frequency-response analyzer (FRA) system for biosensorimpedance spectroscopy.
4.3 Impedance Spectroscopy VLSI Architecture
A small-signal model of the electrode-electrolyte interface in an electrochemical cell is
shown in the center of Fig. 1.8. Fast fourier transform (FFT) and frequency-response an-
alyzer (FRA) are two methods widely used for characterizing the electrode impedance [156].
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 114
DUAL-SLOPE MULTIPLYING ADCBIOSENSOR
CWE
RS
RCT
SRAM1
REWE
OR
REAL
IMAG∫I-V
D=sin(n) OR D=cos(n)
I IN
DAC
sin(n)
WAVEFORM
GENERATOR
SRAM2
CLK
1.2 V
IBIAS VBIAS
CDB
MULTI-FREQUENCY
CLOCK GENERATOR
PATTERN
GENERATOR
Figure 4.2: Impedance spectroscopy microsystem functional block diagram.
Compared to the FFT, the FRA method requires simple circuitry and can be imple-
mented on a small silicon area, making it suitable for sensory array microsystems. A
functional block diagram of the FRA algorithm is shown in Fig. 4.1. The sensor is in-
terrogated with a sinusoidal voltage. Multiplication of the sensor response Asin(ωt+ϕ)
with sin(ωt) or cos(ωt) and integration of the results over one cycle of the interroga-
tion signal results in separation of the real and the imaginary components of the sensor
impedance as follows [156]
Real =
∫ T
0
Asin(ωt+ ϕ)× sin(ωt) dt =
∫ T
0
0.5× (Acos(ϕ) + cos(2ωt+ ϕ)) dt,
=0.5T
π× Acos(ϕ) (4.1)
Imag =
∫ T
0
Asin(ωt+ ϕ)× cos(ωt) dt =
∫ T
0
0.5× (Asin(ϕ) + sin(2ωt+ ϕ)) dt,
=0.5T
π× Asin(ϕ) (4.2)
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 115
where A represents the amplitude, ϕ represents the phase of the sensor impedance and
T is the period of the interrogation signal. Acos(ϕ) is the real portion and Asin(ϕ) is the
imaginary portion of the sensor impedance. These values over a wide frequency range
are sufficient to fully describe the sensor impedance.
D0
D15
SRAM1
CO
NT
RO
L L
OG
IC
MU
LT
I-F
RE
QU
EN
CY
CL
OC
K G
EN
ER
AT
OR
8-BIT
UP/DOWN
COUNTER
8-BIT
R-2R DACOFF-CHIP
DATA
ANALOG
OUTPUT
S 2-bits
00
01
10
11
ON-CHIP OFF-CHIP
Figure 4.3: Waveform generator functional block diagram.
−1−0.8
−0.6
−0.4
−0.2
0
0.2
0.40.6
0.8
1
D0
D1
D15
D14D14
D1
D0D0
-1
D1-1
D15D14 D14
-1
-1
-1
D1-1
D0-1
COUNT UP
S = 00
COUNT DOWN
S = 00
COUNT UP
S = 01
COUNT DOWN
S = 01
45 90 135 180
Angle (Degree)
0
NO
RM
AL
IZE
D A
MP
LIT
UD
E
Figure 4.4: Principle of the sine wave generation.
In this work the FRA algorithm has been chosen to implement a sensory array
impedance spectroscopy microsystem. The two key components in this system are
the multiplier and the digital integrator. Both of these operations are implemented with
an in-channel multiplying dual-slope ADC that reuses the circuits of a conventional
dual-slope ADC [158].
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 116
0.00
0.25
0.50
0.75
1.00
1.25
|REA
L R
ELA
TIV
E ER
RO
R| (
%)
4−110
010
110
210
31010
4−110
010
110
210
31010
FREQUENCY (Hz)
0.00
0.25
0.50
0.75
1.00
1.25
|IMA
G R
ELA
TIV
E ER
RO
R| (
%)
FREQUENCY (Hz)(a)
(b)
NUMBER OF INTEGRATION CYCLES ( )4
100
101
102
103
105
10
NUMBER OF INTEGRATION CYCLES ( )4
100
101
102
103
105
10
N
N
Figure 4.5: Absolute value of the relative error of the biosensor R-C model impedance as afunction of frequency due to stepwise approximation of the interrogation signal for the : (a)real, and (b) imaginary components.
4.4 Circuit Implementation
4.4.1 Multi-channel System-Level Architecture
The functional block diagram of the impedance spectroscopy microsystem based on
the FRA algorithm is shown in Fig. 4.2. The microsystem is comprised of a pro-
gramable analog waveform generator, a programmable digital pattern generator and
an array of impedance extraction units. The waveform generator produces the interro-
gation waveform sin(ωt) and drives the reference electrode with it. The digital pattern
generator generates digital multiplication coefficients representing either sine wave or
cosine wave that are synchronized with the interrogation waveform. Each impedance
extraction unit consists of a dual-slope multiplying ADC (DS-MADC). The front-end
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 117
−
+
S1
S2
S2
IIN
WE
VWE
VWE
IREF+
IREF-
CFS3
VOUT
3
(S1 ,S3,S2 )
CLK
RESET
UP/
DOWN
OR
REAL
IMAG
D = sin(n) OR D = cos(n) (FROM PATTERN GENERATOR)
TIME A
VWES1
UP
/DO
WN
CO
UN
TE
R
IN/O
UT
LA
TC
H
READ_IN
READ_OUT
WRITE
6
CO
NT
RO
L
L
OG
IC
TIME B TIME C
−
+
−
+
−
+
OTA1
VOUT
S
S
UP/DOWN
READ_OUT
WRITE
READ_IN
1
2
3
DT1T
RDDT
2
RESET
A B C
S2OR
t
S
VLATCH
(a)
(b)
Figure 4.6: (a) Dual-slope multiplying ADC VLSI architecture, and (b) timing diagram of allrelevant signals.
current-to-voltage converter is an analog integrator that acquires an input current at
the low-impedance input node set to a controlled potential. The DS-MADC multiplies
the biosensor response IIN with a set of digital coefficients D representing sin(ωt) or
cos(ωt) that are synchronized with the analog sinusoidal interrogation voltage on the
reference electrode. Next the DS-MADC accumulates the results over one period of the
interrogation signal using a digital integrator (counter), thus extracting the real or the
imaginary components of the biosensor impedance.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 118
4.4.2 Waveform Generator and Pattern Generator
The frequency response analysis implementation is the simplest when rectangular wave-
forms are used instead of sine wave for both the interrogation and the multiplication
signals. The problem is that severe systematic errors appear due to the higher order
harmonics existing in the rectangular waveforms. Stepwise approximation of the in-
terrogation waveform and the multiplication signals reduces the effect of higher or-
der harmonics and increases the measurement accuracy. It has been shown [130] that
representing both the interrogation signal and the multiplication signals by a coarsely
quantized approximation can significantly reduces the error due to the higher order har-
monics and can significantly reduce the measurement inaccuracy.
= TI IN
I REF
VOUT
TIME
PHASE I PHASE II
DT
2
T2
T1
1
1
DT
2DT
Figure 4.7: Timing diagram illustrating the ADC multiplication function.
In this work a programmable analog waveform generator is utilized to generate
the stepwise approximation of the interrogation signal. The block diagram of the pro-
grammable waveform generator is shown in Fig. 4.3. It is composed of an 8-bit R-2R
DAC, an on-chip SRAM1 and a bidirectional counter. The DAC coefficients are stored
in the on-chip SRAM1. The on-chip waveform generator generates both stepwise sinu-
soidal and cyclic voltammetry (CV) ramp waveforms. It provides a wide range of user-
controlled rate and amplitude parameters with a maximum CV scan range of 1.2V, and
scan rate ranging between 0.1mV/sec to 400V/sec and the sinusoidal frequency range
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 119
from 100mHz to 50kHz. An off-chip clock generator provides the variable frequency
clock signal enabling the waveform generator to generate the interrogation signal at dif-
ferent frequencies. The DAC occupies an area of 0.012mm2 and dissipates 1.1mW of
power from a 1.2V supply when driving a load of 5nF at 50kHz. At low frequencies the
interrogation sine wave is represented by 64 samples per period. The DAC coefficients
for the first 16 samples (D0 to D15) of the waveform generator output waveform and for
the corresponding digital sin/cos multiplication coefficients are stored in two on-chip
global SRAM banks (SRAM1 and SRAM2, respectively), as shown in Fig. 4.2. The
SRAMs occupy an area of 0.028mm2 and dissipate 0.9µW of power when clocked at
50kHz. By symmetry, 64 samples in one period are generated from the 16 samples
stored on-chip. As shown in Fig. 4.4, for a sine wave, the first 16 samples stored in the
SRAM1 generates the first quadrant of the sine wave. In this case the counter control-
ling the SRAM1 is counting up and S is set to 00, in Fig. 4.3. In the next quadrant the
counter controlling the SRAM1 counts down thus reversing the order of the samples
and generating the second quadrant of the sine wave. S is set to 00 in this case. The
third and forth quadrants are generated in the same manner but in this case the polarities
of the samples fed into the DAC are reversed (by setting S to 01). To generate a cosine,
the cycle starts from the second quadrant instate of the first one. If a CV waveform is
required the up/down counter is directly interfaced to the waveform generator DAC (by
setting S to 11).
As the interrogation frequency increases, the number of samples representing the
interrogation and multiplication signals decreases and at 10kHz both signals are repre-
sented by three samples. This greatly reduces the ADC speed requirement while the
error caused by the reduction in number of samples is kept low by averaging the results
over multiple cycles.
An ideal model of the impedance spectroscopy microsystem has been constructed
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 120
using verilog-A model components (ideal analog integrator and multiplying ADC) to
study the effect of step-wise approximation of the interrogation signal on the overall
system accuracy. First a simulation was performed where a sinusoidal voltage stimulus
(8-bit accurate generated by an ideal DAC) with the frequency swept from 0.1Hz to
10kHz was applied to the biosensor model shown in Fig. 4.2. The value of RS was set
to 1GΩ, CWE was set to 500pF, CDB was set to 300pF and RCT was set to 1MΩ. The
sensor response was recorded with the ideal analog integrator and multiplied, using an
ideal multiplying dual-slope ADC, by an 8-bit accurate digital multiplication coefficient
representing sine or cosine in the FRA algorithm in Fig. 4.1. Next, the same set of sim-
ulations were performed in which both digital multiplication coefficients and the analog
sinusoidal voltage interrogation signal are represented by 64 samples per period at low
frequencies. In this simulation as the interrogation frequency increases, the number of
samples representing the interrogation and multiplication signals decreases. Also, in
this simulation the results are averaged over multiple cycles (N) to reduce the errors
caused by reduction in the number of samples. The absolute value of the relative error
of the biosensor impedance computed using 8-bit accurate interrogation signal and 8-bit
accurate multiplication coefficients versus the simulated biosensor impedance obtained
from stepwise approximation of these signals is shown in Fig. 4.5. The absolute value
of the relative error stays below 0.9% and 1.0% for the real and imaginary component
of the biosensor respectively.
4.4.3 Dual-slope Multiplying ADC Channel
The VLSI architecture of one channel of the integrated spectrum analyzer is depicted in
Fig. 4.6(a). Each channel consists of an integrating amplifier with an on-chip 10pF ca-
pacitor CF , a high-speed latched comparator and digital blocks. The integrator switches
are implemented with low-leakage switches as shown.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 121
The conventional dual-slope ADC operates in two phases as depicted in Fig. 4.7.
In phase I the integrating capacitor CF is charged for a predetermined period of time
T1. Next, during the second phase of the operation, the capacitor is discharged to zero
by a DC reference current. By counting the time T2, a digital representation of IIN
can thus be obtained as (T2/T1)×IREF . To implement multiplication of the input cur-
rent by a digital sin/cos coefficient (D1 to D15) as needed by the FRA algorithm, the
duration of phase I is scaled with a constant coefficient D<1 as shown in Fig. 4.7. In
this case by counting the time DT2, a digital representation of DIIN can be obtained as
D×(T2/T1)×IREF .
To extract the real and imaginary components of the biosensor impedance, the input
current IIN is multiplied by the reference sine or cosine digital coefficient denoted as D
(stored in SRAM2, in Fig. 4.2) and the results are integrated over one period by a 16-bit
counter as follows
Real =
∫ T
0
IIN × sin(ωt)dt =
N/2∑1
IIN × |sin[n]| −N∑
N/2+1
IIN × |sin[n]|(4.3)
Imag =
∫ T
0
IIN × cos(ωt)dt =
N/2∑1
IIN × |cos[n]| −N∑
N/2+1
IIN × |cos[n]|(4.4)
where N is the number of samples in one period and sin[n] and cos[n] are the digital
multiplication coefficients D that are stored in the SRAM2. The multiplying dual slope
ADC performs the multiplication required by equations (5.3) and (4.4), thus the need
for 16 digital multipliers is eliminated.
The timing diagram of the ADC for a typical conversion cycle is shown in Fig. 4.6(b).
First, the integrating counter is reset. At the same time, the sin/cos multiplication coeffi-
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 122
VIN+
VIN-
VBIASN
VCASCP
CASCNVV
OUT
M1 M2
M3 M4
M5 M6
M7 M8
M9 M10M11
chopM
Figure 4.8: Chopper-stabilized folded-cascode OTA1 in the analog integrator.
VIN+ IN-
V
VLATCH
V
OUT+V
OUT-
VLATCH VLATCH
VOUT- VOUT+
VIN+
VIN-
VBIAS
(a) (b)
M1
M2
M3
M4 M
5M
6 M7
M8 M9
M10
M11 M12
M13 M14M15 M16
Figure 4.9: Comparator circuit diagram. (a) One of the three identical gain stages, and (b) thehigh-speed latch.
cient, D, is loaded into the in-channel input latch (time A). Next, the in-channel counter
counts up from zero to time DT1 and the input current is integrated onto capacitor CF .
After time DT1, the voltage on the capacitor is held constant for a fixed time interval
TRD. During this time the content of the output latch (zero for the first conversion cycle)
is loaded into the counter (time B). During time DT2, depending on the comparator out-
put, the integrating capacitor is discharged using the appropriate current source, IREF+
or IREF−. During time DT2 the counter counts up or down depending on the sign of
the input current in phase I and the final value of the counter is written into the output
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 123
Table 4.1: OTA1 and Comparator Transistor Sizing
OTA1 ComparatorTransistor W/L (µm) Transistor W/L (µm)
M1,2 8× 3/1 M1,2 12× 12/0.2M3,4 2× 1/4 M3 3× 2/4M5,6 4× 1/1 M4,5 2× 1.5/0.4M7,8 8× 1/1 M6,7 2× 1.5/0.4M9,10 4× 1/4 M8,9 6× 6/0.5M11 8× 1/2 M10 3× 2/4
– – M11,12 6× 6/0.5– – M13,14 2× 1.5/1
latch (time C). This part of the ADC conversion cycle performs the summation which
implements integration required by the FRA algorithm. This process is repeated for one
full cycle of the sinusoidal stimulation waveform and the final value stored in the output
latch corresponds to the real or imaginary component of the biosensor impedance, for
sin and cos multipliers respectively.
10−2
10−1
100
101
102
103
104
−140
−130
−120
−110
−100
−90
−80
−70
FREQUENCY (Hz)
CHOPPER ON
CHOPPER OFF
INPUT NOISE ( A / Hz ) (dB)
rms
1/2
Figure 4.10: Simulated input-referred noise spectrum of the analog integrator with the chopperon and off (clocked at 100kHz) from 0.01Hz to 10kHz.
The analog integrator amplifier shown in Fig. 4.8 is a folded-cascode transconduc-
tance amplifier consuming 6µW from a 1.2V supply. Impedance spectroscopy is per-
formed over the frequency range of 1Hz to 10kHz. To reduce the effect of flicker noise,
the amplifier utilizes input PMOS devices with a high aspect ratio and internal chop-
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 124
Table 4.2: Analog Integrator Noise Summary
Transistor Noise Total Noise, Total Noise,Source Chopper OFF Chopper ON
M3,4 Flicker 26.4% 11.02%M1,2 Flicker 22.1% 10. 3%M3,4 Thermal 21.2% 23.4%M1,2 Thermal 18.3% 22.1%M9,10 Flicker 5.25% 17.50%M9,10 Thermal 3.26% 8.26%M5,6 Flicker 1.1% 3.38%M7,8 Flicker 1.04% 1.19%M5,6 Thermal 0.9% 1.0%M7,8 Thermal 0.8% 0.9%
M1
M2
M3
M4
M5
M6
M7M8
M9 M10
M11 M
12
M13 M
14
M15
M16
M19
M20
M21
M22
M23
M24
M17
M18
RC
CC
RC
CC
Vin+
Vin-
VbiasN
VbiasP
VbiasP
VbiasP2
VbiasN2
OUTV
M26
M27
(a) (b)
RE
−
+
−
+
V
R1
R2
WAVEFORM
GENERATOR
CE
WE
BIOSENSOR
OTA2
OTA3
WE
Figure 4.11: (a) Circuit architecture of the three-electrode regulation loop, and (b) OTA2 andOTA3 circuit schematic.
ping. As shown in Fig. 4.8, the chopper switches are placed at the input of the OTA.
Another set is placed between the cascoded NMOS current mirrors. This significantly
reduces the flicker noise and DC offsets caused by the input pair transistors and the
NMOS current mirror transistors.
The simulated input-referred noise of the integrator for the cases where the chop-
per is disabled and enabled is shown in Fig. 4.10. The chopping improves the noise
spectrum by 5dB at 10Hz. The relatively low improvement due to the chopping is due
to the noise contribution from the PMOS current sources that are not chopped in this
design. A fully differential design would enable chopping at the input and output of the
op-amp thus minimizing the fliker noise contribution from the PMOS current sources.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 125
The integrated input-referred noise from 0.01Hz to 10kHz is 0.12pA when the chopper
is disabled and 0.07pA when the chopper is enabled. The integrator transistor sizes are
shown in Table 4.1. Contribution of each transistor to the total input-referred noise is
shown Table 4.2. When the chopper is disabled the main contributions are from the
OTA current mirror transistors M3 and M4 and the input pair transistors M1 and M2.
When the chopper is enabled, the current mirror transistors M9 and M10 are the main
contributors to the input-referred noise.
The comparator is implemented with three pre-amplifier stages (Fig. 4.9(a)), with
a total gain of 60dB, and a high-speed output latch as shown in Fig. 4.9(b). The com-
parator is verified in simulation to operate at up to 40MHz. The full channel consumes
42µW of power from a 1.2V supply when clocked at 10MHz. The comparator transistor
sizes are shown in Table 4.1.
4.4.4 Three-electrode Regulation Loop
The functional block diagram of the regulation loop is shown in Fig. 4.11(a). A three-
electrode potentiostat configuration [68] is employed as opposed to the basic two-
electrode configuration. In a two-electrode configuration the current flowing between
the two electrodes alters the voltage drop across CDB due to the non-zero impedance
of the electrolyte solution and the electrode-electrolyte interface. In the three-electrode
configuration, a third, counter electrode (CE), rather than the reference electrode is
placed in the current path. The reference electrode does not sink/source an electric
current. Thus the voltage difference between the working and reference electrode is
maintained at a known voltage independent of the electrochemical cell impedance. The
three-electrode regulation loop is composed of the two OTAs as shown in Fig. 4.11(a).
To allow for wide input and output swings class-AB OTAs with both NMOS and PMOS
input differential pairs are used for the potentiostat as shown in Fig. 4.11(b). OTA tran-
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 126
Table 4.3: OTA2 and OTA3 Transistors Sizing
Transistor W/L (µm) Transistor W/L (µm)M1,2 6× 2/6 M16 1× 1.2/1M3,4 2× 1.5/0.4 M17 1× 1.2/1M5,6 2× 1.5/0.4 M18 1× 1.2/1M7,8 3× 2/0.12 M19,20 1× 1.2/1M9,10 3× 2/0.12 M21,22,23,24 3× 2/0.12M11 1× 1.2/1 M25 3× 2/0.12
M12,13,14,15 3× 2/0.12 M26 1× 1.2/1M9,10 3× 2/0.12
sistor sizing is given in Table 4.3. Assuming that VWE is fixed by the analog integrator,
the regulation loop configuration ensures that VRE-VWE tracks the voltage difference
between the output of the waveform generator and the positive terminal of the OTA3.
4.5 Electrical Experimental Results
1Х6 BANK OF CROSS-VALIDATION CHANNELS
UWB TX
WAVEFORM
GENERATOR & SRAMCONTROL
LOGIC
9×6 ARRAY OF
CHANNELSRECE
WE
2X2μm2
55X55μm
ISFET
5X5μm2X2μm
2
2
2ONE CHANNEL
8Х8 ARRAY OF
2Х2μm WE2
ARRAY OF
WEs
Figure 4.12: Die micrograph of the 54-channel integrated impedance spectrum analyzer fabri-cated in a 0.13µm standard CMOS technology.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 127
0
10100f 1p 10p 100p 1n 10n 100n
140 dB
f =100 f =1000s s
INPUT CURRENT (A)
DIG
ITA
L O
UT
PU
T C
OD
E
1μ
f =500s
1
102
103
104
SNDR=48.2dB
LSB=320fA
SNDR=54.1dB
LSB=12.1pA
SNDR=60.1dB
LSB=0.82nA
Figure 4.13: Experimentally measured transfer characteristics of the impedance spectrum ana-lyzer channel for three sampling frequencies.
0
0 10 20 30 40
−100
−80
−60
−40
−20
0
FREQUENCY(Hz)
NO
RM
AL
IZE
D P
OW
ER
(d
B)
2nd HARMONIC
3rd HARMONIC
SFDR = 60.1dB
SNR = 78.2dB
50
Figure 4.14: Experimentally measured output spectrum of the ADC for a 10Hz sinusoidal input.
The 16-channel 1.2×1.6mm2 integrated impedance spectrum analyzer prototype
was implemented in a 0.13µm CMOS process with a 1.2 V supply. The die micro-
graph is shown in Fig. 4.12. Each channel consists of 4 WEs, with different WE sizes
(55µm×55µm, 5µm×5µm, and two 2µm×2µm) to cover a wide combined dynamic
range. Each column of four working electrodes shares a 45µm-wide Au reference and
counter electrodes driven by the on-chip waveform generator. Each channel consists of
the analog integrator, dual-slope multiplying ADC and in-channel bias and clock gen-
erator. Each channel WE can be set to a specific voltage independently, allowing for
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 128
10−3
10−2
10−1
100
0
10
20
30
40
50
60
MULTIPLICATION FACTOR (D)
SNDR (dB)
Figure 4.15: Experimentally measured MADC SNDR vs. the multiplication factor.
0 32 64 96 128 160 192 224 256
INPUT CODE
DN
L (
LS
B)
-1
-0.5
0
0.5
1
1.5
SIGNAL GENERATOR OUTPUT
Figure 4.16: Waveform generator DNL.
simultaneous detection of different DNA strands.
The digital output of one channel for the input current swept between 100fA and
400nA is shown in Fig. 4.13. The static input dynamic range is 140dB cumulatively for
the three sampling frequency settings, or 55.4dB at 1MHz clock. The dynamic range
for each setting is computed by taking the ratio of the maximum signal that saturates
the ADC to the LSB for a given sampling frequency setting. Dynamic performance
of an entire channel was measured by applying a 10Hz full scale (400nA) sinusoidal
input current with the ADC clocked at 10MHz. Fig. 4.14 shows the 65536-point FFT
of the measured ADC output. The strong second harmonic is due to the single-ended
architecture of the ADC. The resulting effective number of bits (ENOB) is 9.3.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 129
0 32 64 96 128 160 192 224 256
−2
−1. 5
−1
−0.5
0
0.5
1
1.5
2
INL
(L
SB
)
INPUT CODE
SIGNAL GENERATOR OUTPUT
Figure 4.17: Waveform generator INL.
10−1
100
101
102
103
104
105
36
38
40
42
44
46
48
FREQUENCY (Hz)
THD (dB)
Figure 4.18: Total harmonic distortion of waveform generator DAC.
The effect of multiplication of the ADC analog input by a digital coefficient on
the SNDR is studied by measuring the ADC SNDR as the multiplication coefficient is
varied from D = 1 to 0. Fig. 4.15 shows the SNDR of the ADC versus the multiplication
coefficient. The ADC SNDR stays above 30dB down to the multiplication coefficient
of 1/70.
The DNL and INL of the waveform generator are shown in Fig. 4.16 and Fig. 4.17
respectively. The waveform generator achieves an static accuracy of 8 bits. Dynamic
performance of the waveform generator was characterized by measuring the total har-
monic distortion of the DAC versus frequency. Fig. 4.18 shows the THD of the mea-
sured DAC output. The DAC archives a THD of greater than 42dB over the operating
frequency range.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 130
Table 4.4: Experimentally Measured Characteristics
Technology 0.13µm CMOSSupply Voltage 1.2VArea 1.2mm×1.6mmArray Dimensions 4×4 channelsChannel Size 300µm×200µmSensitivity 320fAChannel SNR (fclk=10MHz) 78.2dBChannel SFDR (fclk=10MHz) 60.1dBPower Consumption
DAC 1.1mWSRAM 1.3µWAnalog Integrator 8µWComparator 19µWBiasing 4µWDigital 11µWTotal (channel) 42µW
The electrode model shown in Fig. 1.9 was used first to emulate the biosensor. The
value of RS was set to 1GΩ, CWE was set to 500pF, CDB was set to 300pF and RCT
was set to 1MΩ. To verify the impedance extraction capability of the microsystem, a
sinusoidal voltage stimulus (generated by the on-chip DAC) with the frequency swept
from 0.1Hz to 10kHz was applied to the biosensor model. Figs. 4.19 (a) and (b)
demonstrate that the fabricated prototype tracks the theoretical model well over the
full range of frequencies. The absolute value of the relative error of the ideal biosen-
sor impedance verses the measured biosensor impedance as a function of frequency is
shown in Fig. 4.20. The absolute value of the relative error stays below 8.4% and 7.5%
for real and imaginary component of the biosensor respectively.
Table 4.4 provides a summary of experimentally measured characteristics of the
integrated impedance spectroscopy microsystem.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 131
RE
AL
IMP
ED
AN
CE
(Ω
)
10 5
10 6
10 7
10 8
10 9
IDEAL
MEASUREDIM
AG
IMP
ED
AN
CE
(Ω
)
10 4
10 5
10 6
10 7
10 8
10 9
10 10
IDEAL
MEASURED
500pF1GΩ
1MΩ
WERE300pF
500pF1GΩ
1MΩ
WERE300pF
−110
010
110
210
3
FREQUENCY (Hz)
10 104
(a)
−110
010
110
210
3
FREQUENCY (Hz)
10 104
(b)
Figure 4.19: Off-chip biosensor model impedance as a function of frequency experimentallymeasured by the impedance spectroscopy microsystem: (a) real, and (b) imaginary components.
4.6 Analog vs Digital vs Mixed-Signal Multiplication
Multiplication of the input current by a digital coefficient is implemented by modulat-
ing the counter-controlled duration of the charging phase of the ADC, as described in
Section 4.4.3.
The number of extra logic gates required for implementing in-ADC multiplication
in this design is 23. They are not required to be clocked at the ADC clock speed. The
digital gates required for the multiplications make a state transition only twice during
one entire ADC conversion cycle. For example, if the ADC is generating 10ksps while
being clocked at 10MHz, then the digital logic will be clocked at 20kHz. As a result, the
extra logic cells do not have a significant contribution to the overall power consumption
of the recording channel.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 132
0
2
4
6
8
10
|REA
L R
ELA
TIV
E ER
RO
R| (
%)
4−110
010
110
210
31010
4−110
010
110
210
31010
FREQUENCY (Hz)
0
2
4
6
8
10
|IMA
G R
ELA
TIV
E ER
RO
R| (
%)
FREQUENCY (Hz)(a)
(b)
Figure 4.20: Absolute value of the relative error of the off-chip biosensor model impedance asa function of frequency: (a) real, and (b) imaginary components.
Mixed-signal multiplication approaches presented here can be compared to the ana-
log and digital multiplication approaches in term of area, power and linearity.
Analog multiplication requires a frontend circuit that performs the multiplications
before the signal is passed to the ADC. This will result in added noise, linearity degra-
dation and area requirement which otherwise do not exist in the mixed-signal or digital
approach. Compared to the analog design shown in Fig. 1.16, our approach results in
32µm2 area saving (0.5 percent of total area) and 6.73µW power saving (15.2 percent
of total power) per recording channel. Also, in terms of non-linearity degradation, the
purely analog multiplication approach in Fig. 1.16 adds 4.2 percent linearity degrada-
tion to the channel. This would be in addition to the degradation of the ADC ENOB
(shown in Fig. 4.15) due to the reduction of the signal amplitude vs multiplication
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 133
−1
100
101
102
103
103
104
105
106
10 7
FREQUENCY (Hz)
IMA
G I
MP
ED
AN
CE
(Ω
)
10
103
104
105
106
107
104
−1
100
101
102
103
FREQUENCY (Hz)
10 104
RE
AL
IM
PE
DA
NC
E (
Ω)
(a)
(b)
1.0mM K [Fe(CN) ]3 6
0.1mM K [Fe(CN) ]3 6
1.0mM K [Fe(CN) ]3 6
0.1mM K [Fe(CN) ]3 6
Figure 4.21: Potassium ferricyanide solution impedance as a function of frequency experi-mentally measured by the impedance spectroscopy microsystem: (a) real, and (b) imaginarycomponents.
coefficients.
The main disadvantage of the digital multiplication vs mixed-signal multiplication
approach is the excessive area required by the digital multiplier. For example the digital
multiplier shown in Fig. 1.17 requires 436 logic cells. This results in an area of 0.015
mm2 (adding up the area required by the digital cells listed in Fig. 1.17 scaled to CMOS
0.13µm technology as listed in Table. 4.5 ). The total channel area in this design is 0.06
mm2, thus the area required by the digital multiplier (0.015 mm2) would correspond to
25 percent of the channel area. By comparison the digital overhead (23 gates with a
total area of 0.0009mm2) required by the ADC for multiplication in the mixed signal
approach corresponds to 1.5 percent of the total channel area.
The power consumption of the digital multiplier shown in Fig. 1.17 is 550pJ/MMPS.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 134
Table 4.5: Serial Digital Multiplier Area Breakdown
Gate Type Number of Gates Area/Gate (µm2) Total Gate Area (µm2)AND12 64 1.74107E − 11 1.11429E − 09AOI21 37 3.48214E − 11 1.28839E − 09AOI22 16 5.22321E − 11 8.35714E − 10DFF 32 1.67143E − 10 5.34857E − 09
MUX21 32 1.85714E − 11 5.94286E − 10NAND21 28 2.90179E − 11 8.125E − 10NOR21 54 3.71429E − 11 2.00571E − 09OAI21 27 3.76071E − 11 1.01539E − 09OAI22 15 5.64107E − 11 8.46161E − 10XOR21 32 1.67143E − 11 5.34857E − 10XNOR21 64 1.85714E − 11 1.18857E − 09
TotalMultiplierArea(mm2) 1.55844E-08
Simulations shows that the ADC logic required for digital multiplication consumes
40pJ/MMPS. The total power consumed by the fully digital multiplier or by the extra
logic required by the MADC is not a significant portion of total channel power con-
sumption. The main advantage of the digital multiplier vs the mixed-signal multiplier
is that the multiplication is done after the ADC and the multiplication does not degrade
the ADC ENOB. In our application the degradation of the ADC ENOB does not re-
sult in a significant error in the system level performance. As shown in Figs. 4.20, in
the impedance extraction experiment, the absolute value of the relative error due to the
ADC ENOB degradation stays below 8.4% and 7.5% for real and imaginary component
of the biosensor respectively.
A comparison of the mixed-signal vs analog vs digital multiplication is shown in
Table 4.6. The mixed-signal multiplication approach presented in this work results in
small area and power requirements compared to the fully analog and fully digital multi-
plication approach. The mixed signal approach does not result in linearity degradation
as in the case of the analog multiplication approach. The fully digital approach provides
better system accuracy at the cost of excessive area requirement.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 135
Table 4.6: Comparison of Mixed-Signal vs Analog vs Digital Multiplication
Performance Metric Mixed-Signal Analog DigitalArea Small Small Large
Power Small High SmallLinearity Degradation No Yes NoENOB Degradation Yes Yes No
4.7 Electrochemical Experimental Results
A set of electrochemical experiments have been conducted to validate the function-
ality of the impedance spectroscopy microsystem. In these tests a 3-electrode setup
has been utilized with on-chip gold-plated 55µm×55µm working electrode, on-chip
gold plated counter electrode and an off-chip Ag-AgCl reference electrode. The refer-
ence and counter electrodes are driven by the on-chip three-electrode regulation loop as
shown in Fig. 4.11(a) and all the excitation waveforms are generated using the on-chip
waveform generator.
First, in order to validate the design, impedance spectroscopy recordings of 0.1mM
and 1mM potassium ferricyanide in 1µM potassium phosphate buffer (pH 7.3) were
carried out. A 9mV 0.1Hz to 10kHz sine wave was applied between the WEs and an
off-chip Ag-AgCl reference electrode. The real and imaginary impedance results ob-
tained from the two concentrations of the potassium ferricyanide solution are shown in
Figs. 4.21 (a) and (b). An increase in the concentration of the potassium ferricyanide
results in a decrease in value of RS and RCT and increase in value of CWE . The mea-
surements of potassium ferricyanide validate impedance spectroscopy microsystem in
DNA sensing applications.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 136
Tabl
e4.
7:C
ompa
rativ
eA
naly
sis
ofR
epor
ted
Am
prom
etri
cSe
nsor
yM
icro
syst
em
Syst
emIS
SCC
08JS
SC08
JSSC
09IS
SCC
10IS
SCC
10T
BIO
CA
S07
Thi
sW
ork
[20]
[26]
[84]
[131
][9
7][6
9]Te
chno
logy
(CM
OS)
0.18
µm
0.25
µm
0.5µ
m0.
35µ
m0.
6µm
0.5µ
m0.
13µ
mPo
wer
25m
W16
0mW
0.6m
W84
.5m
W—
1.2m
W0.
35m
WSu
pply
Volta
ge5.
0V2.
5V3.
0V3.
3V3.
3V3.
0V1.
2VC
hip
Are
a11
.2m
m2
15m
m2
2.25
mm
24m
m2
25.8
mm
29m
m2
1.92
mm
2
Ele
ctro
deC
ount
576
4810
010
040
1664
Cha
nnel
Cha
nnel
Cou
nt24
1610
010
040
1616
Type
Of
2D2D
2D2D
—O
ff2D
Ele
ctro
des
Poly
mer
Gol
dG
old
Gol
d—
Chi
pG
old
Sens
ing
Prot
ocol
CV
CV
ISIS
CV
CA
ISPo
wer
—10
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CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 137
The SoC was also extensively validated in DNA analysis for detection of prostate
cancer synthetic DNA. Fig. 4.22(a) shows real and imaginary impedance components
of an on-chip Au electrode hybridized with 5µM single-stranded prostate cancer syn-
thetic probe DNA. Adding a 5µM noncomplementary target DNA does not significantly
change the real and imaginary components of the electrode impedance indicating that
non-specific adsorption is negligible. Adding a 5µM complementary prostate cancer
synthetic target DNA leads to significant reduction of potassium ferrocyanide redox
current, resulting in increase in both real and imaginary components of the electrode
impedance. This is due to the additional negative surface charge resulting from forma-
tion of double-stranded DNA on the electrode surface. The 3-sigma error bars (from 3
chips) with the real and imaginary impedance detection noise margins of approximately
18.3KΩ and 20.9MΩ respectively are shown in Fig. 4.22(b).
Table 4.7 provides a comparative analysis of the presented design and existing
amperometric biochemical sensory microsystems. The design presented in this work
achieves the highest dynamic range and the lowest sensitivity in terms of LSB. Also,
the design presented in this Chapter requires less time to extract real and imaginary
components of the biosensor compared to the FRA implementations in which a square
waveform is utilized for multiplication and integration. The stepwise approximation of
the interrogation waveform and multiplication coefficients significantly reduces the sys-
tematic error caused by higher order harmonics present in the rectangular waveforms,
thus eliminating the need for excessive averaging that is time consuming at the lower
frequency range. This enables real-time monitoring and analysis of DNA hybridization.
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 138
104
105
106
107
108
109
1010
10−1
100
101
102
103
104
FREQUENCY (Hz)
RE
AL
IM
PE
DA
NC
E (
Ω)
PROBE
NONCOMPLEMENTARY TARGET COMPLEMENTARY TARGET
106
107
RE
AL
IM
PE
DA
NC
E (
Ω)
COMPLEMENTARY
TARGET DNA
NONCOMPLEMENTARY
TARGET DNA
PROBE
DNA
COMPLEMENTARY
TARGET DNA
NONCOMPLEMENTARY
TARGET DNA
PROBE
DNA
DETECTION
NOISE MARGIN
DETECTION
NOISE MARGIN
104
105
106
107
108
109
1010
107
108
IMA
G I
MP
ED
AN
CE
(Ω
)
AT 10 HzAT 10 Hz
(a)
(b)
IMA
G I
MP
ED
AN
CE
(Ω
)
Figure 4.22: (a) Impedance spectrum of 5µM prostate cancer synthetic DNA probe, comple-mentary, non-complementary targets and (b) the corresponding 3-sigma error bars (from 3 chips,20 measurements each).
4.8 Chapter Summary
A 54-channel, mixed-signal CMOS impedance spectroscopy DNA analyzer is pre-
sented. It consists of a programable waveform generator, on-chip memory and multiple
impedance extraction units. Multiplication and integration, two operations required
for frequency response analysis (FRA) algorithm, are efficiently performed by the in-
channel current-mode input dual-slope multiplying ADC with negligible resources over-
head. The ADC combines impedance extraction and analog-to-digital conversion into a
single conversion cycle. The impedance spectroscopy microsystem was implemented in
CHAPTER 4. IMPEDANCE SPECTROSCOPY DNA 139
a CMOS 0.13µm technology. Each channel occupies an area of 0.06mm2 and consumes
42µW of power from a 1.2V supply.
140
Chapter 5
Temperature Regulation
A 9×6-arrayed-cell mixed signal CMOS thermal controller for on-die DNA sensing is
presented. The SoC reuses the circuits for impedance spectroscopy and cyclic voltam-
metry to also perform temperature regulation. The on-chip, in-cell heating and temperature-
sensing elements are implemented in standard CMOS without any post-processing.
Using feedback proportional-integral-derivative (PID) control the temperature can be
regulated to within 0.5C of the desired value. The two computationally intensive oper-
ations, the multiplication and subtraction required by the PID algorithm, are performed
by the in-cell dual-slope multiplying ADC in the mixed-signal domain, resulting in
small area and low power consumption. Specifically, multiplication of the input current
by a digital coefficient is implemented by modulating the counter-controlled duration of
the charging phase of the ADC. Subtraction is implemented by the ADC counter. The
3mm×3mm prototype fabricated in a 0.13µm CMOS technology has been fully ex-
perimentally characterized. Each channel occupies an area of 0.06mm2 and consumes
42µW from a 1.2V supply.
CHAPTER 5. TEMPERATURE REGULATION 141
5.1 Introduction
In this Chapter we present a 0.13µm CMOS distributed temperature regulator with an
on-chip mixed-signal PID controller. The hybrid analog-digital nature of the PID con-
troller yields a compact implementation with a low power dissipation overhead. This
enables distributed localized temperature control in large-scale temperature-dependent
parallel sensing applications such as on-CMOS amperometric electrochemical DNA
analysis essays.
The presented temperature controller is a part of a highly-integrated multi-functional
SoC that performs amperometric electrochemical DNA analysis. The DNA analysis
SoC consists of 54 recoding channels and 600 gold microelectrodes. It performs label-
free DNA analysis and pH sensing for prostate cancer detection. We previously reported
on the DNA sensing functionality of this SoC [137]. Accurate DNA analysis requires
distributed temperature control. We reported a brief preliminary summary of how the
DNA sensing circuits and the temperature control circuits are integrated and shared on
the same die [87]. Here we present a detailed report on the VLSI architecture and circuit
implementation of the distributed temperature regulator that extends on [87] and offer
an in-depth treatment of the algorithm design and the circuit implementation, as well as
extensive experimental results illustrating temperature regulation characteristics.
The distributed temperature controller consists of a spatial array of 54 heating ele-
ments and 54 temperature-sensing elements, one such pair for each DNA sensing chan-
nel. The heaters and temperature sensors are interfaced to a distributed mixed-signal
PID controller that regulates the temperature of the chip. The PID controller re-uses
key circuits from the DNA-sensing channel, thus significantly saving silicon area. The
re-used DNA sensing circuits are reconfigured to perform both temperature sensing and
computation needed by the PID temperature control algorithm. This architecture allows
for independent thermal regulation of each channel. Channels can be further thermally
CHAPTER 5. TEMPERATURE REGULATION 142
isolated from each other using a CMOS post-processing technique as described in [170].
In that method a combination of thin-film metal deposition, photolithography and wet
etching is utilized to etch out the dielectric and the bulk silicon around the area of the
interest and thus thermally isolating it from the rest of the chip.
+u(k) = u(k-1) + c e(k)
+ c e(k-1) + c e(k-2)
DESIRED TEMP, t(k)
+
e(k)y(k)
u(k)(c ,c ,c )
0 1 2 PWM
ACTUATOR
PID CONTROLLER
0
1 2
RE
TEMPERATURE
SENSOR
RE
HEATER
TEMPERATURE CONTROLLER
Figure 5.1: Block diagram of PID implementation of the temperature regulation loop.
The rest of the Chapter is organized as follows. Section II provides background on
temperature regulation principles. Section III describes the temperature-sensing princi-
ple. Section IV presents the VLSI architecture of the temperature controller. Section V
details the circuit implementation of the VLSI architecture. Section VI demonstrates
the experimental results obtained from the 0.13µm CMOS prototype.
5.2 Thermal Control Principles
5.2.1 Temperature regulation
The block diagram of the temperature regulation loop is shown in Fig. 5.1. It consists
of a heater, a temperature sensor, a temperature controller, and an actuator as the feed-
back element. In this work, a proportional-integral-derivative (PID) algorithm has been
chosen for the temperature controller, since this class of algorithms is effective in the
regulation of thermal systems [162, 163]. As shown in Fig. 5.1, a discrete-time PID
controller calculates the error value, e(k), as the difference between a measured input
signal, y(k), and a desired input signal, t(k). The controller attempts to minimize the
CHAPTER 5. TEMPERATURE REGULATION 143
error by adjusting the input to the feedback element (actuator), u(k), using the process
control inputs (c0, c1, c2). The PID controller algorithm involves three separate con-
stant parameters, namely, the proportional, the integral, and the derivative components,
which are denoted as P, I, and D, respectively. The proportional component depends on
the present error value, the integral component depends on the past error value, and the
derivative component is a prediction of the future error value. The weighted sum of the
three components can be used to adjust the heat, and thus regulate the temperature of
the microsystem [164].
IREF
IN
VBE1
R1
ᾳ∆VBE
R2
DIG
ITA
L
TE
MP
ER
AT
UR
E
VBE1
VBE2
∆VBE
ᾳ∆VBE
R2
VBE1
R1
V
T T
I
T
I
VBE1
R1
ᾳ∆VBE
R2
(b) (c) (d)
(e)
CHANNEL
I
CTAT
PTAT
(a)
E
C
B
VBE2+
-E
C
B
VBE1
+
-IE1
IE2
IC1
IC2
Q 1
Q 2
IB1
IB2
∆VBE
+ -
Figure 5.2: (a) A pair of BJTs for generating ∆VBE and VBE , (b) Temperature dependenceof the base-emitter voltage, (c) generation of PTAT and CTAT current, (d) generation of tem-perature dependent current and (e) utilization of a current-to-digital channel for temperaturemeasurements.
In this work the temperature of the sensing site is measured using an on-chip temper-
ature sensor. The output of the temperature sensor, y(k), is subtracted from the desired
temperature, t(k), and the resulting error value, e(k), is fed to the PID controller. The
output of the PID controller, u(k), sets the duty cycle of a digital pulse that is gener-
ated by the on-chip digital PWM controlling the on-chip heater. The PID controller is
implemented as a recursive filter [136]. The continuous-time representation of the PID
CHAPTER 5. TEMPERATURE REGULATION 144
controller is given by
u(t) = Kpe(t) +Ki
∫ t
0
e(t)dt+Kdd
dte(t) (5.1)
where Kp is the proportional gain, Ki is the integral gain, Kd is the derivative gain, e(t)
is the error value, and u(t) is the actuation value. A discrete-time representation of (5.1)
in Z-domain is given by
D(z) =u(z)
e(z)= Kp +Ki
Ts
2
z + 1
z − 1+
Kd
Ts
z − 1
z(5.2)
where Ts is the sampling period. Equation (5.2) can be implemented numerically as
follows
u(k) = u(k − 1) + c0e(k) + c1e(k − 1) + c2e(k − 2) (5.3)
where c0, c1, and c2 are the PID coefficients, and k is the discrete time index.
5.2.2 Temperature sensing
Temperature can be measured using two signals linearly dependent on temperature.
Such a temperature sensor measures the temperature by taking the ratio of these two
signals. In a CMOS technology, these signals can be derived from the base-emitter
voltage of substrate pnp transistors [165].
These transistors consist of the p-substrate as the collector, the p+-diffusion as the
emitter, and a n-well as the base. Two signals linearly dependent on temperature can be
generated from the base-emitter voltage (VBE) of a single pnp transistor and from the
difference between the base-emitter voltages (∆VBE) of two pnp transistors biased at
different collector current levels as shown in Fig. 5.2(a). The temperature dependence
CHAPTER 5. TEMPERATURE REGULATION 145
of the VBE can be derived from the exponential relation between the collector current
IC and the base emitter voltage as follows
VBE(T ) = Vg0(1−T
Tr
) +T
Tr
VBETr
− nKT
qln
T
Tr
+KT
qln
ICT
ICTr
(5.4)
where Vg0 is the extrapolated bandgap voltage at 0 Kelvin, n is a process-dependent
constant, K is Boltzmann constant, q is the electron charge, and Tr is an arbitrary refer-
ence temperature [159]. As illustrated in Fig. 5.2(b), VBE is complementary to absolute
temperature (CTAT), with a typical slope of − 2 mV/K. The nonlinearity, or curvature,
is represented by the last two terms of (5.4). These nonlinearities are negligible in the
temperature range of 20oC to 90oC that is required by the DNA analysis SoC.
The slope of the base-emitter voltage depends on the absolute value of the collec-
tor current. This dependence can be used to generate a voltage that is proportional to
absolute temperature (PTAT), as shown in Fig. 5.2(b). The difference between the base-
emitter voltages of two pnp transistors biased at two different collector currents can be
expressed as follows
∆VBE(T ) = VBE2(T )− VBE1(T ) =KT
qln(
IC2
IC1
) (5.5)
where IC1 and IC2 are the collector currents of the two pnp transistors. As can be seen
in (5.5), if the collector current ratio is constant, then the difference between the base-
emitter voltages of the two pnp transistors is proportional to the absolute temperature
(PTAT).
A typical temperature sensor measures the temperature by determining the ratio of
the PTAT voltage to a temperature-independent reference voltage. The temperature-
independent reference voltage can be generated by adding VBE to a scaled version of
CHAPTER 5. TEMPERATURE REGULATION 146
∆VBE [159–161]. The scaling factor α is used to match the temperature dependance
(with an opposite sign) of VBE and ∆VBE . In this work a current-mode temperature sen-
sor is utilized. The PTAT and CTAT voltages are converted to the current domain, using
resistors R1 and R2 as shown in Fig. 5.2(c). Also, instead of generating a temperature-
independent reference signal, the ratio of α∆VBE/R2 to VBE/R1 is determined, which
has a linear temperature dependence, as shown in Fig. 5.2(d). This eliminates the need
for a temperature-independent reference current generator.
In this work a current-to-digital recording channel is utilized for temperature sens-
ing. The channel operates by digitizing the ratio of the input current to the reference
current. As shown in Fig. 5.2(e), the CTAT current is used as the input to the channel,
and the PTAT current is used as the reference of the channel. The current-to-digital
channel digitizes the ratio of these two currents. The factor α, the resistance R1 and R2
are set such that both the input current and the reference current utilize the full input
dynamic range of the channel over the operating temperature range.
CHAPTER 5. TEMPERATURE REGULATION 147
I PTA
T
I CTA
T×5
4V
BE+
-
×5
4
CC
I RE
F
I IN S
CA
LE
D D
ES
IRE
D T
EM
PE
RA
TU
RE
PW
M
H
EA
TE
R
u(k
)
×5
4
CT
AT
c e
(k)
n
(c t
(k),
c t
(k),
c t
(k))
01
2
B0
Z-1
C y
(k)
n
CT
AT
CU
RR
EN
T
S
OU
RC
E
PT
AT
CU
RR
EN
T
S
OU
RC
E
SE
NS
OR
×5
4
B1
B2
B3
B4
B5
B6
MA
DC
CH
AN
NE
L
Q3 Q
1Q
2
×5
4
PT
AT
SE
NS
OR
M
UL
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LIC
AT
ION
CO
EF
FIC
IEN
TS
( c
, c
, c
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01
2
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IT S
RA
M
Figu
re5.
3:To
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arch
itect
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ofte
mpe
ratu
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tion
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(sha
ded
boxe
sar
ein
-cha
nnel
).
CHAPTER 5. TEMPERATURE REGULATION 148
B0
B1
B2
B3
B4
B5
B6
c e(0)0
c e(1)0
c e(2)0
c e(0) 1
c e(2) 1
c e(0)2
c e(1) 1
c e(1)2
c e(2)2
u(0) u(1) u(2)
PID CYCLE
ADC CYCLE
TIME
Figure 5.4: Timing diagram of the temperature regulation loop.
5.2.3 Temperature Regulation
The block diagram of the wireless electrochemical DNA analysis SoC configured for
temperature regulation is shown in Fig. 5.1. In this mode, the SoC utilizes the 54
current-to-digital recording channels to measure temperature. The on-chip PID con-
troller is used to regulate each cell temperature. On-chip SRAMs are utilized to store
PID coefficients and multiplication coefficients. The channel measures temperature by
taking the ratio of a CTAT to PTAT currents as described in Section II. The CTAT
current is used as the input and the PTAT current is used as the reference to the current-
to-digital recording channel. The CTAT and PTAT currents are generated using the
in-cell BJTs. The measured temperature is fed to the on-chip PID controller. The PID
controller regulates the 2D chip temperature profile by modulating the in-cell heaters.
Two computationally intensive operations, the multiplication and subtraction required
by the PID algorithm, are performed by the in-channel MADC in the mixed-signal do-
main, yielding small area and power consumption, as described next.
CHAPTER 5. TEMPERATURE REGULATION 149
S1
S1
CM
VCM
ICTAT
IPTAT
C
S2
CCV
VC
(c t(k), c t(k), c t(k))0 1 2
S2
CURRENT
CONVEYER
DUAL-SLOPE MULTIPLYING
ADC
INT
CALIBRATION
SRAM
2(S
1,S ,S
2)
CLK
RESET
UP/DN
UP/DOWN
COUNTERLOAD
CO
NT
RO
L
L
OG
IC
(c ,c ,c ) 0 1 2
c e(k) n
CLK
OUT_EN
PID_ENPID LATCH
0
1
S 2
D_IN
D_OUT
D_IN
RESET
S 3
S3
3
Figure 5.5: Top-level VLSI architecture of one temperature sensing channel.
5.3 VLSI Architecture
The top-level VLSI architecture of the temperature regulation loop is shown in Fig. 5.3.
The regulation loop consists of CTAT and PTAT BJTs, PTAT and CTAT current sources,
current-to-digital channel, a 7-bit SRAM bank with an adder, a 12-bit digital PWM, and
an in-cell heater. The in-channel heaters are implemented by a PMOS transistors with
width and length of 100µm and 0.13µm and a 15Ω load, as shown in Fig. 5.6. The
in-cell BJTs are interfaced sequentially to the current sources that generate IPTAT and
ICTAT . ICTAT is used as the input to the channel, and IPTAT is used as the reference
current. The channel determines the ratio of ICTAT to IPTAT . Both currents are scaled
such that their magnitude fits within the channel dynamic range over the operating tem-
perature range. The ratio of ICTAT to IPTAT results in a linear transfer characteristic
(versus temperature) [165]. The channel dual-slope multiplying ADC performs three
tasks. First, it computes the ratio of ICTAT to IPTAT . Next, it multiplies this ratio by the
PID coefficients, (c0, c1, c2), and finally it subtracts the results from the scaled version
of the desired temperature, (c0t(k), c1t(k), c2t(k)). The result of these three operations
is the computation of cne(k), as shown in Fig. 5.3. Next, these values are stored in the
on-chip 7-bit SRAM bank. An on-chip adder adds the appropriate values (according to
equation (3)) and computes u(k), which sets the duty cycle of the signal generated by
CHAPTER 5. TEMPERATURE REGULATION 150
VIN 100μm/0.13μm
15Ω
Figure 5.6: In-channel heater schematic.
the digital PWM. The duty cycle of this signal sets the amount of time that the in-cell
heater is on, thus regulating the chip temperature.
The timing diagram of the PID regulation loop is shown in Fig. 5.4. The channel
dual-slope multiplying ADC performs three conversion cycles during one cycle of the
PID controller, thus eliminating the need for three parallel ADCs. As shown in Fig. 5.4,
in the first conversion cycle of the PID controller, the ADC computes c0e(0), c1e(0), and
c2e(0). Next, u(0) is calculated from these values, and the duty cycle of the digital PWM
is set accordingly. Consecutive values of c0e(n), c1e(n), c2e(n), and u(n) are generated
in the same manner.
5.4 Circuit Implementation
5.4.1 Current-to-Digital Channel
The top-level VLSI architecture of the current-to-digital channel is shown in Fig. 5.5.
Each channel consists of a chopper-stabilized current conveyer [166], a dual-slope mul-
tiplying ADC [167], control logic, and on-chip memories and a counter. The dual-slope
multiplying ADC performs both multiplication and subtraction, as required by the PID
algorithm.
The timing diagram of the ADC for a typical conversion cycle is shown in Fig. 5.7.
The conventional dual-slope ADC digitizes the input signal in two phases: charging
CHAPTER 5. TEMPERATURE REGULATION 151
VC
1
c T1
TRD
c T2
RESET
Time
S
n n
2
S 3
S
Figure 5.7: Timing diagram of the dual-slope multiplying ADC.
phase T1 and discharging phase T2, of the integrating capacitor. The ratio of the duration
of the charging phase to the discharging phase represents the input signal level. As
shown in Fig. 5.7, to implement multiplication of the input current by a digital PID
coefficient cn, as required by the PID algorithm, the duration of the charging phase is
scaled with a constant coefficient cn<1 [167]. In this case, by counting the time cnT2,
a digital representation of cnICTAT can be obtained.
As shown in Fig. 5.7, first the ADC counter is reset. At the same time, the PID
multiplication coefficient, cn, is loaded into the in-channel PID latch (S3=1). There is
a large channel-to-channel variation between the BJT current output. In this work to
compensate for this variation, the channel counter is pre-loaded with a digital calibra-
tion value (stored in the in-channel calibration SRAM) at the rising edge of the RESET
signal. Next, the in-channel counter counts up from this value to time cnT1, and the in-
put current ICTAT is integrated onto the capacitor CINT . After time cnT1, the voltage on
the capacitor is held constant for a fixed time interval, TRD. During this time, the digital
representation of the desired temperature that is scaled by the PID coefficients, cnt(k),
is loaded into the counter. During time cnT2, the integrating capacitor is discharged
with the PTAT current source. During time cnT2, the counter counts down, and the final
value of the counter is available at the falling edge of S2 signal. By counting down from
cnt(k) in the second phase of the conversion cycle, the ADC performs subtraction of
CHAPTER 5. TEMPERATURE REGULATION 152
Table 5.1: OTA Transistor Sizing
Transistor W/L (µm)
M1,2 9× 4/1M3,4 4× 1.5/4M5,6 5× 1.5/1M7,8 10× 1.5/1M9,10 4× 1.5/4M11 11× 1.5/2
cny(k) from cnt(k) (as shown in Fig. 5.3) thus computing the error signal cne(k).
The front end bidirectional current conveyer is implemented by a PMOS and an
NMOS transistors connected in the feedback of an OTA [88]. The negative feedback
ensures a known potential at the working electrode is set by the voltage at the non-
inverting input of the OTA. It also enables the current conveyer to source and sink an
input current without the need for a DC offset current. The OTA is implemented as
a folded-cascode amplifier with PMOS input pair. Chopper-stabilization is utilized to
reduce the OTA flicker noise and offset and dynamic element matching is utilized to
reduce the output current mirrors mismatch [88].
The ADC comparator is implemented with three stages of pre-amplifiers, with a
total gain of 60dB and the last stage with a high-speed latch. The first stage of the
comparator is implemented as a cross-coupled diode-connected gain stage to provide a
moderate gain and a high frequency bandwidth. Chopper-stabilization suppresses the
input offset and ensures 9-bit accuracy. The second and third stages are identical to the
first one but with no chopping. The high-speed latch is implemented with an NMOS
input pair gain stage and a NMOS-PMOS cross-coupled load to provides high accuracy,
low offset and a high frequency bandwidth [144].
CHAPTER 5. TEMPERATURE REGULATION 153
−
+
R1
IPTAT
6
VBEtrim
COEFFICIENTS
TRIMMING V P
10:1 DEM
R
VBEtrim
1
VBE
+
-
Q1
×54
CTAT
SENSOR
M 0 M 9 M 10
OTA1
PRBS GEN
Figure 5.8: Circuit diagram of the CTAT sensor and CTAT current source
V IN+
VIN-
V BIASN
V CASCP
CASCNVVOUT
M1 M2
M3 M4
M5 M6
M7 M8
M9 M10M11
CHOPM
Figure 5.9: Chopper-stabilized folded-cascode OTA in the CTAT (OTA1) and PTAT (OTA2)current sources.
5.4.2 CTAT Current Source
A simplified circuit diagram of the CTAT current source is shown in Fig. 5.8. To gen-
erate a digitally programmable base-emitter voltage VBEtrim (compensating for chip-
to-chip variations), a PTAT current (generated by a separate on-chip biasing circuit)
is passed through a 6-bit programmable resistor connected in series with the diode-
connected pnp transistor Q1. The current VBEtrim/R1 is generated by a voltage-to-
current converter, as shown in Fig. 5.8. A large resistor (R1>100MΩ) is required to
ensure that the CTAT current is kept relatively low (20nA) and stays within the dy-
namic range of the ADC. This would result in a large integration area. To reduce the
CHAPTER 5. TEMPERATURE REGULATION 154
10−2
10−1
100
101
102
103
−130
−120
−110
−100
−90
−80
−70
FREQUENCY (Hz)
CHOPPER ON
CHOPPER OFF
INPUT NOISE ( A / Hz ) (dB)
rms
1/2
Figure 5.10: Simulated input-referred noise spectrum of the OTA with chopper enabled anddisabled from 0.01Hz to 1kHz.
size of the resistor, a current mirror with a 10:1 ratio is utilized. A 10:1 dynamic ele-
ment matching is used to reduce the effect of the current mirror mismatch. In this work
R1 is set to 1.5MΩ.
To reduce the effect of flicker noise, OTA1 amplifier in Fig. 5.8 utilizes input PMOS
devices with a high aspect ratio and internal OTA chopping. As shown in Fig. 5.9, the
chopper switches are placed at the input of the OTA. Another set is placed below the
cascoded NMOS transistors in the current mirror. This placement reduces the flicker
noise and DC offsets caused by the input pair transistors and the NMOS current mirror
transistors.
The simulated input-referred noise of OTA1 in the cases where the chopper is dis-
abled and enabled is shown in Fig. 5.10. The integrated input-referred noise from
0.01Hz to 1kHz is 0.11pA when the chopper is disabled and 0.06pA when the chopper
is enabled. The OTA1 transistor sizes are given in Table 5.1. The contribution of each
transistor to the total input-referred noise is shown in Fig. 5.11. When the chopper is
disabled, the main contributions to the input-referred flicker noise are from the OTA
current mirror transistors M3 and M4, and from the input pair transistors M1 and M2.
CHAPTER 5. TEMPERATURE REGULATION 155
M (T)3,4
M (T)1,2
M (T)5,6
M (T)7,8
M (T)9,10
CHOPPER ON
CHOPPER OFF
0
0.005
0.010
0.015
0.020
0.025
0.030
INT
EG
RA
TE
D I
NP
UT
NO
ISE
( p
A )
(a)
M (F)3,4
M (F)1,2
M (F)5,6
M (F)7,8
M (F)9,10
0
0.005
0.010
0.015
0.020
0.025
0.030
INT
EG
RA
TE
D I
NP
UT
NO
ISE
( p
A )
0.035
CHOPPER ON
CHOPPER OFF
(b)
Figure 5.11: Simulated OTA noise summary: (a) thermal noise contribution, and (b) flickernoise contribution.
When the chopper is enabled, the current mirror transistors M9 and M10 are the main
contributors to the input-referred flicker noise.
5.4.3 PTAT Current Source
A simplified circuit diagram of the PTAT current source is shown in Fig. 5.12. The
∆VBE is generated by determining the difference between the VBE of the two substrate
pnp transistors that are biased at 3:1 collector current ratio. The voltage-to-current con-
verter consisting of OTA2 and the NMOS feedback transistor generates ∆VBE across
R2 (split into R2/3 and 2R2/3). In this work R2 is set to 100kΩ. This results in the
desired output current ∆VBE/R2. The resistor R2/3 is added in series with the base of
the Q3 transistor in order to ensure that the base current of the Q3 does not affect the
output current.
The main causes of inaccuracy in the PTAT current source are the input offset of
OTA2, OTA2 flicker noise, and the mismatch in the bias current mirror. Internal OTA
CHAPTER 5. TEMPERATURE REGULATION 156
−
+
IBAIS
3 I I ∆VBE
R2
Q2 Q3
×54
PTAT
SENSOR
R13
R232 2
OTA2
DEM
DEM
∆VBE+ -
Figure 5.12: Circuit diagram of the PTAT sensor and PTAT current source.
chopping is utilized to reduce the effect of flicker noise and input offset voltage. OTA2
has the same amplifier topology and transistor size as those used in the CTAT current
source. Dynamic element matching at 100Hz, by the means of the chopper switches in
series between the current sources and the resistors, is utilized to improve the matching.
5.4.4 Digital Pulse Width Modulator
In the temperature regulation loop, the digital pulse width modulator (PWM) sets the
duty cycle of the pulse that is controlling the in-channel heater. The achievable discrete
set of the duty cycle settings of the pulse depends on the digital PWM resolution. In
this work, a 12-bit digital PWM architecture is selected. The design is based on a hy-
brid delay-line/counter architecture in [168]. The block diagram of the PWM is shown
in Fig. 5.13. In this architecture, a 7-bit counter and 32-stage ring oscillator are used to
achieve the 12-bit resolution. At the beginning of a switching cycle, the output set-reset
(SR) flip-flop is set, and the PWM output pulse goes high. The pulse that propagates
through the ring at the oscillation frequency serves as the clock for the counter. At the
time when the counter output matches the top most significant bits of the digital input
CHAPTER 5. TEMPERATURE REGULATION 157
(nc), and a pulse reaches the tap selected by the least significant bits (nd), the output
flip-flop is reset, and the output pulse goes low [168].
OUT
32 :1
.
32-STAGE RING OSCILLATOR7-BIT
COUNTER
R
SQ7-BIT
COMP
7-BIT
COMPInput [11:0]
n [4:0]d
n [6:0]c
n [6:0]f
. .
n [6:0]f
Figure 5.13: Block diagram of the digital pulse width modulator.
5.5 Experimental Results
9×6 ARRAY OF
CELLS
CONTROL
LOGIC
PULSE WIDTH
MODULATOR
PID
CONTROLLER
PTAT & CTAT
CURRENT SOURCES
CALIBRATION
SRAM
BIAS
CURRENT
CONVEYERCOMPARATOR
HEATER
CONTROL
LOGIC
PID SRAM
COUNTER BJTs
ADDER
PID LATCH
Figure 5.14: Die micrograph of the 54-cell wireless temperature regulated DNA analysis SoC.
CHAPTER 5. TEMPERATURE REGULATION 158
0 5 10 15 20 25 30 35 40 45 50−140
−120
−100
−80
−60
−40
−20
0
2nd Harmonic3rd Harmonic
SFDR = 58.7 dB
NORMALIZED POWER(dB) SNR = 56.9 dB
FREQUENCY(Hz)
I = 350nAin
ADC
OUTPUT
SPECTRUM
Figure 5.15: Experimentally measured output spectrum of the ADC for a 15Hz sinusoidal input.
The die micrograph of the mixed-signal CMOS thermally-controlled DNA-sensing
SoC is shown Fig. 5.14. The 54 cells are arranged in a 9×6 array on a 3mm×3mm
0.13µm CMOS die. Each cell consists of a current conveyer, a dual-slope multiplying
ADC, an in-cell bias and clock generator, a pH sensor, a heater, and temperature-sensing
BJTs. The PID controller, CTAT and PTAT current sources, and the digital PWM are
located in the top section of the die.
0 500 1000 1500 2000 2500 3000 3500 40000
20
40
60
80
100
PWM INPUT CODE
OU
TP
UT
DU
TY
RA
TIO
(%)
Figure 5.16: Experimentally measured transfer function of the pulse-width-modulator.
The dynamic performance of the entire cell was measured by applying a 15Hz full-
scale (400nA) sinusoidal input current, with the ADC clocked at 10MHz. Fig. 5.15
CHAPTER 5. TEMPERATURE REGULATION 159
20 30 40 50 60 70 80200
400
600
800
TEMPERATURE ( C)
OU
TP
UT
DIG
ITA
L C
OD
E
o
90
Figure 5.17: Experimentally measured digital output of the dual-slope ADC vs temperature(in-air).
shows the 65536-point FFT of the measured ADC output. The strong second harmonic
occurs due to the single-ended architecture of the ADC. The resulting effective number
of bits (ENOB) is 9.3.
The digital PWM is characterized by sweeping the digital input code from 0 to
4095 and clocking the digital PWM at 2.5MHz. The experimental results of Fig. 5.16
show the measured duty ratio of the output pulses as a function of the 12-bits digital
input. The minimum (4%) and the maximum (96%) duty ratios are set by design. The
digital PWM achieves a linear transfer function over the programable digital input code
with a 0.82 percent maximum error. The digital PWM achieves a minimum duty cycle
resolution of 0.1µS.
The TP04390A ThermoStream [169], as shown in Fig. 5.18, is utilized to charac-
terize the temperature response of the CMOS temperature sensor. In these experiments,
an external temperature sensor is placed on top of the CMOS chip. The TP04390A
ThermoStream uses the temperature reading from the external temperature sensor to set
the chip temperature to a desired value. In these experiments the CMOS chip is ther-
mally isolated using a rubber thermal insulation pad (DF-32 from Liwung) to ensure a
consistent temperature gradient.
The output digital code of the ADC versus temperature, from 20 to 90 degrees
CHAPTER 5. TEMPERATURE REGULATION 160
Figure 5.18: TP04390A ThermoStream [169] unit used for temperature sensor characterization.
Celsius, is shown in Fig. 5.17. The temperature sensor archives a linear transfer function
over the operating temperature range. Fig. 5.19 shows the measured temperature error of
seven dies from one wafer, which operated at a supply voltage of 1.2V. Their inaccuracy,
after calibration in the temperature range of 20 degrees Celsius to 90 degrees Celsius,
is less than 0.5 degrees Celsius.
CHAPTER 5. TEMPERATURE REGULATION 161
0.0
0.30
ER
RO
R (
C
)o
30 40 50 60 70 80
TEMPERATURE ( C)
90o
0.15
0.45
-0.15
-0.30
-0.45
Figure 5.19: Temperature sensor error experimentally measured on seven dies from one wafer(in-air).
Table 5.2: Experimentally Measured Characteristics
Technology 0.13µm CMOSSupply Voltage 1.2VArea 3mm×3mmArray Dimensions 9×6 channelsChannel Size 300µm×200µmSensitivity 8.6pAPower Consumption(System)
SRAM 1.3µWPID Controller 21µWTemperature Core 12µWHeater 270mW @ 90 degree
Power Consumption(Channel)Current Conveyer 8µWComparator 19µWBiasing 4µWDigital 11µWTotal (channel) 42µW
CHAPTER 5. TEMPERATURE REGULATION 162
NU
MB
ER
OF
OC
CU
RA
NC
ES
49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.30
2
4
6
8
10
12
MEAN = 49.83 C
SD(3σ) = 0.20 C
N= 54
o
o
TEMPERATURE ( C)o
Figure 5.20: Experimentally measured temperature from 54 channels in one chip (in-air).
CHAPTER 5. TEMPERATURE REGULATION 163
Tabl
e5.
3:C
ompa
rativ
eA
naly
sis
ofR
epor
ted
The
rmal
lyR
egul
ated
Bio
sens
ory
Mic
rosy
stem
s
Syst
emIS
SCC
08B
IOC
AS
09T
BIO
CA
S07
ISSC
C10
ISSC
C09
Thi
sW
ork
[20]
[135
][1
32]
[25]
[97]
Tech
nolo
gy(C
MO
S)0.
18µ
m0.
5µm
0.5µ
m0.
13µ
m0.
6µm
0.13
µm
Pow
er25
mW
30m
W—
165m
W—
0.35
mW
Supp
lyVo
ltage
5.0V
5V5.
0V1.
2V3.
3V1.
2VC
hip
Are
a11
.2m
m2
3mm
26m
m2
7.5m
m2
25.8
mm
29m
m2
Ele
ctro
deC
ount
576
91
1640
600
Cha
nnel
Cha
nnel
Cou
nt24
91
1640
54Ty
peof
Ele
ctro
des
2D2D
2D2D
—3D
Gol
dPo
lym
erM
icro
hotp
late
Mic
roho
tpla
teM
agne
ticIS
FET
—D
ynam
icR
ange
—O
ff-C
hip
Off
-Chi
p55
dB80
dB12
8dB
(3-m
ode)
Con
vers
ion
Rat
e10
Hz
——
—1H
z10
kHz
Sens
itivi
ty97
pA—
—0.
3Hz
25µ
V8.
6pA
EN
OB
11bi
ts—
—D
irec
tCon
vers
ion
12bi
ts9.
1bi
tsSi
gnal
Gen
erat
orN
oN
oN
oY
esN
oY
esTy
pe—
——
Sine
Wav
e—
8-bi
tPro
gram
mab
leFr
eque
ncy
——
—1G
Hz
—10
kHz
Pow
er—
——
——
1.1m
W(5
nFL
oad)
Tran
smitt
erN
oN
oN
oN
oN
oY
esPr
otoc
ol—
——
——
0-1
GH
zU
WB
Dat
aR
ate
——
——
—10
Mbs
Pow
er—
——
——
100µ
WE
lect
roch
emic
alSe
nsin
gC
yclic
Volta
mm
etry
Yes
Yes
Yes
No
No
Yes
Impe
danc
eSp
ectr
osco
pyN
oN
oN
oY
esN
oY
espH
No
No
No
No
ISFE
TIS
FET
Tem
pera
ture
Sens
ing
Yes
Yes
Yes
Yes
Yes
Yes
Sens
orC
ount
19
11
4054
Con
trol
No
PID
PID
PID
PID
PID
—(A
nalo
g)(A
nalo
g)(A
nalo
g)(D
igita
l)(M
ixed
-Sig
nal)
—O
ff-C
hip
Off
-Chi
pO
ff-C
hip
On-
Chi
pO
n-C
hip
Acc
urac
y—
0.7o
C2
oC
1o
C0.
5o
C0.
5o
C
CHAPTER 5. TEMPERATURE REGULATION 164
An external heater was utilized to fix the chip temperature at 50 degrees Celsius and
the temperature at each recording channel was recorded to study the effect of channel-
to-channel mismatch. Experimentally measured temperature from 54 channels in one
chip is shown in Fig. 5.20. The mean digital output temperature and the corresponding
standard deviation are 49.83 and 0.20 degree Celsius, respectively.
An example of the temperature regulation cycle in liquid (5mL 1M potassium phos-
phate buffer solution), with steps at 35, 45, 55, and 65 degrees Celsius, is shown
in Fig. 5.21. In these experiments the PWM was clocked at 5kHz and the ADC was
clocked at 10MHz to provide 3 samples (as needed by the timing diagram shown
in Fig. 5.7) in each PID cycle. The solid line is the chip temperature regulated by the
on-chip temperature regulator and the dashed line is the desired temperature. It takes
roughly 10 seconds to achieve a 5 degree increase in the chip temperature. Measured
absolute value of the relative error of the PID regulation loop over the operating tem-
perature range is shown in Fig. 5.22. The absolute value of the error stays below 0.75
degree Celsius over the operating temperature range. In these experiments the CMOS
chip was thermally isolated using a silicone rubber thermal insulation pad.
0 10 20 30 9025
35
45
55
65
75
TIME (S)
TE
MP
ER
AT
UR
E (
C)
o
40 50 60 70 80
DESIRED
TEMPERATURE
REGULATED
TEMPERATURE
Figure 5.21: Temperature regulation cycle with steps at 35, 45, 55 and 65 degree Celsius (in-liquid).
Table 5.2 provides a summary of the experimentally measured characteristics of the
integrated impedance spectroscopy microsystem.
CHAPTER 5. TEMPERATURE REGULATION 165
20 30 40 50 60 70 800.10
0.30
0.60
0.90
TEMPERATURE ( C)o
90
0.15
0.45
0.75
|REL
ATI
VE
ERR
OR
| ( C
)
o
Figure 5.22: Measured absolute value of the relative error of PID regulation loop (in-air).
Table 5.3 provides a comparative analysis of the presented design and existing ther-
mally regulated biochemical sensory microsystems. The design presented in this work
utilizes a mixed signal temperature regulation loop that reuses components from the
DNA-sensing recording channel [137] to perform temperature regulation, thus saving
power and per-channel area as compared to the designs presented in Table 5.3.
5.6 Chapter Summary
A 54-channel, mixed-signal CMOS thermal-controlled, DNA-sensing SoC was devel-
oped. The DNA-sensing SoC shares circuitries to perform impedance spectroscopy,
cyclic voltammetry, and temperature regulation. The on-chip, in-channel heating and
temperature-sensing elements were implemented in standard CMOS without any post-
processing. Using feedback proportional-integral-derivative (PID) control, the temper-
ature can be regulated to within 0.5C of the desired point, a process that enables precise
control of on-chip DNA hybridization during characterization or sensing. Two compu-
tationally intensive operations, the multiplication and subtraction required by the PID
algorithm, are performed by an in-channel, dual-slope multiplying ADC in the mixed-
signal domain, and the result is minimal area and power consumption. The PID regu-
lation loop reuses circuitries from the DNA-sensing channel, and the result is minimal
CHAPTER 5. TEMPERATURE REGULATION 166
area. Each channel occupies an area of only 0.06mm2 and consumes 42µW of power
from a 1.2V supply.
167
Chapter 6
Conclusions and Future Work
6.1 Contributions and Related Publications
This thesis describes a wireless thermally regulated label-free DNA analysis SoC with
nanostructured on-die electrodes. The summary of all contributions by chapter is pre-
sented next.
• Chapter 2
Chapter 2 describes the design, analysis and experimental results of two low-noise
bidirectional current acquisition circuits for interfacing with electrochemical ampero-
metric biosensor arrays. The first design is a switched-capacitor transimpedance am-
plifier (TIA) and the second design is a current conveyer (CC) with regulated-cascode
current mirrors. Both designs were fabricated in 0.13µm CMOS technology. The elec-
trical and electrochemical recording properties of both circuits have been characterized.
It is shown that the current conveyer exhibits superior performance in low-concentration
electrochemical catalytic reporter sensing. This work was presented at the 2011 IEEE
International Symposium on Circuits and Systems [87]. The results from this chapter
are published in IEEE Transactions on Circuits and Systems I [88].
CHAPTER 6. CONCLUSIONS AND FUTURE WORK 168
The main contribution of this chapter is the comparison of the switched-capacitor
transimpedance amplifier to the current conveyer approach for use as a current sens-
ing frontend and providing experimental proofs that the current conveyer (CC) is more
suitable for DNA sensing applications. It is shown through on-chip electrochemical
recording that the CC results in lower charge injection into the working electrode. The
charge injection can disturb the charge balance at the electrode-electrolyte interface
thus affecting the electrochemical reaction. It is shown through extensive electrochem-
ical recordings that the CC is more suitable for DNA sensing from small (2µm×2µm)
working electrodes.
• Chapter 3
Chapter 3 describes the fully integrated 54-channel wireless label-free DNA anal-
ysis SoC configured for cyclic voltammetry and pH sensing. The SoC includes 600
nanostructured DNA sensors and 54 pH sensors, and reuses key circuits for cyclic
voltammetry and pH sensing. The 3mm×3mm prototype fabricated in a 0.13µm stan-
dard CMOS technology has been validated in prostate cancer DNA detection. Each
channel occupies an area of only 0.06mm2 and consumes 42µW of power from a 1.2V
supply. This work was presented in 2012 Symposia on VLSI Technology and Circuits.
The main contribution of this paper is the fabrication of the nanostructured micro-
electrodes (NME) for the first time on a CMOS die. Also, we have characterized the
NME electrodes for the first time for on-CMOS DNA sensing. The detection limit of
10aM is the lowest reported in literature by a CMOS DNA detection system. Another
contribution of this chapter is the design and experimental demonstration of an elec-
trochemical recording channel that achieves the highest sensitivity and dynamic range
compared to designs previously reported in literature and also integration of a fully
digital UWB transmitter. The frontend current conveyer employs chopper stabilization
and dynamic element matching to achieve input-referred noise of less 0.13pA over the
CHAPTER 6. CONCLUSIONS AND FUTURE WORK 169
operating bandwidth and to improve the current conveyer accuracy by 60 percent at the
100nA input current level. The in-channel SRAM allows for in-channel gain calibra-
tion (by adjusting the timing of the ADC) which results in a 17 percent improvement in
channel-to-channel ENOB variation. The UWB transmitter design is adopted from [77]
and the design presented here is optimized for our application by significantly simplify-
ing the previously reported implementations, thus achieving small area and low power
consumption.
• Chapter 4
Chapter 4 presents the fully integrated 54-channel wireless, label-free DNA analysis
SoC configured for impedance spectroscopy. The SoC utilizes frequency response anal-
ysis (FRA) to extract the real and imaginary impedance components of the biosensor.
Two computationally expensive operations, the multiplication and integration required
by the FRA algorithm, are performed by an in-channel dual-slope multiplying ADC
in the mixed-signal domain resulting in high accuracy, small area and low power con-
sumption. Multiplication of the input current by a digital coefficient is implemented
by modulating the counter-controlled duration of the charging phase of the ADC. In-
tegration is implemented by accumulating output digital bits in the ADC counter over
multiple input samples. The 1.2mm×1.6mm prototype fabricated in a 0.13µm standard
CMOS technology has been validated in prostate cancer DNA detection. Each channel
occupies an area of only 0.06mm2 and consumes 42µW of power from a 1.2V supply.
This work was presented in 2012 IEEE Biomedical Circuits and Systems Conference
(BioCAS) [158] and published in IEEE Transactions on Biomedical Circuits and Sys-
tems [144].
The main contribution of this chapter is the design and implementation of a low-
power mixed-signal VLSI approach to implement frequency response algorithm (FRA)
on-chip for DNA impedance extraction. Multiplication, which is the most area-consuming
CHAPTER 6. CONCLUSIONS AND FUTURE WORK 170
and power-intensive operation required by the FRA algorithm is implemented by modi-
fying the timing of the in-channel dual-slope ADC resulting in a low-power, small-area
implementation of the FRA algorithm.
• Chapter 5
Chapter 5 presents the fully integrated 54-channel wireless, label-free DNA anal-
ysis SoC configured for temperature regulation. The on-chip, in-channel heating and
temperature sensing elements were implemented in standard CMOS without any post-
processing using feedback proportional-integral-derivative (PID) control. The tempera-
ture can be regulated to within 0.5C of the desired point, which enables precise control
of on-chip DNA hybridization during characterization or sensing. Two computationally
expensive operations, the multiplication and subtraction required by the PID algorithm,
are performed by the in-channel, dual-slope multiplying ADC in the mixed-signal do-
main, similar to which is described in Chapter 4, and the result is minimal area and
power consumption. The 3mm×3mm prototype fabricated in a 0.13µm standard CMOS
technology has been validated in a portion of the PCR protocol. The PID regulation loop
reuses circuits from the DNA-sensing channel resulting in minimal area. Each channel
occupies an area of only 0.06mm2 and consumes 42µW from a 1.2V supply. This work
was presented at 2012 Symposia on VLSI Technology and Circuits [87].
The main contribution of this chapter is the efficient mixed-signal VLSI implemen-
tation of the PID algorithm for temperature regulation. The multiplication required by
the PID algorithm which is the most area-consuming and power-hungary operation is
efficiently implemented by the in-channel dual-slope ADC. This results is small area
and power consumption and enables a large channel count.
CHAPTER 6. CONCLUSIONS AND FUTURE WORK 171
6.2 Future Work
6.2.1 Power Harvesting and Wireless Communication Chip
An additional 6mm2 chip has been designed and fabricated in 0.13µm CMOS tech-
nology that consists of a wireless inductive power receiver, a command data receiver
and two high-speed transmitters. The chip was co-designed with Karim Abdelhalim, in
order to provide wireless power transfer and wireless data command transfer capabili-
ties to the DNA analysis SoC. The fabricated prototype die micrograph is depicted in
Fig. 6.1.
The power harvesting unit of the chip consists of a low-drop-out rectifier capable
of operating at up to 10MHz, two low-dropout regulators providing 2.5V and 1.2V
supply voltages with a maximum load current of 10mA and an on-chip programable
DAC generating up to 8 bias voltages. A 4MHz amplitude shift keying (ASK)/ on-off
keying (OOK) wireless data receiver was implemented to enable wireless transmission
of configuration and command data to the DNA analysis SoC. Finally, a 915MHz PLL-
based FSK transmitter and a UWB transmitter were also included in the CMOS chip.
This chip will be integrated with the presented SoC in the near future.
6.2.2 Improvements to the SoC
The presented SoC prototype contains a large number of input/output (I/O) and debug
pins and also requires some off-chip current and voltage bias sources. In the next gen-
eration of the SoC the bias voltages and current sources should be implemented on the
chip using on-chip band-gap voltage and current sources. Also, the I/O and debug pins
number needs to be reduced. One approach to reduce the debug pins number is to mux
all the analog test points into a single node and the same should be done for the digital
I/O pins resulting in only one or few analog and one digital I/O pins.
CHAPTER 6. CONCLUSIONS AND FUTURE WORK 172
915MHz OOK TX
3.1-10.6GHz
UWB TX
10MHz
COMMAND
RX
4MHz
POWER
RX
Figure 6.1: Die micrograph of the 2mm×3mm power harvesting and wireless communicationchip. The chip was fabricated in a 0.13µm standard CMOS technology.
Analog improvements to the SoC design include implementation of a differential
front end current acquisition circuitry to reduce the second harmonic interference and
common-mode noise. Another improvement is reduction of flicker noise in the front-
end current acquisition circuits.
Testing improvements include design of a better and more durable packaging for
the CMOS chips. Currently a fill-and-dam technique is used to protect the chip bond-
wires from the electrolyte solution under test. This technique is only protecting the
chip for a limited time and after roughly one hour of testing a chip may become non-
functional. There is a high chance that the pins are shorted due to leakage. Another
improvement to the testing is integration and miniaturization of the Ag/AgCl electrode
on the CMOS chip. Currently a somewhat bulky off-chip Ag/AgCl is used for all the
testing. A number of miniaturized Ag/AgCl electrode fabrication methods have been
reported in literature [78, 170]. These reports can be used as a starting point for full
integration of the reference electrode on the CMOS chip.
173
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187
Appendix A
Supplementary Hardware and
Software Documentation
A.1 Board Design
In order to demonstrate the DNA analysis SoC in applications a 6-layer PCB was de-
signed and fabricated as shown in Fig. A.1. The PCB provides the required digital
control sequence and DC bias voltages and currents to the SoC. The test board is com-
prised of the following components:
• FPGA FPGA: Alterra CYCLONE III FPGA 10K (256-FBGA544-2417-ND).
• FPGA EPROM: Memory to store FPGA pragrams (93LC46C-I/MS-ND)
• USB Controller: Communication link between the test board and PC (USB 768-
1024-1-ND)
• 12-bit DAC: Generating bias voltages for the DNA SoC (AD5328BRUZ-ND)
• Voltage regulator: Generating supply voltage for DNA SoC and the test board
(497-8717-1-ND)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 188
• Crystal: Generating reference clock (XC1426CT-ND)
1
2
3
4
5
6
7
8
9
10
11121314
15
16
17
18
1920
21
22
23
2425 26
27
28
29
30
31
Figure A.1: PCB fabricated for characterizing the DNA analysis SoC.
The parts that are labeled on the board are as follows:
1. Channel digital supply voltage (1.2V)
2. Channel analog supply voltage (1.2V)
3. Channel common mode supply voltage (0.65V)
4. On-chip waveform generator supply voltage (1.5V)
5. On-chip SRAM supply voltage (1.2V)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 189
6. On-chip PID supply voltage (1.2V)
7. On-chip heater supply voltage (1.5V)
8. UWB transmitter supply voltage (1.2V)
9. 5V supply voltage connector
10. On-chip DC bias voltage and current generator (from right to left: 1- channel
opamp voltage bias (300mV), 2-channel opamp voltage bias (700mV), 3- com-
parator voltage bias (500mV), 4-waveform generator voltage bias (320mV), 5-
waveform generator voltage bias (650mV), 6-channel reference current generator
(adjustable from 10pA to 100nA), 6-temperature sensor voltage bias (320mV)).
11. FPGA supply voltage (1.2V)
12. FPGA supply voltage (2.5V)
13. FPGA supply voltage (3.3V)
14. FPGA debug pins
15. USB chip supply voltage (3.3V)
16. USB chip supply voltage (1.8V)
17. USB connector
18. JTAG connector
19. Off-chip waveform generator 3.3V supply voltage
20. Off-chip counter electrode
21. Off-chip reference electrode
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 190
22. Off-chip waveform generator
23. FPGA debug pins
24. Off-chip waveform generator output
25. 3-electrode regulation loop opamps
26. UWB transmitter output
27. CMOS DNA analysis chip
28. On-chip waveform generator output
29. FPGA chip
30. USB controller chip
A.2 DNA Sensing protocol
The following protocol is utilized for preparation of 5µM DNA samples.
1. scan the electrode in 20mM ferro from 0 to 500mV at 100mV/s
2. Prepare the probes purchased from IDT DNA
• Product: 100 nmole DNA oligo
• Purification: Standard Desalting
• Sequence: /5ThioMC6-D/AG CGC GGC AGG AAG CCT TAT
Reduction of thiol modified oligos:
We recommend the use of immobilized TCEP from Pierce for the reduction of thiol
modified oligos. The immobilized TCEP has a number of advantages over alternative
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 191
reducing agents such as the ability to reduce a thiol over a large pH and temperature
range and in a variety of buffers. The protocol below is one we have used and may need
to be optimized for specific conditions/requirements.
1. Resuspend the oligo in PBS pH 7.0, or other appropriate buffer, at about 1nmole/µL.
2. Mix the TCEP slurry and take a volume equal to about 2x the volume of oligo
you want to reduce. Centrifuge and remove the supernatant. If desired you may
wash the TCEP slurry with your reaction buffer.
3. Add your oligo to the TCEP slurry.
4. Incubate at room temperature with constant mixing for 2 hours.
5. Transfer the reaction to a PALL Nanosep 100 microspin column.
6. Centrifuge for 5 min at 10000 rpm. The filtrate contains the reduced thiol oligo.
To ensure full reactivity, thiol-modified oligos should be used immediately after
reduction.
3. From the prepared probe, make a solution of 5µM probe, 25mM NaCl, 25mM
phosphate buffer and 20mM MgCl2.
4. Leave the solution in 3 on the chip for 60 minutes in the room temperature in a
humidity chamber in dark.
5. Remove solution left in 4 and wash with 25mM phosphate buffer and 25mM
NaCl.
6. Repeat the same scan as in 1.
7. Make the DNA target solution as per protocol.
• Product: 25 nmole DNA Oligo
• Purification: Standard Desalting
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 192
• Sequence: ATA AGG CTT CCT GCC GCG CT
There is a protocol although much less complicated than the Thiol reduction. Here
is what we recommend:
1- Spin tube down briefly before opening. This ensures the pellet is at the bottom of
the tube and will not be lost when opening.
2- Under a hood, or in a clean environment, carefully remove cap.
3- Resuspend to desired concentration using TE buffer or DNase free H2O.
Generally, people prefer to resuspend to 100µM stock concentrations. To do this,
you would need to multiply the number of nmoles by 10 and add that many ul of water
or buffer. As an example: If you receive 18.2nm of product, you would resuspend in
182 µl of water or buffer to obtain a 100µM conc. Alternatively, you could resuspend to
any concentration you wish. It is sometimes helpful to use our resuspension calculator
which can be found here:
http://www.idtdna.com/analyzer/Applications/resuspensioncalc/
8. Make a solution of 5µM target, 100mM MgCl2, 25mM NCl, 25mM phosphate
buffer.
9. Leave a drop of solution made in 8 on chip for 60 minutes at 37 degrees in a dark
humidity chamber
10. Remove the drop and wash with 25mM phosphate buffer and 25mM NaCl.
11. Scan the electrode as 1.
12. Repeat the experiment for the other negative target
• Product: 25 nmole DNA Oligo
• Purification: Standard Desalting
• Sequence: TTT TTT TTT TTT TTT TTT TT
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 193
A.3 Data Acquisition
Data acquisition from the board is done using the FTDI USB controller chip. The chip
is connected to the host PC using a USB cable and matlab is used to control and acquire
the data from the board.
Before running the matlab code the user should setup two virtual COM port using
FT-PROG software available from http://www.ftdichip.com/Drivers/VCP.htm.
The matlab code for recording CV plots and calculating the SNR is given below:1 clear all;
2 format long;
3 s1 = serial(’COM57’);
4 s2 = serial(’COM58’);
5 set(s1,’BaudRate’,915200,’DataBits’,8,’Parity’,’none’,’StopBits’,1);
6 set(s2,’BaudRate’,915200,’DataBits’,8,’Parity’,’none’,’StopBits’,1);
78 N=30000;
9 S1BUFF = N;
10 S2BUFF = 2;
1112 s1.InputBufferSize = S1BUFF;
13 s1.OutputBufferSize = S1BUFF;
1415 s2.InputBufferSize = S2BUFF;
16 s2.OutputBufferSize = S2BUFF;
1718 s1.Timeout = 600;
19 s2.Timeout = 600;
2021 fopen(s1);
22 s1.ByteOrder = ’bigEndian’;
2324 x=[4 3];
25 y=[4 4];
2627 fopen(s2);
28 s2.ByteOrder = ’bigEndian’;
29 %
30 fwrite(s2, x , ’int8’);
3132 % fwrite(s2, ’11111110’);
33 data = fread(s1);
34 values(:,1) = data;
3536 fwrite(s2, y , ’int8’);
3738 %just to check properties
39 get(s1)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 194
40 get(s2)
4142 fclose(s1)
43 delete(s1)
44 clear s1
4546 fclose(s2)
47 delete(s2)
48 clear s2
4950 x=0;
51 y=0;
52 z=1;
53 hamed =1;
54 BB1 = 0;
55 BB2 = 0;
56 BB3 = 0;
5758 for i = 1 : S1BUFF
59 str = dec2bin(values(i),8);
60 B11 = bitget(values(i), 8:-1:1);
61 BB = B11(8)*1 +B11(7)*2;
62 for xx = 1:8
63 B(xx)=bitcmp(B11(xx),1);
64 end
65 if (BB == 0 & x==0)
66 x=1;
67 y=1;
68 end
69 if(BB == 0 & y==1 & z==1)
70 BB1 =BB1+1;
71 ii =1;
72 for ii = 1 : 6
73 p1(ii,BB1) = B(ii);
74 end
75 z=2;
76 elseif(BB == 1 & y==1 & z==2)
77 BB2 =BB2+1;
78 for ii = 1 : 6
79 p2(ii,BB2) = B(ii);
80 end
81 z=3;
82 elseif(BB == 2 & y==1 & z==3)
83 BB3 =BB3+1;
84 ii =1;
85 for ii = 1 : 6
86 p3(ii,BB3) = B(ii);
87 end
88 z=1;
89 end
9091 end
9293 for i = 1 : N/3-20
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 195
94 OUTF1(i) = p1(1,i)*2ˆ5 + p1(2,i)*2ˆ4 + p1(3,i)*2ˆ3 + p1(4,i)*2ˆ2 + p1(5,i)*2ˆ1 + p1(6,i)*2ˆ0;
95 OUTF2(i) = p2(1,i)*2ˆ11 + p2(2,i)*2ˆ10 + p2(3,i)*2ˆ9 + p2(4,i)*2ˆ8 + p2(5,i)*2ˆ7 + p2(6,i)*2ˆ6;
96 OUTF3(i) = p3(3,i)*2ˆ15 + p3(4,i)*2ˆ14 + p3(5,i)*2ˆ13 + p3(6,i)*2ˆ12;
97 if (p3(2,i) == 1)
98 OUTF(i) = OUTF1(i)+OUTF2(i)+OUTF3(i);
99 else
100 OUTF(i) = (OUTF1(i)+OUTF2(i)+OUTF3(i))*-1;
101 end
102 end
103 H=1;
104 hh=0;
105 for i = 1 : N/3-21
106 if( OUTF(i)== 65535)
107 hh = 1;
108 elseif (OUTF(i)˜=65535)
109 if(hh == 1)
110 OUTFF(H) = 65535;
111 hh = 0;
112 H=H+1;
113 else
114 OUTFF(H) = OUTF(i);
115 H=H+1;
116 end
117 end
118 end
119120 % figure(1)
121 % X1 = 10:1:H-1;
122 % y = smooth(OUTFF(10:1:H-1));
123 % plot(X1,y)
124 % xlabel(’Sample’)
125 % ylabel(’Current (A)’)
126127 % figure(1)
128129 X1 = 4:1:N/12-21
130 y1 = OUTFF(4:1:N/12-21);
131 y2 = smooth(OUTFF(4:1:N/12-21),0.03,’rloess’);
132 % for i = 1:1:(10898)
133 % if y1(i,1)>= 0
134 % y1(i,1)=y1(i,1);
135 % elseif y1(i,1)<0
136 % y1(i,1)=y1(i,1)*1.5;
137 % end
138 % end
139140 figure(1);
141 subplot(2,1,1), plot(X1,y2)
142 subplot(2,1,2), plot(X1,y1)
143 xlabel(’Sample’)
144 ylabel(’Current (A)’)
145 % plot(X1,y2)
146 N=size(y1);
147 MM = N(1);
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 196
148 MM2=MM-10;
149 M = mean(y1)
150151 k=1;
152 for i=1:length(y1)
153 if y1(i)==65535
154 time_stamp(k)=i;
155 k=k+1;
156 end;
157 end;
158159 for i=1:length(time_stamp)-1
160 m=(time_stamp(i+1) + time_stamp(i))/2;
161 d1=y2(time_stamp(i):m)’;
162 d2=flipdim( y2(m:time_stamp(i+1)),1)’ ;
163 NN=min([length(d1),length(d2)]);
164 hamed_data(i,1,:) = d1(1:NN);
165 hamed_data(i,2,:) = d2(1:NN);
166 end;
167168169 figure(2);
170 for i=1:length(time_stamp)-1
171 plot(-1*[1:NN],-1*squeeze(hamed_data(i,1,:)),-1*[1:NN],-1*squeeze(hamed_data(i,2,:)));
172 hold on;
173 end
174175 fid = fopen(’C:\Users\hamed\Desktop\CV_july_0002_h1.txt’,’w’);
176 fprintf(fid, ’%d’, hamed_data(i,1,:));
177 fclose(fid);
178 fid = fopen(’C:\Users\hamed\Desktop\CV_july3_0002_h2.txt’,’w’);
179 fprintf(fid, ’%d’, hamed_data(i,2,:));
180 fclose(fid);
181 fid = fopen(’C:\Users\hamed\Desktop\CV_july3_0002_y1.txt’,’w’);
182 fprintf(fid, ’%d’, y1);
183 fclose(fid);
184 fid = fopen(’C:\Users\hamed\Desktop\CV_july3_0002_y2.txt’,’w’);
185 fprintf(fid, ’%d’, y2);
186 fclose(fid);
187188 % fs=100;
189 % T = 1/fs;
190 % t = MM2 * T;
191 % w= window(@blackmanharris,MM);
192 % data2=y1;
193 % y1 = y1.*w;
194 % out_fft = fft(y1);
195 % psd = abs(out_fft).ˆ2;
196 %
197 % % scale and plot
198 % psd(1:5,1)=psd(10,1);
199 % psd(end-5:end,1)=psd(end-10,1);
200 % [max_value fbin] = max (psd);
201 % P = fbin
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 197
202 % fin = P/(842) * fs
203 % psd = psd./max_value;
204 % figure(2)
205 % f = fs/2000*linspace(0,1,MM2/2);
206 % % plot (f,10*log10(psd(1:MM2/2)));
207 % % plot (10*log10(psd(1:N/2)));
208 %
209 % nbins =13; % number of signal bins
210 % signal_bins = P +1+ [-(nbins-1)/2:(nbins-1)/2]
211 % inband_bins = 1:842/2;
212 %
213 % noise_bins = setdiff(inband_bins,signal_bins);
214 % noise_bins = setdiff(noise_bins,[1 2 3 4 5 6 7 8 9 10 11 12]);
215 %
216 % snrOut = 10*log10(sum(psd(signal_bins)))- 10*log10(sum(sum(psd(noise_bins))))
217 % X=psd(noise_bins);
A.4 FPGA Verilog Code
The CMOS DNA detection microsystem and the PCB board are controlled by the on-
board FPGA.
The top level FPGA verilog code which is shared between all mode of operations
(CV, IS and temperature regulation) is given below:
A.4.1 Top Level Module
1 // Copyright (C) 1991-2011 Altera Corporation
2 // Your use of Altera Corporation’s design tools, logic functions
3 // and other software and tools, and its AMPP partner logic
4 // functions, and any output files from any of the foregoing
5 // (including device programming or simulation files), and any
6 // associated documentation or information are expressly subject
7 // to the terms and conditions of the Altera Program License
8 // Subscription Agreement, Altera MegaCore Function License
9 // Agreement, or other applicable license agreement, including,
10 // without limitation, that your use is for the sole purpose of
11 // programming logic devices manufactured by Altera and sold by
12 // Altera or its authorized distributors. Please refer to the
13 // applicable agreement for further details.
1415 // PROGRAM "Quartus II 64-Bit"
16 // VERSION "Version 11.0 Build 157 04/27/2011 SJ Full Version"
17 // CREATED "Fri Jun 21 22:26:40 2013"
18
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 198
19 module CHEM_PRO_TOP(
20 OSC_CLK,
21 TXE_USB,
22 RXF_USB_IN,
23 DATA_IN,
24 DIN_USB,
25 CS,
26 WR,
27 PD,
28 GAIN,
29 CLR,
30 ldac1,
31 sync1,
32 ldac2,
33 sync2,
34 din_out2,
35 din_out1,
36 SING,
37 C1,
38 VLATCH,
39 P1,
40 EXT_RESET,
41 BS_A,
42 BS_P,
43 Q,
44 LDAC,
45 DAC_CLK1,
46 DAC_CLK2,
47 CLK_SH1,
48 I_STAT_PAD,
49 CLK_SH2_TEMP,
50 IN_E_PAD_TEMP,
51 CLK_SHIFT_PAD,
52 I_SHIFT_PAD,
53 RESET_CH,
54 CLK_CH,
55 CLK_CV,
56 UP_DOWN_CV,
57 IMP_CV,
58 RESET_SRAM_LOGIC,
59 W,
60 CLK_COEF,
61 OFF_ON_CHIP,
62 COS,
63 OFF_CHIP_DAC_P,
64 ELECTRODE_OFFON,
65 READ_PWM,
66 CLK_SHFIT_RING,
67 CLK_RING,
68 READ_ON_OFF_PWM,
69 RESET_RING,
70 WRITE_PAD,
71 EXT_RING,
72 ON_OFF_RING,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 199
73 B_PID,
74 A_PID,
75 ADC_PID,
76 ADC_MEM_READ,
77 MAINE_READ,
78 RESET_,
79 WP0,
80 WP1,
81 WP2,
82 WP3,
83 RESET_P,
84 CLK_P,
85 PAR_P,
86 RESET_PS,
87 CLK_PS,
88 LOAD_SHIFT,
89 RESET_SHIFT,
90 IN_COEF_PAD,
91 CLK_SH3_PAD,
92 IN_SHIFT_RING_PAD,
93 CLK_TEMP,
94 CHAMBER_RESET,
95 CHAMBER_CLK,
96 WR_USB,
97 RD_USB,
98 SIWUA,
99 SIWUB,
100 B,
101 DATA_OUT,
102 DATA_OUT_USB
103 );
104105106 input wire OSC_CLK;
107 input wire TXE_USB;
108 input wire RXF_USB_IN;
109 input wire [16:0] DATA_IN;
110 input wire [7:0] DIN_USB;
111 output wire CS;
112 output wire WR;
113 output wire PD;
114 output wire GAIN;
115 output wire CLR;
116 output wire ldac1;
117 output wire sync1;
118 output wire ldac2;
119 output wire sync2;
120 output wire din_out2;
121 output wire din_out1;
122 output wire SING;
123 output wire C1;
124 output wire VLATCH;
125 output wire P1;
126 output wire EXT_RESET;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 200
127 output wire BS_A;
128 output wire BS_P;
129 output wire Q;
130 output wire LDAC;
131 output wire DAC_CLK1;
132 output wire DAC_CLK2;
133 output wire CLK_SH1;
134 output wire I_STAT_PAD;
135 output wire CLK_SH2_TEMP;
136 output wire IN_E_PAD_TEMP;
137 output wire CLK_SHIFT_PAD;
138 output wire I_SHIFT_PAD;
139 output wire RESET_CH;
140 output wire CLK_CH;
141 output wire CLK_CV;
142 output wire UP_DOWN_CV;
143 output wire IMP_CV;
144 output wire RESET_SRAM_LOGIC;
145 output wire W;
146 output wire CLK_COEF;
147 output wire OFF_ON_CHIP;
148 output wire COS;
149 output wire OFF_CHIP_DAC_P;
150 output wire ELECTRODE_OFFON;
151 output wire READ_PWM;
152 output wire CLK_SHFIT_RING;
153 output wire CLK_RING;
154 output wire READ_ON_OFF_PWM;
155 output wire RESET_RING;
156 output wire WRITE_PAD;
157 output wire EXT_RING;
158 output wire ON_OFF_RING;
159 output wire B_PID;
160 output wire A_PID;
161 output wire ADC_PID;
162 output wire ADC_MEM_READ;
163 output wire MAINE_READ;
164 output wire RESET_;
165 output wire WP0;
166 output wire WP1;
167 output wire WP2;
168 output wire WP3;
169 output wire RESET_P;
170 output wire CLK_P;
171 output wire PAR_P;
172 output wire RESET_PS;
173 output wire CLK_PS;
174 output wire LOAD_SHIFT;
175 output wire RESET_SHIFT;
176 output wire IN_COEF_PAD;
177 output wire CLK_SH3_PAD;
178 output wire IN_SHIFT_RING_PAD;
179 output wire CLK_TEMP;
180 output wire CHAMBER_RESET;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 201
181 output wire CHAMBER_CLK;
182 output wire WR_USB;
183 output wire RD_USB;
184 output wire SIWUA;
185 output wire SIWUB;
186 output wire [9:0] B;
187 output wire [16:0] DATA_OUT;
188 output wire [7:0] DATA_OUT_USB;
189190 wire CLK_DAC;
191 wire [17:0] DIN;
192 wire idel;
193 wire idel2;
194 wire idel3;
195 wire idel4;
196 wire start_DAC;
197 wire SYNTHESIZED_WIRE_25;
198 wire SYNTHESIZED_WIRE_1;
199 wire SYNTHESIZED_WIRE_2;
200 wire SYNTHESIZED_WIRE_5;
201 wire SYNTHESIZED_WIRE_6;
202 wire SYNTHESIZED_WIRE_26;
203 wire SYNTHESIZED_WIRE_8;
204 wire SYNTHESIZED_WIRE_9;
205 wire [16:0] SYNTHESIZED_WIRE_10;
206 wire SYNTHESIZED_WIRE_12;
207 wire SYNTHESIZED_WIRE_27;
208 wire SYNTHESIZED_WIRE_19;
209 wire SYNTHESIZED_WIRE_20;
210 wire SYNTHESIZED_WIRE_21;
211 wire SYNTHESIZED_WIRE_22;
212 wire SYNTHESIZED_WIRE_23;
213 wire SYNTHESIZED_WIRE_24;
214215 assign DAC_CLK1 = SYNTHESIZED_WIRE_23;
216 assign DAC_CLK2 = SYNTHESIZED_WIRE_23;
217 assign CLK_CH = SYNTHESIZED_WIRE_24;
218 assign RESET_SHIFT = SYNTHESIZED_WIRE_27;
219 assign CLK_TEMP = SYNTHESIZED_WIRE_24;
220 assign DATA_OUT = SYNTHESIZED_WIRE_10;
221222223224225 Reference_generator b2v_inst(
226 .clkIn(OSC_CLK),
227 .CS(CS),
228 .WR(WR),
229 .LDAC(LDAC),
230 .PD(PD),
231 .GAIN(GAIN),
232 .CLR(CLR),
233 .stop(SYNTHESIZED_WIRE_12),
234 .counter(B));
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 202
235236237 CH_TIMING b2v_inst1(
238 .clkIn(OSC_CLK),
239 .RESET_MASTER(SYNTHESIZED_WIRE_25),
240 .SING(SING),
241 .C1(C1),
242 .VLATCH(VLATCH),
243 .P1(P1),
244 .EXT_RESET(EXT_RESET),
245 .BS_A(BS_A),
246 .BS_P(BS_P),
247 .Q(Q));
248249250 Inv b2v_inst10(
251 .a(idel2),
252 .y(SYNTHESIZED_WIRE_21));
253254255 andgate b2v_inst11(
256 .a(SYNTHESIZED_WIRE_1),
257 .b(SYNTHESIZED_WIRE_2),
258 .y(CLK_SHIFT_PAD));
259260261 Inv b2v_inst12(
262 .a(idel3),
263 .y(SYNTHESIZED_WIRE_1));
264265266 Channel_Control b2v_inst13(
267 .clkIn(OSC_CLK),
268 .RESET_IN(SYNTHESIZED_WIRE_25),
269 .RESET_CH(RESET_CH),
270 .CLK_CH(SYNTHESIZED_WIRE_24));
271272273 Channel_Control b2v_inst14(
274 .clkIn(OSC_CLK),
275 .RESET_IN(SYNTHESIZED_WIRE_25),
276 .RESET_CH(CHAMBER_RESET),
277 .CLK_CH(CHAMBER_CLK));
278279280 SHIFT_REG_RESET b2v_inst15(
281 .clkIn(OSC_CLK),
282 .RESET_SHIFT(SYNTHESIZED_WIRE_27));
283284285 PID_CONT b2v_inst17(
286 .clkIn(OSC_CLK),
287 .READ_PWM(READ_PWM),
288 .CLK_SHIFT_RING(CLK_SHFIT_RING),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 203
289 .IN_SHIFT(IN_SHIFT_RING_PAD),
290 .CLK_RING(CLK_RING),
291 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
292 .RESET_RING(RESET_RING),
293 .WRITE_PAD(WRITE_PAD),
294 .EXT_RING(EXT_RING),
295 .ON__OFF_RING(ON_OFF_RING),
296 .B_PID(B_PID),
297 .A_PID(A_PID),
298 .ADC_PID(ADC_PID),
299 .ADC_MEM_READ(ADC_MEM_READ),
300 .MAINE_READ(MAINE_READ),
301 .RESET_(RESET_),
302 .WP0(WP0),
303 .WP1(WP1),
304 .WP2(WP2),
305 .WP3(WP3),
306 .RESET_P(RESET_P),
307 .CLK_P(CLK_P),
308 .PAR_P(PAR_P));
309310311 TX b2v_inst18(
312 .clkIn(OSC_CLK),
313 .RESET_PS(RESET_PS),
314 .CLK_PS(CLK_PS),
315 .LOADSHIFT(LOAD_SHIFT));
316317318 andgate b2v_inst19(
319 .a(SYNTHESIZED_WIRE_5),
320 .b(SYNTHESIZED_WIRE_6),
321 .y(CLK_SH3_PAD));
322323324 Voltage_DAC_cont b2v_inst2(
325 .clkIn(OSC_CLK),
326 .start(start_DAC),
327 .clkout(CLK_DAC),
328 .DIN(DIN));
329330331 Inv b2v_inst20(
332 .a(idel4),
333 .y(SYNTHESIZED_WIRE_5));
334335336 Datap b2v_inst21(
337 .clkIn(SYNTHESIZED_WIRE_26),
338 .start(SYNTHESIZED_WIRE_8),
339 .TXE(TXE_USB),
340 .reset(SYNTHESIZED_WIRE_9),
341 .DIN(SYNTHESIZED_WIRE_10),
342 .WR(WR_USB),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 204
343 .SIWUA(SIWUA),
344 .DATA_OUT(DATA_OUT_USB));
345346347 IO_B b2v_inst22(
348 .clkIn(SYNTHESIZED_WIRE_26),
349 .stop(SYNTHESIZED_WIRE_12),
350 .DATA_IN(DATA_IN),
351 .DATA_OUT(SYNTHESIZED_WIRE_10));
352353354 Startp b2v_inst23(
355 .clkIn(SYNTHESIZED_WIRE_26),
356 .RXF(RXF_USB_IN),
357 .DIN(DIN_USB),
358 .start(SYNTHESIZED_WIRE_8),
359 .RD(RD_USB),
360 .SIWUB(SIWUB),
361 .reset(SYNTHESIZED_WIRE_9)
362 );
363364365 DummyData b2v_inst24(
366 .clkIn(SYNTHESIZED_WIRE_26)
367 );
368369370 divider_usb b2v_inst25(
371 .clkIn(OSC_CLK),
372 .clk_out(SYNTHESIZED_WIRE_26));
373374375 Shift_Reg_COEFF b2v_inst29(
376 .clkIn(OSC_CLK),
377 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
378 .CLK_SH3(SYNTHESIZED_WIRE_6),
379 .I_COEFF_PAD(IN_COEF_PAD),
380 .IDEL_COEFF(idel4));
381382383 Shift_Reg_TEMP b2v_inst3(
384 .clkIn(OSC_CLK),
385 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
386 .CLK_SH2(SYNTHESIZED_WIRE_22),
387 .I_STAT_PAD(IN_E_PAD_TEMP),
388 .idel_TMEP(idel2));
389390391 SRAM b2v_inst30(
392 .clkIn(OSC_CLK),
393 .CLK_CV(CLK_CV),
394 .UP_DOWN_CV(UP_DOWN_CV),
395 .IMP_CV(IMP_CV),
396 .RESET_SRAM_LOGIC(RESET_SRAM_LOGIC),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 205
397 .W(W),
398 .CLK_COEF(CLK_COEF),
399 .OFF_ON_CHIP(OFF_ON_CHIP),
400 .COS(COS),
401 .OFF_CHIP_DAC_P(OFF_CHIP_DAC_P),
402 .ELECTRODE_OFFON(ELECTRODE_OFFON));
403404405 Voltage_DAC b2v_inst4(
406 .clkIn(CLK_DAC),
407 .start(start_DAC),
408 .Data(DIN),
409 .clkDAC(SYNTHESIZED_WIRE_23),
410 .din1(din_out1),
411 .ldac1(ldac1),
412 .sync1(sync1),
413 .din2(din_out2),
414 .ldac2(ldac2),
415 .sync2(sync2));
416417418 Shift_Reg_TEMP_STAT b2v_inst5(
419 .clkIn(OSC_CLK),
420 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
421 .CLK_SHIFT_PAD(SYNTHESIZED_WIRE_2),
422 .I_SHIFT_PAD(I_SHIFT_PAD),
423 .idel_TMEP_STAT(idel3));
424425426 Shift_Reg_POT b2v_inst6(
427 .clkIn(OSC_CLK),
428 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
429 .clk_POT(SYNTHESIZED_WIRE_20),
430 .I_STAT_PAD_POT(I_STAT_PAD),
431 .idel_POT(idel));
432433434 RESET_CONT b2v_inst64(
435 .clkIn(OSC_CLK),
436 .IDEL1(idel),
437 .IDEL2(idel2),
438 .IDEL3(idel3),
439 .IDEL4(idel4),
440 .RESET_OUT(SYNTHESIZED_WIRE_25));
441442443 andgate b2v_inst7(
444 .a(SYNTHESIZED_WIRE_19),
445 .b(SYNTHESIZED_WIRE_20),
446 .y(CLK_SH1));
447448449 Inv b2v_inst8(
450 .a(idel),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 206
451 .y(SYNTHESIZED_WIRE_19));
452453454 andgate b2v_inst9(
455 .a(SYNTHESIZED_WIRE_21),
456 .b(SYNTHESIZED_WIRE_22),
457 .y(CLK_SH2_TEMP));
458459460 endmodule
This code must be run prior to each measurements.
The Verilog code for each of the submodules are given below:
A.4.2 USB Controller
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Voltage_DAC_cont
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Datap(clkIn, start, DIN, TXE, WR, DATA_OUT, SIWUA, reset);
1213 input clkIn;
14 input start;
15 input TXE;
16 input [16:0] DIN; //16
17 output WR;
18 output [7:0] DATA_OUT;
19 output SIWUA;
20 input reset;
2122 //----------------------------------------------------------------------------
23 reg [29:0] count = 0;
24 reg WR = 0;
25 reg clkout;
26 reg [4:0] timer = 5’b00000;
27 reg [16:0] DATA_MID; //16
28 reg [7:0] DATA_OUT;
29 reg [7:0] DATAA;
30 reg [7:0] DATAB;
31 reg [7:0] DATAC;
32 reg [2:0] run = 3’b000;
33 reg SIWUA;
34 //----------------------------------------------------------------------------
35
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 207
3637 always @ (posedge clkIn)
38 begin
39 if (count < 40) //200
40 begin
41 clkout <= 1;
42 count <= count+1;
43 end
44 else if (count < 79) //399
45 begin
46 clkout <= 0;
47 count <= count+1;
48 end
49 if (count == 79) //399
50 count <= 0;
51 end
5253 //----------------------------------------------------------------------------
5455 always @ (posedge clkout)
56 begin
5758 SIWUA <= 1;
5960 // if (reset == 0)
61 // begin
62 // timer <= 0;
63 // end
64 if (!start)
65 begin
66 DATAA <= 8’b00000000;
67 DATAB <= 8’b00000001;
68 DATAC <= 8’b00000010;
69 end
7071 if (˜TXE && start)
72 begin
73 case (timer)
74 0:
75 begin
76 DATA_MID <= DIN;
77 end
78 5:
79 begin
80 WR <= 1;
81 end
82 10:
83 begin
84 if (run == 0)
85 begin
8687 DATAA[7:2] <= DATA_MID[5:0];
88 // DATAA[7] <= DATA_MID[0];
89 // DATAA[6] <= DATA_MID[1];
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 208
90 // DATAA[5] <= DATA_MID[2];
91 // DATAA[4] <= DATA_MID[3];
92 // DATAA[3] <= DATA_MID[4];
93 // DATAA[2] <= DATA_MID[5];
94 DATA_OUT <= DATAA[7:0];
95 run <= run +1 ;
96 end
97 else if (run == 1)
98 begin
99100 DATAB[7:2] <= DATA_MID[11:6];
101 // DATAA[7] <= DATA_MID[6];
102 // DATAA[6] <= DATA_MID[7];
103 // DATAA[5] <= DATA_MID[8];
104 // DATAA[4] <= DATA_MID[9];
105 // DATAA[3] <= DATA_MID[10];
106 // DATAA[2] <= DATA_MID[11];
107 DATA_OUT <= DATAB[7:0]; //[15:8]
108 run <= run +1 ;
109 end
110 else if (run == 2)
111 begin
112113 DATAC[6:2] <= DATA_MID[16:12];
114 // DATAA[6] <= DATA_MID[12];
115 // DATAA[5] <= DATA_MID[13];
116 // DATAA[4] <= DATA_MID[14];
117 // DATAA[3] <= DATA_MID[15];
118 // DATAA[2] <= DATA_MID[16];
119 DATA_OUT <= DATAC[7:0]; //[16:9]
120 run <= 0;
121 end
122 end
123 15:
124 begin
125 WR <= 0;
126 end
127 endcase
128 end
129130 if (timer < 16 && ˜TXE && reset)
131 timer <= timer + 1;
132 else if (timer == 16 || ˜reset)
133 timer <= 0;
134135136 end
137 endmodule
A.4.3 Master Clock Divider
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 209
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Channel_Control
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Divider(clkIn, clkout);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 output clkout;
15 ///////////////////////////////////////////////////////////////////////////////
16 reg clkout;
17 ///////////////////////////////////////////////////////////////////////////////
18 reg [29:0] count = 0;
19 ///////////////////////////////////////////////////////////////////////////////
20 always @ (posedge clkIn)
21 begin
22 if (count < 4)
23 begin
24 clkout <= 1;
25 count <= count+1;
26 end
27 else if (count < 7)
28 begin
29 clkout <= 0;
30 count <= count+1;
31 end
32 if (count == 7)
33 count <= 0;
34 end
35 ///////////////////////////////////////////////////////////////////////////////
3637 endmodule
38 ///////////////////////////////////////////////////////////////////////////////
A.4.4 USB Clock Divider
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Channel_Control
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module divider_usb(clkIn, clk_out);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 output clk_out;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 210
15 ///////////////////////////////////////////////////////////////////////////////
16 reg clk_out;
1718 reg [9:0] timer = 10’b0000000000;
19 ///////////////////////////////////////////////////////////////////////////////
20 reg [29:0] count = 0;
21 ///////////////////////////////////////////////////////////////////////////////
22 always @ (posedge clkIn)
23 begin
24 if (count < 8)
25 begin
26 clk_out <= 1;
27 count <= count+1;
28 end
29 else if (count < 15)
30 begin
31 clk_out <= 0;
32 count <= count+1;
33 end
34 if (count == 15)
35 count <= 0;
36 end
37 endmodule
38 ///////////////////////////////////////////////////////////////////////////////
A.4.5 One Channel FIFO Controller
1 // megafunction wizard: %FIFO%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: dcfifo
56 // ============================================================
7 // File Name: FIFO_ONE_CH.v
8 // Megafunction Name(s):
9 // dcfifo
10 //
11 // Simulation Library Files(s):
12 // altera_mf
13 // ============================================================
14 // ************************************************************
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 //
17 // 10.0 Build 218 06/27/2010 SJ Full Version
18 // ************************************************************
192021 //Copyright (C) 1991-2010 Altera Corporation
22 //Your use of Altera Corporation’s design tools, logic functions
23 //and other software and tools, and its AMPP partner logic
24 //functions, and any output files from any of the foregoing
25 //(including device programming or simulation files), and any
26 //associated documentation or information are expressly subject
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 211
27 //to the terms and conditions of the Altera Program License
28 //Subscription Agreement, Altera MegaCore Function License
29 //Agreement, or other applicable license agreement, including,
30 //without limitation, that your use is for the sole purpose of
31 //programming logic devices manufactured by Altera and sold by
32 //Altera or its authorized distributors. Please refer to the
33 //applicable agreement for further details.
343536 // synopsys translate_off
37 ‘timescale 1 ps / 1 ps
38 // synopsys translate_on
39 module FIFO_ONE_CH (
40 aclr,
41 data,
42 rdclk,
43 rdreq,
44 wrclk,
45 wrreq,
46 q,
47 rdempty,
48 rdfull,
49 wrempty,
50 wrfull);
5152 input aclr;
53 input [16:0] data;
54 input rdclk;
55 input rdreq;
56 input wrclk;
57 input wrreq;
58 output [16:0] q;
59 output rdempty;
60 output rdfull;
61 output wrempty;
62 output wrfull;
63 ‘ifndef ALTERA_RESERVED_QIS
64 // synopsys translate_off
65 ‘endif
66 tri0 aclr;
67 ‘ifndef ALTERA_RESERVED_QIS
68 // synopsys translate_on
69 ‘endif
7071 wire sub_wire0;
72 wire sub_wire1;
73 wire [16:0] sub_wire2;
74 wire sub_wire3;
75 wire sub_wire4;
76 wire wrempty = sub_wire0;
77 wire wrfull = sub_wire1;
78 wire [16:0] q = sub_wire2[16:0];
79 wire rdempty = sub_wire3;
80 wire rdfull = sub_wire4;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 212
8182 dcfifo dcfifo_component (
83 .rdclk (rdclk),
84 .wrclk (wrclk),
85 .wrreq (wrreq),
86 .aclr (aclr),
87 .data (data),
88 .rdreq (rdreq),
89 .wrempty (sub_wire0),
90 .wrfull (sub_wire1),
91 .q (sub_wire2),
92 .rdempty (sub_wire3),
93 .rdfull (sub_wire4),
94 .rdusedw (),
95 .wrusedw ());
96 defparam
97 dcfifo_component.intended_device_family = "Cyclone III",
98 dcfifo_component.lpm_numwords = 131072,
99 dcfifo_component.lpm_showahead = "OFF",
100 dcfifo_component.lpm_type = "dcfifo",
101 dcfifo_component.lpm_width = 17,
102 dcfifo_component.lpm_widthu = 17,
103 dcfifo_component.overflow_checking = "ON",
104 dcfifo_component.rdsync_delaypipe = 8,
105 dcfifo_component.underflow_checking = "ON",
106 dcfifo_component.use_eab = "ON",
107 dcfifo_component.write_aclr_synch = "ON",
108 dcfifo_component.wrsync_delaypipe = 8;
109110111 endmodule
112113 // ============================================================
114 // CNX file retrieval info
115 // ============================================================
116 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
117 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
118 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
119 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
120 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
121 // Retrieval info: PRIVATE: Clock NUMERIC "4"
122 // Retrieval info: PRIVATE: Depth NUMERIC "131072"
123 // Retrieval info: PRIVATE: Empty NUMERIC "1"
124 // Retrieval info: PRIVATE: Full NUMERIC "1"
125 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
126 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
127 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
128 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
129 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
130 // Retrieval info: PRIVATE: Optimize NUMERIC "1"
131 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
132 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
133 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
134 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 213
135 // Retrieval info: PRIVATE: Width NUMERIC "17"
136 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
137 // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
138 // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
139 // Retrieval info: PRIVATE: output_width NUMERIC "17"
140 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
141 // Retrieval info: PRIVATE: rsFull NUMERIC "1"
142 // Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
143 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
144 // Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
145 // Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
146 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
147 // Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
148 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
149 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
150 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "131072"
151 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
152 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
153 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
154 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "17"
155 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
156 // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "8"
157 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
158 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
159 // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
160 // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "8"
161 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
162 // Retrieval info: USED_PORT: data 0 0 17 0 INPUT NODEFVAL "data[16..0]"
163 // Retrieval info: USED_PORT: q 0 0 17 0 OUTPUT NODEFVAL "q[16..0]"
164 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
165 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
166 // Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
167 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
168 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
169 // Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
170 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
171 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
172 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
173 // Retrieval info: CONNECT: @data 0 0 17 0 data 0 0 17 0
174 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
175 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
176 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
177 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
178 // Retrieval info: CONNECT: q 0 0 17 0 @q 0 0 17 0
179 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
180 // Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
181 // Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
182 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
183 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH.v TRUE
184 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH.inc FALSE
185 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH.cmp FALSE
186 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH.bsf TRUE FALSE
187 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH_inst.v TRUE
188 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ONE_CH_bb.v TRUE
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 214
189 // Retrieval info: LIB_FILE: altera_mf
A.4.6 FIFO Controller
1 // megafunction wizard: %FIFO%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: scfifo
56 // ============================================================
7 // File Name: FIFO_OUT.v
8 // Megafunction Name(s):
9 // scfifo
10 //
11 // Simulation Library Files(s):
12 // altera_mf
13 // ============================================================
14 // ************************************************************
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 //
17 // 10.0 Build 218 06/27/2010 SJ Full Version
18 // ************************************************************
192021 //Copyright (C) 1991-2010 Altera Corporation
22 //Your use of Altera Corporation’s design tools, logic functions
23 //and other software and tools, and its AMPP partner logic
24 //functions, and any output files from any of the foregoing
25 //(including device programming or simulation files), and any
26 //associated documentation or information are expressly subject
27 //to the terms and conditions of the Altera Program License
28 //Subscription Agreement, Altera MegaCore Function License
29 //Agreement, or other applicable license agreement, including,
30 //without limitation, that your use is for the sole purpose of
31 //programming logic devices manufactured by Altera and sold by
32 //Altera or its authorized distributors. Please refer to the
33 //applicable agreement for further details.
343536 // synopsys translate_off
37 ‘timescale 1 ps / 1 ps
38 // synopsys translate_on
39 module FIFO_OUT (
40 clock,
41 data,
42 rdreq,
43 wrreq,
44 empty,
45 full,
46 q);
4748 input clock;
49 input [16:0] data;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 215
50 input rdreq;
51 input wrreq;
52 output empty;
53 output full;
54 output [16:0] q;
5556 wire sub_wire0;
57 wire sub_wire1;
58 wire [16:0] sub_wire2;
59 wire empty = sub_wire0;
60 wire full = sub_wire1;
61 wire [16:0] q = sub_wire2[16:0];
6263 scfifo scfifo_component (
64 .clock (clock),
65 .data (data),
66 .rdreq (rdreq),
67 .wrreq (wrreq),
68 .empty (sub_wire0),
69 .full (sub_wire1),
70 .q (sub_wire2),
71 .aclr (),
72 .almost_empty (),
73 .almost_full (),
74 .sclr (),
75 .usedw ());
76 defparam
77 scfifo_component.add_ram_output_register = "ON",
78 scfifo_component.intended_device_family = "Cyclone III",
79 scfifo_component.lpm_numwords = 256,
80 scfifo_component.lpm_showahead = "OFF",
81 scfifo_component.lpm_type = "scfifo",
82 scfifo_component.lpm_width = 17,
83 scfifo_component.lpm_widthu = 8,
84 scfifo_component.overflow_checking = "ON",
85 scfifo_component.underflow_checking = "ON",
86 scfifo_component.use_eab = "ON";
878889 endmodule
9091 // ============================================================
92 // CNX file retrieval info
93 // ============================================================
94 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
95 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
96 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
97 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
98 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
99 // Retrieval info: PRIVATE: Clock NUMERIC "0"
100 // Retrieval info: PRIVATE: Depth NUMERIC "256"
101 // Retrieval info: PRIVATE: Empty NUMERIC "1"
102 // Retrieval info: PRIVATE: Full NUMERIC "1"
103 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 216
104 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
105 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
106 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
107 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
108 // Retrieval info: PRIVATE: Optimize NUMERIC "1"
109 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
110 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
111 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
112 // Retrieval info: PRIVATE: UsedW NUMERIC "0"
113 // Retrieval info: PRIVATE: Width NUMERIC "17"
114 // Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
115 // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
116 // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
117 // Retrieval info: PRIVATE: output_width NUMERIC "17"
118 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
119 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
120 // Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
121 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
122 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
123 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
124 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
125 // Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
126 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
127 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
128 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
129 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
130 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
131 // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
132 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
133 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
134 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
135 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
136 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
137 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
138 // Retrieval info: USED_PORT: data 0 0 17 0 INPUT NODEFVAL "data[16..0]"
139 // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
140 // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
141 // Retrieval info: USED_PORT: q 0 0 17 0 OUTPUT NODEFVAL "q[16..0]"
142 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
143 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
144 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
145 // Retrieval info: CONNECT: @data 0 0 17 0 data 0 0 17 0
146 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
147 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
148 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
149 // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
150 // Retrieval info: CONNECT: q 0 0 17 0 @q 0 0 17 0
151 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT.v TRUE
152 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT.inc FALSE
153 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT.cmp FALSE
154 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT.bsf TRUE FALSE
155 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT_inst.v FALSE
156 // Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_OUT_bb.v TRUE
157 // Retrieval info: LIB_FILE: altera_mf
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 217
A.4.7 16-bits Parallel to Serial Converter
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: parallel to serial
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
1112 module parallel_to_serial (
13 clkIn,
14 DATA_IN,
15 start,
16 din1,
17 clkUSB
18 );
1920 // Inputs
21 input clkIn;
22 input [16:0] DATA_IN; // Incoming data
23 input start;
2425 //Wires
26 output wire din1;
27 output wire clkUSB;
28293031 // Registers
32 reg [4:0] timer = 5’b00000;
33 reg [29:0] count = 0;
34 reg [16:0] DATA_MID;
35 reg clkout;
3637 //----------------------------------------------------------------------------
383940 //always @ (posedge clkIn)
41 // begin
42 // if (count < 4) //200
43 // begin
44 // clkout <= 1;
45 // count <= count+1;
46 // end
47 // else if (count < 7) //399
48 // begin
49 // clkout <= 0;
50 // count <= count+1;
51 // end
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 218
52 // if (count == 7) //399
53 // count <= 0;
54 // end
5556 //----------------------------------------------------------------------------
575859 always @ (posedge clkIn)
60 begin
61 case (timer)
62 0:
63 begin
64 if (start)
65 DATA_MID <= DATA_IN;
66 end
67 17:
68 begin
69 timer <=0;
70 end
71 endcase
72 if (timer < 17 & start)
73 timer <= timer + 1;
7475 if (timer < 15 & start)
76 DATA_MID <= DATA_MID[15:0] , DATA_MID[16];
777879 end
8081 assign din1 = DATA_MID[16];
82 assign clkUSB = clkIn && start;
8384 endmodule
A.4.8 Timing PLL
1 // megafunction wizard: %ALTPLL%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altpll
56 // ============================================================
7 // File Name: PLL1.v
8 // Megafunction Name(s):
9 // altpll
10 //
11 // Simulation Library Files(s):
12 // altera_mf
13 // ============================================================
14 // ************************************************************
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 //
17 // 10.0 Build 218 06/27/2010 SJ Full Version
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 219
18 // ************************************************************
192021 //Copyright (C) 1991-2010 Altera Corporation
22 //Your use of Altera Corporation’s design tools, logic functions
23 //and other software and tools, and its AMPP partner logic
24 //functions, and any output files from any of the foregoing
25 //(including device programming or simulation files), and any
26 //associated documentation or information are expressly subject
27 //to the terms and conditions of the Altera Program License
28 //Subscription Agreement, Altera MegaCore Function License
29 //Agreement, or other applicable license agreement, including,
30 //without limitation, that your use is for the sole purpose of
31 //programming logic devices manufactured by Altera and sold by
32 //Altera or its authorized distributors. Please refer to the
33 //applicable agreement for further details.
343536 // synopsys translate_off
37 ‘timescale 1 ps / 1 ps
38 // synopsys translate_on
39 module PLL1 (
40 inclk0,
41 c0);
4243 input inclk0;
44 output c0;
4546 wire [4:0] sub_wire0;
47 wire [0:0] sub_wire4 = 1’h0;
48 wire [0:0] sub_wire1 = sub_wire0[0:0];
49 wire c0 = sub_wire1;
50 wire sub_wire2 = inclk0;
51 wire [1:0] sub_wire3 = sub_wire4, sub_wire2;
5253 altpll altpll_component (
54 .inclk (sub_wire3),
55 .clk (sub_wire0),
56 .activeclock (),
57 .areset (1’b0),
58 .clkbad (),
59 .clkena (61’b1),
60 .clkloss (),
61 .clkswitch (1’b0),
62 .configupdate (1’b0),
63 .enable0 (),
64 .enable1 (),
65 .extclk (),
66 .extclkena (41’b1),
67 .fbin (1’b1),
68 .fbmimicbidir (),
69 .fbout (),
70 .fref (),
71 .icdrclk (),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 220
72 .locked (),
73 .pfdena (1’b1),
74 .phasecounterselect (41’b1),
75 .phasedone (),
76 .phasestep (1’b1),
77 .phaseupdown (1’b1),
78 .pllena (1’b1),
79 .scanaclr (1’b0),
80 .scanclk (1’b0),
81 .scanclkena (1’b1),
82 .scandata (1’b0),
83 .scandataout (),
84 .scandone (),
85 .scanread (1’b0),
86 .scanwrite (1’b0),
87 .sclkout0 (),
88 .sclkout1 (),
89 .vcooverrange (),
90 .vcounderrange ());
91 defparam
92 altpll_component.bandwidth_type = "AUTO",
93 altpll_component.clk0_divide_by = 10,
94 altpll_component.clk0_duty_cycle = 50,
95 altpll_component.clk0_multiply_by = 1,
96 altpll_component.clk0_phase_shift = "0",
97 altpll_component.compensate_clock = "CLK0",
98 altpll_component.inclk0_input_frequency = 20000,
99 altpll_component.intended_device_family = "Cyclone III",
100 altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL1",
101 altpll_component.lpm_type = "altpll",
102 altpll_component.operation_mode = "NORMAL",
103 altpll_component.pll_type = "AUTO",
104 altpll_component.port_activeclock = "PORT_UNUSED",
105 altpll_component.port_areset = "PORT_UNUSED",
106 altpll_component.port_clkbad0 = "PORT_UNUSED",
107 altpll_component.port_clkbad1 = "PORT_UNUSED",
108 altpll_component.port_clkloss = "PORT_UNUSED",
109 altpll_component.port_clkswitch = "PORT_UNUSED",
110 altpll_component.port_configupdate = "PORT_UNUSED",
111 altpll_component.port_fbin = "PORT_UNUSED",
112 altpll_component.port_inclk0 = "PORT_USED",
113 altpll_component.port_inclk1 = "PORT_UNUSED",
114 altpll_component.port_locked = "PORT_UNUSED",
115 altpll_component.port_pfdena = "PORT_UNUSED",
116 altpll_component.port_phasecounterselect = "PORT_UNUSED",
117 altpll_component.port_phasedone = "PORT_UNUSED",
118 altpll_component.port_phasestep = "PORT_UNUSED",
119 altpll_component.port_phaseupdown = "PORT_UNUSED",
120 altpll_component.port_pllena = "PORT_UNUSED",
121 altpll_component.port_scanaclr = "PORT_UNUSED",
122 altpll_component.port_scanclk = "PORT_UNUSED",
123 altpll_component.port_scanclkena = "PORT_UNUSED",
124 altpll_component.port_scandata = "PORT_UNUSED",
125 altpll_component.port_scandataout = "PORT_UNUSED",
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 221
126 altpll_component.port_scandone = "PORT_UNUSED",
127 altpll_component.port_scanread = "PORT_UNUSED",
128 altpll_component.port_scanwrite = "PORT_UNUSED",
129 altpll_component.port_clk0 = "PORT_USED",
130 altpll_component.port_clk1 = "PORT_UNUSED",
131 altpll_component.port_clk2 = "PORT_UNUSED",
132 altpll_component.port_clk3 = "PORT_UNUSED",
133 altpll_component.port_clk4 = "PORT_UNUSED",
134 altpll_component.port_clk5 = "PORT_UNUSED",
135 altpll_component.port_clkena0 = "PORT_UNUSED",
136 altpll_component.port_clkena1 = "PORT_UNUSED",
137 altpll_component.port_clkena2 = "PORT_UNUSED",
138 altpll_component.port_clkena3 = "PORT_UNUSED",
139 altpll_component.port_clkena4 = "PORT_UNUSED",
140 altpll_component.port_clkena5 = "PORT_UNUSED",
141 altpll_component.port_extclk0 = "PORT_UNUSED",
142 altpll_component.port_extclk1 = "PORT_UNUSED",
143 altpll_component.port_extclk2 = "PORT_UNUSED",
144 altpll_component.port_extclk3 = "PORT_UNUSED",
145 altpll_component.width_clock = 5;
146147148 endmodule
149150 // ============================================================
151 // CNX file retrieval info
152 // ============================================================
153 // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
154 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
155 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
156 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
157 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
158 // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
159 // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
160 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
161 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
162 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
163 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
164 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
165 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
166 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
167 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
168 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
169 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
170 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
171 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
172 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
173 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
174 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
175 // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
176 // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
177 // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
178 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
179 // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 222
180 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
181 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
182 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
183 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
184 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
185 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
186 // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
187 // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
188 // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
189 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
190 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
191 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
192 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
193 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
194 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
195 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
196 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
197 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
198 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
199 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
200 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
201 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
202 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
203 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
204 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
205 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
206 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
207 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
208 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
209 // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
210 // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
211 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
212 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
213 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
214 // Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL1.mif"
215 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
216 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
217 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
218 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
219 // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
220 // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
221 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
222 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
223 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
224 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
225 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
226 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
227 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
228 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
229 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
230 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
231 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
232 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
233 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 223
234 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
235 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
236 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
237 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
238 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
239 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
240 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
241 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
242 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
243 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
244 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
245 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
246 // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
247 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
248 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
249 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
250 // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
251 // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
252 // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
253 // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
254 // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
255 // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
256 // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
257 // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
258 // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
259 // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
260 // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
261 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
262 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
263 // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
264 // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
265 // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
266 // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
267 // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
268 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
269 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
270 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
271 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
272 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
273 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
274 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
275 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
276 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
277 // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
278 // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
279 // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
280 // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
281 // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
282 // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
283 // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
284 // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
285 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
286 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
287 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 224
288 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
289 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
290 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
291 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
292 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
293 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.v TRUE
294 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.ppf TRUE
295 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.inc FALSE
296 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.cmp FALSE
297 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.bsf TRUE FALSE
298 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_inst.v FALSE
299 // Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_bb.v TRUE
300 // Retrieval info: LIB_FILE: altera_mf
301 // Retrieval info: CBX_MODULE_PREFIX: ON
A.4.9 Waveform Generator
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Reference_generator
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Reference_generator(clkIn,counter,CS,WR,LDAC,PD,GAIN,CLR,stop);
1213 input clkIn;
1415 output [9:0] counter;
16 output CS,WR,LDAC,PD,GAIN,CLR,stop;
1718 reg [9:0] counter = 0;
19 reg [9:0] counter2 = 0;
20 reg upward = 1;
21 reg [20:0] clk_count = 0;
22 reg [29:0] count = 0;
23 reg [29:0] count2 = 0;
24 reg [9:0] up = 430;
25 reg [9:0] pause_time = 300;
26 reg [9:0] base = 231;
27 reg [29:0] pause = 0;
28 reg stop = 0;
29 reg clkout;
3031 reg clkout2;
323334 //----------------------------------------------------------------------------
3536 assign CS = 0;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 225
37 assign WR = clkout;
38 assign PD = 1;
39 assign GAIN = 0;
40 assign CLR = 1;
41 assign LDAC = 0;
424344 //----------------------------------------------------------------------------
4546 always @ (posedge clkIn)
47 begin
48 if (count < 250) //200
49 begin
50 clkout <= 1;
51 count <= count+1;
52 end
53 else if (count < 499) //399
54 begin
55 clkout <= 0;
56 count <= count+1;
57 end
58 if (count == 499) //399
59 count <= 0;
60 end
6162 //----------------------------------------------------------------------------
6364 always @ (posedge clkIn)
65 begin
66 if (count2 < 100000) //200
67 begin
68 clkout2 <= 1;
69 count2 <= count2+1;
70 end
71 else if (count2 < 199999) //399
72 begin
73 clkout2 <= 0;
74 count2 <= count2+1;
75 end
76 if (count2 == 199999) //399
77 count2 <= 0;
78 end
798081 always @ (negedge clkout2)
82 begin
8384 // clk_count <= clk_count + 1;
85 counter <= base;
86 counter2 <= base; //276
87 if ( (counter2 < up+1) & (upward == 1) ) //563
88 begin
89 counter <= counter - 1;
90 counter2 <= counter2 + 1;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 226
91 stop <=0;
92 end
93 if ( (counter2 == up) & (upward == 1) ) //562
94 begin
95 upward <= 0;
96 stop <=0;
97 end
98 if ( (counter2 < up+2) & (upward == 0) ) //564
99 begin
100 counter <= counter + 1;
101 counter2 <= counter2 - 1;
102 stop <=0;
103 end
104 if ( (counter2 == base+1) & (upward == 0) ) //277
105 if (pause < pause_time) //200
106 begin
107 pause <= pause+1;
108 counter <= base+1;
109 counter2 <= base+1;
110 stop <=0;
111 end
112 else //399
113 begin
114 pause <= 0;
115 // clk_count <= 0;
116 upward <= 1;
117 counter <= base;
118 counter2 <= base;
119 stop <=0;
120 end
121 end
122123 endmodule
A.4.10 Master Reset
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: CH_TIMING
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module RESET_CONT(clkIn, IDEL1, IDEL2, IDEL3, IDEL4, RESET_OUT);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn, IDEL1, IDEL2, IDEL3, IDEL4;
14 output RESET_OUT;
15 ///////////////////////////////////////////////////////////////////////////////
16 reg clk;
17 reg RESET_OUT = 0;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 227
18 reg [29:0] count = 0;
19 ///////////////////////////////////////////////////////////////////////////////
20 always @ (posedge clkIn)
21 begin
22 if (count < 4)
23 begin
24 clk <= 1;
25 count <= count+1;
26 end
27 else if (count < 7)
28 begin
29 clk <= 0;
30 count <= count+1;
31 end
32 if (count == 7)
33 count <= 0;
34 end
35 ///////////////////////////////////////////////////////////////////////////////
36 always @ (posedge clkIn)
37 begin
3839 if ( !IDEL1 && !IDEL2 && !IDEL3 && !IDEL4)
40 RESET_OUT <= 1;
41 else
42 RESET_OUT <= 0;
43 end
44 endmodule
A.4.11 Seven Bit Counter
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: TX
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Seven_bit_counter(clkIn,
12 Timer, start
13 );
14 ///////////////////////////////////////////////////////////////////////////////
15 input clkIn;
16 output [16:0] Timer;
17 output start;
18 ///////////////////////////////////////////////////////////////////////////////
19 reg [16:0] Timer =0;
20 reg clk;
21 reg start;
22 ///////////////////////////////////////////////////////////////////////////////
23 reg [29:0] count = 0;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 228
24 ///////////////////////////////////////////////////////////////////////////////
25 always @ (posedge clkIn)
26 begin
27 if (count < 8)
28 begin
29 clk <= 1;
30 count <= count+1;
31 end
32 else if (count < 15)
33 begin
34 clk <= 0;
35 count <= count+1;
36 end
37 if (count == 15)
38 count <= 0;
39 end
40 ////////////////////////////////////////////////////////////////////////////////
41 always @ (negedge clk)
42 begin
43 start <= 1;
44 Timer <= Timer +1;
45 end
46 endmodule
A.4.12 Chip Timing Coefficients
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Shift_Reg_TEMP
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Shift_Reg_COEFF(clkIn, RESET_SHIFT, CLK_SH3, I_COEFF_PAD, IDEL_COEFF);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 input RESET_SHIFT;
15 output CLK_SH3, IDEL_COEFF;
16 output wire I_COEFF_PAD;
17 ///////////////////////////////////////////////////////////////////////////////
18 reg CLK_SH3;
19 reg IDEL_COEFF =1;
20 reg [4:0] timer = 5’b00000;
21 reg [29:0] count = 0;
22 reg [29:0] DATA = 30’b000001000000000000011111111111; //30’b000001000000000001111111111111; ’
b000001000000011111111111111011; 30’b00000100000000001100000000000;30’b000001000000000000111111111111;30’
b000001000000000000011111111111;
23 reg Dataout;
24 ///////////////////////////////////////////////////////////////////////////////
25 always @ (posedge clkIn)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 229
26 begin
27 if (count < 10000)
28 begin
29 CLK_SH3 <= 1;
30 count <= count+1;
31 end
32 else if (count < 19999)
33 begin
34 CLK_SH3 <= 0;
35 count <= count+1;
36 end
37 if (count == 19999)
38 count <= 0;
39 end
40 ///////////////////////////////////////////////////////////////////////////////
4142 always @ (negedge CLK_SH3)
43 begin
44 case (timer)
45 0:
46 begin
47 IDEL_COEFF = 1;
48 Dataout <= DATA[29];
49 end
50 endcase
5152 if (timer < 30 && RESET_SHIFT)
53 begin
54 timer <= timer + 1;
55 DATA <= DATA[28:0] , DATA[29];
56 Dataout <= DATA[29];
57 end
58 else if (timer == 30)
59 begin
60 IDEL_COEFF = 0;
61 Dataout <= 0;
62 end
63 end
64 assign I_COEFF_PAD = Dataout;
65 endmodule
A.4.13 SRAM Timing Coefficients
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Shift_Reg_TEMP
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 230
11 module Shift_Reg_COEFF_SRAM(clkIn, RESET_SHIFT, CLK_SH3, I_COEFF_PAD, IDEL_COEFF, clk_SRAM);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 input RESET_SHIFT;
15 input clk_SRAM;
16 output CLK_SH3, IDEL_COEFF;
17 output wire I_COEFF_PAD;
18 ///////////////////////////////////////////////////////////////////////////////
19 reg CLK_SH3;
20 reg IDEL_COEFF =1;
21 reg [4:0] timer = 5’b00000;
22 reg [4:0] SRAM = 5’b00000;
23 reg [4:0] SRAMIDEL = 5’b00000;
24 reg timerX = 0;
2526 reg [29:0] count = 0;
2728 reg [29:0] DATA1 = 30’b000001000000000000000000011111; //000001000000000000000000011111
000001000000001111111110011111
29 reg [29:0] DATA2 = 30’b000001000000000000000000011111;
30 reg [29:0] DATA3 = 30’b000001000000000000000000011111;
31 reg [29:0] DATA4 = 30’b000001000000000000000000011111;
32 reg [29:0] DATA5 = 30’b000001000000000000000000011111;
33 reg [29:0] DATA6 = 30’b000001000000000000000000011111;
34 reg [29:0] DATA7 = 30’b000001000000000000000000011111;
35 reg [29:0] DATA8 = 30’b000001000000000000000000011111;
36 reg [29:0] DATA9 = 30’b000001000000000000000000011111;
37 reg [29:0] DATA10 = 30’b000001000000000000000000011111;
38 reg [29:0] DATA11 = 30’b000001000000000000000000011111;
39 reg [29:0] DATA12 = 30’b000001000000000000000000011111;
40 reg [29:0] DATA13 = 30’b000001000000000000000000011111;
41 reg [29:0] DATA14 = 30’b000001000000000000000000011111;
42 reg [29:0] DATA15 = 30’b000001000000000000000000011111;
43 reg [29:0] DATA16 = 30’b000001000000000000000000011111;
4445 reg Dataout;
46 ///////////////////////////////////////////////////////////////////////////////
47 always @ (posedge clkIn)
48 begin
49 if (count < 50)
50 begin
51 CLK_SH3 <= 1;
52 count <= count+1;
53 end
54 else if (count < 99)
55 begin
56 CLK_SH3 <= 0;
57 count <= count+1;
58 end
59 if (count == 99)
60 count <= 0;
61 end
62 ///////////////////////////////////////////////////////////////////////////////
63 always @ (negedge clk_SRAM)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 231
64 begin
65 SRAMIDEL = SRAMIDEL +1;
66 if (RESET_SHIFT && SRAMIDEL > 4)
67 begin
68 timerX <= 1;
69 SRAM <= SRAM +1;
70 end
71 if (SRAM == 16)
72 begin
73 SRAM <= 5’b00000;
74 timerX <= 0;
75 end
76 end
77 ///////////////////////////////////////////////////////////////////////////////
78 always @ (negedge CLK_SH3)
79 begin
8081 if (timer == 0)
82 begin
83 IDEL_COEFF = 1;
8485 if (SRAM == 0)
86 Dataout <= DATA1[29];
87 else if (SRAM == 1)
88 Dataout <= DATA2[29];
89 else if (SRAM == 2)
90 Dataout <= DATA3[29];
91 else if (SRAM == 3)
92 Dataout <= DATA4[29];
93 else if (SRAM == 4)
94 Dataout <= DATA5[29];
95 else if (SRAM == 5)
96 Dataout <= DATA6[29];
97 else if (SRAM == 6)
98 Dataout <= DATA7[29];
99 else if (SRAM == 7)
100 Dataout <= DATA8[29];
101 else if (SRAM == 8)
102 Dataout <= DATA9[29];
103 else if (SRAM == 9)
104 Dataout <= DATA10[29];
105 else if (SRAM == 10)
106 Dataout <= DATA11[29];
107 else if (SRAM == 11)
108 Dataout <= DATA12[29];
109 else if (SRAM == 12)
110 Dataout <= DATA13[29];
111 else if (SRAM == 13)
112 Dataout <= DATA14[29];
113 else if (SRAM == 14)
114 Dataout <= DATA15[29];
115 else if (SRAM == 15)
116 Dataout <= DATA16[29];
117
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 232
118 end
119120121 if (timer < 30 && RESET_SHIFT)
122 begin
123 timer <= timer + 1;
124125 if (SRAM == 0)
126 begin
127 DATA1 <= DATA1[28:0] , DATA1[29];
128 Dataout <= DATA1[29];
129 end
130 if (SRAM == 1)
131 begin
132 DATA2 <= DATA2[28:0] , DATA2[29];
133 Dataout <= DATA2[29];
134 end
135 if (SRAM == 2)
136 begin
137 DATA3 <= DATA3[28:0] , DATA3[29];
138 Dataout <= DATA3[29];
139 end
140 if (SRAM == 3)
141 begin
142 DATA4 <= DATA4[28:0] , DATA4[29];
143 Dataout <= DATA4[29];
144 end
145 if (SRAM == 4)
146 begin
147 DATA5 <= DATA5[28:0] , DATA5[29];
148 Dataout <= DATA5[29];
149 end
150 if (SRAM == 5)
151 begin
152 DATA6 <= DATA6[28:0] , DATA6[29];
153 Dataout <= DATA6[29];
154 end
155 if (SRAM == 6)
156 begin
157 DATA7 <= DATA7[28:0] , DATA7[29];
158 Dataout <= DATA7[29];
159 end
160 if (SRAM == 7)
161 begin
162 DATA8 <= DATA8[28:0] , DATA8[29];
163 Dataout <= DATA8[29];
164 end
165 if (SRAM == 8)
166 begin
167 DATA9 <= DATA9[28:0] , DATA9[29];
168 Dataout <= DATA9[29];
169 end
170 if (SRAM == 9)
171 begin
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 233
172 DATA10 <= DATA10[28:0] , DATA10[29];
173 Dataout <= DATA10[29];
174 end
175 if (SRAM == 10)
176 begin
177 DATA11 <= DATA11[28:0] , DATA11[29];
178 Dataout <= DATA11[29];
179 end
180 if (SRAM == 11)
181 begin
182 DATA12 <= DATA12[28:0] , DATA12[29];
183 Dataout <= DATA12[29];
184 end
185 if (SRAM == 12)
186 begin
187 DATA13 <= DATA13[28:0] , DATA13[29];
188 Dataout <= DATA13[29];
189 end
190 if (SRAM == 13)
191 begin
192 DATA14 <= DATA14[28:0] , DATA14[29];
193 Dataout <= DATA14[29];
194 end
195 if (SRAM == 14)
196 begin
197 DATA15 <= DATA15[28:0] , DATA15[29];
198 Dataout <= DATA15[29];
199 end
200 if (SRAM == 15)
201 begin
202 DATA16 <= DATA16[28:0] , DATA16[29];
203 Dataout <= DATA16[29];
204 end
205 end
206 else if (timer == 30)
207 begin
208 IDEL_COEFF = 0;
209 Dataout <= 0;
210 end
211 if (timerX == 1)
212 timer <= 0;
213 end
214 assign I_COEFF_PAD = Dataout;
215216 endmodule
A.4.14 Channel Range Controller Coefficients
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 234
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Shift_Reg_POT
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Shift_Reg_POT(clkIn, RESET_SHIFT, clk_POT, I_STAT_PAD_POT, idel_POT);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 input RESET_SHIFT;
15 output clk_POT, idel_POT;
16 output wire I_STAT_PAD_POT;
1718 ///////////////////////////////////////////////////////////////////////////////
19 reg clk_POT;
20 reg idel_POT =1;
21 reg [4:0] timer = 5’b00000;
22 reg [29:0] count = 0;
23 reg [17:0] DATA = 18’b000001101000010011; //1101000000011 1100000001011 b000001101000010011;
24 reg Dataout;
25 ///////////////////////////////////////////////////////////////////////////////
26 always @ (posedge clkIn)
27 begin
28 if (count < 10000)
29 begin
30 clk_POT <= 1;
31 count <= count+1;
32 end
33 else if (count < 19999)
34 begin
35 clk_POT <= 0;
36 count <= count+1;
37 end
38 if (count == 19999)
39 count <= 0;
40 end
41 ///////////////////////////////////////////////////////////////////////////////
4243 always @ (negedge clk_POT)
44 begin
45 case (timer)
46 0:
47 begin
48 idel_POT = 1;
49 Dataout <= DATA[17];
50 end
51 endcase
5253 if (timer < 18 && RESET_SHIFT)
54 begin
55 timer <= timer + 1;
56 DATA <= DATA[16:0] , DATA[17];
57 Dataout <= DATA[17];
58 end
59 else if (timer == 18)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 235
60 begin
61 idel_POT = 0;
62 Dataout <= 0;
63 end
64 end
65 assign I_STAT_PAD_POT = Dataout;
66 endmodule
A.4.15 Impedance Spectroscopy SRAM Coefficients
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Channel_Control
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module SHIFT_REG_RESET(clkIn, RESET_SHIFT);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 output RESET_SHIFT;
15 ///////////////////////////////////////////////////////////////////////////////
16 reg RESET_SHIFT = 0;
17 reg clk;
18 reg [9:0] timer = 10’b0000000000;
19 ///////////////////////////////////////////////////////////////////////////////
20 reg [29:0] count = 0;
21 ///////////////////////////////////////////////////////////////////////////////
22 always @ (posedge clkIn)
23 begin
24 if (count < 10000)
25 begin
26 clk <= 1;
27 count <= count+1;
28 end
29 else if (count < 19999)
30 begin
31 clk <= 0;
32 count <= count+1;
33 end
34 if (count == 19999)
35 count <= 0;
36 end
37 ///////////////////////////////////////////////////////////////////////////////
38 always @ (negedge clk)
39 begin
40 if (timer < 500)
41 begin
42 timer <= timer + 1;
43 RESET_SHIFT <= 0;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 236
44 end
45 else
46 RESET_SHIFT <= 1;
47 end
48 endmodule
49 ///////////////////////////////////////////////////////////////////////////////
A.4.16 Temperature Regulation SRAM Coefficients
1 ‘timescale 1ns / 1ps
2 ////////////////////////////////////////////////////////////////////////////////
3 // Company: U of T
4 // Engineer: Hamed
5 //
6 // Create Date: 2:44pm 12/08/2010
7 // Module Name: Shift_Reg_TEMP
8 // Target Device: EP3C10-FBGA256-2
9 //
10 ////////////////////////////////////////////////////////////////////////////////
11 module Shift_Reg_TEMP(clkIn, RESET_SHIFT, CLK_SH2, I_STAT_PAD, IDEL_TMEP);
12 ///////////////////////////////////////////////////////////////////////////////
13 input clkIn;
14 input RESET_SHIFT;
15 output CLK_SH2, IDEL_TMEP;
16 output wire I_STAT_PAD;
17 ///////////////////////////////////////////////////////////////////////////////
18 reg CLK_SH2;
19 reg IDEL_TEMP =1;
20 reg [4:0] timer = 5’b00000;
21 reg [29:0] count = 0;
22 reg [15:0] DATA = 16’b0000000010000000;
23 reg Dataout;
24 ///////////////////////////////////////////////////////////////////////////////
25 always @ (posedge clkIn)
26 begin
27 if (count < 10000)
28 begin
29 CLK_SH2 <= 1;
30 count <= count+1;
31 end
32 else if (count < 19999)
33 begin
34 CLK_SH2 <= 0;
35 count <= count+1;
36 end
37 if (count == 19999)
38 count <= 0;
39 end
40 ///////////////////////////////////////////////////////////////////////////////
4142 always @ (negedge CLK_SH2)
43 begin
44 case (timer)
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 237
45 0:
46 begin
47 IDEL_TEMP = 1;
48 Dataout <= DATA[15];
49 end
50 endcase
5152 if (timer < 16 && RESET_SHIFT)
53 begin
54 timer <= timer + 1;
55 DATA <= DATA[14:0] , DATA[15];
56 Dataout <= DATA[15];
57 end
58 else if (timer == 16)
59 begin
60 IDEL_TEMP = 0;
61 Dataout <= 0;
62 end
63 end
64 assign I_STAT_PAD = Dataout;
65 endmodule
A.4.17 Test Channel Controller
1 ////////////////////////////////////////////////////////////////////////////////
2 // Company: U of T
3 // Engineer: Hamed
4 //
5 // Create Date: 2:44pm 12/08/2010
6 // Module Name: Channel_control test bench
7 // Target Device: EP3C10-FBGA256-2
8 //
9 ////////////////////////////////////////////////////////////////////////////////
1011 module TEST_Channel_Control;
1213 reg clkIn, RESET_IN ;
1415 wire RESET_CH, CLK_CH;
1617 Channel_Control dut (clkIn, RESET_CH, RESET_IN, CLK_CH);
1819 initial // Clock generator
20 begin
21 clkIn=0;
22 RESET_IN = 1;
23 forever #10 clkIn = !clkIn;
24 end
2526 initial
27 $monitor($stime,, clkIn,, RESET_CH,, RESET_IN,, CLK_CH);
28 endmodule
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 238
A.5 Example CV Recording Verilog Code
The following code generates a 0 to 700mV CV waveform with scan rate of 100mV/s
and simultaneously records the resulting current on 54 channels.1 // Copyright (C) 1991-2011 Altera Corporation
2 // Your use of Altera Corporation’s design tools, logic functions
3 // and other software and tools, and its AMPP partner logic
4 // functions, and any output files from any of the foregoing
5 // (including device programming or simulation files), and any
6 // associated documentation or information are expressly subject
7 // to the terms and conditions of the Altera Program License
8 // Subscription Agreement, Altera MegaCore Function License
9 // Agreement, or other applicable license agreement, including,
10 // without limitation, that your use is for the sole purpose of
11 // programming logic devices manufactured by Altera and sold by
12 // Altera or its authorized distributors. Please refer to the
13 // applicable agreement for further details.
1415 // PROGRAM "Quartus II 64-Bit"
16 // VERSION "Version 11.0 Build 157 04/27/2011 SJ Full Version"
17 // CREATED "Sun Jul 21 20:24:15 2013"
1819 module CHEM_PRO_TOP(
20 OSC_CLK,
21 TXE_USB,
22 RXF_USB_IN,
23 DATA_IN,
24 DIN_USB,
25 CS,
26 WR,
27 PD,
28 GAIN,
29 CLR,
30 ldac1,
31 sync1,
32 ldac2,
33 sync2,
34 din_out2,
35 din_out1,
36 SING,
37 C1,
38 VLATCH,
39 P1,
40 EXT_RESET,
41 BS_A,
42 BS_P,
43 Q,
44 LDAC,
45 DAC_CLK1,
46 DAC_CLK2,
47 CLK_SH1,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 239
48 I_STAT_PAD,
49 CLK_SH2_TEMP,
50 IN_E_PAD_TEMP,
51 CLK_SHIFT_PAD,
52 I_SHIFT_PAD,
53 RESET_CH,
54 CLK_CH,
55 CLK_CV,
56 UP_DOWN_CV,
57 IMP_CV,
58 RESET_SRAM_LOGIC,
59 W,
60 CLK_COEF,
61 OFF_ON_CHIP,
62 COS,
63 OFF_CHIP_DAC_P,
64 ELECTRODE_OFFON,
65 READ_PWM,
66 CLK_SHFIT_RING,
67 CLK_RING,
68 READ_ON_OFF_PWM,
69 RESET_RING,
70 WRITE_PAD,
71 EXT_RING,
72 ON_OFF_RING,
73 B_PID,
74 A_PID,
75 ADC_PID,
76 ADC_MEM_READ,
77 MAINE_READ,
78 RESET_,
79 WP0,
80 WP1,
81 WP2,
82 WP3,
83 RESET_P,
84 CLK_P,
85 PAR_P,
86 RESET_PS,
87 CLK_PS,
88 LOAD_SHIFT,
89 RESET_SHIFT,
90 IN_COEF_PAD,
91 CLK_SH3_PAD,
92 IN_SHIFT_RING_PAD,
93 CLK_TEMP,
94 CHAMBER_RESET,
95 CHAMBER_CLK,
96 WR_USB,
97 RD_USB,
98 SIWUA,
99 SIWUB,
100 B,
101 DATA_OUT,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 240
102 DATA_OUT_USB
103 );
104105106 input wire OSC_CLK;
107 input wire TXE_USB;
108 input wire RXF_USB_IN;
109 input wire [16:0] DATA_IN;
110 input wire [7:0] DIN_USB;
111 output wire CS;
112 output wire WR;
113 output wire PD;
114 output wire GAIN;
115 output wire CLR;
116 output wire ldac1;
117 output wire sync1;
118 output wire ldac2;
119 output wire sync2;
120 output wire din_out2;
121 output wire din_out1;
122 output wire SING;
123 output wire C1;
124 output wire VLATCH;
125 output wire P1;
126 output wire EXT_RESET;
127 output wire BS_A;
128 output wire BS_P;
129 output wire Q;
130 output wire LDAC;
131 output wire DAC_CLK1;
132 output wire DAC_CLK2;
133 output wire CLK_SH1;
134 output wire I_STAT_PAD;
135 output wire CLK_SH2_TEMP;
136 output wire IN_E_PAD_TEMP;
137 output wire CLK_SHIFT_PAD;
138 output wire I_SHIFT_PAD;
139 output wire RESET_CH;
140 output wire CLK_CH;
141 output wire CLK_CV;
142 output wire UP_DOWN_CV;
143 output wire IMP_CV;
144 output wire RESET_SRAM_LOGIC;
145 output wire W;
146 output wire CLK_COEF;
147 output wire OFF_ON_CHIP;
148 output wire COS;
149 output wire OFF_CHIP_DAC_P;
150 output wire ELECTRODE_OFFON;
151 output wire READ_PWM;
152 output wire CLK_SHFIT_RING;
153 output wire CLK_RING;
154 output wire READ_ON_OFF_PWM;
155 output wire RESET_RING;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 241
156 output wire WRITE_PAD;
157 output wire EXT_RING;
158 output wire ON_OFF_RING;
159 output wire B_PID;
160 output wire A_PID;
161 output wire ADC_PID;
162 output wire ADC_MEM_READ;
163 output wire MAINE_READ;
164 output wire RESET_;
165 output wire WP0;
166 output wire WP1;
167 output wire WP2;
168 output wire WP3;
169 output wire RESET_P;
170 output wire CLK_P;
171 output wire PAR_P;
172 output wire RESET_PS;
173 output wire CLK_PS;
174 output wire LOAD_SHIFT;
175 output wire RESET_SHIFT;
176 output wire IN_COEF_PAD;
177 output wire CLK_SH3_PAD;
178 output wire IN_SHIFT_RING_PAD;
179 output wire CLK_TEMP;
180 output wire CHAMBER_RESET;
181 output wire CHAMBER_CLK;
182 output wire WR_USB;
183 output wire RD_USB;
184 output wire SIWUA;
185 output wire SIWUB;
186 output wire [9:0] B;
187 output wire [16:0] DATA_OUT;
188 output wire [7:0] DATA_OUT_USB;
189190 wire CLK_DAC;
191 wire [17:0] DIN;
192 wire idel;
193 wire idel2;
194 wire idel3;
195 wire idel4;
196 wire start_DAC;
197 wire SYNTHESIZED_WIRE_26;
198 wire SYNTHESIZED_WIRE_1;
199 wire SYNTHESIZED_WIRE_2;
200 wire SYNTHESIZED_WIRE_5;
201 wire SYNTHESIZED_WIRE_6;
202 wire SYNTHESIZED_WIRE_27;
203 wire SYNTHESIZED_WIRE_8;
204 wire SYNTHESIZED_WIRE_9;
205 wire [16:0] SYNTHESIZED_WIRE_28;
206 wire SYNTHESIZED_WIRE_12;
207 wire SYNTHESIZED_WIRE_29;
208 wire SYNTHESIZED_WIRE_20;
209 wire SYNTHESIZED_WIRE_21;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 242
210 wire SYNTHESIZED_WIRE_22;
211 wire SYNTHESIZED_WIRE_23;
212 wire SYNTHESIZED_WIRE_24;
213 wire SYNTHESIZED_WIRE_25;
214215 assign DAC_CLK1 = SYNTHESIZED_WIRE_24;
216 assign DAC_CLK2 = SYNTHESIZED_WIRE_24;
217 assign CLK_CH = SYNTHESIZED_WIRE_25;
218 assign RESET_SHIFT = SYNTHESIZED_WIRE_29;
219 assign CLK_TEMP = SYNTHESIZED_WIRE_25;
220221222223224 Reference_generator b2v_inst(
225 .clkIn(OSC_CLK),
226 .CS(CS),
227 .WR(WR),
228 .LDAC(LDAC),
229 .PD(PD),
230 .GAIN(GAIN),
231 .CLR(CLR),
232 .stop(SYNTHESIZED_WIRE_12),
233 .counter(B));
234235236 CH_TIMING b2v_inst1(
237 .clkIn(OSC_CLK),
238 .RESET_MASTER(SYNTHESIZED_WIRE_26),
239 .SING(SING),
240 .C1(C1),
241 .VLATCH(VLATCH),
242 .P1(P1),
243 .EXT_RESET(EXT_RESET),
244 .BS_A(BS_A),
245 .BS_P(BS_P),
246 .Q(Q));
247248249 Inv b2v_inst10(
250 .a(idel2),
251 .y(SYNTHESIZED_WIRE_22));
252253254 andgate b2v_inst11(
255 .a(SYNTHESIZED_WIRE_1),
256 .b(SYNTHESIZED_WIRE_2),
257 .y(CLK_SHIFT_PAD));
258259260 Inv b2v_inst12(
261 .a(idel3),
262 .y(SYNTHESIZED_WIRE_1));
263
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 243
264265 Channel_Control b2v_inst13(
266 .clkIn(OSC_CLK),
267 .RESET_IN(SYNTHESIZED_WIRE_26),
268 .RESET_CH(RESET_CH),
269 .CLK_CH(SYNTHESIZED_WIRE_25));
270271272 Channel_Control b2v_inst14(
273 .clkIn(OSC_CLK),
274 .RESET_IN(SYNTHESIZED_WIRE_26),
275 .RESET_CH(CHAMBER_RESET),
276 .CLK_CH(CHAMBER_CLK));
277278279 SHIFT_REG_RESET b2v_inst15(
280 .clkIn(OSC_CLK),
281 .RESET_SHIFT(SYNTHESIZED_WIRE_29));
282283284 PID_CONT b2v_inst17(
285 .clkIn(OSC_CLK),
286 .READ_PWM(READ_PWM),
287 .CLK_SHIFT_RING(CLK_SHFIT_RING),
288 .IN_SHIFT(IN_SHIFT_RING_PAD),
289 .CLK_RING(CLK_RING),
290 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
291 .RESET_RING(RESET_RING),
292 .WRITE_PAD(WRITE_PAD),
293 .EXT_RING(EXT_RING),
294 .ON__OFF_RING(ON_OFF_RING),
295 .B_PID(B_PID),
296 .A_PID(A_PID),
297 .ADC_PID(ADC_PID),
298 .ADC_MEM_READ(ADC_MEM_READ),
299 .MAINE_READ(MAINE_READ),
300 .RESET_(RESET_),
301 .WP0(WP0),
302 .WP1(WP1),
303 .WP2(WP2),
304 .WP3(WP3),
305 .RESET_P(RESET_P),
306 .CLK_P(CLK_P),
307 .PAR_P(PAR_P));
308309310 TX b2v_inst18(
311 .clkIn(OSC_CLK),
312 .RESET_PS(RESET_PS),
313 .CLK_PS(CLK_PS),
314 .LOADSHIFT(LOAD_SHIFT));
315316317 andgate b2v_inst19(
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 244
318 .a(SYNTHESIZED_WIRE_5),
319 .b(SYNTHESIZED_WIRE_6),
320 .y(CLK_SH3_PAD));
321322323 Voltage_DAC_cont b2v_inst2(
324 .clkIn(OSC_CLK),
325 .start(start_DAC),
326 .clkout(CLK_DAC),
327 .DIN(DIN));
328329330 Inv b2v_inst20(
331 .a(idel4),
332 .y(SYNTHESIZED_WIRE_5));
333334335 Datap b2v_inst21(
336 .clkIn(SYNTHESIZED_WIRE_27),
337 .start(SYNTHESIZED_WIRE_8),
338 .TXE(TXE_USB),
339 .reset(SYNTHESIZED_WIRE_9),
340 .DIN(SYNTHESIZED_WIRE_28),
341 .WR(WR_USB),
342 .SIWUA(SIWUA),
343 .DATA_OUT(DATA_OUT_USB));
344345346 IO_B b2v_inst22(
347 .clkIn(SYNTHESIZED_WIRE_27),
348 .stop(SYNTHESIZED_WIRE_12),
349 .DATA_IN(DATA_IN),
350 .DATA_OUT(SYNTHESIZED_WIRE_28));
351352353 Startp b2v_inst23(
354 .clkIn(SYNTHESIZED_WIRE_27),
355 .RXF(RXF_USB_IN),
356 .DIN(DIN_USB),
357 .start(SYNTHESIZED_WIRE_8),
358 .RD(RD_USB),
359 .SIWUB(SIWUB),
360 .reset(SYNTHESIZED_WIRE_9)
361 );
362363364 DummyData b2v_inst24(
365 .clkIn(SYNTHESIZED_WIRE_27)
366 );
367368369 divider_usb b2v_inst25(
370 .clkIn(OSC_CLK),
371 .clk_out(SYNTHESIZED_WIRE_27));
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 245
372373374 Inv16 b2v_inst26(
375 .DATA_IN(SYNTHESIZED_WIRE_28),
376 .DATA_OUT(DATA_OUT));
377378379 Shift_Reg_COEFF b2v_inst29(
380 .clkIn(OSC_CLK),
381 .RESET_SHIFT(SYNTHESIZED_WIRE_29),
382 .CLK_SH3(SYNTHESIZED_WIRE_6),
383 .I_COEFF_PAD(IN_COEF_PAD),
384 .IDEL_COEFF(idel4));
385386387 Shift_Reg_TEMP b2v_inst3(
388 .clkIn(OSC_CLK),
389 .RESET_SHIFT(SYNTHESIZED_WIRE_29),
390 .CLK_SH2(SYNTHESIZED_WIRE_23),
391 .I_STAT_PAD(IN_E_PAD_TEMP),
392 .idel_TMEP(idel2));
393394395 SRAM b2v_inst30(
396 .clkIn(OSC_CLK),
397 .CLK_CV(CLK_CV),
398 .UP_DOWN_CV(UP_DOWN_CV),
399 .IMP_CV(IMP_CV),
400 .RESET_SRAM_LOGIC(RESET_SRAM_LOGIC),
401 .W(W),
402 .CLK_COEF(CLK_COEF),
403 .OFF_ON_CHIP(OFF_ON_CHIP),
404 .COS(COS),
405 .OFF_CHIP_DAC_P(OFF_CHIP_DAC_P),
406 .ELECTRODE_OFFON(ELECTRODE_OFFON));
407 PID_CONT b2v_inst17(
408 .clkIn(OSC_CLK),
409 .READ_PWM(READ_PWM),
410 .CLK_SHIFT_RING(CLK_SHFIT_RING),
411 .IN_SHIFT(IN_SHIFT_RING_PAD),
412 .CLK_RING(CLK_RING),
413 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
414 .RESET_RING(RESET_RING),
415 .WRITE_PAD(WRITE_PAD),
416 .EXT_RING(EXT_RING),
417 .ON__OFF_RING(ON_OFF_RING),
418 .B_PID(B_PID),
419 .A_PID(A_PID),
420 .ADC_PID(ADC_PID),
421 .ADC_MEM_READ(ADC_MEM_READ),
422 .MAINE_READ(MAINE_READ),
423 .RESET_(RESET_),
424 .WP0(WP0),
425 .WP1(WP1),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 246
426 .WP2(WP2),
427 .WP3(WP3),
428 .RESET_P(RESET_P),
429 .CLK_P(CLK_P),
430 .PAR_P(PAR_P));
431432433 TX b2v_inst18(
434 .clkIn(OSC_CLK),
435 .RESET_PS(RESET_PS),
436 .CLK_PS(CLK_PS),
437 .LOADSHIFT(LOAD_SHIFT));
438439440 andgate b2v_inst19(
441 .a(SYNTHESIZED_WIRE_5),
442 .b(SYNTHESIZED_WIRE_6),
443 .y(CLK_SH3_PAD));
444445446 Voltage_DAC_cont b2v_inst2(
447 .clkIn(OSC_CLK),
448 .start(start_DAC),
449 .clkout(CLK_DAC),
450 .DIN(DIN));
451452453 Inv b2v_inst20(
454 .a(idel4),
455 .y(SYNTHESIZED_WIRE_5));
456457458 Datap b2v_inst21(
459 .clkIn(SYNTHESIZED_WIRE_27),
460 .start(SYNTHESIZED_WIRE_8),
461 .TXE(TXE_USB),
462 .reset(SYNTHESIZED_WIRE_9),
463 .DIN(SYNTHESIZED_WIRE_28),
464 .WR(WR_USB),
465 .SIWUA(SIWUA),
466 .DATA_OUT(DATA_OUT_USB));
467468469 IO_B b2v_inst22(
470 .clkIn(SYNTHESIZED_WIRE_27),
471 .stop(SYNTHESIZED_WIRE_12),
472 .DATA_IN(DATA_IN),
473 .DATA_OUT(SYNTHESIZED_WIRE_28));
474475476 Startp b2v_inst23(
477 .clkIn(SYNTHESIZED_WIRE_27),
478 .RXF(RXF_USB_IN),
479 .DIN(DIN_USB),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 247
480 .start(SYNTHESIZED_WIRE_8),
481 .RD(RD_USB),
482 .SIWUB(SIWUB),
483 .reset(SYNTHESIZED_WIRE_9)
484 );
485486 Voltage_DAC b2v_inst4(
487 .clkIn(CLK_DAC),
488 .start(start_DAC),
489 .Data(DIN),
490 .clkDAC(SYNTHESIZED_WIRE_24),
491 .din1(din_out1),
492 .ldac1(ldac1),
493 .sync1(sync1),
494 .din2(din_out2),
495 .ldac2(ldac2),
496 .sync2(sync2));
497498 endmodule
A.6 Example IS Recording Verilog Code
The following code generates a 50mV peak-to-peak sinusoid waveform from 0.1Hz to
1kHz and simultaneously extract the on-chip electrode impedance from 54 channels.1 // Copyright (C) 1991-2011 Altera Corporation
2 // Your use of Altera Corporation’s design tools, logic functions
3 // and other software and tools, and its AMPP partner logic
4 // functions, and any output files from any of the foregoing
5 // (including device programming or simulation files), and any
6 // associated documentation or information are expressly subject
7 // to the terms and conditions of the Altera Program License
8 // Subscription Agreement, Altera MegaCore Function License
9 // Agreement, or other applicable license agreement, including,
10 // without limitation, that your use is for the sole purpose of
11 // programming logic devices manufactured by Altera and sold by
12 // Altera or its authorized distributors. Please refer to the
13 // applicable agreement for further details.
1415 // PROGRAM "Quartus II 64-Bit"
16 // VERSION "Version 11.0 Build 157 04/27/2011 SJ Full Version"
17 // CREATED "Sun Jul 21 20:31:33 2013"
1819 module CHEM_PRO_TOP(
20 OSC_CLK,
21 TXE_USB,
22 RXF_USB_IN,
23 DATA_IN,
24 DIN_USB,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 248
25 CS,
26 WR,
27 PD,
28 GAIN,
29 CLR,
30 ldac1,
31 sync1,
32 ldac2,
33 sync2,
34 din_out2,
35 din_out1,
36 SING,
37 C1,
38 VLATCH,
39 P1,
40 EXT_RESET,
41 BS_A,
42 BS_P,
43 Q,
44 LDAC,
45 DAC_CLK1,
46 DAC_CLK2,
47 CLK_SH1,
48 I_STAT_PAD,
49 CLK_SH2_TEMP,
50 IN_E_PAD_TEMP,
51 CLK_SHIFT_PAD,
52 I_SHIFT_PAD,
53 RESET_CH,
54 CLK_CH,
55 CLK_CV,
56 UP_DOWN_CV,
57 IMP_CV,
58 RESET_SRAM_LOGIC,
59 W,
60 CLK_COEF,
61 OFF_ON_CHIP,
62 COS,
63 OFF_CHIP_DAC_P,
64 ELECTRODE_OFFON,
65 READ_PWM,
66 CLK_SHFIT_RING,
67 CLK_RING,
68 READ_ON_OFF_PWM,
69 RESET_RING,
70 WRITE_PAD,
71 EXT_RING,
72 ON_OFF_RING,
73 B_PID,
74 A_PID,
75 ADC_PID,
76 ADC_MEM_READ,
77 MAINE_READ,
78 RESET_,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 249
79 WP0,
80 WP1,
81 WP2,
82 WP3,
83 RESET_P,
84 CLK_P,
85 PAR_P,
86 RESET_PS,
87 CLK_PS,
88 LOAD_SHIFT,
89 RESET_SHIFT,
90 IN_COEF_PAD,
91 CLK_SH3_PAD,
92 IN_SHIFT_RING_PAD,
93 CLK_TEMP,
94 CHAMBER_RESET,
95 CHAMBER_CLK,
96 WR_USB,
97 RD_USB,
98 SIWUA,
99 SIWUB,
100 B,
101 DATA_OUT,
102 DATA_OUT_USB
103 );
104105106 input wire OSC_CLK;
107 input wire TXE_USB;
108 input wire RXF_USB_IN;
109 input wire [16:0] DATA_IN;
110 input wire [7:0] DIN_USB;
111 output wire CS;
112 output wire WR;
113 output wire PD;
114 output wire GAIN;
115 output wire CLR;
116 output wire ldac1;
117 output wire sync1;
118 output wire ldac2;
119 output wire sync2;
120 output wire din_out2;
121 output wire din_out1;
122 output wire SING;
123 output wire C1;
124 output wire VLATCH;
125 output wire P1;
126 output wire EXT_RESET;
127 output wire BS_A;
128 output wire BS_P;
129 output wire Q;
130 output wire LDAC;
131 output wire DAC_CLK1;
132 output wire DAC_CLK2;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 250
133 output wire CLK_SH1;
134 output wire I_STAT_PAD;
135 output wire CLK_SH2_TEMP;
136 output wire IN_E_PAD_TEMP;
137 output wire CLK_SHIFT_PAD;
138 output wire I_SHIFT_PAD;
139 output wire RESET_CH;
140 output wire CLK_CH;
141 output wire CLK_CV;
142 output wire UP_DOWN_CV;
143 output wire IMP_CV;
144 output wire RESET_SRAM_LOGIC;
145 output wire W;
146 output wire CLK_COEF;
147 output wire OFF_ON_CHIP;
148 output wire COS;
149 output wire OFF_CHIP_DAC_P;
150 output wire ELECTRODE_OFFON;
151 output wire READ_PWM;
152 output wire CLK_SHFIT_RING;
153 output wire CLK_RING;
154 output wire READ_ON_OFF_PWM;
155 output wire RESET_RING;
156 output wire WRITE_PAD;
157 output wire EXT_RING;
158 output wire ON_OFF_RING;
159 output wire B_PID;
160 output wire A_PID;
161 output wire ADC_PID;
162 output wire ADC_MEM_READ;
163 output wire MAINE_READ;
164 output wire RESET_;
165 output wire WP0;
166 output wire WP1;
167 output wire WP2;
168 output wire WP3;
169 output wire RESET_P;
170 output wire CLK_P;
171 output wire PAR_P;
172 output wire RESET_PS;
173 output wire CLK_PS;
174 output wire LOAD_SHIFT;
175 output wire RESET_SHIFT;
176 output wire IN_COEF_PAD;
177 output wire CLK_SH3_PAD;
178 output wire IN_SHIFT_RING_PAD;
179 output wire CLK_TEMP;
180 output wire CHAMBER_RESET;
181 output wire CHAMBER_CLK;
182 output wire WR_USB;
183 output wire RD_USB;
184 output wire SIWUA;
185 output wire SIWUB;
186 output wire [9:0] B;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 251
187 output wire [16:0] DATA_OUT;
188 output wire [7:0] DATA_OUT_USB;
189190 wire CLK_DAC;
191 wire [17:0] DIN;
192 wire idel;
193 wire idel2;
194 wire idel3;
195 wire idel4;
196 wire start_DAC;
197 wire SYNTHESIZED_WIRE_25;
198 wire SYNTHESIZED_WIRE_1;
199 wire SYNTHESIZED_WIRE_2;
200 wire SYNTHESIZED_WIRE_5;
201 wire SYNTHESIZED_WIRE_6;
202 wire SYNTHESIZED_WIRE_26;
203 wire SYNTHESIZED_WIRE_8;
204 wire SYNTHESIZED_WIRE_9;
205 wire [16:0] SYNTHESIZED_WIRE_10;
206 wire SYNTHESIZED_WIRE_12;
207 wire SYNTHESIZED_WIRE_27;
208 wire SYNTHESIZED_WIRE_19;
209 wire SYNTHESIZED_WIRE_20;
210 wire SYNTHESIZED_WIRE_21;
211 wire SYNTHESIZED_WIRE_22;
212 wire SYNTHESIZED_WIRE_23;
213 wire SYNTHESIZED_WIRE_24;
214215 assign DAC_CLK1 = SYNTHESIZED_WIRE_23;
216 assign DAC_CLK2 = SYNTHESIZED_WIRE_23;
217 assign CLK_CH = SYNTHESIZED_WIRE_24;
218 assign RESET_SHIFT = SYNTHESIZED_WIRE_27;
219 assign CLK_TEMP = SYNTHESIZED_WIRE_24;
220 assign DATA_OUT = SYNTHESIZED_WIRE_10;
221222223224225 Reference_generator b2v_inst(
226 .clkIn(OSC_CLK),
227 .CS(CS),
228 .WR(WR),
229 .LDAC(LDAC),
230 .PD(PD),
231 .GAIN(GAIN),
232 .CLR(CLR),
233 .stop(SYNTHESIZED_WIRE_12),
234 .counter(B));
235236237 CH_TIMING b2v_inst1(
238 .clkIn(OSC_CLK),
239 .RESET_MASTER(SYNTHESIZED_WIRE_25),
240 .SING(SING),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 252
241 .C1(C1),
242 .VLATCH(VLATCH),
243 .P1(P1),
244 .EXT_RESET(EXT_RESET),
245 .BS_A(BS_A),
246 .BS_P(BS_P),
247 .Q(Q));
248249250 Inv b2v_inst10(
251 .a(idel2),
252 .y(SYNTHESIZED_WIRE_21));
253254255 andgate b2v_inst11(
256 .a(SYNTHESIZED_WIRE_1),
257 .b(SYNTHESIZED_WIRE_2),
258 .y(CLK_SHIFT_PAD));
259260261 Inv b2v_inst12(
262 .a(idel3),
263 .y(SYNTHESIZED_WIRE_1));
264265266 Channel_Control b2v_inst13(
267 .clkIn(OSC_CLK),
268 .RESET_IN(SYNTHESIZED_WIRE_25),
269 .RESET_CH(RESET_CH),
270 .CLK_CH(SYNTHESIZED_WIRE_24));
271272273 Channel_Control b2v_inst14(
274 .clkIn(OSC_CLK),
275 .RESET_IN(SYNTHESIZED_WIRE_25),
276 .RESET_CH(CHAMBER_RESET),
277 .CLK_CH(CHAMBER_CLK));
278279280 SHIFT_REG_RESET b2v_inst15(
281 .clkIn(OSC_CLK),
282 .RESET_SHIFT(SYNTHESIZED_WIRE_27));
283284285286 PID_CONT b2v_inst17(
287 .clkIn(OSC_CLK),
288 .READ_PWM(READ_PWM),
289 .CLK_SHIFT_RING(CLK_SHFIT_RING),
290 .IN_SHIFT(IN_SHIFT_RING_PAD),
291 .CLK_RING(CLK_RING),
292 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
293 .RESET_RING(RESET_RING),
294 .WRITE_PAD(WRITE_PAD),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 253
295 .EXT_RING(EXT_RING),
296 .ON__OFF_RING(ON_OFF_RING),
297 .B_PID(B_PID),
298 .A_PID(A_PID),
299 .ADC_PID(ADC_PID),
300 .ADC_MEM_READ(ADC_MEM_READ),
301 .MAINE_READ(MAINE_READ),
302 .RESET_(RESET_),
303 .WP0(WP0),
304 .WP1(WP1),
305 .WP2(WP2),
306 .WP3(WP3),
307 .RESET_P(RESET_P),
308 .CLK_P(CLK_P),
309 .PAR_P(PAR_P));
310 PID_CONT b2v_inst17(
311 .clkIn(OSC_CLK),
312 .READ_PWM(READ_PWM),
313 .CLK_SHIFT_RING(CLK_SHFIT_RING),
314 .IN_SHIFT(IN_SHIFT_RING_PAD),
315 .CLK_RING(CLK_RING),
316 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
317 .RESET_RING(RESET_RING),
318 .WRITE_PAD(WRITE_PAD),
319 .EXT_RING(EXT_RING),
320 .ON__OFF_RING(ON_OFF_RING),
321 .B_PID(B_PID),
322 .A_PID(A_PID),
323 .ADC_PID(ADC_PID),
324 .ADC_MEM_READ(ADC_MEM_READ),
325 .MAINE_READ(MAINE_READ),
326 .RESET_(RESET_),
327 .WP0(WP0),
328 .WP1(WP1),
329 .WP2(WP2),
330 .WP3(WP3),
331 .RESET_P(RESET_P),
332 .CLK_P(CLK_P),
333 .PAR_P(PAR_P));
334335336 TX b2v_inst18(
337 .clkIn(OSC_CLK),
338 .RESET_PS(RESET_PS),
339 .CLK_PS(CLK_PS),
340 .LOADSHIFT(LOAD_SHIFT));
341342343 andgate b2v_inst19(
344 .a(SYNTHESIZED_WIRE_5),
345 .b(SYNTHESIZED_WIRE_6),
346 .y(CLK_SH3_PAD));
347348
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 254
349 Voltage_DAC_cont b2v_inst2(
350 .clkIn(OSC_CLK),
351 .start(start_DAC),
352 .clkout(CLK_DAC),
353 .DIN(DIN));
354355356 Inv b2v_inst20(
357 .a(idel4),
358 .y(SYNTHESIZED_WIRE_5));
359360361 Datap b2v_inst21(
362 .clkIn(SYNTHESIZED_WIRE_27),
363 .start(SYNTHESIZED_WIRE_8),
364 .TXE(TXE_USB),
365 .reset(SYNTHESIZED_WIRE_9),
366 .DIN(SYNTHESIZED_WIRE_28),
367 .WR(WR_USB),
368 .SIWUA(SIWUA),
369 .DATA_OUT(DATA_OUT_USB));
370371372 IO_B b2v_inst22(
373 .clkIn(SYNTHESIZED_WIRE_27),
374 .stop(SYNTHESIZED_WIRE_12),
375 .DATA_IN(DATA_IN),
376 .DATA_OUT(SYNTHESIZED_WIRE_28));
377378379 Startp b2v_inst23(
380 .clkIn(SYNTHESIZED_WIRE_27),
381 .RXF(RXF_USB_IN),
382 .DIN(DIN_USB),
383 .start(SYNTHESIZED_WIRE_8),
384 .RD(RD_USB),
385 .SIWUB(SIWUB),
386 .reset(SYNTHESIZED_WIRE_9)
387 );
388389 TX b2v_inst18(
390 .clkIn(OSC_CLK),
391 .RESET_PS(RESET_PS),
392 .CLK_PS(CLK_PS),
393 .LOADSHIFT(LOAD_SHIFT));
394395396 andgate b2v_inst19(
397 .a(SYNTHESIZED_WIRE_5),
398 .b(SYNTHESIZED_WIRE_6),
399 .y(CLK_SH3_PAD));
400401402 Voltage_DAC_cont b2v_inst2(
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 255
403 .clkIn(OSC_CLK),
404 .start(start_DAC),
405 .clkout(CLK_DAC),
406 .DIN(DIN));
407408409 Inv b2v_inst20(
410 .a(idel4),
411 .y(SYNTHESIZED_WIRE_5));
412413414 Datap b2v_inst21(
415 .clkIn(SYNTHESIZED_WIRE_26),
416 .start(SYNTHESIZED_WIRE_8),
417 .TXE(TXE_USB),
418 .reset(SYNTHESIZED_WIRE_9),
419 .DIN(SYNTHESIZED_WIRE_10),
420 .WR(WR_USB),
421 .SIWUA(SIWUA),
422 .DATA_OUT(DATA_OUT_USB));
423424425 IO_B b2v_inst22(
426 .clkIn(SYNTHESIZED_WIRE_26),
427 .stop(SYNTHESIZED_WIRE_12),
428 .DATA_IN(DATA_IN),
429 .DATA_OUT(SYNTHESIZED_WIRE_10));
430431432 Startp b2v_inst23(
433 .clkIn(SYNTHESIZED_WIRE_26),
434 .RXF(RXF_USB_IN),
435 .DIN(DIN_USB),
436 .start(SYNTHESIZED_WIRE_8),
437 .RD(RD_USB),
438 .SIWUB(SIWUB),
439 .reset(SYNTHESIZED_WIRE_9)
440 );
441442443 DummyData b2v_inst24(
444 .clkIn(SYNTHESIZED_WIRE_26)
445 );
446447448 divider_usb b2v_inst25(
449 .clkIn(OSC_CLK),
450 .clk_out(SYNTHESIZED_WIRE_26));
451452453 Shift_Reg_COEFF b2v_inst29(
454 .clkIn(OSC_CLK),
455 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
456 .CLK_SH3(SYNTHESIZED_WIRE_6),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 256
457 .I_COEFF_PAD(IN_COEF_PAD),
458 .IDEL_COEFF(idel4));
459460461 Shift_Reg_TEMP b2v_inst3(
462 .clkIn(OSC_CLK),
463 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
464 .CLK_SH2(SYNTHESIZED_WIRE_22),
465 .I_STAT_PAD(IN_E_PAD_TEMP),
466 .idel_TMEP(idel2));
467468469 SRAM b2v_inst30(
470 .clkIn(OSC_CLK),
471 .CLK_CV(CLK_CV),
472 .UP_DOWN_CV(UP_DOWN_CV),
473 .IMP_CV(IMP_CV),
474 .RESET_SRAM_LOGIC(RESET_SRAM_LOGIC),
475 .W(W),
476 .CLK_COEF(CLK_COEF),
477 .OFF_ON_CHIP(OFF_ON_CHIP),
478 .COS(COS),
479 .OFF_CHIP_DAC_P(OFF_CHIP_DAC_P),
480 .ELECTRODE_OFFON(ELECTRODE_OFFON));
481482483 Voltage_DAC b2v_inst4(
484 .clkIn(CLK_DAC),
485 .start(start_DAC),
486 .Data(DIN),
487 .clkDAC(SYNTHESIZED_WIRE_23),
488 .din1(din_out1),
489 .ldac1(ldac1),
490 .sync1(sync1),
491 .din2(din_out2),
492 .ldac2(ldac2),
493 .sync2(sync2));
494495496 Shift_Reg_TEMP_STAT b2v_inst5(
497 .clkIn(OSC_CLK),
498 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
499 .CLK_SHIFT_PAD(SYNTHESIZED_WIRE_2),
500 .I_SHIFT_PAD(I_SHIFT_PAD),
501 .idel_TMEP_STAT(idel3));
502503504 Shift_Reg_POT b2v_inst6(
505 .clkIn(OSC_CLK),
506 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
507 .clk_POT(SYNTHESIZED_WIRE_20),
508 .I_STAT_PAD_POT(I_STAT_PAD),
509 .idel_POT(idel));
510
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 257
511512 RESET_CONT b2v_inst64(
513 .clkIn(OSC_CLK),
514 .IDEL1(idel),
515 .IDEL2(idel2),
516 .IDEL3(idel3),
517 .IDEL4(idel4),
518 .RESET_OUT(SYNTHESIZED_WIRE_25));
519520521 andgate b2v_inst7(
522 .a(SYNTHESIZED_WIRE_19),
523 .b(SYNTHESIZED_WIRE_20),
524 .y(CLK_SH1));
525526527 Inv b2v_inst8(
528 .a(idel),
529 .y(SYNTHESIZED_WIRE_19));
530531532 andgate b2v_inst9(
533 .a(SYNTHESIZED_WIRE_21),
534 .b(SYNTHESIZED_WIRE_22),
535 .y(CLK_SH2_TEMP));
536 SRAM b2v_inst30(
537 .clkIn(OSC_CLK),
538 .CLK_CV(CLK_CV),
539 .UP_DOWN_CV(UP_DOWN_CV),
540 .IMP_CV(IMP_CV),
541 .RESET_SRAM_LOGIC(RESET_SRAM_LOGIC),
542 .W(W),
543 .CLK_COEF(CLK_COEF),
544 .OFF_ON_CHIP(OFF_ON_CHIP),
545 .COS(COS),
546 .OFF_CHIP_DAC_P(OFF_CHIP_DAC_P),
547 .ELECTRODE_OFFON(ELECTRODE_OFFON));
548549550 Voltage_DAC b2v_inst4(
551 .clkIn(CLK_DAC),
552 .start(start_DAC),
553 .Data(DIN),
554 .clkDAC(SYNTHESIZED_WIRE_23),
555 .din1(din_out1),
556 .ldac1(ldac1),
557 .sync1(sync1),
558 .din2(din_out2),
559 .ldac2(ldac2),
560 .sync2(sync2));
561562563 Shift_Reg_TEMP_STAT b2v_inst5(
564 .clkIn(OSC_CLK),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 258
565 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
566 .CLK_SHIFT_PAD(SYNTHESIZED_WIRE_2),
567 .I_SHIFT_PAD(I_SHIFT_PAD),
568 .idel_TMEP_STAT(idel3));
569570571 Shift_Reg_POT b2v_inst6(
572 .clkIn(OSC_CLK),
573 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
574 .clk_POT(SYNTHESIZED_WIRE_20),
575 .I_STAT_PAD_POT(I_STAT_PAD),
576 .idel_POT(idel));
577578579 endmodule
A.7 Example Temperature Regulation Verilog Code
The following code generate the results shown in Fig. 5.21.1 // Copyright (C) 1991-2011 Altera Corporation
2 // Your use of Altera Corporation’s design tools, logic functions
3 // and other software and tools, and its AMPP partner logic
4 // functions, and any output files from any of the foregoing
5 // (including device programming or simulation files), and any
6 // associated documentation or information are expressly subject
7 // to the terms and conditions of the Altera Program License
8 // Subscription Agreement, Altera MegaCore Function License
9 // Agreement, or other applicable license agreement, including,
10 // without limitation, that your use is for the sole purpose of
11 // programming logic devices manufactured by Altera and sold by
12 // Altera or its authorized distributors. Please refer to the
13 // applicable agreement for further details.
1415 // PROGRAM "Quartus II 64-Bit"
16 // VERSION "Version 11.0 Build 157 04/27/2011 SJ Full Version"
17 // CREATED "Sun Jul 21 20:36:38 2013"
1819 module CHEM_PRO_TOP(
20 OSC_CLK,
21 TXE_USB,
22 RXF_USB_IN,
23 DATA_IN,
24 DIN_USB,
25 CS,
26 WR,
27 PD,
28 GAIN,
29 CLR,
30 ldac1,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 259
31 sync1,
32 ldac2,
33 sync2,
34 din_out2,
35 din_out1,
36 SING,
37 C1,
38 VLATCH,
39 P1,
40 EXT_RESET,
41 BS_A,
42 BS_P,
43 Q,
44 LDAC,
45 DAC_CLK1,
46 DAC_CLK2,
47 CLK_SH1,
48 I_STAT_PAD,
49 CLK_SH2_TEMP,
50 IN_E_PAD_TEMP,
51 CLK_SHIFT_PAD,
52 I_SHIFT_PAD,
53 RESET_CH,
54 CLK_CH,
55 CLK_CV,
56 UP_DOWN_CV,
57 IMP_CV,
58 RESET_SRAM_LOGIC,
59 W,
60 CLK_COEF,
61 OFF_ON_CHIP,
62 COS,
63 OFF_CHIP_DAC_P,
64 ELECTRODE_OFFON,
65 READ_PWM,
66 CLK_SHFIT_RING,
67 CLK_RING,
68 READ_ON_OFF_PWM,
69 RESET_RING,
70 WRITE_PAD,
71 EXT_RING,
72 ON_OFF_RING,
73 B_PID,
74 A_PID,
75 ADC_PID,
76 ADC_MEM_READ,
77 MAINE_READ,
78 RESET_,
79 WP0,
80 WP1,
81 WP2,
82 WP3,
83 RESET_P,
84 CLK_P,
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 260
85 PAR_P,
86 RESET_PS,
87 CLK_PS,
88 LOAD_SHIFT,
89 RESET_SHIFT,
90 IN_COEF_PAD,
91 CLK_SH3_PAD,
92 IN_SHIFT_RING_PAD,
93 CLK_TEMP,
94 CHAMBER_RESET,
95 CHAMBER_CLK,
96 WR_USB,
97 RD_USB,
98 SIWUA,
99 SIWUB,
100 B,
101 DATA_OUT,
102 DATA_OUT_USB
103 );
104105106 input wire OSC_CLK;
107 input wire TXE_USB;
108 input wire RXF_USB_IN;
109 input wire [16:0] DATA_IN;
110 input wire [7:0] DIN_USB;
111 output wire CS;
112 output wire WR;
113 output wire PD;
114 output wire GAIN;
115 output wire CLR;
116 output wire ldac1;
117 output wire sync1;
118 output wire ldac2;
119 output wire sync2;
120 output wire din_out2;
121 output wire din_out1;
122 output wire SING;
123 output wire C1;
124 output wire VLATCH;
125 output wire P1;
126 output wire EXT_RESET;
127 output wire BS_A;
128 output wire BS_P;
129 output wire Q;
130 output wire LDAC;
131 output wire DAC_CLK1;
132 output wire DAC_CLK2;
133 output wire CLK_SH1;
134 output wire I_STAT_PAD;
135 output wire CLK_SH2_TEMP;
136 output wire IN_E_PAD_TEMP;
137 output wire CLK_SHIFT_PAD;
138 output wire I_SHIFT_PAD;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 261
139 output wire RESET_CH;
140 output wire CLK_CH;
141 output wire CLK_CV;
142 output wire UP_DOWN_CV;
143 output wire IMP_CV;
144 output wire RESET_SRAM_LOGIC;
145 output wire W;
146 output wire CLK_COEF;
147 output wire OFF_ON_CHIP;
148 output wire COS;
149 output wire OFF_CHIP_DAC_P;
150 output wire ELECTRODE_OFFON;
151 output wire READ_PWM;
152 output wire CLK_SHFIT_RING;
153 output wire CLK_RING;
154 output wire READ_ON_OFF_PWM;
155 output wire RESET_RING;
156 output wire WRITE_PAD;
157 output wire EXT_RING;
158 output wire ON_OFF_RING;
159 output wire B_PID;
160 output wire A_PID;
161 output wire ADC_PID;
162 output wire ADC_MEM_READ;
163 output wire MAINE_READ;
164 output wire RESET_;
165 output wire WP0;
166 output wire WP1;
167 output wire WP2;
168 output wire WP3;
169 output wire RESET_P;
170 output wire CLK_P;
171 output wire PAR_P;
172 output wire RESET_PS;
173 output wire CLK_PS;
174 output wire LOAD_SHIFT;
175 output wire RESET_SHIFT;
176 output wire IN_COEF_PAD;
177 output wire CLK_SH3_PAD;
178 output wire IN_SHIFT_RING_PAD;
179 output wire CLK_TEMP;
180 output wire CHAMBER_RESET;
181 output wire CHAMBER_CLK;
182 output wire WR_USB;
183 output wire RD_USB;
184 output wire SIWUA;
185 output wire SIWUB;
186 output wire [9:0] B;
187 output wire [16:0] DATA_OUT;
188 output wire [7:0] DATA_OUT_USB;
189190 wire CLK_DAC;
191 wire [17:0] DIN;
192 wire idel;
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 262
193 wire idel2;
194 wire idel3;
195 wire idel4;
196 wire start_DAC;
197 wire SYNTHESIZED_WIRE_25;
198 wire SYNTHESIZED_WIRE_1;
199 wire SYNTHESIZED_WIRE_2;
200 wire SYNTHESIZED_WIRE_5;
201 wire SYNTHESIZED_WIRE_6;
202 wire SYNTHESIZED_WIRE_26;
203 wire SYNTHESIZED_WIRE_8;
204 wire SYNTHESIZED_WIRE_9;
205 wire [16:0] SYNTHESIZED_WIRE_10;
206 wire SYNTHESIZED_WIRE_12;
207 wire SYNTHESIZED_WIRE_27;
208 wire SYNTHESIZED_WIRE_19;
209 wire SYNTHESIZED_WIRE_20;
210 wire SYNTHESIZED_WIRE_21;
211 wire SYNTHESIZED_WIRE_22;
212 wire SYNTHESIZED_WIRE_23;
213 wire SYNTHESIZED_WIRE_24;
214215 assign DAC_CLK1 = SYNTHESIZED_WIRE_23;
216 assign DAC_CLK2 = SYNTHESIZED_WIRE_23;
217 assign CLK_CH = SYNTHESIZED_WIRE_24;
218 assign RESET_SHIFT = SYNTHESIZED_WIRE_27;
219 assign CLK_TEMP = SYNTHESIZED_WIRE_24;
220 assign DATA_OUT = SYNTHESIZED_WIRE_10;
221222 PID_CONT b2v_inst17(
223 .clkIn(OSC_CLK),
224 .READ_PWM(READ_PWM),
225 .CLK_SHIFT_RING(CLK_SHFIT_RING),
226 .IN_SHIFT(IN_SHIFT_RING_PAD),
227 .CLK_RING(CLK_RING),
228 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
229 .RESET_RING(RESET_RING),
230 .WRITE_PAD(WRITE_PAD),
231 .EXT_RING(EXT_RING),
232 .ON__OFF_RING(ON_OFF_RING),
233 .B_PID(B_PID),
234 .A_PID(A_PID),
235 .ADC_PID(ADC_PID),
236 .ADC_MEM_READ(ADC_MEM_READ),
237 .MAINE_READ(MAINE_READ),
238 .RESET_(RESET_),
239 .WP0(WP0),
240 .WP1(WP1),
241 .WP2(WP2),
242 .WP3(WP3),
243 .RESET_P(RESET_P),
244 .CLK_P(CLK_P),
245 .PAR_P(PAR_P));
246
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 263
247248 TX b2v_inst18(
249 .clkIn(OSC_CLK),
250 .RESET_PS(RESET_PS),
251 .CLK_PS(CLK_PS),
252 .LOADSHIFT(LOAD_SHIFT));
253254255 andgate b2v_inst19(
256 .a(SYNTHESIZED_WIRE_5),
257 .b(SYNTHESIZED_WIRE_6),
258 .y(CLK_SH3_PAD));
259260261 Voltage_DAC_cont b2v_inst2(
262 .clkIn(OSC_CLK),
263 .start(start_DAC),
264 .clkout(CLK_DAC),
265 .DIN(DIN));
266267268 Inv b2v_inst20(
269 .a(idel4),
270 .y(SYNTHESIZED_WIRE_5));
271272273 Datap b2v_inst21(
274 .clkIn(SYNTHESIZED_WIRE_27),
275 .start(SYNTHESIZED_WIRE_8),
276 .TXE(TXE_USB),
277 .reset(SYNTHESIZED_WIRE_9),
278 .DIN(SYNTHESIZED_WIRE_28),
279 .WR(WR_USB),
280 .SIWUA(SIWUA),
281 .DATA_OUT(DATA_OUT_USB));
282283284 IO_B b2v_inst22(
285 .clkIn(SYNTHESIZED_WIRE_27),
286 .stop(SYNTHESIZED_WIRE_12),
287 .DATA_IN(DATA_IN),
288 .DATA_OUT(SYNTHESIZED_WIRE_28));
289290291 Startp b2v_inst23(
292 .clkIn(SYNTHESIZED_WIRE_27),
293 .RXF(RXF_USB_IN),
294 .DIN(DIN_USB),
295 .start(SYNTHESIZED_WIRE_8),
296 .RD(RD_USB),
297 .SIWUB(SIWUB),
298 .reset(SYNTHESIZED_WIRE_9)
299 );
300
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 264
301302 Reference_generator b2v_inst(
303 .clkIn(OSC_CLK),
304 .CS(CS),
305 .WR(WR),
306 .LDAC(LDAC),
307 .PD(PD),
308 .GAIN(GAIN),
309 .CLR(CLR),
310 .stop(SYNTHESIZED_WIRE_12),
311 .counter(B));
312313314 CH_TIMING b2v_inst1(
315 .clkIn(OSC_CLK),
316 .RESET_MASTER(SYNTHESIZED_WIRE_25),
317 .SING(SING),
318 .C1(C1),
319 .VLATCH(VLATCH),
320 .P1(P1),
321 .EXT_RESET(EXT_RESET),
322 .BS_A(BS_A),
323 .BS_P(BS_P),
324 .Q(Q));
325326327 Inv b2v_inst10(
328 .a(idel2),
329 .y(SYNTHESIZED_WIRE_21));
330331332 andgate b2v_inst11(
333 .a(SYNTHESIZED_WIRE_1),
334 .b(SYNTHESIZED_WIRE_2),
335 .y(CLK_SHIFT_PAD));
336337338 Inv b2v_inst12(
339 .a(idel3),
340 .y(SYNTHESIZED_WIRE_1));
341342343 Channel_Control b2v_inst13(
344 .clkIn(OSC_CLK),
345 .RESET_IN(SYNTHESIZED_WIRE_25),
346 .RESET_CH(RESET_CH),
347 .CLK_CH(SYNTHESIZED_WIRE_24));
348349350 Channel_Control b2v_inst14(
351 .clkIn(OSC_CLK),
352 .RESET_IN(SYNTHESIZED_WIRE_25),
353 .RESET_CH(CHAMBER_RESET),
354 .CLK_CH(CHAMBER_CLK));
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 265
355356357 SHIFT_REG_RESET b2v_inst15(
358 .clkIn(OSC_CLK),
359 .RESET_SHIFT(SYNTHESIZED_WIRE_27));
360361362363 PID_CONT b2v_inst17(
364 .clkIn(OSC_CLK),
365 .READ_PWM(READ_PWM),
366 .CLK_SHIFT_RING(CLK_SHFIT_RING),
367 .IN_SHIFT(IN_SHIFT_RING_PAD),
368 .CLK_RING(CLK_RING),
369 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
370 .RESET_RING(RESET_RING),
371 .WRITE_PAD(WRITE_PAD),
372 .EXT_RING(EXT_RING),
373 .ON__OFF_RING(ON_OFF_RING),
374 .B_PID(B_PID),
375 .A_PID(A_PID),
376 .ADC_PID(ADC_PID),
377 .ADC_MEM_READ(ADC_MEM_READ),
378 .MAINE_READ(MAINE_READ),
379 .RESET_(RESET_),
380 .WP0(WP0),
381 .WP1(WP1),
382 .WP2(WP2),
383 .WP3(WP3),
384 .RESET_P(RESET_P),
385 .CLK_P(CLK_P),
386 .PAR_P(PAR_P));
387388389 TX b2v_inst18(
390 .clkIn(OSC_CLK),
391 .RESET_PS(RESET_PS),
392 .CLK_PS(CLK_PS),
393 .LOADSHIFT(LOAD_SHIFT));
394395396 andgate b2v_inst19(
397 .a(SYNTHESIZED_WIRE_5),
398 .b(SYNTHESIZED_WIRE_6),
399 .y(CLK_SH3_PAD));
400401402 Voltage_DAC_cont b2v_inst2(
403 .clkIn(OSC_CLK),
404 .start(start_DAC),
405 .clkout(CLK_DAC),
406 .DIN(DIN));
407408
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 266
409 Inv b2v_inst20(
410 .a(idel4),
411 .y(SYNTHESIZED_WIRE_5));
412413414 Datap b2v_inst21(
415 .clkIn(SYNTHESIZED_WIRE_26),
416 .start(SYNTHESIZED_WIRE_8),
417 .TXE(TXE_USB),
418 .reset(SYNTHESIZED_WIRE_9),
419 .DIN(SYNTHESIZED_WIRE_10),
420 .WR(WR_USB),
421 .SIWUA(SIWUA),
422 .DATA_OUT(DATA_OUT_USB));
423424425 IO_B b2v_inst22(
426 .clkIn(SYNTHESIZED_WIRE_26),
427 .stop(SYNTHESIZED_WIRE_12),
428 .DATA_IN(DATA_IN),
429 .DATA_OUT(SYNTHESIZED_WIRE_10));
430431432 Startp b2v_inst23(
433 .clkIn(SYNTHESIZED_WIRE_26),
434 .RXF(RXF_USB_IN),
435 .DIN(DIN_USB),
436 .start(SYNTHESIZED_WIRE_8),
437 .RD(RD_USB),
438 .SIWUB(SIWUB),
439 .reset(SYNTHESIZED_WIRE_9)
440 );
441442443 DummyData b2v_inst24(
444 .clkIn(SYNTHESIZED_WIRE_26)
445 );
446447448 divider_usb b2v_inst25(
449 .clkIn(OSC_CLK),
450 .clk_out(SYNTHESIZED_WIRE_26));
451452453454455 Shift_Reg_COEFF b2v_inst29(
456 .clkIn(OSC_CLK),
457 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
458 .CLK_SH3(SYNTHESIZED_WIRE_6),
459 .I_COEFF_PAD(IN_COEF_PAD),
460 .IDEL_COEFF(idel4));
461462
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 267
463 Shift_Reg_TEMP b2v_inst3(
464 .clkIn(OSC_CLK),
465 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
466 .CLK_SH2(SYNTHESIZED_WIRE_22),
467 .I_STAT_PAD(IN_E_PAD_TEMP),
468 .idel_TMEP(idel2));
469470471 SRAM b2v_inst30(
472 .clkIn(OSC_CLK),
473 .CLK_CV(CLK_CV),
474 .UP_DOWN_CV(UP_DOWN_CV),
475 .IMP_CV(IMP_CV),
476 .RESET_SRAM_LOGIC(RESET_SRAM_LOGIC),
477 .W(W),
478 .CLK_COEF(CLK_COEF),
479 .OFF_ON_CHIP(OFF_ON_CHIP),
480 .COS(COS),
481 .OFF_CHIP_DAC_P(OFF_CHIP_DAC_P),
482 .ELECTRODE_OFFON(ELECTRODE_OFFON));
483484485 Voltage_DAC b2v_inst4(
486 .clkIn(CLK_DAC),
487 .start(start_DAC),
488 .Data(DIN),
489 .clkDAC(SYNTHESIZED_WIRE_23),
490 .din1(din_out1),
491 .ldac1(ldac1),
492 .sync1(sync1),
493 .din2(din_out2),
494 .ldac2(ldac2),
495 .sync2(sync2));
496497498 Shift_Reg_TEMP_STAT b2v_inst5(
499 .clkIn(OSC_CLK),
500 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
501 .CLK_SHIFT_PAD(SYNTHESIZED_WIRE_2),
502 .I_SHIFT_PAD(I_SHIFT_PAD),
503 .idel_TMEP_STAT(idel3));
504505506 Shift_Reg_POT b2v_inst6(
507 .clkIn(OSC_CLK),
508 .RESET_SHIFT(SYNTHESIZED_WIRE_27),
509 .clk_POT(SYNTHESIZED_WIRE_20),
510 .I_STAT_PAD_POT(I_STAT_PAD),
511 .idel_POT(idel));
512513514 RESET_CONT b2v_inst64(
515 .clkIn(OSC_CLK),
516 .IDEL1(idel),
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 268
517 .IDEL2(idel2),
518 .IDEL3(idel3),
519 .IDEL4(idel4),
520 .RESET_OUT(SYNTHESIZED_WIRE_25));
521522523 andgate b2v_inst7(
524 .a(SYNTHESIZED_WIRE_19),
525 .b(SYNTHESIZED_WIRE_20),
526 .y(CLK_SH1));
527528529 Inv b2v_inst8(
530 .a(idel),
531 .y(SYNTHESIZED_WIRE_19));
532533534 andgate b2v_inst9(
535 .a(SYNTHESIZED_WIRE_21),
536 .b(SYNTHESIZED_WIRE_22),
537 .y(CLK_SH2_TEMP));
538 PID_CONT b2v_inst17(
539 .clkIn(OSC_CLK),
540 .READ_PWM(READ_PWM),
541 .CLK_SHIFT_RING(CLK_SHFIT_RING),
542 .IN_SHIFT(IN_SHIFT_RING_PAD),
543 .CLK_RING(CLK_RING),
544 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
545 .RESET_RING(RESET_RING),
546 .WRITE_PAD(WRITE_PAD),
547 .EXT_RING(EXT_RING),
548 .ON__OFF_RING(ON_OFF_RING),
549 .B_PID(B_PID),
550 .A_PID(A_PID),
551 .ADC_PID(ADC_PID),
552 .ADC_MEM_READ(ADC_MEM_READ),
553 .MAINE_READ(MAINE_READ),
554 .RESET_(RESET_),
555 .WP0(WP0),
556 .WP1(WP1),
557 .WP2(WP2),
558 .WP3(WP3),
559 .RESET_P(RESET_P),
560 .CLK_P(CLK_P),
561 .PAR_P(PAR_P));
562563564 TX b2v_inst18(
565 .clkIn(OSC_CLK),
566 .RESET_PS(RESET_PS),
567 .CLK_PS(CLK_PS),
568 .LOADSHIFT(LOAD_SHIFT));
569570
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 269
571 andgate b2v_inst19(
572 .a(SYNTHESIZED_WIRE_5),
573 .b(SYNTHESIZED_WIRE_6),
574 .y(CLK_SH3_PAD));
575576577 Voltage_DAC_cont b2v_inst2(
578 .clkIn(OSC_CLK),
579 .start(start_DAC),
580 .clkout(CLK_DAC),
581 .DIN(DIN));
582583584 Inv b2v_inst20(
585 .a(idel4),
586 .y(SYNTHESIZED_WIRE_5));
587588589 Datap b2v_inst21(
590 .clkIn(SYNTHESIZED_WIRE_27),
591 .start(SYNTHESIZED_WIRE_8),
592 .TXE(TXE_USB),
593 .reset(SYNTHESIZED_WIRE_9),
594 .DIN(SYNTHESIZED_WIRE_28),
595 .WR(WR_USB),
596 .SIWUA(SIWUA),
597 .DATA_OUT(DATA_OUT_USB));
598599600 IO_B b2v_inst22(
601 .clkIn(SYNTHESIZED_WIRE_27),
602 .stop(SYNTHESIZED_WIRE_12),
603 .DATA_IN(DATA_IN),
604 .DATA_OUT(SYNTHESIZED_WIRE_28));
605606607 Startp b2v_inst23(
608 .clkIn(SYNTHESIZED_WIRE_27),
609 .RXF(RXF_USB_IN),
610 .DIN(DIN_USB),
611 .start(SYNTHESIZED_WIRE_8),
612 .RD(RD_USB),
613 .SIWUB(SIWUB),
614 .reset(SYNTHESIZED_WIRE_9)
615 );
616 Inv b2v_inst8(
617 .a(idel),
618 .y(SYNTHESIZED_WIRE_19));
619620621 andgate b2v_inst9(
622 .a(SYNTHESIZED_WIRE_21),
623 .b(SYNTHESIZED_WIRE_22),
624 .y(CLK_SH2_TEMP));
CHAPTER A. SUPPLEMENTARY HARDWARE AND SOFTWARE DOCUMENTATION 270
625 PID_CONT b2v_inst17(
626 .clkIn(OSC_CLK),
627 .READ_PWM(READ_PWM),
628 .CLK_SHIFT_RING(CLK_SHFIT_RING),
629 .IN_SHIFT(IN_SHIFT_RING_PAD),
630 .CLK_RING(CLK_RING),
631 .READ_ON_OFF_PWM(READ_ON_OFF_PWM),
632 .RESET_RING(RESET_RING),
633 .WRITE_PAD(WRITE_PAD),
634 .EXT_RING(EXT_RING),
635 .ON__OFF_RING(ON_OFF_RING),
636 .B_PID(B_PID),
637 .A_PID(A_PID),
638 .ADC_PID(ADC_PID),
639 .ADC_MEM_READ(ADC_MEM_READ),
640 .MAINE_READ(MAINE_READ),
641 .RESET_(RESET_),
642 .WP0(WP0),
643 .WP1(WP1),
644 .WP2(WP2),
645 .WP3(WP3),
646 .RESET_P(RESET_P),
647 .CLK_P(CLK_P),
648 .PAR_P(PAR_P));
649650651 TX b2v_inst18(
652 .clkIn(OSC_CLK),
653 .RESET_PS(RESET_PS),
654 .CLK_PS(CLK_PS),
655 .LOADSHIFT(LOAD_SHIFT));
656657 endmodule
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